1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 #ifndef __DCE_HWSEQ_H__ 26 #define __DCE_HWSEQ_H__ 27 28 #include "dc_types.h" 29 30 #define HWSEQ_DCEF_REG_LIST_DCE8() \ 31 .DCFE_CLOCK_CONTROL[0] = mmCRTC0_CRTC_DCFE_CLOCK_CONTROL, \ 32 .DCFE_CLOCK_CONTROL[1] = mmCRTC1_CRTC_DCFE_CLOCK_CONTROL, \ 33 .DCFE_CLOCK_CONTROL[2] = mmCRTC2_CRTC_DCFE_CLOCK_CONTROL, \ 34 .DCFE_CLOCK_CONTROL[3] = mmCRTC3_CRTC_DCFE_CLOCK_CONTROL, \ 35 .DCFE_CLOCK_CONTROL[4] = mmCRTC4_CRTC_DCFE_CLOCK_CONTROL, \ 36 .DCFE_CLOCK_CONTROL[5] = mmCRTC5_CRTC_DCFE_CLOCK_CONTROL 37 38 #define HWSEQ_DCEF_REG_LIST() \ 39 SRII(DCFE_CLOCK_CONTROL, DCFE, 0), \ 40 SRII(DCFE_CLOCK_CONTROL, DCFE, 1), \ 41 SRII(DCFE_CLOCK_CONTROL, DCFE, 2), \ 42 SRII(DCFE_CLOCK_CONTROL, DCFE, 3), \ 43 SRII(DCFE_CLOCK_CONTROL, DCFE, 4), \ 44 SRII(DCFE_CLOCK_CONTROL, DCFE, 5), \ 45 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL) 46 47 #define HWSEQ_BLND_REG_LIST() \ 48 SRII(BLND_V_UPDATE_LOCK, BLND, 0), \ 49 SRII(BLND_V_UPDATE_LOCK, BLND, 1), \ 50 SRII(BLND_V_UPDATE_LOCK, BLND, 2), \ 51 SRII(BLND_V_UPDATE_LOCK, BLND, 3), \ 52 SRII(BLND_V_UPDATE_LOCK, BLND, 4), \ 53 SRII(BLND_V_UPDATE_LOCK, BLND, 5), \ 54 SRII(BLND_CONTROL, BLND, 0), \ 55 SRII(BLND_CONTROL, BLND, 1), \ 56 SRII(BLND_CONTROL, BLND, 2), \ 57 SRII(BLND_CONTROL, BLND, 3), \ 58 SRII(BLND_CONTROL, BLND, 4), \ 59 SRII(BLND_CONTROL, BLND, 5) 60 61 #define HSWEQ_DCN_PIXEL_RATE_REG_LIST(blk, inst) \ 62 SRII(PIXEL_RATE_CNTL, blk, inst), \ 63 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, inst) 64 65 #define HWSEQ_PIXEL_RATE_REG_LIST(blk) \ 66 SRII(PIXEL_RATE_CNTL, blk, 0), \ 67 SRII(PIXEL_RATE_CNTL, blk, 1), \ 68 SRII(PIXEL_RATE_CNTL, blk, 2), \ 69 SRII(PIXEL_RATE_CNTL, blk, 3), \ 70 SRII(PIXEL_RATE_CNTL, blk, 4), \ 71 SRII(PIXEL_RATE_CNTL, blk, 5) 72 73 #define HWSEQ_PHYPLL_REG_LIST(blk) \ 74 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 0), \ 75 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 1), \ 76 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 2), \ 77 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 3), \ 78 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 4), \ 79 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 5) 80 81 #if defined(CONFIG_DRM_AMD_DC_DCN3_0) 82 #define HWSEQ_PIXEL_RATE_REG_LIST_3(blk) \ 83 SRII(PIXEL_RATE_CNTL, blk, 0), \ 84 SRII(PIXEL_RATE_CNTL, blk, 1),\ 85 SRII(PIXEL_RATE_CNTL, blk, 2),\ 86 SRII(PIXEL_RATE_CNTL, blk, 3), \ 87 SRII(PIXEL_RATE_CNTL, blk, 4), \ 88 SRII(PIXEL_RATE_CNTL, blk, 5) 89 90 #define HWSEQ_PHYPLL_REG_LIST_3(blk) \ 91 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 0), \ 92 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 1),\ 93 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 2),\ 94 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 3), \ 95 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 4), \ 96 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 5) 97 #endif 98 99 #define HWSEQ_DCE11_REG_LIST_BASE() \ 100 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \ 101 SR(DCFEV_CLOCK_CONTROL), \ 102 SRII(DCFE_CLOCK_CONTROL, DCFE, 0), \ 103 SRII(DCFE_CLOCK_CONTROL, DCFE, 1), \ 104 SRII(CRTC_H_BLANK_START_END, CRTC, 0),\ 105 SRII(CRTC_H_BLANK_START_END, CRTC, 1),\ 106 SRII(BLND_V_UPDATE_LOCK, BLND, 0),\ 107 SRII(BLND_V_UPDATE_LOCK, BLND, 1),\ 108 SRII(BLND_CONTROL, BLND, 0),\ 109 SRII(BLND_CONTROL, BLND, 1),\ 110 SR(BLNDV_CONTROL),\ 111 HWSEQ_PIXEL_RATE_REG_LIST(CRTC) 112 113 #if defined(CONFIG_DRM_AMD_DC_SI) 114 #define HWSEQ_DCE6_REG_LIST() \ 115 HWSEQ_DCEF_REG_LIST_DCE8(), \ 116 HWSEQ_PIXEL_RATE_REG_LIST(CRTC) 117 #endif 118 119 #define HWSEQ_DCE8_REG_LIST() \ 120 HWSEQ_DCEF_REG_LIST_DCE8(), \ 121 HWSEQ_BLND_REG_LIST(), \ 122 HWSEQ_PIXEL_RATE_REG_LIST(CRTC) 123 124 #define HWSEQ_DCE10_REG_LIST() \ 125 HWSEQ_DCEF_REG_LIST(), \ 126 HWSEQ_BLND_REG_LIST(), \ 127 HWSEQ_PIXEL_RATE_REG_LIST(CRTC) 128 129 #define HWSEQ_ST_REG_LIST() \ 130 HWSEQ_DCE11_REG_LIST_BASE(), \ 131 .DCFE_CLOCK_CONTROL[2] = mmDCFEV_CLOCK_CONTROL, \ 132 .CRTC_H_BLANK_START_END[2] = mmCRTCV_H_BLANK_START_END, \ 133 .BLND_V_UPDATE_LOCK[2] = mmBLNDV_V_UPDATE_LOCK, \ 134 .BLND_CONTROL[2] = mmBLNDV_CONTROL 135 136 #define HWSEQ_CZ_REG_LIST() \ 137 HWSEQ_DCE11_REG_LIST_BASE(), \ 138 SRII(DCFE_CLOCK_CONTROL, DCFE, 2), \ 139 SRII(CRTC_H_BLANK_START_END, CRTC, 2), \ 140 SRII(BLND_V_UPDATE_LOCK, BLND, 2), \ 141 SRII(BLND_CONTROL, BLND, 2), \ 142 .DCFE_CLOCK_CONTROL[3] = mmDCFEV_CLOCK_CONTROL, \ 143 .CRTC_H_BLANK_START_END[3] = mmCRTCV_H_BLANK_START_END, \ 144 .BLND_V_UPDATE_LOCK[3] = mmBLNDV_V_UPDATE_LOCK, \ 145 .BLND_CONTROL[3] = mmBLNDV_CONTROL 146 147 #define HWSEQ_DCE120_REG_LIST() \ 148 HWSEQ_DCE10_REG_LIST(), \ 149 HWSEQ_PIXEL_RATE_REG_LIST(CRTC), \ 150 HWSEQ_PHYPLL_REG_LIST(CRTC), \ 151 SR(DCHUB_FB_LOCATION),\ 152 SR(DCHUB_AGP_BASE),\ 153 SR(DCHUB_AGP_BOT),\ 154 SR(DCHUB_AGP_TOP) 155 156 #define HWSEQ_VG20_REG_LIST() \ 157 HWSEQ_DCE120_REG_LIST(),\ 158 MMHUB_SR(MC_VM_XGMI_LFB_CNTL) 159 160 #define HWSEQ_DCE112_REG_LIST() \ 161 HWSEQ_DCE10_REG_LIST(), \ 162 HWSEQ_PIXEL_RATE_REG_LIST(CRTC), \ 163 HWSEQ_PHYPLL_REG_LIST(CRTC) 164 165 #define HWSEQ_DCN_REG_LIST()\ 166 SR(REFCLK_CNTL), \ 167 SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \ 168 SR(DIO_MEM_PWR_CTRL), \ 169 SR(DCCG_GATE_DISABLE_CNTL), \ 170 SR(DCCG_GATE_DISABLE_CNTL2), \ 171 SR(DCFCLK_CNTL),\ 172 SR(DCFCLK_CNTL), \ 173 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL) 174 175 176 #define MMHUB_DCN_REG_LIST()\ 177 /* todo: get these from GVM instead of reading registers ourselves */\ 178 MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32),\ 179 MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32),\ 180 MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32),\ 181 MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32),\ 182 MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32),\ 183 MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32),\ 184 MMHUB_SR(VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32),\ 185 MMHUB_SR(VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32),\ 186 MMHUB_SR(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB),\ 187 MMHUB_SR(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB),\ 188 MMHUB_SR(MC_VM_SYSTEM_APERTURE_LOW_ADDR),\ 189 MMHUB_SR(MC_VM_SYSTEM_APERTURE_HIGH_ADDR) 190 191 192 #define HWSEQ_DCN1_REG_LIST()\ 193 HWSEQ_DCN_REG_LIST(), \ 194 MMHUB_DCN_REG_LIST(), \ 195 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 0), \ 196 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 1), \ 197 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 2), \ 198 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 3), \ 199 SR(DCHUBBUB_SDPIF_FB_BASE),\ 200 SR(DCHUBBUB_SDPIF_FB_OFFSET),\ 201 SR(DCHUBBUB_SDPIF_AGP_BASE),\ 202 SR(DCHUBBUB_SDPIF_AGP_BOT),\ 203 SR(DCHUBBUB_SDPIF_AGP_TOP),\ 204 SR(DOMAIN0_PG_CONFIG), \ 205 SR(DOMAIN1_PG_CONFIG), \ 206 SR(DOMAIN2_PG_CONFIG), \ 207 SR(DOMAIN3_PG_CONFIG), \ 208 SR(DOMAIN4_PG_CONFIG), \ 209 SR(DOMAIN5_PG_CONFIG), \ 210 SR(DOMAIN6_PG_CONFIG), \ 211 SR(DOMAIN7_PG_CONFIG), \ 212 SR(DOMAIN0_PG_STATUS), \ 213 SR(DOMAIN1_PG_STATUS), \ 214 SR(DOMAIN2_PG_STATUS), \ 215 SR(DOMAIN3_PG_STATUS), \ 216 SR(DOMAIN4_PG_STATUS), \ 217 SR(DOMAIN5_PG_STATUS), \ 218 SR(DOMAIN6_PG_STATUS), \ 219 SR(DOMAIN7_PG_STATUS), \ 220 SR(D1VGA_CONTROL), \ 221 SR(D2VGA_CONTROL), \ 222 SR(D3VGA_CONTROL), \ 223 SR(D4VGA_CONTROL), \ 224 SR(VGA_TEST_CONTROL), \ 225 SR(DC_IP_REQUEST_CNTL) 226 227 #if defined(CONFIG_DRM_AMD_DC_DCN3_0) 228 #define HWSEQ_DCN30_REG_LIST()\ 229 HWSEQ_DCN2_REG_LIST(),\ 230 HWSEQ_DCN_REG_LIST(), \ 231 HWSEQ_PIXEL_RATE_REG_LIST_3(OTG), \ 232 HWSEQ_PHYPLL_REG_LIST_3(OTG), \ 233 SR(MICROSECOND_TIME_BASE_DIV), \ 234 SR(MILLISECOND_TIME_BASE_DIV), \ 235 SR(DISPCLK_FREQ_CHANGE_CNTL), \ 236 SR(RBBMIF_TIMEOUT_DIS), \ 237 SR(RBBMIF_TIMEOUT_DIS_2), \ 238 SR(DCHUBBUB_CRC_CTRL), \ 239 SR(DPP_TOP0_DPP_CRC_CTRL), \ 240 SR(DPP_TOP0_DPP_CRC_VAL_B_A), \ 241 SR(DPP_TOP0_DPP_CRC_VAL_R_G), \ 242 SR(MPC_CRC_CTRL), \ 243 SR(MPC_CRC_RESULT_GB), \ 244 SR(MPC_CRC_RESULT_C), \ 245 SR(MPC_CRC_RESULT_AR), \ 246 SR(AZALIA_AUDIO_DTO), \ 247 SR(AZALIA_CONTROLLER_CLOCK_GATING) 248 #endif 249 #define HWSEQ_DCN2_REG_LIST()\ 250 HWSEQ_DCN_REG_LIST(), \ 251 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 0), \ 252 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 1), \ 253 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 2), \ 254 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 3), \ 255 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 4), \ 256 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 5), \ 257 SR(MICROSECOND_TIME_BASE_DIV), \ 258 SR(MILLISECOND_TIME_BASE_DIV), \ 259 SR(DISPCLK_FREQ_CHANGE_CNTL), \ 260 SR(RBBMIF_TIMEOUT_DIS), \ 261 SR(RBBMIF_TIMEOUT_DIS_2), \ 262 SR(DCHUBBUB_CRC_CTRL), \ 263 SR(DPP_TOP0_DPP_CRC_CTRL), \ 264 SR(DPP_TOP0_DPP_CRC_VAL_B_A), \ 265 SR(DPP_TOP0_DPP_CRC_VAL_R_G), \ 266 SR(MPC_CRC_CTRL), \ 267 SR(MPC_CRC_RESULT_GB), \ 268 SR(MPC_CRC_RESULT_C), \ 269 SR(MPC_CRC_RESULT_AR), \ 270 SR(DOMAIN0_PG_CONFIG), \ 271 SR(DOMAIN1_PG_CONFIG), \ 272 SR(DOMAIN2_PG_CONFIG), \ 273 SR(DOMAIN3_PG_CONFIG), \ 274 SR(DOMAIN4_PG_CONFIG), \ 275 SR(DOMAIN5_PG_CONFIG), \ 276 SR(DOMAIN6_PG_CONFIG), \ 277 SR(DOMAIN7_PG_CONFIG), \ 278 SR(DOMAIN8_PG_CONFIG), \ 279 SR(DOMAIN9_PG_CONFIG), \ 280 /* SR(DOMAIN10_PG_CONFIG), Navi1x HUBP5 not powergate-able*/\ 281 /* SR(DOMAIN11_PG_CONFIG), Navi1x DPP5 is not powergate-able */\ 282 SR(DOMAIN16_PG_CONFIG), \ 283 SR(DOMAIN17_PG_CONFIG), \ 284 SR(DOMAIN18_PG_CONFIG), \ 285 SR(DOMAIN19_PG_CONFIG), \ 286 SR(DOMAIN20_PG_CONFIG), \ 287 SR(DOMAIN21_PG_CONFIG), \ 288 SR(DOMAIN0_PG_STATUS), \ 289 SR(DOMAIN1_PG_STATUS), \ 290 SR(DOMAIN2_PG_STATUS), \ 291 SR(DOMAIN3_PG_STATUS), \ 292 SR(DOMAIN4_PG_STATUS), \ 293 SR(DOMAIN5_PG_STATUS), \ 294 SR(DOMAIN6_PG_STATUS), \ 295 SR(DOMAIN7_PG_STATUS), \ 296 SR(DOMAIN8_PG_STATUS), \ 297 SR(DOMAIN9_PG_STATUS), \ 298 SR(DOMAIN10_PG_STATUS), \ 299 SR(DOMAIN11_PG_STATUS), \ 300 SR(DOMAIN16_PG_STATUS), \ 301 SR(DOMAIN17_PG_STATUS), \ 302 SR(DOMAIN18_PG_STATUS), \ 303 SR(DOMAIN19_PG_STATUS), \ 304 SR(DOMAIN20_PG_STATUS), \ 305 SR(DOMAIN21_PG_STATUS), \ 306 SR(D1VGA_CONTROL), \ 307 SR(D2VGA_CONTROL), \ 308 SR(D3VGA_CONTROL), \ 309 SR(D4VGA_CONTROL), \ 310 SR(D5VGA_CONTROL), \ 311 SR(D6VGA_CONTROL), \ 312 SR(DC_IP_REQUEST_CNTL) 313 314 #define HWSEQ_DCN21_REG_LIST()\ 315 HWSEQ_DCN_REG_LIST(), \ 316 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 0), \ 317 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 1), \ 318 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 2), \ 319 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 3), \ 320 MMHUB_DCN_REG_LIST(), \ 321 SR(MICROSECOND_TIME_BASE_DIV), \ 322 SR(MILLISECOND_TIME_BASE_DIV), \ 323 SR(DISPCLK_FREQ_CHANGE_CNTL), \ 324 SR(RBBMIF_TIMEOUT_DIS), \ 325 SR(RBBMIF_TIMEOUT_DIS_2), \ 326 SR(DCHUBBUB_CRC_CTRL), \ 327 SR(DPP_TOP0_DPP_CRC_CTRL), \ 328 SR(DPP_TOP0_DPP_CRC_VAL_B_A), \ 329 SR(DPP_TOP0_DPP_CRC_VAL_R_G), \ 330 SR(MPC_CRC_CTRL), \ 331 SR(MPC_CRC_RESULT_GB), \ 332 SR(MPC_CRC_RESULT_C), \ 333 SR(MPC_CRC_RESULT_AR), \ 334 SR(DOMAIN0_PG_CONFIG), \ 335 SR(DOMAIN1_PG_CONFIG), \ 336 SR(DOMAIN2_PG_CONFIG), \ 337 SR(DOMAIN3_PG_CONFIG), \ 338 SR(DOMAIN4_PG_CONFIG), \ 339 SR(DOMAIN5_PG_CONFIG), \ 340 SR(DOMAIN6_PG_CONFIG), \ 341 SR(DOMAIN7_PG_CONFIG), \ 342 SR(DOMAIN16_PG_CONFIG), \ 343 SR(DOMAIN17_PG_CONFIG), \ 344 SR(DOMAIN18_PG_CONFIG), \ 345 SR(DOMAIN0_PG_STATUS), \ 346 SR(DOMAIN1_PG_STATUS), \ 347 SR(DOMAIN2_PG_STATUS), \ 348 SR(DOMAIN3_PG_STATUS), \ 349 SR(DOMAIN4_PG_STATUS), \ 350 SR(DOMAIN5_PG_STATUS), \ 351 SR(DOMAIN6_PG_STATUS), \ 352 SR(DOMAIN7_PG_STATUS), \ 353 SR(DOMAIN16_PG_STATUS), \ 354 SR(DOMAIN17_PG_STATUS), \ 355 SR(DOMAIN18_PG_STATUS), \ 356 SR(D1VGA_CONTROL), \ 357 SR(D2VGA_CONTROL), \ 358 SR(D3VGA_CONTROL), \ 359 SR(D4VGA_CONTROL), \ 360 SR(D5VGA_CONTROL), \ 361 SR(D6VGA_CONTROL), \ 362 SR(DC_IP_REQUEST_CNTL) 363 364 struct dce_hwseq_registers { 365 uint32_t DCFE_CLOCK_CONTROL[6]; 366 uint32_t DCFEV_CLOCK_CONTROL; 367 uint32_t DC_MEM_GLOBAL_PWR_REQ_CNTL; 368 uint32_t BLND_V_UPDATE_LOCK[6]; 369 uint32_t BLND_CONTROL[6]; 370 uint32_t BLNDV_CONTROL; 371 uint32_t CRTC_H_BLANK_START_END[6]; 372 uint32_t PIXEL_RATE_CNTL[6]; 373 uint32_t PHYPLL_PIXEL_RATE_CNTL[6]; 374 /*DCHUB*/ 375 uint32_t DCHUB_FB_LOCATION; 376 uint32_t DCHUB_AGP_BASE; 377 uint32_t DCHUB_AGP_BOT; 378 uint32_t DCHUB_AGP_TOP; 379 380 uint32_t REFCLK_CNTL; 381 382 uint32_t DCHUBBUB_GLOBAL_TIMER_CNTL; 383 uint32_t DCHUBBUB_SDPIF_FB_BASE; 384 uint32_t DCHUBBUB_SDPIF_FB_OFFSET; 385 uint32_t DCHUBBUB_SDPIF_AGP_BASE; 386 uint32_t DCHUBBUB_SDPIF_AGP_BOT; 387 uint32_t DCHUBBUB_SDPIF_AGP_TOP; 388 uint32_t DC_IP_REQUEST_CNTL; 389 uint32_t DOMAIN0_PG_CONFIG; 390 uint32_t DOMAIN1_PG_CONFIG; 391 uint32_t DOMAIN2_PG_CONFIG; 392 uint32_t DOMAIN3_PG_CONFIG; 393 uint32_t DOMAIN4_PG_CONFIG; 394 uint32_t DOMAIN5_PG_CONFIG; 395 uint32_t DOMAIN6_PG_CONFIG; 396 uint32_t DOMAIN7_PG_CONFIG; 397 uint32_t DOMAIN8_PG_CONFIG; 398 uint32_t DOMAIN9_PG_CONFIG; 399 uint32_t DOMAIN10_PG_CONFIG; 400 uint32_t DOMAIN11_PG_CONFIG; 401 uint32_t DOMAIN16_PG_CONFIG; 402 uint32_t DOMAIN17_PG_CONFIG; 403 uint32_t DOMAIN18_PG_CONFIG; 404 uint32_t DOMAIN19_PG_CONFIG; 405 uint32_t DOMAIN20_PG_CONFIG; 406 uint32_t DOMAIN21_PG_CONFIG; 407 uint32_t DOMAIN0_PG_STATUS; 408 uint32_t DOMAIN1_PG_STATUS; 409 uint32_t DOMAIN2_PG_STATUS; 410 uint32_t DOMAIN3_PG_STATUS; 411 uint32_t DOMAIN4_PG_STATUS; 412 uint32_t DOMAIN5_PG_STATUS; 413 uint32_t DOMAIN6_PG_STATUS; 414 uint32_t DOMAIN7_PG_STATUS; 415 uint32_t DOMAIN8_PG_STATUS; 416 uint32_t DOMAIN9_PG_STATUS; 417 uint32_t DOMAIN10_PG_STATUS; 418 uint32_t DOMAIN11_PG_STATUS; 419 uint32_t DOMAIN16_PG_STATUS; 420 uint32_t DOMAIN17_PG_STATUS; 421 uint32_t DOMAIN18_PG_STATUS; 422 uint32_t DOMAIN19_PG_STATUS; 423 uint32_t DOMAIN20_PG_STATUS; 424 uint32_t DOMAIN21_PG_STATUS; 425 uint32_t DIO_MEM_PWR_CTRL; 426 uint32_t DCCG_GATE_DISABLE_CNTL; 427 uint32_t DCCG_GATE_DISABLE_CNTL2; 428 uint32_t DCFCLK_CNTL; 429 uint32_t MICROSECOND_TIME_BASE_DIV; 430 uint32_t MILLISECOND_TIME_BASE_DIV; 431 uint32_t DISPCLK_FREQ_CHANGE_CNTL; 432 uint32_t RBBMIF_TIMEOUT_DIS; 433 uint32_t RBBMIF_TIMEOUT_DIS_2; 434 uint32_t DCHUBBUB_CRC_CTRL; 435 uint32_t DPP_TOP0_DPP_CRC_CTRL; 436 uint32_t DPP_TOP0_DPP_CRC_VAL_R_G; 437 uint32_t DPP_TOP0_DPP_CRC_VAL_B_A; 438 uint32_t MPC_CRC_CTRL; 439 uint32_t MPC_CRC_RESULT_GB; 440 uint32_t MPC_CRC_RESULT_C; 441 uint32_t MPC_CRC_RESULT_AR; 442 uint32_t D1VGA_CONTROL; 443 uint32_t D2VGA_CONTROL; 444 uint32_t D3VGA_CONTROL; 445 uint32_t D4VGA_CONTROL; 446 uint32_t D5VGA_CONTROL; 447 uint32_t D6VGA_CONTROL; 448 uint32_t VGA_TEST_CONTROL; 449 /* MMHUB registers. read only. temporary hack */ 450 uint32_t VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32; 451 uint32_t VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32; 452 uint32_t VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32; 453 uint32_t VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32; 454 uint32_t VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32; 455 uint32_t VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32; 456 uint32_t VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32; 457 uint32_t VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32; 458 uint32_t MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB; 459 uint32_t MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB; 460 uint32_t MC_VM_SYSTEM_APERTURE_LOW_ADDR; 461 uint32_t MC_VM_SYSTEM_APERTURE_HIGH_ADDR; 462 uint32_t MC_VM_XGMI_LFB_CNTL; 463 uint32_t AZALIA_AUDIO_DTO; 464 uint32_t AZALIA_CONTROLLER_CLOCK_GATING; 465 }; 466 /* set field name */ 467 #define HWS_SF(blk_name, reg_name, field_name, post_fix)\ 468 .field_name = blk_name ## reg_name ## __ ## field_name ## post_fix 469 470 #define HWS_SF1(blk_name, reg_name, field_name, post_fix)\ 471 .field_name = blk_name ## reg_name ## __ ## blk_name ## field_name ## post_fix 472 473 474 #define HWSEQ_DCEF_MASK_SH_LIST(mask_sh, blk)\ 475 HWS_SF(blk, CLOCK_CONTROL, DCFE_CLOCK_ENABLE, mask_sh),\ 476 SF(DC_MEM_GLOBAL_PWR_REQ_CNTL, DC_MEM_GLOBAL_PWR_REQ_DIS, mask_sh) 477 478 #define HWSEQ_BLND_MASK_SH_LIST(mask_sh, blk)\ 479 HWS_SF(blk, V_UPDATE_LOCK, BLND_DCP_GRPH_V_UPDATE_LOCK, mask_sh),\ 480 HWS_SF(blk, V_UPDATE_LOCK, BLND_SCL_V_UPDATE_LOCK, mask_sh),\ 481 HWS_SF(blk, V_UPDATE_LOCK, BLND_DCP_GRPH_SURF_V_UPDATE_LOCK, mask_sh),\ 482 HWS_SF(blk, V_UPDATE_LOCK, BLND_BLND_V_UPDATE_LOCK, mask_sh),\ 483 HWS_SF(blk, V_UPDATE_LOCK, BLND_V_UPDATE_LOCK_MODE, mask_sh),\ 484 HWS_SF(blk, CONTROL, BLND_FEEDTHROUGH_EN, mask_sh),\ 485 HWS_SF(blk, CONTROL, BLND_ALPHA_MODE, mask_sh),\ 486 HWS_SF(blk, CONTROL, BLND_MODE, mask_sh),\ 487 HWS_SF(blk, CONTROL, BLND_MULTIPLIED_MODE, mask_sh) 488 489 #define HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, blk)\ 490 HWS_SF1(blk, PIXEL_RATE_CNTL, PIXEL_RATE_SOURCE, mask_sh),\ 491 HWS_SF(blk, PIXEL_RATE_CNTL, DP_DTO0_ENABLE, mask_sh) 492 493 #define HWSEQ_PHYPLL_MASK_SH_LIST(mask_sh, blk)\ 494 HWS_SF1(blk, PHYPLL_PIXEL_RATE_CNTL, PHYPLL_PIXEL_RATE_SOURCE, mask_sh),\ 495 HWS_SF1(blk, PHYPLL_PIXEL_RATE_CNTL, PIXEL_RATE_PLL_SOURCE, mask_sh) 496 497 #if defined(CONFIG_DRM_AMD_DC_SI) 498 #define HWSEQ_DCE6_MASK_SH_LIST(mask_sh)\ 499 .DCFE_CLOCK_ENABLE = CRTC_DCFE_CLOCK_CONTROL__CRTC_DCFE_CLOCK_ENABLE ## mask_sh, \ 500 HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_) 501 #endif 502 503 #define HWSEQ_DCE8_MASK_SH_LIST(mask_sh)\ 504 .DCFE_CLOCK_ENABLE = CRTC_DCFE_CLOCK_CONTROL__CRTC_DCFE_CLOCK_ENABLE ## mask_sh, \ 505 HWS_SF(BLND_, V_UPDATE_LOCK, BLND_DCP_GRPH_V_UPDATE_LOCK, mask_sh),\ 506 HWS_SF(BLND_, V_UPDATE_LOCK, BLND_SCL_V_UPDATE_LOCK, mask_sh),\ 507 HWS_SF(BLND_, V_UPDATE_LOCK, BLND_DCP_GRPH_SURF_V_UPDATE_LOCK, mask_sh),\ 508 HWS_SF(BLND_, CONTROL, BLND_MODE, mask_sh),\ 509 HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_) 510 511 #define HWSEQ_DCE10_MASK_SH_LIST(mask_sh)\ 512 HWSEQ_DCEF_MASK_SH_LIST(mask_sh, DCFE_),\ 513 HWSEQ_BLND_MASK_SH_LIST(mask_sh, BLND_),\ 514 HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_) 515 516 #define HWSEQ_DCE11_MASK_SH_LIST(mask_sh)\ 517 HWSEQ_DCE10_MASK_SH_LIST(mask_sh),\ 518 SF(DCFEV_CLOCK_CONTROL, DCFEV_CLOCK_ENABLE, mask_sh),\ 519 HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_) 520 521 #define HWSEQ_DCE112_MASK_SH_LIST(mask_sh)\ 522 HWSEQ_DCE10_MASK_SH_LIST(mask_sh),\ 523 HWSEQ_PHYPLL_MASK_SH_LIST(mask_sh, CRTC0_) 524 525 #define HWSEQ_GFX9_DCHUB_MASK_SH_LIST(mask_sh)\ 526 SF(DCHUB_FB_LOCATION, FB_TOP, mask_sh),\ 527 SF(DCHUB_FB_LOCATION, FB_BASE, mask_sh),\ 528 SF(DCHUB_AGP_BASE, AGP_BASE, mask_sh),\ 529 SF(DCHUB_AGP_BOT, AGP_BOT, mask_sh),\ 530 SF(DCHUB_AGP_TOP, AGP_TOP, mask_sh) 531 532 #define HWSEQ_DCE12_MASK_SH_LIST(mask_sh)\ 533 HWSEQ_DCEF_MASK_SH_LIST(mask_sh, DCFE0_DCFE_),\ 534 HWSEQ_BLND_MASK_SH_LIST(mask_sh, BLND0_BLND_),\ 535 HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_),\ 536 HWSEQ_PHYPLL_MASK_SH_LIST(mask_sh, CRTC0_),\ 537 HWSEQ_GFX9_DCHUB_MASK_SH_LIST(mask_sh) 538 539 #define HWSEQ_VG20_MASK_SH_LIST(mask_sh)\ 540 HWSEQ_DCE12_MASK_SH_LIST(mask_sh),\ 541 HWS_SF(, MC_VM_XGMI_LFB_CNTL, PF_LFB_REGION, mask_sh),\ 542 HWS_SF(, MC_VM_XGMI_LFB_CNTL, PF_MAX_REGION, mask_sh) 543 544 #define HWSEQ_DCN_MASK_SH_LIST(mask_sh)\ 545 HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, OTG0_),\ 546 HWS_SF1(OTG0_, PHYPLL_PIXEL_RATE_CNTL, PHYPLL_PIXEL_RATE_SOURCE, mask_sh), \ 547 HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, mask_sh), \ 548 HWS_SF(, DCFCLK_CNTL, DCFCLK_GATE_DIS, mask_sh), \ 549 HWS_SF(, DC_MEM_GLOBAL_PWR_REQ_CNTL, DC_MEM_GLOBAL_PWR_REQ_DIS, mask_sh) 550 551 #define HWSEQ_DCN1_MASK_SH_LIST(mask_sh)\ 552 HWSEQ_DCN_MASK_SH_LIST(mask_sh), \ 553 HWS_SF1(OTG0_, PHYPLL_PIXEL_RATE_CNTL, PIXEL_RATE_PLL_SOURCE, mask_sh), \ 554 HWS_SF(, DCHUBBUB_SDPIF_FB_BASE, SDPIF_FB_BASE, mask_sh), \ 555 HWS_SF(, DCHUBBUB_SDPIF_FB_OFFSET, SDPIF_FB_OFFSET, mask_sh), \ 556 HWS_SF(, DCHUBBUB_SDPIF_AGP_BASE, SDPIF_AGP_BASE, mask_sh), \ 557 HWS_SF(, DCHUBBUB_SDPIF_AGP_BOT, SDPIF_AGP_BOT, mask_sh), \ 558 HWS_SF(, DCHUBBUB_SDPIF_AGP_TOP, SDPIF_AGP_TOP, mask_sh), \ 559 /* todo: get these from GVM instead of reading registers ourselves */\ 560 HWS_SF(, VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, PAGE_DIRECTORY_ENTRY_HI32, mask_sh),\ 561 HWS_SF(, VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, PAGE_DIRECTORY_ENTRY_LO32, mask_sh),\ 562 HWS_SF(, VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, LOGICAL_PAGE_NUMBER_HI4, mask_sh),\ 563 HWS_SF(, VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, LOGICAL_PAGE_NUMBER_LO32, mask_sh),\ 564 HWS_SF(, VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32, PHYSICAL_PAGE_ADDR_HI4, mask_sh),\ 565 HWS_SF(, VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32, PHYSICAL_PAGE_ADDR_LO32, mask_sh),\ 566 HWS_SF(, MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, PHYSICAL_PAGE_NUMBER_MSB, mask_sh),\ 567 HWS_SF(, MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, PHYSICAL_PAGE_NUMBER_LSB, mask_sh),\ 568 HWS_SF(, MC_VM_SYSTEM_APERTURE_LOW_ADDR, LOGICAL_ADDR, mask_sh),\ 569 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, mask_sh), \ 570 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_GATE, mask_sh), \ 571 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN1_POWER_FORCEON, mask_sh), \ 572 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN1_POWER_GATE, mask_sh), \ 573 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN2_POWER_FORCEON, mask_sh), \ 574 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN2_POWER_GATE, mask_sh), \ 575 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN3_POWER_FORCEON, mask_sh), \ 576 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN3_POWER_GATE, mask_sh), \ 577 HWS_SF(, DOMAIN4_PG_CONFIG, DOMAIN4_POWER_FORCEON, mask_sh), \ 578 HWS_SF(, DOMAIN4_PG_CONFIG, DOMAIN4_POWER_GATE, mask_sh), \ 579 HWS_SF(, DOMAIN5_PG_CONFIG, DOMAIN5_POWER_FORCEON, mask_sh), \ 580 HWS_SF(, DOMAIN5_PG_CONFIG, DOMAIN5_POWER_GATE, mask_sh), \ 581 HWS_SF(, DOMAIN6_PG_CONFIG, DOMAIN6_POWER_FORCEON, mask_sh), \ 582 HWS_SF(, DOMAIN6_PG_CONFIG, DOMAIN6_POWER_GATE, mask_sh), \ 583 HWS_SF(, DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, mask_sh), \ 584 HWS_SF(, DOMAIN7_PG_CONFIG, DOMAIN7_POWER_GATE, mask_sh), \ 585 HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN0_PGFSM_PWR_STATUS, mask_sh), \ 586 HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN1_PGFSM_PWR_STATUS, mask_sh), \ 587 HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN2_PGFSM_PWR_STATUS, mask_sh), \ 588 HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN3_PGFSM_PWR_STATUS, mask_sh), \ 589 HWS_SF(, DOMAIN4_PG_STATUS, DOMAIN4_PGFSM_PWR_STATUS, mask_sh), \ 590 HWS_SF(, DOMAIN5_PG_STATUS, DOMAIN5_PGFSM_PWR_STATUS, mask_sh), \ 591 HWS_SF(, DOMAIN6_PG_STATUS, DOMAIN6_PGFSM_PWR_STATUS, mask_sh), \ 592 HWS_SF(, DOMAIN7_PG_STATUS, DOMAIN7_PGFSM_PWR_STATUS, mask_sh), \ 593 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \ 594 HWS_SF(, D1VGA_CONTROL, D1VGA_MODE_ENABLE, mask_sh),\ 595 HWS_SF(, D2VGA_CONTROL, D2VGA_MODE_ENABLE, mask_sh),\ 596 HWS_SF(, D3VGA_CONTROL, D3VGA_MODE_ENABLE, mask_sh),\ 597 HWS_SF(, D4VGA_CONTROL, D4VGA_MODE_ENABLE, mask_sh),\ 598 HWS_SF(, VGA_TEST_CONTROL, VGA_TEST_ENABLE, mask_sh),\ 599 HWS_SF(, VGA_TEST_CONTROL, VGA_TEST_RENDER_START, mask_sh) 600 601 #if defined(CONFIG_DRM_AMD_DC_DCN3_0) 602 #define HWSEQ_DCN30_MASK_SH_LIST(mask_sh)\ 603 HWSEQ_DCN2_MASK_SH_LIST(mask_sh), \ 604 HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh) 605 #endif 606 607 #define HWSEQ_DCN2_MASK_SH_LIST(mask_sh)\ 608 HWSEQ_DCN_MASK_SH_LIST(mask_sh), \ 609 HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \ 610 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, mask_sh), \ 611 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_GATE, mask_sh), \ 612 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN1_POWER_FORCEON, mask_sh), \ 613 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN1_POWER_GATE, mask_sh), \ 614 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN2_POWER_FORCEON, mask_sh), \ 615 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN2_POWER_GATE, mask_sh), \ 616 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN3_POWER_FORCEON, mask_sh), \ 617 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN3_POWER_GATE, mask_sh), \ 618 HWS_SF(, DOMAIN4_PG_CONFIG, DOMAIN4_POWER_FORCEON, mask_sh), \ 619 HWS_SF(, DOMAIN4_PG_CONFIG, DOMAIN4_POWER_GATE, mask_sh), \ 620 HWS_SF(, DOMAIN5_PG_CONFIG, DOMAIN5_POWER_FORCEON, mask_sh), \ 621 HWS_SF(, DOMAIN5_PG_CONFIG, DOMAIN5_POWER_GATE, mask_sh), \ 622 HWS_SF(, DOMAIN6_PG_CONFIG, DOMAIN6_POWER_FORCEON, mask_sh), \ 623 HWS_SF(, DOMAIN6_PG_CONFIG, DOMAIN6_POWER_GATE, mask_sh), \ 624 HWS_SF(, DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, mask_sh), \ 625 HWS_SF(, DOMAIN7_PG_CONFIG, DOMAIN7_POWER_GATE, mask_sh), \ 626 HWS_SF(, DOMAIN8_PG_CONFIG, DOMAIN8_POWER_FORCEON, mask_sh), \ 627 HWS_SF(, DOMAIN8_PG_CONFIG, DOMAIN8_POWER_GATE, mask_sh), \ 628 HWS_SF(, DOMAIN9_PG_CONFIG, DOMAIN9_POWER_FORCEON, mask_sh), \ 629 HWS_SF(, DOMAIN9_PG_CONFIG, DOMAIN9_POWER_GATE, mask_sh), \ 630 HWS_SF(, DOMAIN10_PG_CONFIG, DOMAIN10_POWER_FORCEON, mask_sh), \ 631 HWS_SF(, DOMAIN10_PG_CONFIG, DOMAIN10_POWER_GATE, mask_sh), \ 632 HWS_SF(, DOMAIN11_PG_CONFIG, DOMAIN11_POWER_FORCEON, mask_sh), \ 633 HWS_SF(, DOMAIN11_PG_CONFIG, DOMAIN11_POWER_GATE, mask_sh), \ 634 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN16_POWER_FORCEON, mask_sh), \ 635 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN16_POWER_GATE, mask_sh), \ 636 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN17_POWER_FORCEON, mask_sh), \ 637 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN17_POWER_GATE, mask_sh), \ 638 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN18_POWER_FORCEON, mask_sh), \ 639 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN18_POWER_GATE, mask_sh), \ 640 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN19_POWER_FORCEON, mask_sh), \ 641 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN19_POWER_GATE, mask_sh), \ 642 HWS_SF(, DOMAIN20_PG_CONFIG, DOMAIN20_POWER_FORCEON, mask_sh), \ 643 HWS_SF(, DOMAIN20_PG_CONFIG, DOMAIN20_POWER_GATE, mask_sh), \ 644 HWS_SF(, DOMAIN21_PG_CONFIG, DOMAIN21_POWER_FORCEON, mask_sh), \ 645 HWS_SF(, DOMAIN21_PG_CONFIG, DOMAIN21_POWER_GATE, mask_sh), \ 646 HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN0_PGFSM_PWR_STATUS, mask_sh), \ 647 HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN1_PGFSM_PWR_STATUS, mask_sh), \ 648 HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN2_PGFSM_PWR_STATUS, mask_sh), \ 649 HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN3_PGFSM_PWR_STATUS, mask_sh), \ 650 HWS_SF(, DOMAIN4_PG_STATUS, DOMAIN4_PGFSM_PWR_STATUS, mask_sh), \ 651 HWS_SF(, DOMAIN5_PG_STATUS, DOMAIN5_PGFSM_PWR_STATUS, mask_sh), \ 652 HWS_SF(, DOMAIN6_PG_STATUS, DOMAIN6_PGFSM_PWR_STATUS, mask_sh), \ 653 HWS_SF(, DOMAIN7_PG_STATUS, DOMAIN7_PGFSM_PWR_STATUS, mask_sh), \ 654 HWS_SF(, DOMAIN8_PG_STATUS, DOMAIN8_PGFSM_PWR_STATUS, mask_sh), \ 655 HWS_SF(, DOMAIN9_PG_STATUS, DOMAIN9_PGFSM_PWR_STATUS, mask_sh), \ 656 HWS_SF(, DOMAIN10_PG_STATUS, DOMAIN10_PGFSM_PWR_STATUS, mask_sh), \ 657 HWS_SF(, DOMAIN11_PG_STATUS, DOMAIN11_PGFSM_PWR_STATUS, mask_sh), \ 658 HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN16_PGFSM_PWR_STATUS, mask_sh), \ 659 HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN17_PGFSM_PWR_STATUS, mask_sh), \ 660 HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN18_PGFSM_PWR_STATUS, mask_sh), \ 661 HWS_SF(, DOMAIN19_PG_STATUS, DOMAIN19_PGFSM_PWR_STATUS, mask_sh), \ 662 HWS_SF(, DOMAIN20_PG_STATUS, DOMAIN20_PGFSM_PWR_STATUS, mask_sh), \ 663 HWS_SF(, DOMAIN21_PG_STATUS, DOMAIN21_PGFSM_PWR_STATUS, mask_sh), \ 664 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh) 665 666 #define HWSEQ_DCN21_MASK_SH_LIST(mask_sh)\ 667 HWSEQ_DCN_MASK_SH_LIST(mask_sh), \ 668 HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \ 669 HWS_SF(, MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, PAGE_DIRECTORY_ENTRY_HI32, mask_sh),\ 670 HWS_SF(, MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, PAGE_DIRECTORY_ENTRY_LO32, mask_sh),\ 671 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, mask_sh), \ 672 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_GATE, mask_sh), \ 673 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN1_POWER_FORCEON, mask_sh), \ 674 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN1_POWER_GATE, mask_sh), \ 675 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN2_POWER_FORCEON, mask_sh), \ 676 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN2_POWER_GATE, mask_sh), \ 677 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN3_POWER_FORCEON, mask_sh), \ 678 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN3_POWER_GATE, mask_sh), \ 679 HWS_SF(, DOMAIN4_PG_CONFIG, DOMAIN4_POWER_FORCEON, mask_sh), \ 680 HWS_SF(, DOMAIN4_PG_CONFIG, DOMAIN4_POWER_GATE, mask_sh), \ 681 HWS_SF(, DOMAIN5_PG_CONFIG, DOMAIN5_POWER_FORCEON, mask_sh), \ 682 HWS_SF(, DOMAIN5_PG_CONFIG, DOMAIN5_POWER_GATE, mask_sh), \ 683 HWS_SF(, DOMAIN6_PG_CONFIG, DOMAIN6_POWER_FORCEON, mask_sh), \ 684 HWS_SF(, DOMAIN6_PG_CONFIG, DOMAIN6_POWER_GATE, mask_sh), \ 685 HWS_SF(, DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, mask_sh), \ 686 HWS_SF(, DOMAIN7_PG_CONFIG, DOMAIN7_POWER_GATE, mask_sh), \ 687 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN16_POWER_FORCEON, mask_sh), \ 688 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN16_POWER_GATE, mask_sh), \ 689 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN17_POWER_FORCEON, mask_sh), \ 690 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN17_POWER_GATE, mask_sh), \ 691 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN18_POWER_FORCEON, mask_sh), \ 692 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN18_POWER_GATE, mask_sh), \ 693 HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN0_PGFSM_PWR_STATUS, mask_sh), \ 694 HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN1_PGFSM_PWR_STATUS, mask_sh), \ 695 HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN2_PGFSM_PWR_STATUS, mask_sh), \ 696 HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN3_PGFSM_PWR_STATUS, mask_sh), \ 697 HWS_SF(, DOMAIN4_PG_STATUS, DOMAIN4_PGFSM_PWR_STATUS, mask_sh), \ 698 HWS_SF(, DOMAIN5_PG_STATUS, DOMAIN5_PGFSM_PWR_STATUS, mask_sh), \ 699 HWS_SF(, DOMAIN6_PG_STATUS, DOMAIN6_PGFSM_PWR_STATUS, mask_sh), \ 700 HWS_SF(, DOMAIN7_PG_STATUS, DOMAIN7_PGFSM_PWR_STATUS, mask_sh), \ 701 HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN16_PGFSM_PWR_STATUS, mask_sh), \ 702 HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN17_PGFSM_PWR_STATUS, mask_sh), \ 703 HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN18_PGFSM_PWR_STATUS, mask_sh), \ 704 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh) 705 706 #define HWSEQ_REG_FIELD_LIST(type) \ 707 type DCFE_CLOCK_ENABLE; \ 708 type DCFEV_CLOCK_ENABLE; \ 709 type DC_MEM_GLOBAL_PWR_REQ_DIS; \ 710 type BLND_DCP_GRPH_V_UPDATE_LOCK; \ 711 type BLND_SCL_V_UPDATE_LOCK; \ 712 type BLND_DCP_GRPH_SURF_V_UPDATE_LOCK; \ 713 type BLND_BLND_V_UPDATE_LOCK; \ 714 type BLND_V_UPDATE_LOCK_MODE; \ 715 type BLND_FEEDTHROUGH_EN; \ 716 type BLND_ALPHA_MODE; \ 717 type BLND_MODE; \ 718 type BLND_MULTIPLIED_MODE; \ 719 type DP_DTO0_ENABLE; \ 720 type PIXEL_RATE_SOURCE; \ 721 type PHYPLL_PIXEL_RATE_SOURCE; \ 722 type PIXEL_RATE_PLL_SOURCE; \ 723 /* todo: get these from GVM instead of reading registers ourselves */\ 724 type PAGE_DIRECTORY_ENTRY_HI32;\ 725 type PAGE_DIRECTORY_ENTRY_LO32;\ 726 type LOGICAL_PAGE_NUMBER_HI4;\ 727 type LOGICAL_PAGE_NUMBER_LO32;\ 728 type PHYSICAL_PAGE_ADDR_HI4;\ 729 type PHYSICAL_PAGE_ADDR_LO32;\ 730 type PHYSICAL_PAGE_NUMBER_MSB;\ 731 type PHYSICAL_PAGE_NUMBER_LSB;\ 732 type LOGICAL_ADDR; \ 733 type PF_LFB_REGION;\ 734 type PF_MAX_REGION;\ 735 type ENABLE_L1_TLB;\ 736 type SYSTEM_ACCESS_MODE; 737 738 #define HWSEQ_DCN_REG_FIELD_LIST(type) \ 739 type HUBP_VTG_SEL; \ 740 type HUBP_CLOCK_ENABLE; \ 741 type DPP_CLOCK_ENABLE; \ 742 type SDPIF_FB_BASE;\ 743 type SDPIF_FB_OFFSET;\ 744 type SDPIF_AGP_BASE;\ 745 type SDPIF_AGP_BOT;\ 746 type SDPIF_AGP_TOP;\ 747 type FB_TOP;\ 748 type FB_BASE;\ 749 type FB_OFFSET;\ 750 type AGP_BASE;\ 751 type AGP_BOT;\ 752 type AGP_TOP;\ 753 type DCHUBBUB_GLOBAL_TIMER_ENABLE; \ 754 type OPP_PIPE_CLOCK_EN;\ 755 type IP_REQUEST_EN; \ 756 type DOMAIN0_POWER_FORCEON; \ 757 type DOMAIN0_POWER_GATE; \ 758 type DOMAIN1_POWER_FORCEON; \ 759 type DOMAIN1_POWER_GATE; \ 760 type DOMAIN2_POWER_FORCEON; \ 761 type DOMAIN2_POWER_GATE; \ 762 type DOMAIN3_POWER_FORCEON; \ 763 type DOMAIN3_POWER_GATE; \ 764 type DOMAIN4_POWER_FORCEON; \ 765 type DOMAIN4_POWER_GATE; \ 766 type DOMAIN5_POWER_FORCEON; \ 767 type DOMAIN5_POWER_GATE; \ 768 type DOMAIN6_POWER_FORCEON; \ 769 type DOMAIN6_POWER_GATE; \ 770 type DOMAIN7_POWER_FORCEON; \ 771 type DOMAIN7_POWER_GATE; \ 772 type DOMAIN8_POWER_FORCEON; \ 773 type DOMAIN8_POWER_GATE; \ 774 type DOMAIN9_POWER_FORCEON; \ 775 type DOMAIN9_POWER_GATE; \ 776 type DOMAIN10_POWER_FORCEON; \ 777 type DOMAIN10_POWER_GATE; \ 778 type DOMAIN11_POWER_FORCEON; \ 779 type DOMAIN11_POWER_GATE; \ 780 type DOMAIN16_POWER_FORCEON; \ 781 type DOMAIN16_POWER_GATE; \ 782 type DOMAIN17_POWER_FORCEON; \ 783 type DOMAIN17_POWER_GATE; \ 784 type DOMAIN18_POWER_FORCEON; \ 785 type DOMAIN18_POWER_GATE; \ 786 type DOMAIN19_POWER_FORCEON; \ 787 type DOMAIN19_POWER_GATE; \ 788 type DOMAIN20_POWER_FORCEON; \ 789 type DOMAIN20_POWER_GATE; \ 790 type DOMAIN21_POWER_FORCEON; \ 791 type DOMAIN21_POWER_GATE; \ 792 type DOMAIN0_PGFSM_PWR_STATUS; \ 793 type DOMAIN1_PGFSM_PWR_STATUS; \ 794 type DOMAIN2_PGFSM_PWR_STATUS; \ 795 type DOMAIN3_PGFSM_PWR_STATUS; \ 796 type DOMAIN4_PGFSM_PWR_STATUS; \ 797 type DOMAIN5_PGFSM_PWR_STATUS; \ 798 type DOMAIN6_PGFSM_PWR_STATUS; \ 799 type DOMAIN7_PGFSM_PWR_STATUS; \ 800 type DOMAIN8_PGFSM_PWR_STATUS; \ 801 type DOMAIN9_PGFSM_PWR_STATUS; \ 802 type DOMAIN10_PGFSM_PWR_STATUS; \ 803 type DOMAIN11_PGFSM_PWR_STATUS; \ 804 type DOMAIN16_PGFSM_PWR_STATUS; \ 805 type DOMAIN17_PGFSM_PWR_STATUS; \ 806 type DOMAIN18_PGFSM_PWR_STATUS; \ 807 type DOMAIN19_PGFSM_PWR_STATUS; \ 808 type DOMAIN20_PGFSM_PWR_STATUS; \ 809 type DOMAIN21_PGFSM_PWR_STATUS; \ 810 type DCFCLK_GATE_DIS; \ 811 type DCHUBBUB_GLOBAL_TIMER_REFDIV; \ 812 type VGA_TEST_ENABLE; \ 813 type VGA_TEST_RENDER_START; \ 814 type D1VGA_MODE_ENABLE; \ 815 type D2VGA_MODE_ENABLE; \ 816 type D3VGA_MODE_ENABLE; \ 817 type D4VGA_MODE_ENABLE; \ 818 type AZALIA_AUDIO_DTO_MODULE; 819 820 struct dce_hwseq_shift { 821 HWSEQ_REG_FIELD_LIST(uint8_t) 822 HWSEQ_DCN_REG_FIELD_LIST(uint8_t) 823 }; 824 825 struct dce_hwseq_mask { 826 HWSEQ_REG_FIELD_LIST(uint32_t) 827 HWSEQ_DCN_REG_FIELD_LIST(uint32_t) 828 }; 829 830 831 enum blnd_mode { 832 BLND_MODE_CURRENT_PIPE = 0,/* Data from current pipe only */ 833 BLND_MODE_OTHER_PIPE, /* Data from other pipe only */ 834 BLND_MODE_BLENDING,/* Alpha blending - blend 'current' and 'other' */ 835 }; 836 837 struct dce_hwseq; 838 struct pipe_ctx; 839 struct clock_source; 840 841 void dce_enable_fe_clock(struct dce_hwseq *hwss, 842 unsigned int inst, bool enable); 843 844 void dce_pipe_control_lock(struct dc *dc, 845 struct pipe_ctx *pipe, 846 bool lock); 847 848 void dce_set_blender_mode(struct dce_hwseq *hws, 849 unsigned int blnd_inst, enum blnd_mode mode); 850 851 #if defined(CONFIG_DRM_AMD_DC_SI) 852 void dce60_pipe_control_lock(struct dc *dc, 853 struct pipe_ctx *pipe, 854 bool lock); 855 #endif 856 857 void dce_clock_gating_power_up(struct dce_hwseq *hws, 858 bool enable); 859 860 void dce_crtc_switch_to_clk_src(struct dce_hwseq *hws, 861 struct clock_source *clk_src, 862 unsigned int tg_inst); 863 864 bool dce_use_lut(enum surface_pixel_format format); 865 #endif /*__DCE_HWSEQ_H__*/ 866
