1 /*
2 * Copyright 2012-15 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include <linux/delay.h>
27 #include <linux/slab.h>
28
29 #include "dm_services.h"
30 #include "core_types.h"
31 #include "dce_aux.h"
32 #include "dce/dce_11_0_sh_mask.h"
33 #include "dm_event_log.h"
34 #include "dm_helpers.h"
35 #include "dmub/inc/dmub_cmd.h"
36
37 #define CTX \
38 aux110->base.ctx
39 #define REG(reg_name)\
40 (aux110->regs->reg_name)
41
42 #define DC_LOGGER \
43 engine->ctx->logger
44
45 #define DC_TRACE_LEVEL_MESSAGE(...) do { } while (0)
46 #define IS_DC_I2CAUX_LOGGING_ENABLED() (false)
47 #define LOG_FLAG_Error_I2cAux LOG_ERROR
48 #define LOG_FLAG_I2cAux_DceAux LOG_I2C_AUX
49
50 #include "reg_helper.h"
51
52 #undef FN
53 #define FN(reg_name, field_name) \
54 aux110->shift->field_name, aux110->mask->field_name
55
56 #define FROM_AUX_ENGINE(ptr) \
57 container_of((ptr), struct aux_engine_dce110, base)
58
59 #define FROM_ENGINE(ptr) \
60 FROM_AUX_ENGINE(container_of((ptr), struct dce_aux, base))
61
62 #define FROM_AUX_ENGINE_ENGINE(ptr) \
63 container_of((ptr), struct dce_aux, base)
64 enum {
65 AUX_INVALID_REPLY_RETRY_COUNTER = 1,
66 AUX_TIMED_OUT_RETRY_COUNTER = 2,
67 AUX_DEFER_RETRY_COUNTER = 6
68 };
69
70 #define TIME_OUT_INCREMENT 1016
71 #define TIME_OUT_MULTIPLIER_8 8
72 #define TIME_OUT_MULTIPLIER_16 16
73 #define TIME_OUT_MULTIPLIER_32 32
74 #define TIME_OUT_MULTIPLIER_64 64
75 #define MAX_TIMEOUT_LENGTH 127
76 #define DEFAULT_AUX_ENGINE_MULT 0
77 #define DEFAULT_AUX_ENGINE_LENGTH 69
78
79 #define DC_TRACE_LEVEL_MESSAGE(...) do { } while (0)
80
release_engine(struct dce_aux * engine)81 static void release_engine(
82 struct dce_aux *engine)
83 {
84 struct aux_engine_dce110 *aux110 = FROM_AUX_ENGINE(engine);
85
86 dal_ddc_close(engine->ddc);
87
88 engine->ddc = NULL;
89
90 REG_UPDATE(AUX_ARB_CONTROL, AUX_SW_DONE_USING_AUX_REG, 1);
91 }
92
93 #define SW_CAN_ACCESS_AUX 1
94 #define DMCU_CAN_ACCESS_AUX 2
95
is_engine_available(struct dce_aux * engine)96 static bool is_engine_available(
97 struct dce_aux *engine)
98 {
99 struct aux_engine_dce110 *aux110 = FROM_AUX_ENGINE(engine);
100
101 uint32_t value = REG_READ(AUX_ARB_CONTROL);
102 uint32_t field = get_reg_field_value(
103 value,
104 AUX_ARB_CONTROL,
105 AUX_REG_RW_CNTL_STATUS);
106
107 return (field != DMCU_CAN_ACCESS_AUX);
108 }
acquire_engine(struct dce_aux * engine)109 static bool acquire_engine(
110 struct dce_aux *engine)
111 {
112 struct aux_engine_dce110 *aux110 = FROM_AUX_ENGINE(engine);
113
114 uint32_t value = REG_READ(AUX_ARB_CONTROL);
115 uint32_t field = get_reg_field_value(
116 value,
117 AUX_ARB_CONTROL,
118 AUX_REG_RW_CNTL_STATUS);
119 if (field == DMCU_CAN_ACCESS_AUX)
120 return false;
121 /* enable AUX before request SW to access AUX */
122 value = REG_READ(AUX_CONTROL);
123 field = get_reg_field_value(value,
124 AUX_CONTROL,
125 AUX_EN);
126
127 if (field == 0) {
128 set_reg_field_value(
129 value,
130 1,
131 AUX_CONTROL,
132 AUX_EN);
133
134 if (REG(AUX_RESET_MASK)) {
135 /*DP_AUX block as part of the enable sequence*/
136 set_reg_field_value(
137 value,
138 1,
139 AUX_CONTROL,
140 AUX_RESET);
141 }
142
143 REG_WRITE(AUX_CONTROL, value);
144
145 if (REG(AUX_RESET_MASK)) {
146 /*poll HW to make sure reset it done*/
147
148 REG_WAIT(AUX_CONTROL, AUX_RESET_DONE, 1,
149 1, 11);
150
151 set_reg_field_value(
152 value,
153 0,
154 AUX_CONTROL,
155 AUX_RESET);
156
157 REG_WRITE(AUX_CONTROL, value);
158
159 REG_WAIT(AUX_CONTROL, AUX_RESET_DONE, 0,
160 1, 11);
161 }
162 } /*if (field)*/
163
164 /* request SW to access AUX */
165 REG_UPDATE(AUX_ARB_CONTROL, AUX_SW_USE_AUX_REG_REQ, 1);
166
167 value = REG_READ(AUX_ARB_CONTROL);
168 field = get_reg_field_value(
169 value,
170 AUX_ARB_CONTROL,
171 AUX_REG_RW_CNTL_STATUS);
172
173 return (field == SW_CAN_ACCESS_AUX);
174 }
175
176 #define COMPOSE_AUX_SW_DATA_16_20(command, address) \
177 ((command) | ((0xF0000 & (address)) >> 16))
178
179 #define COMPOSE_AUX_SW_DATA_8_15(address) \
180 ((0xFF00 & (address)) >> 8)
181
182 #define COMPOSE_AUX_SW_DATA_0_7(address) \
183 (0xFF & (address))
184
submit_channel_request(struct dce_aux * engine,struct aux_request_transaction_data * request)185 static void submit_channel_request(
186 struct dce_aux *engine,
187 struct aux_request_transaction_data *request)
188 {
189 struct aux_engine_dce110 *aux110 = FROM_AUX_ENGINE(engine);
190 uint32_t value;
191 uint32_t length;
192
193 bool is_write =
194 ((request->type == AUX_TRANSACTION_TYPE_DP) &&
195 (request->action == I2CAUX_TRANSACTION_ACTION_DP_WRITE)) ||
196 ((request->type == AUX_TRANSACTION_TYPE_I2C) &&
197 ((request->action == I2CAUX_TRANSACTION_ACTION_I2C_WRITE) ||
198 (request->action == I2CAUX_TRANSACTION_ACTION_I2C_WRITE_MOT)));
199 if (REG(AUXN_IMPCAL)) {
200 /* clear_aux_error */
201 REG_UPDATE_SEQ_2(AUXN_IMPCAL,
202 AUXN_CALOUT_ERROR_AK, 1,
203 AUXN_CALOUT_ERROR_AK, 0);
204
205 REG_UPDATE_SEQ_2(AUXP_IMPCAL,
206 AUXP_CALOUT_ERROR_AK, 1,
207 AUXP_CALOUT_ERROR_AK, 0);
208
209 /* force_default_calibrate */
210 REG_UPDATE_SEQ_2(AUXN_IMPCAL,
211 AUXN_IMPCAL_ENABLE, 1,
212 AUXN_IMPCAL_OVERRIDE_ENABLE, 0);
213
214 /* bug? why AUXN update EN and OVERRIDE_EN 1 by 1 while AUX P toggles OVERRIDE? */
215
216 REG_UPDATE_SEQ_2(AUXP_IMPCAL,
217 AUXP_IMPCAL_OVERRIDE_ENABLE, 1,
218 AUXP_IMPCAL_OVERRIDE_ENABLE, 0);
219 }
220
221 REG_UPDATE(AUX_INTERRUPT_CONTROL, AUX_SW_DONE_ACK, 1);
222
223 REG_WAIT(AUX_SW_STATUS, AUX_SW_DONE, 0,
224 10, aux110->polling_timeout_period/10);
225
226 /* set the delay and the number of bytes to write */
227
228 /* The length include
229 * the 4 bit header and the 20 bit address
230 * (that is 3 byte).
231 * If the requested length is non zero this means
232 * an addition byte specifying the length is required.
233 */
234
235 length = request->length ? 4 : 3;
236 if (is_write)
237 length += request->length;
238
239 REG_UPDATE_2(AUX_SW_CONTROL,
240 AUX_SW_START_DELAY, request->delay,
241 AUX_SW_WR_BYTES, length);
242
243 /* program action and address and payload data (if 'is_write') */
244 value = REG_UPDATE_4(AUX_SW_DATA,
245 AUX_SW_INDEX, 0,
246 AUX_SW_DATA_RW, 0,
247 AUX_SW_AUTOINCREMENT_DISABLE, 1,
248 AUX_SW_DATA, COMPOSE_AUX_SW_DATA_16_20(request->action, request->address));
249
250 value = REG_SET_2(AUX_SW_DATA, value,
251 AUX_SW_AUTOINCREMENT_DISABLE, 0,
252 AUX_SW_DATA, COMPOSE_AUX_SW_DATA_8_15(request->address));
253
254 value = REG_SET(AUX_SW_DATA, value,
255 AUX_SW_DATA, COMPOSE_AUX_SW_DATA_0_7(request->address));
256
257 if (request->length) {
258 value = REG_SET(AUX_SW_DATA, value,
259 AUX_SW_DATA, request->length - 1);
260 }
261
262 if (is_write) {
263 /* Load the HW buffer with the Data to be sent.
264 * This is relevant for write operation.
265 * For read, the data recived data will be
266 * processed in process_channel_reply().
267 */
268 uint32_t i = 0;
269
270 while (i < request->length) {
271 value = REG_SET(AUX_SW_DATA, value,
272 AUX_SW_DATA, request->data[i]);
273
274 ++i;
275 }
276 }
277
278 REG_UPDATE(AUX_SW_CONTROL, AUX_SW_GO, 1);
279 EVENT_LOG_AUX_REQ(engine->ddc->pin_data->en, EVENT_LOG_AUX_ORIGIN_NATIVE,
280 request->action, request->address, request->length, request->data);
281 }
282
read_channel_reply(struct dce_aux * engine,uint32_t size,uint8_t * buffer,uint8_t * reply_result,uint32_t * sw_status)283 static int read_channel_reply(struct dce_aux *engine, uint32_t size,
284 uint8_t *buffer, uint8_t *reply_result,
285 uint32_t *sw_status)
286 {
287 struct aux_engine_dce110 *aux110 = FROM_AUX_ENGINE(engine);
288 uint32_t bytes_replied;
289 uint32_t reply_result_32;
290
291 *sw_status = REG_GET(AUX_SW_STATUS, AUX_SW_REPLY_BYTE_COUNT,
292 &bytes_replied);
293
294 /* In case HPD is LOW, exit AUX transaction */
295 if ((*sw_status & AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK))
296 return -1;
297
298 /* Need at least the status byte */
299 if (!bytes_replied)
300 return -1;
301
302 REG_UPDATE_SEQ_3(AUX_SW_DATA,
303 AUX_SW_INDEX, 0,
304 AUX_SW_AUTOINCREMENT_DISABLE, 1,
305 AUX_SW_DATA_RW, 1);
306
307 REG_GET(AUX_SW_DATA, AUX_SW_DATA, &reply_result_32);
308 reply_result_32 = reply_result_32 >> 4;
309 if (reply_result != NULL)
310 *reply_result = (uint8_t)reply_result_32;
311
312 if (reply_result_32 == 0) { /* ACK */
313 uint32_t i = 0;
314
315 /* First byte was already used to get the command status */
316 --bytes_replied;
317
318 /* Do not overflow buffer */
319 if (bytes_replied > size)
320 return -1;
321
322 while (i < bytes_replied) {
323 uint32_t aux_sw_data_val;
324
325 REG_GET(AUX_SW_DATA, AUX_SW_DATA, &aux_sw_data_val);
326 buffer[i] = aux_sw_data_val;
327 ++i;
328 }
329
330 return i;
331 }
332
333 return 0;
334 }
335
get_channel_status(struct dce_aux * engine,uint8_t * returned_bytes)336 static enum aux_return_code_type get_channel_status(
337 struct dce_aux *engine,
338 uint8_t *returned_bytes)
339 {
340 struct aux_engine_dce110 *aux110 = FROM_AUX_ENGINE(engine);
341
342 uint32_t value;
343
344 if (returned_bytes == NULL) {
345 /*caller pass NULL pointer*/
346 ASSERT_CRITICAL(false);
347 return AUX_RET_ERROR_UNKNOWN;
348 }
349 *returned_bytes = 0;
350
351 /* poll to make sure that SW_DONE is asserted */
352 REG_WAIT(AUX_SW_STATUS, AUX_SW_DONE, 1,
353 10, aux110->polling_timeout_period/10);
354
355 value = REG_READ(AUX_SW_STATUS);
356 /* in case HPD is LOW, exit AUX transaction */
357 if ((value & AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK))
358 return AUX_RET_ERROR_HPD_DISCON;
359
360 /* Note that the following bits are set in 'status.bits'
361 * during CTS 4.2.1.2 (FW 3.3.1):
362 * AUX_SW_RX_MIN_COUNT_VIOL, AUX_SW_RX_INVALID_STOP,
363 * AUX_SW_RX_RECV_NO_DET, AUX_SW_RX_RECV_INVALID_H.
364 *
365 * AUX_SW_RX_MIN_COUNT_VIOL is an internal,
366 * HW debugging bit and should be ignored.
367 */
368 if (value & AUX_SW_STATUS__AUX_SW_DONE_MASK) {
369 if ((value & AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK) ||
370 (value & AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK))
371 return AUX_RET_ERROR_TIMEOUT;
372
373 else if ((value & AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK) ||
374 (value & AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK) ||
375 (value &
376 AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK) ||
377 (value & AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK))
378 return AUX_RET_ERROR_INVALID_REPLY;
379
380 *returned_bytes = get_reg_field_value(value,
381 AUX_SW_STATUS,
382 AUX_SW_REPLY_BYTE_COUNT);
383
384 if (*returned_bytes == 0)
385 return
386 AUX_RET_ERROR_INVALID_REPLY;
387 else {
388 *returned_bytes -= 1;
389 return AUX_RET_SUCCESS;
390 }
391 } else {
392 /*time_elapsed >= aux_engine->timeout_period
393 * AUX_SW_STATUS__AUX_SW_HPD_DISCON = at this point
394 */
395 ASSERT_CRITICAL(false);
396 return AUX_RET_ERROR_TIMEOUT;
397 }
398 }
399
acquire(struct dce_aux * engine,struct ddc * ddc)400 static bool acquire(
401 struct dce_aux *engine,
402 struct ddc *ddc)
403 {
404 enum gpio_result result;
405
406 if ((engine == NULL) || !is_engine_available(engine))
407 return false;
408
409 result = dal_ddc_open(ddc, GPIO_MODE_HARDWARE,
410 GPIO_DDC_CONFIG_TYPE_MODE_AUX);
411
412 if (result != GPIO_RESULT_OK)
413 return false;
414
415 if (!acquire_engine(engine)) {
416 dal_ddc_close(ddc);
417 return false;
418 }
419
420 engine->ddc = ddc;
421
422 return true;
423 }
424
dce110_engine_destroy(struct dce_aux ** engine)425 void dce110_engine_destroy(struct dce_aux **engine)
426 {
427
428 struct aux_engine_dce110 *engine110 = FROM_AUX_ENGINE(*engine);
429
430 kfree(engine110);
431 *engine = NULL;
432
433 }
434
dce_aux_configure_timeout(struct ddc_service * ddc,uint32_t timeout_in_us)435 static uint32_t dce_aux_configure_timeout(struct ddc_service *ddc,
436 uint32_t timeout_in_us)
437 {
438 uint32_t multiplier = 0;
439 uint32_t length = 0;
440 uint32_t prev_length = 0;
441 uint32_t prev_mult = 0;
442 uint32_t prev_timeout_val = 0;
443 struct ddc *ddc_pin = ddc->ddc_pin;
444 struct dce_aux *aux_engine = ddc->ctx->dc->res_pool->engines[ddc_pin->pin_data->en];
445 struct aux_engine_dce110 *aux110 = FROM_AUX_ENGINE(aux_engine);
446
447 /* 1-Update polling timeout period */
448 aux110->polling_timeout_period = timeout_in_us * SW_AUX_TIMEOUT_PERIOD_MULTIPLIER;
449
450 /* 2-Update aux timeout period length and multiplier */
451 if (timeout_in_us == 0) {
452 multiplier = DEFAULT_AUX_ENGINE_MULT;
453 length = DEFAULT_AUX_ENGINE_LENGTH;
454 } else if (timeout_in_us <= TIME_OUT_INCREMENT) {
455 multiplier = 0;
456 length = timeout_in_us/TIME_OUT_MULTIPLIER_8;
457 if (timeout_in_us % TIME_OUT_MULTIPLIER_8 != 0)
458 length++;
459 } else if (timeout_in_us <= 2 * TIME_OUT_INCREMENT) {
460 multiplier = 1;
461 length = timeout_in_us/TIME_OUT_MULTIPLIER_16;
462 if (timeout_in_us % TIME_OUT_MULTIPLIER_16 != 0)
463 length++;
464 } else if (timeout_in_us <= 4 * TIME_OUT_INCREMENT) {
465 multiplier = 2;
466 length = timeout_in_us/TIME_OUT_MULTIPLIER_32;
467 if (timeout_in_us % TIME_OUT_MULTIPLIER_32 != 0)
468 length++;
469 } else if (timeout_in_us > 4 * TIME_OUT_INCREMENT) {
470 multiplier = 3;
471 length = timeout_in_us/TIME_OUT_MULTIPLIER_64;
472 if (timeout_in_us % TIME_OUT_MULTIPLIER_64 != 0)
473 length++;
474 }
475
476 length = (length < MAX_TIMEOUT_LENGTH) ? length : MAX_TIMEOUT_LENGTH;
477
478 REG_GET_2(AUX_DPHY_RX_CONTROL1, AUX_RX_TIMEOUT_LEN, &prev_length, AUX_RX_TIMEOUT_LEN_MUL, &prev_mult);
479
480 switch (prev_mult) {
481 case 0:
482 prev_timeout_val = prev_length * TIME_OUT_MULTIPLIER_8;
483 break;
484 case 1:
485 prev_timeout_val = prev_length * TIME_OUT_MULTIPLIER_16;
486 break;
487 case 2:
488 prev_timeout_val = prev_length * TIME_OUT_MULTIPLIER_32;
489 break;
490 case 3:
491 prev_timeout_val = prev_length * TIME_OUT_MULTIPLIER_64;
492 break;
493 default:
494 prev_timeout_val = DEFAULT_AUX_ENGINE_LENGTH * TIME_OUT_MULTIPLIER_8;
495 break;
496 }
497
498 REG_UPDATE_SEQ_2(AUX_DPHY_RX_CONTROL1, AUX_RX_TIMEOUT_LEN, length, AUX_RX_TIMEOUT_LEN_MUL, multiplier);
499
500 return prev_timeout_val;
501 }
502
503 static struct dce_aux_funcs aux_functions = {
504 .configure_timeout = NULL,
505 .destroy = NULL,
506 };
507
dce110_aux_engine_construct(struct aux_engine_dce110 * aux_engine110,struct dc_context * ctx,uint32_t inst,uint32_t timeout_period,const struct dce110_aux_registers * regs,const struct dce110_aux_registers_mask * mask,const struct dce110_aux_registers_shift * shift,bool is_ext_aux_timeout_configurable)508 struct dce_aux *dce110_aux_engine_construct(struct aux_engine_dce110 *aux_engine110,
509 struct dc_context *ctx,
510 uint32_t inst,
511 uint32_t timeout_period,
512 const struct dce110_aux_registers *regs,
513 const struct dce110_aux_registers_mask *mask,
514 const struct dce110_aux_registers_shift *shift,
515 bool is_ext_aux_timeout_configurable)
516 {
517 aux_engine110->base.ddc = NULL;
518 aux_engine110->base.ctx = ctx;
519 aux_engine110->base.delay = 0;
520 aux_engine110->base.max_defer_write_retry = 0;
521 aux_engine110->base.inst = inst;
522 aux_engine110->polling_timeout_period = timeout_period;
523 aux_engine110->regs = regs;
524
525 aux_engine110->mask = mask;
526 aux_engine110->shift = shift;
527 aux_engine110->base.funcs = &aux_functions;
528 if (is_ext_aux_timeout_configurable)
529 aux_engine110->base.funcs->configure_timeout = &dce_aux_configure_timeout;
530
531 return &aux_engine110->base;
532 }
533
i2caux_action_from_payload(struct aux_payload * payload)534 static enum i2caux_transaction_action i2caux_action_from_payload(struct aux_payload *payload)
535 {
536 if (payload->i2c_over_aux) {
537 if (payload->write) {
538 if (payload->mot)
539 return I2CAUX_TRANSACTION_ACTION_I2C_WRITE_MOT;
540 return I2CAUX_TRANSACTION_ACTION_I2C_WRITE;
541 }
542 if (payload->mot)
543 return I2CAUX_TRANSACTION_ACTION_I2C_READ_MOT;
544 return I2CAUX_TRANSACTION_ACTION_I2C_READ;
545 }
546 if (payload->write)
547 return I2CAUX_TRANSACTION_ACTION_DP_WRITE;
548 return I2CAUX_TRANSACTION_ACTION_DP_READ;
549 }
550
dce_aux_transfer_raw(struct ddc_service * ddc,struct aux_payload * payload,enum aux_return_code_type * operation_result)551 int dce_aux_transfer_raw(struct ddc_service *ddc,
552 struct aux_payload *payload,
553 enum aux_return_code_type *operation_result)
554 {
555 struct ddc *ddc_pin = ddc->ddc_pin;
556 struct dce_aux *aux_engine;
557 struct aux_request_transaction_data aux_req;
558 struct aux_reply_transaction_data aux_rep;
559 uint8_t returned_bytes = 0;
560 int res = -1;
561 uint32_t status;
562
563 memset(&aux_req, 0, sizeof(aux_req));
564 memset(&aux_rep, 0, sizeof(aux_rep));
565
566 aux_engine = ddc->ctx->dc->res_pool->engines[ddc_pin->pin_data->en];
567 if (!acquire(aux_engine, ddc_pin)) {
568 *operation_result = AUX_RET_ERROR_ENGINE_ACQUIRE;
569 return -1;
570 }
571
572 if (payload->i2c_over_aux)
573 aux_req.type = AUX_TRANSACTION_TYPE_I2C;
574 else
575 aux_req.type = AUX_TRANSACTION_TYPE_DP;
576
577 aux_req.action = i2caux_action_from_payload(payload);
578
579 aux_req.address = payload->address;
580 aux_req.delay = 0;
581 aux_req.length = payload->length;
582 aux_req.data = payload->data;
583
584 submit_channel_request(aux_engine, &aux_req);
585 *operation_result = get_channel_status(aux_engine, &returned_bytes);
586
587 if (*operation_result == AUX_RET_SUCCESS) {
588 int __maybe_unused bytes_replied = 0;
589
590 bytes_replied = read_channel_reply(aux_engine, payload->length,
591 payload->data, payload->reply,
592 &status);
593 EVENT_LOG_AUX_REP(aux_engine->ddc->pin_data->en,
594 EVENT_LOG_AUX_ORIGIN_NATIVE, *payload->reply,
595 bytes_replied, payload->data);
596 res = returned_bytes;
597 } else {
598 res = -1;
599 }
600
601 release_engine(aux_engine);
602 return res;
603 }
604
dce_aux_transfer_dmub_raw(struct ddc_service * ddc,struct aux_payload * payload,enum aux_return_code_type * operation_result)605 int dce_aux_transfer_dmub_raw(struct ddc_service *ddc,
606 struct aux_payload *payload,
607 enum aux_return_code_type *operation_result)
608 {
609 struct ddc *ddc_pin = ddc->ddc_pin;
610
611 if (ddc_pin != NULL) {
612 struct dce_aux *aux_engine = ddc->ctx->dc->res_pool->engines[ddc_pin->pin_data->en];
613 /* XXX: Workaround to configure ddc channels for aux transactions */
614 if (!acquire(aux_engine, ddc_pin)) {
615 *operation_result = AUX_RET_ERROR_ENGINE_ACQUIRE;
616 return -1;
617 }
618 release_engine(aux_engine);
619 }
620
621 return dm_helper_dmub_aux_transfer_sync(ddc->ctx, ddc->link, payload, operation_result);
622 }
623
624 #define AUX_MAX_RETRIES 7
625 #define AUX_MIN_DEFER_RETRIES 7
626 #define AUX_MAX_DEFER_TIMEOUT_MS 50
627 #define AUX_MAX_I2C_DEFER_RETRIES 7
628 #define AUX_MAX_INVALID_REPLY_RETRIES 2
629 #define AUX_MAX_TIMEOUT_RETRIES 3
630
dce_aux_log_payload(const char * payload_name,unsigned char * payload,uint32_t length,uint32_t max_length_to_log)631 static void dce_aux_log_payload(const char *payload_name,
632 unsigned char *payload, uint32_t length, uint32_t max_length_to_log)
633 {
634 if (!IS_DC_I2CAUX_LOGGING_ENABLED())
635 return;
636
637 if (payload && length) {
638 char hex_str[128] = {0};
639 char *hex_str_ptr = &hex_str[0];
640 uint32_t hex_str_remaining = sizeof(hex_str);
641 unsigned char *payload_ptr = payload;
642 unsigned char *payload_max_to_log_ptr = payload_ptr + min(max_length_to_log, length);
643 unsigned int count;
644 char *padding = "";
645
646 while (payload_ptr < payload_max_to_log_ptr) {
647 count = snprintf_count(hex_str_ptr, hex_str_remaining, "%s%02X", padding, *payload_ptr);
648 padding = " ";
649 hex_str_remaining -= count;
650 hex_str_ptr += count;
651 payload_ptr++;
652 }
653
654 count = snprintf_count(hex_str_ptr, hex_str_remaining, " ");
655 hex_str_remaining -= count;
656 hex_str_ptr += count;
657
658 payload_ptr = payload;
659 while (payload_ptr < payload_max_to_log_ptr) {
660 count = snprintf_count(hex_str_ptr, hex_str_remaining, "%c",
661 *payload_ptr >= ' ' ? *payload_ptr : '.');
662 hex_str_remaining -= count;
663 hex_str_ptr += count;
664 payload_ptr++;
665 }
666
667 DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_VERBOSE,
668 LOG_FLAG_I2cAux_DceAux,
669 "dce_aux_log_payload: %s: length=%u: data: %s%s",
670 payload_name,
671 length,
672 hex_str,
673 (length > max_length_to_log ? " (...)" : " "));
674 } else {
675 DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_VERBOSE,
676 LOG_FLAG_I2cAux_DceAux,
677 "dce_aux_log_payload: %s: length=%u: data: <empty payload>",
678 payload_name,
679 length);
680 }
681 }
682
dce_aux_transfer_with_retries(struct ddc_service * ddc,struct aux_payload * payload)683 bool dce_aux_transfer_with_retries(struct ddc_service *ddc,
684 struct aux_payload *payload)
685 {
686 int i, ret = 0;
687 uint8_t reply;
688 bool payload_reply = true;
689 enum aux_return_code_type operation_result;
690 bool retry_on_defer = false;
691 struct ddc *ddc_pin = ddc->ddc_pin;
692 struct dce_aux *aux_engine = ddc->ctx->dc->res_pool->engines[ddc_pin->pin_data->en];
693 struct aux_engine_dce110 *aux110 = FROM_AUX_ENGINE(aux_engine);
694 uint32_t defer_time_in_ms = 0;
695
696 int aux_ack_retries = 0,
697 aux_defer_retries = 0,
698 aux_i2c_defer_retries = 0,
699 aux_timeout_retries = 0,
700 aux_invalid_reply_retries = 0;
701
702 if (!payload->reply) {
703 payload_reply = false;
704 payload->reply = &reply;
705 }
706
707 for (i = 0; i < AUX_MAX_RETRIES; i++) {
708 DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_INFORMATION,
709 LOG_FLAG_I2cAux_DceAux,
710 "dce_aux_transfer_with_retries: link_index=%u: START: retry %d of %d: address=0x%04x length=%u write=%d mot=%d",
711 ddc && ddc->link ? ddc->link->link_index : UINT_MAX,
712 i + 1,
713 (int)AUX_MAX_RETRIES,
714 payload->address,
715 payload->length,
716 (unsigned int) payload->write,
717 (unsigned int) payload->mot);
718 if (payload->write)
719 dce_aux_log_payload(" write", payload->data, payload->length, 16);
720 ret = dce_aux_transfer_raw(ddc, payload, &operation_result);
721 DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_INFORMATION,
722 LOG_FLAG_I2cAux_DceAux,
723 "dce_aux_transfer_with_retries: link_index=%u: END: retry %d of %d: address=0x%04x length=%u write=%d mot=%d: ret=%d operation_result=%d payload->reply=%u",
724 ddc && ddc->link ? ddc->link->link_index : UINT_MAX,
725 i + 1,
726 (int)AUX_MAX_RETRIES,
727 payload->address,
728 payload->length,
729 (unsigned int) payload->write,
730 (unsigned int) payload->mot,
731 ret,
732 (int)operation_result,
733 (unsigned int) *payload->reply);
734 if (!payload->write)
735 dce_aux_log_payload(" read", payload->data, ret > 0 ? ret : 0, 16);
736
737 switch (operation_result) {
738 case AUX_RET_SUCCESS:
739 aux_timeout_retries = 0;
740 aux_invalid_reply_retries = 0;
741
742 switch (*payload->reply) {
743 case AUX_TRANSACTION_REPLY_AUX_ACK:
744 DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_INFORMATION,
745 LOG_FLAG_I2cAux_DceAux,
746 "dce_aux_transfer_with_retries: AUX_RET_SUCCESS: AUX_TRANSACTION_REPLY_AUX_ACK");
747 if (!payload->write && payload->length != ret) {
748 if (++aux_ack_retries >= AUX_MAX_RETRIES) {
749 DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_ERROR,
750 LOG_FLAG_Error_I2cAux,
751 "dce_aux_transfer_with_retries: FAILURE: aux_ack_retries=%d >= AUX_MAX_RETRIES=%d",
752 aux_defer_retries,
753 AUX_MAX_RETRIES);
754 goto fail;
755 } else {
756 udelay(300);
757 }
758 } else
759 return true;
760 break;
761
762 case AUX_TRANSACTION_REPLY_AUX_DEFER:
763 DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_INFORMATION,
764 LOG_FLAG_I2cAux_DceAux,
765 "dce_aux_transfer_with_retries: AUX_RET_SUCCESS: AUX_TRANSACTION_REPLY_AUX_DEFER");
766
767 /* polling_timeout_period is in us */
768 defer_time_in_ms += aux110->polling_timeout_period / 1000;
769 ++aux_defer_retries;
770 fallthrough;
771 case AUX_TRANSACTION_REPLY_I2C_OVER_AUX_DEFER:
772 if (*payload->reply == AUX_TRANSACTION_REPLY_I2C_OVER_AUX_DEFER)
773 DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_INFORMATION,
774 LOG_FLAG_I2cAux_DceAux,
775 "dce_aux_transfer_with_retries: AUX_RET_SUCCESS: AUX_TRANSACTION_REPLY_I2C_OVER_AUX_DEFER");
776
777 retry_on_defer = true;
778 fallthrough;
779 case AUX_TRANSACTION_REPLY_I2C_OVER_AUX_NACK:
780 if (*payload->reply == AUX_TRANSACTION_REPLY_I2C_OVER_AUX_NACK)
781 DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_INFORMATION,
782 LOG_FLAG_I2cAux_DceAux,
783 "dce_aux_transfer_with_retries: AUX_RET_SUCCESS: AUX_TRANSACTION_REPLY_I2C_OVER_AUX_NACK");
784
785 if (aux_defer_retries >= AUX_MIN_DEFER_RETRIES
786 && defer_time_in_ms >= AUX_MAX_DEFER_TIMEOUT_MS) {
787 DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_ERROR,
788 LOG_FLAG_Error_I2cAux,
789 "dce_aux_transfer_with_retries: FAILURE: aux_defer_retries=%d >= AUX_MIN_DEFER_RETRIES=%d && defer_time_in_ms=%d >= AUX_MAX_DEFER_TIMEOUT_MS=%d",
790 aux_defer_retries,
791 AUX_MIN_DEFER_RETRIES,
792 defer_time_in_ms,
793 AUX_MAX_DEFER_TIMEOUT_MS);
794 goto fail;
795 } else {
796 if ((*payload->reply == AUX_TRANSACTION_REPLY_AUX_DEFER) ||
797 (*payload->reply == AUX_TRANSACTION_REPLY_I2C_OVER_AUX_DEFER)) {
798 DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_INFORMATION,
799 LOG_FLAG_I2cAux_DceAux,
800 "dce_aux_transfer_with_retries: payload->defer_delay=%u",
801 payload->defer_delay);
802 if (payload->defer_delay > 1) {
803 msleep(payload->defer_delay);
804 defer_time_in_ms += payload->defer_delay;
805 } else if (payload->defer_delay <= 1) {
806 udelay(payload->defer_delay * 1000);
807 defer_time_in_ms += payload->defer_delay;
808 }
809 }
810 }
811 break;
812
813 case AUX_TRANSACTION_REPLY_I2C_DEFER:
814 DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_INFORMATION,
815 LOG_FLAG_I2cAux_DceAux,
816 "dce_aux_transfer_with_retries: AUX_RET_SUCCESS: AUX_TRANSACTION_REPLY_I2C_DEFER");
817
818 aux_defer_retries = 0;
819 if (++aux_i2c_defer_retries >= AUX_MAX_I2C_DEFER_RETRIES) {
820 DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_ERROR,
821 LOG_FLAG_Error_I2cAux,
822 "dce_aux_transfer_with_retries: FAILURE: aux_i2c_defer_retries=%d >= AUX_MAX_I2C_DEFER_RETRIES=%d",
823 aux_i2c_defer_retries,
824 AUX_MAX_I2C_DEFER_RETRIES);
825 goto fail;
826 }
827 break;
828
829 case AUX_TRANSACTION_REPLY_AUX_NACK:
830 DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_INFORMATION,
831 LOG_FLAG_I2cAux_DceAux,
832 "dce_aux_transfer_with_retries: AUX_RET_SUCCESS: AUX_TRANSACTION_REPLY_AUX_NACK");
833 goto fail;
834
835 case AUX_TRANSACTION_REPLY_HPD_DISCON:
836 DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_INFORMATION,
837 LOG_FLAG_I2cAux_DceAux,
838 "dce_aux_transfer_with_retries: AUX_RET_SUCCESS: AUX_TRANSACTION_REPLY_HPD_DISCON");
839 goto fail;
840
841 default:
842 DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_ERROR,
843 LOG_FLAG_Error_I2cAux,
844 "dce_aux_transfer_with_retries: AUX_RET_SUCCESS: FAILURE: AUX_TRANSACTION_REPLY_* unknown, default case.");
845 goto fail;
846 }
847 break;
848
849 case AUX_RET_ERROR_INVALID_REPLY:
850 DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_INFORMATION,
851 LOG_FLAG_I2cAux_DceAux,
852 "dce_aux_transfer_with_retries: AUX_RET_ERROR_INVALID_REPLY");
853 if (++aux_invalid_reply_retries >= AUX_MAX_INVALID_REPLY_RETRIES) {
854 DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_ERROR,
855 LOG_FLAG_Error_I2cAux,
856 "dce_aux_transfer_with_retries: FAILURE: aux_invalid_reply_retries=%d >= AUX_MAX_INVALID_REPLY_RETRIES=%d",
857 aux_invalid_reply_retries,
858 AUX_MAX_INVALID_REPLY_RETRIES);
859 goto fail;
860 } else
861 udelay(400);
862 break;
863
864 case AUX_RET_ERROR_TIMEOUT:
865 DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_INFORMATION,
866 LOG_FLAG_I2cAux_DceAux,
867 "dce_aux_transfer_with_retries: AUX_RET_ERROR_TIMEOUT");
868 // Check whether a DEFER had occurred before the timeout.
869 // If so, treat timeout as a DEFER.
870 if (retry_on_defer) {
871 if (++aux_defer_retries >= AUX_MIN_DEFER_RETRIES) {
872 DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_ERROR,
873 LOG_FLAG_Error_I2cAux,
874 "dce_aux_transfer_with_retries: FAILURE: aux_defer_retries=%d >= AUX_MIN_DEFER_RETRIES=%d",
875 aux_defer_retries,
876 AUX_MIN_DEFER_RETRIES);
877 goto fail;
878 } else if (payload->defer_delay > 0) {
879 DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_INFORMATION,
880 LOG_FLAG_I2cAux_DceAux,
881 "dce_aux_transfer_with_retries: payload->defer_delay=%u",
882 payload->defer_delay);
883 msleep(payload->defer_delay);
884 }
885 } else {
886 if (++aux_timeout_retries >= AUX_MAX_TIMEOUT_RETRIES) {
887 DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_ERROR,
888 LOG_FLAG_Error_I2cAux,
889 "dce_aux_transfer_with_retries: FAILURE: aux_timeout_retries=%d >= AUX_MAX_TIMEOUT_RETRIES=%d",
890 aux_timeout_retries,
891 AUX_MAX_TIMEOUT_RETRIES);
892 goto fail;
893 } else {
894 /*
895 * DP 1.4, 2.8.2: AUX Transaction Response/Reply Timeouts
896 * According to the DP spec there should be 3 retries total
897 * with a 400us wait inbetween each. Hardware already waits
898 * for 550us therefore no wait is required here.
899 */
900 }
901 }
902 break;
903
904 case AUX_RET_ERROR_HPD_DISCON:
905 case AUX_RET_ERROR_ENGINE_ACQUIRE:
906 case AUX_RET_ERROR_UNKNOWN:
907 default:
908 DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_INFORMATION,
909 LOG_FLAG_I2cAux_DceAux,
910 "dce_aux_transfer_with_retries: Failure: operation_result=%d",
911 (int)operation_result);
912 goto fail;
913 }
914 }
915
916 fail:
917 DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_ERROR,
918 LOG_FLAG_Error_I2cAux,
919 "dce_aux_transfer_with_retries: FAILURE");
920 if (!payload_reply)
921 payload->reply = NULL;
922
923 DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_ERROR,
924 WPP_BIT_FLAG_DC_ERROR,
925 "AUX transaction failed. Result: %d",
926 operation_result);
927
928 return false;
929 }
930
