1 /* 2 * Copyright 2012-16 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 27 #ifndef _DCE_ABM_H_ 28 #define _DCE_ABM_H_ 29 30 #include "abm.h" 31 32 #define ABM_COMMON_REG_LIST_DCE_BASE() \ 33 SR(MASTER_COMM_CNTL_REG), \ 34 SR(MASTER_COMM_CMD_REG), \ 35 SR(MASTER_COMM_DATA_REG1) 36 37 #define ABM_DCE110_COMMON_REG_LIST() \ 38 ABM_COMMON_REG_LIST_DCE_BASE(), \ 39 SR(DC_ABM1_HG_SAMPLE_RATE), \ 40 SR(DC_ABM1_LS_SAMPLE_RATE), \ 41 SR(BL1_PWM_BL_UPDATE_SAMPLE_RATE), \ 42 SR(DC_ABM1_HG_MISC_CTRL), \ 43 SR(DC_ABM1_IPCSC_COEFF_SEL), \ 44 SR(BL1_PWM_CURRENT_ABM_LEVEL), \ 45 SR(BL1_PWM_TARGET_ABM_LEVEL), \ 46 SR(BL1_PWM_USER_LEVEL), \ 47 SR(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES), \ 48 SR(DC_ABM1_HGLS_REG_READ_PROGRESS), \ 49 SR(DC_ABM1_ACE_OFFSET_SLOPE_0), \ 50 SR(DC_ABM1_ACE_THRES_12), \ 51 SR(BIOS_SCRATCH_2) 52 53 #define ABM_DCN10_REG_LIST(id)\ 54 ABM_COMMON_REG_LIST_DCE_BASE(), \ 55 SRI(DC_ABM1_HG_SAMPLE_RATE, ABM, id), \ 56 SRI(DC_ABM1_LS_SAMPLE_RATE, ABM, id), \ 57 SRI(BL1_PWM_BL_UPDATE_SAMPLE_RATE, ABM, id), \ 58 SRI(DC_ABM1_HG_MISC_CTRL, ABM, id), \ 59 SRI(DC_ABM1_IPCSC_COEFF_SEL, ABM, id), \ 60 SRI(BL1_PWM_CURRENT_ABM_LEVEL, ABM, id), \ 61 SRI(BL1_PWM_TARGET_ABM_LEVEL, ABM, id), \ 62 SRI(BL1_PWM_USER_LEVEL, ABM, id), \ 63 SRI(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, ABM, id), \ 64 SRI(DC_ABM1_HGLS_REG_READ_PROGRESS, ABM, id), \ 65 SRI(DC_ABM1_ACE_OFFSET_SLOPE_0, ABM, id), \ 66 SRI(DC_ABM1_ACE_THRES_12, ABM, id), \ 67 NBIO_SR(BIOS_SCRATCH_2) 68 69 #define ABM_DCN20_REG_LIST() \ 70 ABM_COMMON_REG_LIST_DCE_BASE(), \ 71 SR(DC_ABM1_HG_SAMPLE_RATE), \ 72 SR(DC_ABM1_LS_SAMPLE_RATE), \ 73 SR(BL1_PWM_BL_UPDATE_SAMPLE_RATE), \ 74 SR(DC_ABM1_HG_MISC_CTRL), \ 75 SR(DC_ABM1_IPCSC_COEFF_SEL), \ 76 SR(BL1_PWM_CURRENT_ABM_LEVEL), \ 77 SR(BL1_PWM_TARGET_ABM_LEVEL), \ 78 SR(BL1_PWM_USER_LEVEL), \ 79 SR(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES), \ 80 SR(DC_ABM1_HGLS_REG_READ_PROGRESS), \ 81 SR(DC_ABM1_ACE_OFFSET_SLOPE_0), \ 82 SR(DC_ABM1_ACE_THRES_12), \ 83 NBIO_SR(BIOS_SCRATCH_2) 84 85 #if defined(CONFIG_DRM_AMD_DC_DCN3_0) 86 #define ABM_DCN30_REG_LIST(id)\ 87 ABM_COMMON_REG_LIST_DCE_BASE(), \ 88 SRI(DC_ABM1_HG_SAMPLE_RATE, ABM, id), \ 89 SRI(DC_ABM1_LS_SAMPLE_RATE, ABM, id), \ 90 SRI(BL1_PWM_BL_UPDATE_SAMPLE_RATE, ABM, id), \ 91 SRI(DC_ABM1_HG_MISC_CTRL, ABM, id), \ 92 SRI(DC_ABM1_IPCSC_COEFF_SEL, ABM, id), \ 93 SRI(BL1_PWM_CURRENT_ABM_LEVEL, ABM, id), \ 94 SRI(BL1_PWM_TARGET_ABM_LEVEL, ABM, id), \ 95 SRI(BL1_PWM_USER_LEVEL, ABM, id), \ 96 SRI(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, ABM, id), \ 97 SRI(DC_ABM1_HGLS_REG_READ_PROGRESS, ABM, id), \ 98 SRI(DC_ABM1_ACE_OFFSET_SLOPE_0, ABM, id), \ 99 SRI(DC_ABM1_ACE_THRES_12, ABM, id), \ 100 NBIO_SR(BIOS_SCRATCH_2) 101 #endif 102 103 #define ABM_SF(reg_name, field_name, post_fix)\ 104 .field_name = reg_name ## __ ## field_name ## post_fix 105 106 #define ABM_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh) \ 107 ABM_SF(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, mask_sh), \ 108 ABM_SF(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, mask_sh), \ 109 ABM_SF(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE1, mask_sh), \ 110 ABM_SF(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE2, mask_sh) 111 112 #define ABM_MASK_SH_LIST_DCE110(mask_sh) \ 113 ABM_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh), \ 114 ABM_SF(DC_ABM1_HG_MISC_CTRL, \ 115 ABM1_HG_NUM_OF_BINS_SEL, mask_sh), \ 116 ABM_SF(DC_ABM1_HG_MISC_CTRL, \ 117 ABM1_HG_VMAX_SEL, mask_sh), \ 118 ABM_SF(DC_ABM1_HG_MISC_CTRL, \ 119 ABM1_HG_BIN_BITWIDTH_SIZE_SEL, mask_sh), \ 120 ABM_SF(DC_ABM1_IPCSC_COEFF_SEL, \ 121 ABM1_IPCSC_COEFF_SEL_R, mask_sh), \ 122 ABM_SF(DC_ABM1_IPCSC_COEFF_SEL, \ 123 ABM1_IPCSC_COEFF_SEL_G, mask_sh), \ 124 ABM_SF(DC_ABM1_IPCSC_COEFF_SEL, \ 125 ABM1_IPCSC_COEFF_SEL_B, mask_sh), \ 126 ABM_SF(BL1_PWM_CURRENT_ABM_LEVEL, \ 127 BL1_PWM_CURRENT_ABM_LEVEL, mask_sh), \ 128 ABM_SF(BL1_PWM_TARGET_ABM_LEVEL, \ 129 BL1_PWM_TARGET_ABM_LEVEL, mask_sh), \ 130 ABM_SF(BL1_PWM_USER_LEVEL, \ 131 BL1_PWM_USER_LEVEL, mask_sh), \ 132 ABM_SF(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, \ 133 ABM1_LS_MIN_PIXEL_VALUE_THRES, mask_sh), \ 134 ABM_SF(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, \ 135 ABM1_LS_MAX_PIXEL_VALUE_THRES, mask_sh), \ 136 ABM_SF(DC_ABM1_HGLS_REG_READ_PROGRESS, \ 137 ABM1_HG_REG_READ_MISSED_FRAME_CLEAR, mask_sh), \ 138 ABM_SF(DC_ABM1_HGLS_REG_READ_PROGRESS, \ 139 ABM1_LS_REG_READ_MISSED_FRAME_CLEAR, mask_sh), \ 140 ABM_SF(DC_ABM1_HGLS_REG_READ_PROGRESS, \ 141 ABM1_BL_REG_READ_MISSED_FRAME_CLEAR, mask_sh) 142 143 #define ABM_MASK_SH_LIST_DCN10(mask_sh) \ 144 ABM_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh), \ 145 ABM_SF(ABM0_DC_ABM1_HG_MISC_CTRL, \ 146 ABM1_HG_NUM_OF_BINS_SEL, mask_sh), \ 147 ABM_SF(ABM0_DC_ABM1_HG_MISC_CTRL, \ 148 ABM1_HG_VMAX_SEL, mask_sh), \ 149 ABM_SF(ABM0_DC_ABM1_HG_MISC_CTRL, \ 150 ABM1_HG_BIN_BITWIDTH_SIZE_SEL, mask_sh), \ 151 ABM_SF(ABM0_DC_ABM1_IPCSC_COEFF_SEL, \ 152 ABM1_IPCSC_COEFF_SEL_R, mask_sh), \ 153 ABM_SF(ABM0_DC_ABM1_IPCSC_COEFF_SEL, \ 154 ABM1_IPCSC_COEFF_SEL_G, mask_sh), \ 155 ABM_SF(ABM0_DC_ABM1_IPCSC_COEFF_SEL, \ 156 ABM1_IPCSC_COEFF_SEL_B, mask_sh), \ 157 ABM_SF(ABM0_BL1_PWM_CURRENT_ABM_LEVEL, \ 158 BL1_PWM_CURRENT_ABM_LEVEL, mask_sh), \ 159 ABM_SF(ABM0_BL1_PWM_TARGET_ABM_LEVEL, \ 160 BL1_PWM_TARGET_ABM_LEVEL, mask_sh), \ 161 ABM_SF(ABM0_BL1_PWM_USER_LEVEL, \ 162 BL1_PWM_USER_LEVEL, mask_sh), \ 163 ABM_SF(ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, \ 164 ABM1_LS_MIN_PIXEL_VALUE_THRES, mask_sh), \ 165 ABM_SF(ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, \ 166 ABM1_LS_MAX_PIXEL_VALUE_THRES, mask_sh), \ 167 ABM_SF(ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS, \ 168 ABM1_HG_REG_READ_MISSED_FRAME_CLEAR, mask_sh), \ 169 ABM_SF(ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS, \ 170 ABM1_LS_REG_READ_MISSED_FRAME_CLEAR, mask_sh), \ 171 ABM_SF(ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS, \ 172 ABM1_BL_REG_READ_MISSED_FRAME_CLEAR, mask_sh) 173 174 #define ABM_MASK_SH_LIST_DCN20(mask_sh) ABM_MASK_SH_LIST_DCE110(mask_sh) 175 176 #if defined(CONFIG_DRM_AMD_DC_DCN3_0) 177 #define ABM_MASK_SH_LIST_DCN301(mask_sh) ABM_MASK_SH_LIST_DCN10(mask_sh) 178 #endif 179 180 #define ABM_REG_FIELD_LIST(type) \ 181 type ABM1_HG_NUM_OF_BINS_SEL; \ 182 type ABM1_HG_VMAX_SEL; \ 183 type ABM1_HG_BIN_BITWIDTH_SIZE_SEL; \ 184 type ABM1_IPCSC_COEFF_SEL_R; \ 185 type ABM1_IPCSC_COEFF_SEL_G; \ 186 type ABM1_IPCSC_COEFF_SEL_B; \ 187 type BL1_PWM_CURRENT_ABM_LEVEL; \ 188 type BL1_PWM_TARGET_ABM_LEVEL; \ 189 type BL1_PWM_USER_LEVEL; \ 190 type ABM1_LS_MIN_PIXEL_VALUE_THRES; \ 191 type ABM1_LS_MAX_PIXEL_VALUE_THRES; \ 192 type ABM1_HG_REG_READ_MISSED_FRAME_CLEAR; \ 193 type ABM1_LS_REG_READ_MISSED_FRAME_CLEAR; \ 194 type ABM1_BL_REG_READ_MISSED_FRAME_CLEAR; \ 195 type MASTER_COMM_INTERRUPT; \ 196 type MASTER_COMM_CMD_REG_BYTE0; \ 197 type MASTER_COMM_CMD_REG_BYTE1; \ 198 type MASTER_COMM_CMD_REG_BYTE2 199 200 struct dce_abm_shift { 201 ABM_REG_FIELD_LIST(uint8_t); 202 }; 203 204 struct dce_abm_mask { 205 ABM_REG_FIELD_LIST(uint32_t); 206 }; 207 208 struct dce_abm_registers { 209 uint32_t DC_ABM1_HG_SAMPLE_RATE; 210 uint32_t DC_ABM1_LS_SAMPLE_RATE; 211 uint32_t BL1_PWM_BL_UPDATE_SAMPLE_RATE; 212 uint32_t DC_ABM1_HG_MISC_CTRL; 213 uint32_t DC_ABM1_IPCSC_COEFF_SEL; 214 uint32_t BL1_PWM_CURRENT_ABM_LEVEL; 215 uint32_t BL1_PWM_TARGET_ABM_LEVEL; 216 uint32_t BL1_PWM_USER_LEVEL; 217 uint32_t DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES; 218 uint32_t DC_ABM1_HGLS_REG_READ_PROGRESS; 219 uint32_t DC_ABM1_ACE_OFFSET_SLOPE_0; 220 uint32_t DC_ABM1_ACE_THRES_12; 221 uint32_t MASTER_COMM_CNTL_REG; 222 uint32_t MASTER_COMM_CMD_REG; 223 uint32_t MASTER_COMM_DATA_REG1; 224 uint32_t BIOS_SCRATCH_2; 225 }; 226 227 struct dce_abm { 228 struct abm base; 229 const struct dce_abm_registers *regs; 230 const struct dce_abm_shift *abm_shift; 231 const struct dce_abm_mask *abm_mask; 232 }; 233 234 struct abm *dce_abm_create( 235 struct dc_context *ctx, 236 const struct dce_abm_registers *regs, 237 const struct dce_abm_shift *abm_shift, 238 const struct dce_abm_mask *abm_mask); 239 240 void dce_abm_destroy(struct abm **abm); 241 242 #endif /* _DCE_ABM_H_ */ 243
