1 /*
2 * Copyright 2012-15 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include "dce/dce_8_0_d.h"
27 #include "dce/dce_8_0_sh_mask.h"
28
29 #include "dm_services.h"
30
31 #include "link_encoder.h"
32 #include "stream_encoder.h"
33
34 #include "resource.h"
35 #include "include/irq_service_interface.h"
36 #include "irq/dce80/irq_service_dce80.h"
37 #include "dce110/dce110_timing_generator.h"
38 #include "dce110/dce110_resource.h"
39 #include "dce80/dce80_timing_generator.h"
40 #include "dce/dce_mem_input.h"
41 #include "dce/dce_link_encoder.h"
42 #include "dce/dce_stream_encoder.h"
43 #include "dce/dce_ipp.h"
44 #include "dce/dce_transform.h"
45 #include "dce/dce_opp.h"
46 #include "dce/dce_clock_source.h"
47 #include "dce/dce_audio.h"
48 #include "dce/dce_hwseq.h"
49 #include "dce80/dce80_hw_sequencer.h"
50 #include "dce100/dce100_resource.h"
51 #include "dce/dce_panel_cntl.h"
52
53 #include "reg_helper.h"
54
55 #include "dce/dce_dmcu.h"
56 #include "dce/dce_aux.h"
57 #include "dce/dce_abm.h"
58 #include "dce/dce_i2c.h"
59 /* TODO remove this include */
60
61 #include "dce80_resource.h"
62
63 #ifndef mmMC_HUB_RDREQ_DMIF_LIMIT
64 #include "gmc/gmc_7_1_d.h"
65 #include "gmc/gmc_7_1_sh_mask.h"
66 #endif
67
68 #ifndef mmDP_DPHY_INTERNAL_CTRL
69 #define mmDP_DPHY_INTERNAL_CTRL 0x1CDE
70 #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x1CDE
71 #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x1FDE
72 #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x42DE
73 #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x45DE
74 #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x48DE
75 #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x4BDE
76 #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x4EDE
77 #endif
78
79
80 #ifndef mmBIOS_SCRATCH_2
81 #define mmBIOS_SCRATCH_2 0x05CB
82 #define mmBIOS_SCRATCH_3 0x05CC
83 #define mmBIOS_SCRATCH_6 0x05CF
84 #endif
85
86 #ifndef mmDP_DPHY_FAST_TRAINING
87 #define mmDP_DPHY_FAST_TRAINING 0x1CCE
88 #define mmDP0_DP_DPHY_FAST_TRAINING 0x1CCE
89 #define mmDP1_DP_DPHY_FAST_TRAINING 0x1FCE
90 #define mmDP2_DP_DPHY_FAST_TRAINING 0x42CE
91 #define mmDP3_DP_DPHY_FAST_TRAINING 0x45CE
92 #define mmDP4_DP_DPHY_FAST_TRAINING 0x48CE
93 #define mmDP5_DP_DPHY_FAST_TRAINING 0x4BCE
94 #define mmDP6_DP_DPHY_FAST_TRAINING 0x4ECE
95 #endif
96
97
98 #ifndef mmHPD_DC_HPD_CONTROL
99 #define mmHPD_DC_HPD_CONTROL 0x189A
100 #define mmHPD0_DC_HPD_CONTROL 0x189A
101 #define mmHPD1_DC_HPD_CONTROL 0x18A2
102 #define mmHPD2_DC_HPD_CONTROL 0x18AA
103 #define mmHPD3_DC_HPD_CONTROL 0x18B2
104 #define mmHPD4_DC_HPD_CONTROL 0x18BA
105 #define mmHPD5_DC_HPD_CONTROL 0x18C2
106 #endif
107
108 #define DCE11_DIG_FE_CNTL 0x4a00
109 #define DCE11_DIG_BE_CNTL 0x4a47
110 #define DCE11_DP_SEC 0x4ac3
111
112 static const struct dce110_timing_generator_offsets dce80_tg_offsets[] = {
113 {
114 .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL),
115 .dcp = (mmGRPH_CONTROL - mmGRPH_CONTROL),
116 .dmif = (mmDMIF_PG0_DPG_WATERMARK_MASK_CONTROL
117 - mmDPG_WATERMARK_MASK_CONTROL),
118 },
119 {
120 .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL),
121 .dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL),
122 .dmif = (mmDMIF_PG1_DPG_WATERMARK_MASK_CONTROL
123 - mmDPG_WATERMARK_MASK_CONTROL),
124 },
125 {
126 .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL),
127 .dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL),
128 .dmif = (mmDMIF_PG2_DPG_WATERMARK_MASK_CONTROL
129 - mmDPG_WATERMARK_MASK_CONTROL),
130 },
131 {
132 .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL),
133 .dcp = (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL),
134 .dmif = (mmDMIF_PG3_DPG_WATERMARK_MASK_CONTROL
135 - mmDPG_WATERMARK_MASK_CONTROL),
136 },
137 {
138 .crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC_CONTROL),
139 .dcp = (mmDCP4_GRPH_CONTROL - mmGRPH_CONTROL),
140 .dmif = (mmDMIF_PG4_DPG_WATERMARK_MASK_CONTROL
141 - mmDPG_WATERMARK_MASK_CONTROL),
142 },
143 {
144 .crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC_CONTROL),
145 .dcp = (mmDCP5_GRPH_CONTROL - mmGRPH_CONTROL),
146 .dmif = (mmDMIF_PG5_DPG_WATERMARK_MASK_CONTROL
147 - mmDPG_WATERMARK_MASK_CONTROL),
148 }
149 };
150
151 /* set register offset */
152 #define SR(reg_name)\
153 .reg_name = mm ## reg_name
154
155 /* set register offset with instance */
156 #define SRI(reg_name, block, id)\
157 .reg_name = mm ## block ## id ## _ ## reg_name
158
159 #define ipp_regs(id)\
160 [id] = {\
161 IPP_COMMON_REG_LIST_DCE_BASE(id)\
162 }
163
164 static const struct dce_ipp_registers ipp_regs[] = {
165 ipp_regs(0),
166 ipp_regs(1),
167 ipp_regs(2),
168 ipp_regs(3),
169 ipp_regs(4),
170 ipp_regs(5)
171 };
172
173 static const struct dce_ipp_shift ipp_shift = {
174 IPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
175 };
176
177 static const struct dce_ipp_mask ipp_mask = {
178 IPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
179 };
180
181 #define transform_regs(id)\
182 [id] = {\
183 XFM_COMMON_REG_LIST_DCE80(id)\
184 }
185
186 static const struct dce_transform_registers xfm_regs[] = {
187 transform_regs(0),
188 transform_regs(1),
189 transform_regs(2),
190 transform_regs(3),
191 transform_regs(4),
192 transform_regs(5)
193 };
194
195 static const struct dce_transform_shift xfm_shift = {
196 XFM_COMMON_MASK_SH_LIST_DCE80(__SHIFT)
197 };
198
199 static const struct dce_transform_mask xfm_mask = {
200 XFM_COMMON_MASK_SH_LIST_DCE80(_MASK)
201 };
202
203 #define aux_regs(id)\
204 [id] = {\
205 AUX_REG_LIST(id)\
206 }
207
208 static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = {
209 aux_regs(0),
210 aux_regs(1),
211 aux_regs(2),
212 aux_regs(3),
213 aux_regs(4),
214 aux_regs(5)
215 };
216
217 #define hpd_regs(id)\
218 [id] = {\
219 HPD_REG_LIST(id)\
220 }
221
222 static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = {
223 hpd_regs(0),
224 hpd_regs(1),
225 hpd_regs(2),
226 hpd_regs(3),
227 hpd_regs(4),
228 hpd_regs(5)
229 };
230
231 #define link_regs(id)\
232 [id] = {\
233 LE_DCE80_REG_LIST(id)\
234 }
235
236 static const struct dce110_link_enc_registers link_enc_regs[] = {
237 link_regs(0),
238 link_regs(1),
239 link_regs(2),
240 link_regs(3),
241 link_regs(4),
242 link_regs(5),
243 link_regs(6),
244 };
245
246 #define stream_enc_regs(id)\
247 [id] = {\
248 SE_COMMON_REG_LIST_DCE_BASE(id),\
249 .AFMT_CNTL = 0,\
250 }
251
252 static const struct dce110_stream_enc_registers stream_enc_regs[] = {
253 stream_enc_regs(0),
254 stream_enc_regs(1),
255 stream_enc_regs(2),
256 stream_enc_regs(3),
257 stream_enc_regs(4),
258 stream_enc_regs(5),
259 stream_enc_regs(6)
260 };
261
262 static const struct dce_stream_encoder_shift se_shift = {
263 SE_COMMON_MASK_SH_LIST_DCE80_100(__SHIFT)
264 };
265
266 static const struct dce_stream_encoder_mask se_mask = {
267 SE_COMMON_MASK_SH_LIST_DCE80_100(_MASK)
268 };
269
270 static const struct dce_panel_cntl_registers panel_cntl_regs[] = {
271 { DCE_PANEL_CNTL_REG_LIST() }
272 };
273
274 static const struct dce_panel_cntl_shift panel_cntl_shift = {
275 DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT)
276 };
277
278 static const struct dce_panel_cntl_mask panel_cntl_mask = {
279 DCE_PANEL_CNTL_MASK_SH_LIST(_MASK)
280 };
281
282 #define opp_regs(id)\
283 [id] = {\
284 OPP_DCE_80_REG_LIST(id),\
285 }
286
287 static const struct dce_opp_registers opp_regs[] = {
288 opp_regs(0),
289 opp_regs(1),
290 opp_regs(2),
291 opp_regs(3),
292 opp_regs(4),
293 opp_regs(5)
294 };
295
296 static const struct dce_opp_shift opp_shift = {
297 OPP_COMMON_MASK_SH_LIST_DCE_80(__SHIFT)
298 };
299
300 static const struct dce_opp_mask opp_mask = {
301 OPP_COMMON_MASK_SH_LIST_DCE_80(_MASK)
302 };
303
304 static const struct dce110_aux_registers_shift aux_shift = {
305 DCE10_AUX_MASK_SH_LIST(__SHIFT)
306 };
307
308 static const struct dce110_aux_registers_mask aux_mask = {
309 DCE10_AUX_MASK_SH_LIST(_MASK)
310 };
311
312 #define aux_engine_regs(id)\
313 [id] = {\
314 AUX_COMMON_REG_LIST(id), \
315 .AUX_RESET_MASK = 0 \
316 }
317
318 static const struct dce110_aux_registers aux_engine_regs[] = {
319 aux_engine_regs(0),
320 aux_engine_regs(1),
321 aux_engine_regs(2),
322 aux_engine_regs(3),
323 aux_engine_regs(4),
324 aux_engine_regs(5)
325 };
326
327 #define audio_regs(id)\
328 [id] = {\
329 AUD_COMMON_REG_LIST(id)\
330 }
331
332 static const struct dce_audio_registers audio_regs[] = {
333 audio_regs(0),
334 audio_regs(1),
335 audio_regs(2),
336 audio_regs(3),
337 audio_regs(4),
338 audio_regs(5),
339 audio_regs(6),
340 };
341
342 static const struct dce_audio_shift audio_shift = {
343 AUD_COMMON_MASK_SH_LIST(__SHIFT)
344 };
345
346 static const struct dce_audio_mask audio_mask = {
347 AUD_COMMON_MASK_SH_LIST(_MASK)
348 };
349
350 #define clk_src_regs(id)\
351 [id] = {\
352 CS_COMMON_REG_LIST_DCE_80(id),\
353 }
354
355
356 static const struct dce110_clk_src_regs clk_src_regs[] = {
357 clk_src_regs(0),
358 clk_src_regs(1),
359 clk_src_regs(2)
360 };
361
362 static const struct dce110_clk_src_shift cs_shift = {
363 CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
364 };
365
366 static const struct dce110_clk_src_mask cs_mask = {
367 CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
368 };
369
370 static const struct bios_registers bios_regs = {
371 .BIOS_SCRATCH_3 = mmBIOS_SCRATCH_3,
372 .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6
373 };
374
375 static const struct resource_caps res_cap = {
376 .num_timing_generator = 6,
377 .num_audio = 6,
378 .num_stream_encoder = 6,
379 .num_pll = 3,
380 .num_ddc = 6,
381 };
382
383 static const struct resource_caps res_cap_81 = {
384 .num_timing_generator = 4,
385 .num_audio = 7,
386 .num_stream_encoder = 7,
387 .num_pll = 3,
388 .num_ddc = 6,
389 };
390
391 static const struct resource_caps res_cap_83 = {
392 .num_timing_generator = 2,
393 .num_audio = 6,
394 .num_stream_encoder = 6,
395 .num_pll = 2,
396 .num_ddc = 2,
397 };
398
399 static const struct dc_plane_cap plane_cap = {
400 .type = DC_PLANE_TYPE_DCE_RGB,
401
402 .pixel_format_support = {
403 .argb8888 = true,
404 .nv12 = false,
405 .fp16 = true
406 },
407
408 .max_upscale_factor = {
409 .argb8888 = 16000,
410 .nv12 = 1,
411 .fp16 = 1
412 },
413
414 .max_downscale_factor = {
415 .argb8888 = 250,
416 .nv12 = 1,
417 .fp16 = 1
418 }
419 };
420
421 static const struct dce_dmcu_registers dmcu_regs = {
422 DMCU_DCE80_REG_LIST()
423 };
424
425 static const struct dce_dmcu_shift dmcu_shift = {
426 DMCU_MASK_SH_LIST_DCE80(__SHIFT)
427 };
428
429 static const struct dce_dmcu_mask dmcu_mask = {
430 DMCU_MASK_SH_LIST_DCE80(_MASK)
431 };
432 static const struct dce_abm_registers abm_regs = {
433 ABM_DCE110_COMMON_REG_LIST()
434 };
435
436 static const struct dce_abm_shift abm_shift = {
437 ABM_MASK_SH_LIST_DCE110(__SHIFT)
438 };
439
440 static const struct dce_abm_mask abm_mask = {
441 ABM_MASK_SH_LIST_DCE110(_MASK)
442 };
443
444 #define CTX ctx
445 #define REG(reg) mm ## reg
446
447 #ifndef mmCC_DC_HDMI_STRAPS
448 #define mmCC_DC_HDMI_STRAPS 0x1918
449 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE_MASK 0x40
450 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE__SHIFT 0x6
451 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER_MASK 0x700
452 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER__SHIFT 0x8
453 #endif
454
map_transmitter_id_to_phy_instance(enum transmitter transmitter)455 static int map_transmitter_id_to_phy_instance(
456 enum transmitter transmitter)
457 {
458 switch (transmitter) {
459 case TRANSMITTER_UNIPHY_A:
460 return 0;
461 case TRANSMITTER_UNIPHY_B:
462 return 1;
463 case TRANSMITTER_UNIPHY_C:
464 return 2;
465 case TRANSMITTER_UNIPHY_D:
466 return 3;
467 case TRANSMITTER_UNIPHY_E:
468 return 4;
469 case TRANSMITTER_UNIPHY_F:
470 return 5;
471 case TRANSMITTER_UNIPHY_G:
472 return 6;
473 default:
474 ASSERT(0);
475 return 0;
476 }
477 }
478
read_dce_straps(struct dc_context * ctx,struct resource_straps * straps)479 static void read_dce_straps(
480 struct dc_context *ctx,
481 struct resource_straps *straps)
482 {
483 REG_GET_2(CC_DC_HDMI_STRAPS,
484 HDMI_DISABLE, &straps->hdmi_disable,
485 AUDIO_STREAM_NUMBER, &straps->audio_stream_number);
486
487 REG_GET(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO, &straps->dc_pinstraps_audio);
488 }
489
create_audio(struct dc_context * ctx,unsigned int inst)490 static struct audio *create_audio(
491 struct dc_context *ctx, unsigned int inst)
492 {
493 return dce_audio_create(ctx, inst,
494 &audio_regs[inst], &audio_shift, &audio_mask);
495 }
496
dce80_timing_generator_create(struct dc_context * ctx,uint32_t instance,const struct dce110_timing_generator_offsets * offsets)497 static struct timing_generator *dce80_timing_generator_create(
498 struct dc_context *ctx,
499 uint32_t instance,
500 const struct dce110_timing_generator_offsets *offsets)
501 {
502 struct dce110_timing_generator *tg110 =
503 kzalloc(sizeof(struct dce110_timing_generator), GFP_KERNEL);
504
505 if (!tg110)
506 return NULL;
507
508 dce80_timing_generator_construct(tg110, ctx, instance, offsets);
509 return &tg110->base;
510 }
511
dce80_opp_create(struct dc_context * ctx,uint32_t inst)512 static struct output_pixel_processor *dce80_opp_create(
513 struct dc_context *ctx,
514 uint32_t inst)
515 {
516 struct dce110_opp *opp =
517 kzalloc(sizeof(struct dce110_opp), GFP_KERNEL);
518
519 if (!opp)
520 return NULL;
521
522 dce110_opp_construct(opp,
523 ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask);
524 return &opp->base;
525 }
526
dce80_aux_engine_create(struct dc_context * ctx,uint32_t inst)527 static struct dce_aux *dce80_aux_engine_create(
528 struct dc_context *ctx,
529 uint32_t inst)
530 {
531 struct aux_engine_dce110 *aux_engine =
532 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
533
534 if (!aux_engine)
535 return NULL;
536
537 dce110_aux_engine_construct(aux_engine, ctx, inst,
538 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
539 &aux_engine_regs[inst],
540 &aux_mask,
541 &aux_shift,
542 ctx->dc->caps.extended_aux_timeout_support);
543
544 return &aux_engine->base;
545 }
546 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
547
548 static const struct dce_i2c_registers i2c_hw_regs[] = {
549 i2c_inst_regs(1),
550 i2c_inst_regs(2),
551 i2c_inst_regs(3),
552 i2c_inst_regs(4),
553 i2c_inst_regs(5),
554 i2c_inst_regs(6),
555 };
556
557 static const struct dce_i2c_shift i2c_shifts = {
558 I2C_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
559 };
560
561 static const struct dce_i2c_mask i2c_masks = {
562 I2C_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
563 };
564
dce80_i2c_hw_create(struct dc_context * ctx,uint32_t inst)565 static struct dce_i2c_hw *dce80_i2c_hw_create(
566 struct dc_context *ctx,
567 uint32_t inst)
568 {
569 struct dce_i2c_hw *dce_i2c_hw =
570 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
571
572 if (!dce_i2c_hw)
573 return NULL;
574
575 dce_i2c_hw_construct(dce_i2c_hw, ctx, inst,
576 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
577
578 return dce_i2c_hw;
579 }
580
dce80_i2c_sw_create(struct dc_context * ctx)581 static struct dce_i2c_sw *dce80_i2c_sw_create(
582 struct dc_context *ctx)
583 {
584 struct dce_i2c_sw *dce_i2c_sw =
585 kzalloc(sizeof(struct dce_i2c_sw), GFP_KERNEL);
586
587 if (!dce_i2c_sw)
588 return NULL;
589
590 dce_i2c_sw_construct(dce_i2c_sw, ctx);
591
592 return dce_i2c_sw;
593 }
dce80_stream_encoder_create(enum engine_id eng_id,struct dc_context * ctx)594 static struct stream_encoder *dce80_stream_encoder_create(
595 enum engine_id eng_id,
596 struct dc_context *ctx)
597 {
598 struct dce110_stream_encoder *enc110 =
599 kzalloc(sizeof(struct dce110_stream_encoder), GFP_KERNEL);
600
601 if (!enc110)
602 return NULL;
603
604 dce110_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id,
605 &stream_enc_regs[eng_id],
606 &se_shift, &se_mask);
607 return &enc110->base;
608 }
609
610 #define SRII(reg_name, block, id)\
611 .reg_name[id] = mm ## block ## id ## _ ## reg_name
612
613 static const struct dce_hwseq_registers hwseq_reg = {
614 HWSEQ_DCE8_REG_LIST()
615 };
616
617 static const struct dce_hwseq_shift hwseq_shift = {
618 HWSEQ_DCE8_MASK_SH_LIST(__SHIFT)
619 };
620
621 static const struct dce_hwseq_mask hwseq_mask = {
622 HWSEQ_DCE8_MASK_SH_LIST(_MASK)
623 };
624
dce80_hwseq_create(struct dc_context * ctx)625 static struct dce_hwseq *dce80_hwseq_create(
626 struct dc_context *ctx)
627 {
628 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
629
630 if (hws) {
631 hws->ctx = ctx;
632 hws->regs = &hwseq_reg;
633 hws->shifts = &hwseq_shift;
634 hws->masks = &hwseq_mask;
635 }
636 return hws;
637 }
638
639 static const struct resource_create_funcs res_create_funcs = {
640 .read_dce_straps = read_dce_straps,
641 .create_audio = create_audio,
642 .create_stream_encoder = dce80_stream_encoder_create,
643 .create_hwseq = dce80_hwseq_create,
644 };
645
646 #define mi_inst_regs(id) { \
647 MI_DCE8_REG_LIST(id), \
648 .MC_HUB_RDREQ_DMIF_LIMIT = mmMC_HUB_RDREQ_DMIF_LIMIT \
649 }
650 static const struct dce_mem_input_registers mi_regs[] = {
651 mi_inst_regs(0),
652 mi_inst_regs(1),
653 mi_inst_regs(2),
654 mi_inst_regs(3),
655 mi_inst_regs(4),
656 mi_inst_regs(5),
657 };
658
659 static const struct dce_mem_input_shift mi_shifts = {
660 MI_DCE8_MASK_SH_LIST(__SHIFT),
661 .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE__SHIFT
662 };
663
664 static const struct dce_mem_input_mask mi_masks = {
665 MI_DCE8_MASK_SH_LIST(_MASK),
666 .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE_MASK
667 };
668
dce80_mem_input_create(struct dc_context * ctx,uint32_t inst)669 static struct mem_input *dce80_mem_input_create(
670 struct dc_context *ctx,
671 uint32_t inst)
672 {
673 struct dce_mem_input *dce_mi = kzalloc(sizeof(struct dce_mem_input),
674 GFP_KERNEL);
675
676 if (!dce_mi) {
677 BREAK_TO_DEBUGGER();
678 return NULL;
679 }
680
681 dce_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks);
682 dce_mi->wa.single_head_rdreq_dmif_limit = 2;
683 return &dce_mi->base;
684 }
685
dce80_transform_destroy(struct transform ** xfm)686 static void dce80_transform_destroy(struct transform **xfm)
687 {
688 kfree(TO_DCE_TRANSFORM(*xfm));
689 *xfm = NULL;
690 }
691
dce80_transform_create(struct dc_context * ctx,uint32_t inst)692 static struct transform *dce80_transform_create(
693 struct dc_context *ctx,
694 uint32_t inst)
695 {
696 struct dce_transform *transform =
697 kzalloc(sizeof(struct dce_transform), GFP_KERNEL);
698
699 if (!transform)
700 return NULL;
701
702 dce_transform_construct(transform, ctx, inst,
703 &xfm_regs[inst], &xfm_shift, &xfm_mask);
704 transform->prescaler_on = false;
705 return &transform->base;
706 }
707
708 static const struct encoder_feature_support link_enc_feature = {
709 .max_hdmi_deep_color = COLOR_DEPTH_121212,
710 .max_hdmi_pixel_clock = 297000,
711 .flags.bits.IS_HBR2_CAPABLE = true,
712 .flags.bits.IS_TPS3_CAPABLE = true
713 };
714
dce80_link_encoder_create(struct dc_context * ctx,const struct encoder_init_data * enc_init_data)715 static struct link_encoder *dce80_link_encoder_create(
716 struct dc_context *ctx,
717 const struct encoder_init_data *enc_init_data)
718 {
719 struct dce110_link_encoder *enc110 =
720 kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL);
721 int link_regs_id;
722
723 if (!enc110)
724 return NULL;
725
726 link_regs_id =
727 map_transmitter_id_to_phy_instance(enc_init_data->transmitter);
728
729 dce110_link_encoder_construct(enc110,
730 enc_init_data,
731 &link_enc_feature,
732 &link_enc_regs[link_regs_id],
733 &link_enc_aux_regs[enc_init_data->channel - 1],
734 &link_enc_hpd_regs[enc_init_data->hpd_source]);
735 return &enc110->base;
736 }
737
dce80_panel_cntl_create(const struct panel_cntl_init_data * init_data)738 static struct panel_cntl *dce80_panel_cntl_create(const struct panel_cntl_init_data *init_data)
739 {
740 struct dce_panel_cntl *panel_cntl =
741 kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL);
742
743 if (!panel_cntl)
744 return NULL;
745
746 dce_panel_cntl_construct(panel_cntl,
747 init_data,
748 &panel_cntl_regs[init_data->inst],
749 &panel_cntl_shift,
750 &panel_cntl_mask);
751
752 return &panel_cntl->base;
753 }
754
dce80_clock_source_create(struct dc_context * ctx,struct dc_bios * bios,enum clock_source_id id,const struct dce110_clk_src_regs * regs,bool dp_clk_src)755 static struct clock_source *dce80_clock_source_create(
756 struct dc_context *ctx,
757 struct dc_bios *bios,
758 enum clock_source_id id,
759 const struct dce110_clk_src_regs *regs,
760 bool dp_clk_src)
761 {
762 struct dce110_clk_src *clk_src =
763 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
764
765 if (!clk_src)
766 return NULL;
767
768 if (dce110_clk_src_construct(clk_src, ctx, bios, id,
769 regs, &cs_shift, &cs_mask)) {
770 clk_src->base.dp_clk_src = dp_clk_src;
771 return &clk_src->base;
772 }
773
774 kfree(clk_src);
775 BREAK_TO_DEBUGGER();
776 return NULL;
777 }
778
dce80_clock_source_destroy(struct clock_source ** clk_src)779 static void dce80_clock_source_destroy(struct clock_source **clk_src)
780 {
781 kfree(TO_DCE110_CLK_SRC(*clk_src));
782 *clk_src = NULL;
783 }
784
dce80_ipp_create(struct dc_context * ctx,uint32_t inst)785 static struct input_pixel_processor *dce80_ipp_create(
786 struct dc_context *ctx, uint32_t inst)
787 {
788 struct dce_ipp *ipp = kzalloc(sizeof(struct dce_ipp), GFP_KERNEL);
789
790 if (!ipp) {
791 BREAK_TO_DEBUGGER();
792 return NULL;
793 }
794
795 dce_ipp_construct(ipp, ctx, inst,
796 &ipp_regs[inst], &ipp_shift, &ipp_mask);
797 return &ipp->base;
798 }
799
dce80_resource_destruct(struct dce110_resource_pool * pool)800 static void dce80_resource_destruct(struct dce110_resource_pool *pool)
801 {
802 unsigned int i;
803
804 for (i = 0; i < pool->base.pipe_count; i++) {
805 if (pool->base.opps[i] != NULL)
806 dce110_opp_destroy(&pool->base.opps[i]);
807
808 if (pool->base.transforms[i] != NULL)
809 dce80_transform_destroy(&pool->base.transforms[i]);
810
811 if (pool->base.ipps[i] != NULL)
812 dce_ipp_destroy(&pool->base.ipps[i]);
813
814 if (pool->base.mis[i] != NULL) {
815 kfree(TO_DCE_MEM_INPUT(pool->base.mis[i]));
816 pool->base.mis[i] = NULL;
817 }
818
819 if (pool->base.timing_generators[i] != NULL) {
820 kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i]));
821 pool->base.timing_generators[i] = NULL;
822 }
823 }
824
825 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
826 if (pool->base.engines[i] != NULL)
827 dce110_engine_destroy(&pool->base.engines[i]);
828 if (pool->base.hw_i2cs[i] != NULL) {
829 kfree(pool->base.hw_i2cs[i]);
830 pool->base.hw_i2cs[i] = NULL;
831 }
832 if (pool->base.sw_i2cs[i] != NULL) {
833 kfree(pool->base.sw_i2cs[i]);
834 pool->base.sw_i2cs[i] = NULL;
835 }
836 }
837
838 for (i = 0; i < pool->base.stream_enc_count; i++) {
839 if (pool->base.stream_enc[i] != NULL)
840 kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i]));
841 }
842
843 for (i = 0; i < pool->base.clk_src_count; i++) {
844 if (pool->base.clock_sources[i] != NULL) {
845 dce80_clock_source_destroy(&pool->base.clock_sources[i]);
846 }
847 }
848
849 if (pool->base.abm != NULL)
850 dce_abm_destroy(&pool->base.abm);
851
852 if (pool->base.dmcu != NULL)
853 dce_dmcu_destroy(&pool->base.dmcu);
854
855 if (pool->base.dp_clock_source != NULL)
856 dce80_clock_source_destroy(&pool->base.dp_clock_source);
857
858 for (i = 0; i < pool->base.audio_count; i++) {
859 if (pool->base.audios[i] != NULL) {
860 dce_aud_destroy(&pool->base.audios[i]);
861 }
862 }
863
864 if (pool->base.irqs != NULL) {
865 dal_irq_service_destroy(&pool->base.irqs);
866 }
867 }
868
dce80_validate_bandwidth(struct dc * dc,struct dc_state * context,bool fast_validate)869 static bool dce80_validate_bandwidth(
870 struct dc *dc,
871 struct dc_state *context,
872 bool fast_validate)
873 {
874 int i;
875 bool at_least_one_pipe = false;
876
877 for (i = 0; i < dc->res_pool->pipe_count; i++) {
878 if (context->res_ctx.pipe_ctx[i].stream)
879 at_least_one_pipe = true;
880 }
881
882 if (at_least_one_pipe) {
883 /* TODO implement when needed but for now hardcode max value*/
884 context->bw_ctx.bw.dce.dispclk_khz = 681000;
885 context->bw_ctx.bw.dce.yclk_khz = 250000 * MEMORY_TYPE_MULTIPLIER_CZ;
886 } else {
887 context->bw_ctx.bw.dce.dispclk_khz = 0;
888 context->bw_ctx.bw.dce.yclk_khz = 0;
889 }
890
891 return true;
892 }
893
dce80_validate_surface_sets(struct dc_state * context)894 static bool dce80_validate_surface_sets(
895 struct dc_state *context)
896 {
897 int i;
898
899 for (i = 0; i < context->stream_count; i++) {
900 if (context->stream_status[i].plane_count == 0)
901 continue;
902
903 if (context->stream_status[i].plane_count > 1)
904 return false;
905
906 if (context->stream_status[i].plane_states[0]->format
907 >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
908 return false;
909 }
910
911 return true;
912 }
913
dce80_validate_global(struct dc * dc,struct dc_state * context)914 static enum dc_status dce80_validate_global(
915 struct dc *dc,
916 struct dc_state *context)
917 {
918 if (!dce80_validate_surface_sets(context))
919 return DC_FAIL_SURFACE_VALIDATE;
920
921 return DC_OK;
922 }
923
dce80_destroy_resource_pool(struct resource_pool ** pool)924 static void dce80_destroy_resource_pool(struct resource_pool **pool)
925 {
926 struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool);
927
928 dce80_resource_destruct(dce110_pool);
929 kfree(dce110_pool);
930 *pool = NULL;
931 }
932
933 static const struct resource_funcs dce80_res_pool_funcs = {
934 .destroy = dce80_destroy_resource_pool,
935 .link_enc_create = dce80_link_encoder_create,
936 .panel_cntl_create = dce80_panel_cntl_create,
937 .validate_bandwidth = dce80_validate_bandwidth,
938 .validate_plane = dce100_validate_plane,
939 .add_stream_to_ctx = dce100_add_stream_to_ctx,
940 .validate_global = dce80_validate_global,
941 .find_first_free_match_stream_enc_for_link = dce100_find_first_free_match_stream_enc_for_link
942 };
943
dce80_construct(uint8_t num_virtual_links,struct dc * dc,struct dce110_resource_pool * pool)944 static bool dce80_construct(
945 uint8_t num_virtual_links,
946 struct dc *dc,
947 struct dce110_resource_pool *pool)
948 {
949 unsigned int i;
950 struct dc_context *ctx = dc->ctx;
951 struct dc_bios *bp;
952
953 ctx->dc_bios->regs = &bios_regs;
954
955 pool->base.res_cap = &res_cap;
956 pool->base.funcs = &dce80_res_pool_funcs;
957
958
959 /*************************************************
960 * Resource + asic cap harcoding *
961 *************************************************/
962 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
963 pool->base.pipe_count = res_cap.num_timing_generator;
964 pool->base.timing_generator_count = res_cap.num_timing_generator;
965 dc->caps.max_downscale_ratio = 200;
966 dc->caps.i2c_speed_in_khz = 40;
967 dc->caps.i2c_speed_in_khz_hdcp = 40;
968 dc->caps.max_cursor_size = 128;
969 dc->caps.min_horizontal_blanking_period = 80;
970 dc->caps.dual_link_dvi = true;
971 dc->caps.extended_aux_timeout_support = false;
972
973 /*************************************************
974 * Create resources *
975 *************************************************/
976
977 bp = ctx->dc_bios;
978
979 if (bp->fw_info_valid && bp->fw_info.external_clock_source_frequency_for_dp != 0) {
980 pool->base.dp_clock_source =
981 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true);
982
983 pool->base.clock_sources[0] =
984 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], false);
985 pool->base.clock_sources[1] =
986 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
987 pool->base.clock_sources[2] =
988 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
989 pool->base.clk_src_count = 3;
990
991 } else {
992 pool->base.dp_clock_source =
993 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true);
994
995 pool->base.clock_sources[0] =
996 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
997 pool->base.clock_sources[1] =
998 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
999 pool->base.clk_src_count = 2;
1000 }
1001
1002 if (pool->base.dp_clock_source == NULL) {
1003 dm_error("DC: failed to create dp clock source!\n");
1004 BREAK_TO_DEBUGGER();
1005 goto res_create_fail;
1006 }
1007
1008 for (i = 0; i < pool->base.clk_src_count; i++) {
1009 if (pool->base.clock_sources[i] == NULL) {
1010 dm_error("DC: failed to create clock sources!\n");
1011 BREAK_TO_DEBUGGER();
1012 goto res_create_fail;
1013 }
1014 }
1015
1016 pool->base.dmcu = dce_dmcu_create(ctx,
1017 &dmcu_regs,
1018 &dmcu_shift,
1019 &dmcu_mask);
1020 if (pool->base.dmcu == NULL) {
1021 dm_error("DC: failed to create dmcu!\n");
1022 BREAK_TO_DEBUGGER();
1023 goto res_create_fail;
1024 }
1025
1026 pool->base.abm = dce_abm_create(ctx,
1027 &abm_regs,
1028 &abm_shift,
1029 &abm_mask);
1030 if (pool->base.abm == NULL) {
1031 dm_error("DC: failed to create abm!\n");
1032 BREAK_TO_DEBUGGER();
1033 goto res_create_fail;
1034 }
1035
1036 {
1037 struct irq_service_init_data init_data;
1038 init_data.ctx = dc->ctx;
1039 pool->base.irqs = dal_irq_service_dce80_create(&init_data);
1040 if (!pool->base.irqs)
1041 goto res_create_fail;
1042 }
1043
1044 for (i = 0; i < pool->base.pipe_count; i++) {
1045 pool->base.timing_generators[i] = dce80_timing_generator_create(
1046 ctx, i, &dce80_tg_offsets[i]);
1047 if (pool->base.timing_generators[i] == NULL) {
1048 BREAK_TO_DEBUGGER();
1049 dm_error("DC: failed to create tg!\n");
1050 goto res_create_fail;
1051 }
1052
1053 pool->base.mis[i] = dce80_mem_input_create(ctx, i);
1054 if (pool->base.mis[i] == NULL) {
1055 BREAK_TO_DEBUGGER();
1056 dm_error("DC: failed to create memory input!\n");
1057 goto res_create_fail;
1058 }
1059
1060 pool->base.ipps[i] = dce80_ipp_create(ctx, i);
1061 if (pool->base.ipps[i] == NULL) {
1062 BREAK_TO_DEBUGGER();
1063 dm_error("DC: failed to create input pixel processor!\n");
1064 goto res_create_fail;
1065 }
1066
1067 pool->base.transforms[i] = dce80_transform_create(ctx, i);
1068 if (pool->base.transforms[i] == NULL) {
1069 BREAK_TO_DEBUGGER();
1070 dm_error("DC: failed to create transform!\n");
1071 goto res_create_fail;
1072 }
1073
1074 pool->base.opps[i] = dce80_opp_create(ctx, i);
1075 if (pool->base.opps[i] == NULL) {
1076 BREAK_TO_DEBUGGER();
1077 dm_error("DC: failed to create output pixel processor!\n");
1078 goto res_create_fail;
1079 }
1080 }
1081
1082 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1083 pool->base.engines[i] = dce80_aux_engine_create(ctx, i);
1084 if (pool->base.engines[i] == NULL) {
1085 BREAK_TO_DEBUGGER();
1086 dm_error(
1087 "DC:failed to create aux engine!!\n");
1088 goto res_create_fail;
1089 }
1090 pool->base.hw_i2cs[i] = dce80_i2c_hw_create(ctx, i);
1091 if (pool->base.hw_i2cs[i] == NULL) {
1092 BREAK_TO_DEBUGGER();
1093 dm_error(
1094 "DC:failed to create i2c engine!!\n");
1095 goto res_create_fail;
1096 }
1097 pool->base.sw_i2cs[i] = dce80_i2c_sw_create(ctx);
1098 if (pool->base.sw_i2cs[i] == NULL) {
1099 BREAK_TO_DEBUGGER();
1100 dm_error(
1101 "DC:failed to create sw i2c!!\n");
1102 goto res_create_fail;
1103 }
1104 }
1105
1106 dc->caps.max_planes = pool->base.pipe_count;
1107
1108 for (i = 0; i < dc->caps.max_planes; ++i)
1109 dc->caps.planes[i] = plane_cap;
1110
1111 dc->caps.disable_dp_clk_share = true;
1112
1113 if (!resource_construct(num_virtual_links, dc, &pool->base,
1114 &res_create_funcs))
1115 goto res_create_fail;
1116
1117 /* Create hardware sequencer */
1118 dce80_hw_sequencer_construct(dc);
1119
1120 return true;
1121
1122 res_create_fail:
1123 dce80_resource_destruct(pool);
1124 return false;
1125 }
1126
dce80_create_resource_pool(uint8_t num_virtual_links,struct dc * dc)1127 struct resource_pool *dce80_create_resource_pool(
1128 uint8_t num_virtual_links,
1129 struct dc *dc)
1130 {
1131 struct dce110_resource_pool *pool =
1132 kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL);
1133
1134 if (!pool)
1135 return NULL;
1136
1137 if (dce80_construct(num_virtual_links, dc, pool))
1138 return &pool->base;
1139
1140 BREAK_TO_DEBUGGER();
1141 return NULL;
1142 }
1143
dce81_construct(uint8_t num_virtual_links,struct dc * dc,struct dce110_resource_pool * pool)1144 static bool dce81_construct(
1145 uint8_t num_virtual_links,
1146 struct dc *dc,
1147 struct dce110_resource_pool *pool)
1148 {
1149 unsigned int i;
1150 struct dc_context *ctx = dc->ctx;
1151 struct dc_bios *bp;
1152
1153 ctx->dc_bios->regs = &bios_regs;
1154
1155 pool->base.res_cap = &res_cap_81;
1156 pool->base.funcs = &dce80_res_pool_funcs;
1157
1158
1159 /*************************************************
1160 * Resource + asic cap harcoding *
1161 *************************************************/
1162 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1163 pool->base.pipe_count = res_cap_81.num_timing_generator;
1164 pool->base.timing_generator_count = res_cap_81.num_timing_generator;
1165 dc->caps.max_downscale_ratio = 200;
1166 dc->caps.i2c_speed_in_khz = 40;
1167 dc->caps.i2c_speed_in_khz_hdcp = 40;
1168 dc->caps.max_cursor_size = 128;
1169 dc->caps.min_horizontal_blanking_period = 80;
1170 dc->caps.is_apu = true;
1171
1172 /*************************************************
1173 * Create resources *
1174 *************************************************/
1175
1176 bp = ctx->dc_bios;
1177
1178 if (bp->fw_info_valid && bp->fw_info.external_clock_source_frequency_for_dp != 0) {
1179 pool->base.dp_clock_source =
1180 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true);
1181
1182 pool->base.clock_sources[0] =
1183 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], false);
1184 pool->base.clock_sources[1] =
1185 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
1186 pool->base.clock_sources[2] =
1187 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
1188 pool->base.clk_src_count = 3;
1189
1190 } else {
1191 pool->base.dp_clock_source =
1192 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true);
1193
1194 pool->base.clock_sources[0] =
1195 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
1196 pool->base.clock_sources[1] =
1197 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
1198 pool->base.clk_src_count = 2;
1199 }
1200
1201 if (pool->base.dp_clock_source == NULL) {
1202 dm_error("DC: failed to create dp clock source!\n");
1203 BREAK_TO_DEBUGGER();
1204 goto res_create_fail;
1205 }
1206
1207 for (i = 0; i < pool->base.clk_src_count; i++) {
1208 if (pool->base.clock_sources[i] == NULL) {
1209 dm_error("DC: failed to create clock sources!\n");
1210 BREAK_TO_DEBUGGER();
1211 goto res_create_fail;
1212 }
1213 }
1214
1215 pool->base.dmcu = dce_dmcu_create(ctx,
1216 &dmcu_regs,
1217 &dmcu_shift,
1218 &dmcu_mask);
1219 if (pool->base.dmcu == NULL) {
1220 dm_error("DC: failed to create dmcu!\n");
1221 BREAK_TO_DEBUGGER();
1222 goto res_create_fail;
1223 }
1224
1225 pool->base.abm = dce_abm_create(ctx,
1226 &abm_regs,
1227 &abm_shift,
1228 &abm_mask);
1229 if (pool->base.abm == NULL) {
1230 dm_error("DC: failed to create abm!\n");
1231 BREAK_TO_DEBUGGER();
1232 goto res_create_fail;
1233 }
1234
1235 {
1236 struct irq_service_init_data init_data;
1237 init_data.ctx = dc->ctx;
1238 pool->base.irqs = dal_irq_service_dce80_create(&init_data);
1239 if (!pool->base.irqs)
1240 goto res_create_fail;
1241 }
1242
1243 for (i = 0; i < pool->base.pipe_count; i++) {
1244 pool->base.timing_generators[i] = dce80_timing_generator_create(
1245 ctx, i, &dce80_tg_offsets[i]);
1246 if (pool->base.timing_generators[i] == NULL) {
1247 BREAK_TO_DEBUGGER();
1248 dm_error("DC: failed to create tg!\n");
1249 goto res_create_fail;
1250 }
1251
1252 pool->base.mis[i] = dce80_mem_input_create(ctx, i);
1253 if (pool->base.mis[i] == NULL) {
1254 BREAK_TO_DEBUGGER();
1255 dm_error("DC: failed to create memory input!\n");
1256 goto res_create_fail;
1257 }
1258
1259 pool->base.ipps[i] = dce80_ipp_create(ctx, i);
1260 if (pool->base.ipps[i] == NULL) {
1261 BREAK_TO_DEBUGGER();
1262 dm_error("DC: failed to create input pixel processor!\n");
1263 goto res_create_fail;
1264 }
1265
1266 pool->base.transforms[i] = dce80_transform_create(ctx, i);
1267 if (pool->base.transforms[i] == NULL) {
1268 BREAK_TO_DEBUGGER();
1269 dm_error("DC: failed to create transform!\n");
1270 goto res_create_fail;
1271 }
1272
1273 pool->base.opps[i] = dce80_opp_create(ctx, i);
1274 if (pool->base.opps[i] == NULL) {
1275 BREAK_TO_DEBUGGER();
1276 dm_error("DC: failed to create output pixel processor!\n");
1277 goto res_create_fail;
1278 }
1279 }
1280
1281 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1282 pool->base.engines[i] = dce80_aux_engine_create(ctx, i);
1283 if (pool->base.engines[i] == NULL) {
1284 BREAK_TO_DEBUGGER();
1285 dm_error(
1286 "DC:failed to create aux engine!!\n");
1287 goto res_create_fail;
1288 }
1289 pool->base.hw_i2cs[i] = dce80_i2c_hw_create(ctx, i);
1290 if (pool->base.hw_i2cs[i] == NULL) {
1291 BREAK_TO_DEBUGGER();
1292 dm_error(
1293 "DC:failed to create i2c engine!!\n");
1294 goto res_create_fail;
1295 }
1296 pool->base.sw_i2cs[i] = dce80_i2c_sw_create(ctx);
1297 if (pool->base.sw_i2cs[i] == NULL) {
1298 BREAK_TO_DEBUGGER();
1299 dm_error(
1300 "DC:failed to create sw i2c!!\n");
1301 goto res_create_fail;
1302 }
1303 }
1304
1305 dc->caps.max_planes = pool->base.pipe_count;
1306
1307 for (i = 0; i < dc->caps.max_planes; ++i)
1308 dc->caps.planes[i] = plane_cap;
1309
1310 dc->caps.disable_dp_clk_share = true;
1311
1312 if (!resource_construct(num_virtual_links, dc, &pool->base,
1313 &res_create_funcs))
1314 goto res_create_fail;
1315
1316 /* Create hardware sequencer */
1317 dce80_hw_sequencer_construct(dc);
1318
1319 return true;
1320
1321 res_create_fail:
1322 dce80_resource_destruct(pool);
1323 return false;
1324 }
1325
dce81_create_resource_pool(uint8_t num_virtual_links,struct dc * dc)1326 struct resource_pool *dce81_create_resource_pool(
1327 uint8_t num_virtual_links,
1328 struct dc *dc)
1329 {
1330 struct dce110_resource_pool *pool =
1331 kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL);
1332
1333 if (!pool)
1334 return NULL;
1335
1336 if (dce81_construct(num_virtual_links, dc, pool))
1337 return &pool->base;
1338
1339 BREAK_TO_DEBUGGER();
1340 return NULL;
1341 }
1342
dce83_construct(uint8_t num_virtual_links,struct dc * dc,struct dce110_resource_pool * pool)1343 static bool dce83_construct(
1344 uint8_t num_virtual_links,
1345 struct dc *dc,
1346 struct dce110_resource_pool *pool)
1347 {
1348 unsigned int i;
1349 struct dc_context *ctx = dc->ctx;
1350 struct dc_bios *bp;
1351
1352 ctx->dc_bios->regs = &bios_regs;
1353
1354 pool->base.res_cap = &res_cap_83;
1355 pool->base.funcs = &dce80_res_pool_funcs;
1356
1357
1358 /*************************************************
1359 * Resource + asic cap harcoding *
1360 *************************************************/
1361 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1362 pool->base.pipe_count = res_cap_83.num_timing_generator;
1363 pool->base.timing_generator_count = res_cap_83.num_timing_generator;
1364 dc->caps.max_downscale_ratio = 200;
1365 dc->caps.i2c_speed_in_khz = 40;
1366 dc->caps.i2c_speed_in_khz_hdcp = 40;
1367 dc->caps.max_cursor_size = 128;
1368 dc->caps.min_horizontal_blanking_period = 80;
1369 dc->caps.is_apu = true;
1370
1371 /*************************************************
1372 * Create resources *
1373 *************************************************/
1374
1375 bp = ctx->dc_bios;
1376
1377 if (bp->fw_info_valid && bp->fw_info.external_clock_source_frequency_for_dp != 0) {
1378 pool->base.dp_clock_source =
1379 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true);
1380
1381 pool->base.clock_sources[0] =
1382 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[0], false);
1383 pool->base.clock_sources[1] =
1384 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[1], false);
1385 pool->base.clk_src_count = 2;
1386
1387 } else {
1388 pool->base.dp_clock_source =
1389 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[0], true);
1390
1391 pool->base.clock_sources[0] =
1392 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[1], false);
1393 pool->base.clk_src_count = 1;
1394 }
1395
1396 if (pool->base.dp_clock_source == NULL) {
1397 dm_error("DC: failed to create dp clock source!\n");
1398 BREAK_TO_DEBUGGER();
1399 goto res_create_fail;
1400 }
1401
1402 for (i = 0; i < pool->base.clk_src_count; i++) {
1403 if (pool->base.clock_sources[i] == NULL) {
1404 dm_error("DC: failed to create clock sources!\n");
1405 BREAK_TO_DEBUGGER();
1406 goto res_create_fail;
1407 }
1408 }
1409
1410 pool->base.dmcu = dce_dmcu_create(ctx,
1411 &dmcu_regs,
1412 &dmcu_shift,
1413 &dmcu_mask);
1414 if (pool->base.dmcu == NULL) {
1415 dm_error("DC: failed to create dmcu!\n");
1416 BREAK_TO_DEBUGGER();
1417 goto res_create_fail;
1418 }
1419
1420 pool->base.abm = dce_abm_create(ctx,
1421 &abm_regs,
1422 &abm_shift,
1423 &abm_mask);
1424 if (pool->base.abm == NULL) {
1425 dm_error("DC: failed to create abm!\n");
1426 BREAK_TO_DEBUGGER();
1427 goto res_create_fail;
1428 }
1429
1430 {
1431 struct irq_service_init_data init_data;
1432 init_data.ctx = dc->ctx;
1433 pool->base.irqs = dal_irq_service_dce80_create(&init_data);
1434 if (!pool->base.irqs)
1435 goto res_create_fail;
1436 }
1437
1438 for (i = 0; i < pool->base.pipe_count; i++) {
1439 pool->base.timing_generators[i] = dce80_timing_generator_create(
1440 ctx, i, &dce80_tg_offsets[i]);
1441 if (pool->base.timing_generators[i] == NULL) {
1442 BREAK_TO_DEBUGGER();
1443 dm_error("DC: failed to create tg!\n");
1444 goto res_create_fail;
1445 }
1446
1447 pool->base.mis[i] = dce80_mem_input_create(ctx, i);
1448 if (pool->base.mis[i] == NULL) {
1449 BREAK_TO_DEBUGGER();
1450 dm_error("DC: failed to create memory input!\n");
1451 goto res_create_fail;
1452 }
1453
1454 pool->base.ipps[i] = dce80_ipp_create(ctx, i);
1455 if (pool->base.ipps[i] == NULL) {
1456 BREAK_TO_DEBUGGER();
1457 dm_error("DC: failed to create input pixel processor!\n");
1458 goto res_create_fail;
1459 }
1460
1461 pool->base.transforms[i] = dce80_transform_create(ctx, i);
1462 if (pool->base.transforms[i] == NULL) {
1463 BREAK_TO_DEBUGGER();
1464 dm_error("DC: failed to create transform!\n");
1465 goto res_create_fail;
1466 }
1467
1468 pool->base.opps[i] = dce80_opp_create(ctx, i);
1469 if (pool->base.opps[i] == NULL) {
1470 BREAK_TO_DEBUGGER();
1471 dm_error("DC: failed to create output pixel processor!\n");
1472 goto res_create_fail;
1473 }
1474 }
1475
1476 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1477 pool->base.engines[i] = dce80_aux_engine_create(ctx, i);
1478 if (pool->base.engines[i] == NULL) {
1479 BREAK_TO_DEBUGGER();
1480 dm_error(
1481 "DC:failed to create aux engine!!\n");
1482 goto res_create_fail;
1483 }
1484 pool->base.hw_i2cs[i] = dce80_i2c_hw_create(ctx, i);
1485 if (pool->base.hw_i2cs[i] == NULL) {
1486 BREAK_TO_DEBUGGER();
1487 dm_error(
1488 "DC:failed to create i2c engine!!\n");
1489 goto res_create_fail;
1490 }
1491 pool->base.sw_i2cs[i] = dce80_i2c_sw_create(ctx);
1492 if (pool->base.sw_i2cs[i] == NULL) {
1493 BREAK_TO_DEBUGGER();
1494 dm_error(
1495 "DC:failed to create sw i2c!!\n");
1496 goto res_create_fail;
1497 }
1498 }
1499
1500 dc->caps.max_planes = pool->base.pipe_count;
1501
1502 for (i = 0; i < dc->caps.max_planes; ++i)
1503 dc->caps.planes[i] = plane_cap;
1504
1505 dc->caps.disable_dp_clk_share = true;
1506
1507 if (!resource_construct(num_virtual_links, dc, &pool->base,
1508 &res_create_funcs))
1509 goto res_create_fail;
1510
1511 /* Create hardware sequencer */
1512 dce80_hw_sequencer_construct(dc);
1513
1514 return true;
1515
1516 res_create_fail:
1517 dce80_resource_destruct(pool);
1518 return false;
1519 }
1520
dce83_create_resource_pool(uint8_t num_virtual_links,struct dc * dc)1521 struct resource_pool *dce83_create_resource_pool(
1522 uint8_t num_virtual_links,
1523 struct dc *dc)
1524 {
1525 struct dce110_resource_pool *pool =
1526 kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL);
1527
1528 if (!pool)
1529 return NULL;
1530
1531 if (dce83_construct(num_virtual_links, dc, pool))
1532 return &pool->base;
1533
1534 BREAK_TO_DEBUGGER();
1535 return NULL;
1536 }
1537
