1 /*
2 * Copyright 2012-15 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include "dm_services.h"
27
28 #include "link_encoder.h"
29 #include "stream_encoder.h"
30
31 #include "resource.h"
32 #include "dce110/dce110_resource.h"
33
34 #include "include/irq_service_interface.h"
35 #include "dce/dce_audio.h"
36 #include "dce110/dce110_timing_generator.h"
37 #include "irq/dce110/irq_service_dce110.h"
38 #include "dce110/dce110_timing_generator_v.h"
39 #include "dce/dce_link_encoder.h"
40 #include "dce/dce_stream_encoder.h"
41 #include "dce/dce_mem_input.h"
42 #include "dce110/dce110_mem_input_v.h"
43 #include "dce/dce_ipp.h"
44 #include "dce/dce_transform.h"
45 #include "dce110/dce110_transform_v.h"
46 #include "dce/dce_opp.h"
47 #include "dce110/dce110_opp_v.h"
48 #include "dce/dce_clocks.h"
49 #include "dce/dce_clock_source.h"
50 #include "dce/dce_hwseq.h"
51 #include "dce110/dce110_hw_sequencer.h"
52 #include "dce/dce_aux.h"
53 #include "dce/dce_abm.h"
54 #include "dce/dce_dmcu.h"
55
56 #define DC_LOGGER \
57 dc->ctx->logger
58
59 #include "dce110/dce110_compressor.h"
60
61 #include "reg_helper.h"
62
63 #include "dce/dce_11_0_d.h"
64 #include "dce/dce_11_0_sh_mask.h"
65
66 #ifndef mmMC_HUB_RDREQ_DMIF_LIMIT
67 #include "gmc/gmc_8_2_d.h"
68 #include "gmc/gmc_8_2_sh_mask.h"
69 #endif
70
71 #ifndef mmDP_DPHY_INTERNAL_CTRL
72 #define mmDP_DPHY_INTERNAL_CTRL 0x4aa7
73 #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x4aa7
74 #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x4ba7
75 #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x4ca7
76 #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x4da7
77 #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x4ea7
78 #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x4fa7
79 #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x54a7
80 #define mmDP7_DP_DPHY_INTERNAL_CTRL 0x56a7
81 #define mmDP8_DP_DPHY_INTERNAL_CTRL 0x57a7
82 #endif
83
84 #ifndef mmBIOS_SCRATCH_2
85 #define mmBIOS_SCRATCH_2 0x05CB
86 #define mmBIOS_SCRATCH_6 0x05CF
87 #endif
88
89 #ifndef mmDP_DPHY_BS_SR_SWAP_CNTL
90 #define mmDP_DPHY_BS_SR_SWAP_CNTL 0x4ADC
91 #define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL 0x4ADC
92 #define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL 0x4BDC
93 #define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL 0x4CDC
94 #define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL 0x4DDC
95 #define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL 0x4EDC
96 #define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL 0x4FDC
97 #define mmDP6_DP_DPHY_BS_SR_SWAP_CNTL 0x54DC
98 #endif
99
100 #ifndef mmDP_DPHY_FAST_TRAINING
101 #define mmDP_DPHY_FAST_TRAINING 0x4ABC
102 #define mmDP0_DP_DPHY_FAST_TRAINING 0x4ABC
103 #define mmDP1_DP_DPHY_FAST_TRAINING 0x4BBC
104 #define mmDP2_DP_DPHY_FAST_TRAINING 0x4CBC
105 #define mmDP3_DP_DPHY_FAST_TRAINING 0x4DBC
106 #define mmDP4_DP_DPHY_FAST_TRAINING 0x4EBC
107 #define mmDP5_DP_DPHY_FAST_TRAINING 0x4FBC
108 #define mmDP6_DP_DPHY_FAST_TRAINING 0x54BC
109 #endif
110
111 #ifndef DPHY_RX_FAST_TRAINING_CAPABLE
112 #define DPHY_RX_FAST_TRAINING_CAPABLE 0x1
113 #endif
114
115 static const struct dce110_timing_generator_offsets dce110_tg_offsets[] = {
116 {
117 .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL),
118 .dcp = (mmDCP0_GRPH_CONTROL - mmGRPH_CONTROL),
119 },
120 {
121 .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL),
122 .dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL),
123 },
124 {
125 .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL),
126 .dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL),
127 },
128 {
129 .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL),
130 .dcp = (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL),
131 },
132 {
133 .crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC_CONTROL),
134 .dcp = (mmDCP4_GRPH_CONTROL - mmGRPH_CONTROL),
135 },
136 {
137 .crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC_CONTROL),
138 .dcp = (mmDCP5_GRPH_CONTROL - mmGRPH_CONTROL),
139 }
140 };
141
142 /* set register offset */
143 #define SR(reg_name)\
144 .reg_name = mm ## reg_name
145
146 /* set register offset with instance */
147 #define SRI(reg_name, block, id)\
148 .reg_name = mm ## block ## id ## _ ## reg_name
149
150 static const struct dccg_registers disp_clk_regs = {
151 CLK_COMMON_REG_LIST_DCE_BASE()
152 };
153
154 static const struct dccg_shift disp_clk_shift = {
155 CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
156 };
157
158 static const struct dccg_mask disp_clk_mask = {
159 CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
160 };
161
162 static const struct dce_dmcu_registers dmcu_regs = {
163 DMCU_DCE110_COMMON_REG_LIST()
164 };
165
166 static const struct dce_dmcu_shift dmcu_shift = {
167 DMCU_MASK_SH_LIST_DCE110(__SHIFT)
168 };
169
170 static const struct dce_dmcu_mask dmcu_mask = {
171 DMCU_MASK_SH_LIST_DCE110(_MASK)
172 };
173
174 static const struct dce_abm_registers abm_regs = {
175 ABM_DCE110_COMMON_REG_LIST()
176 };
177
178 static const struct dce_abm_shift abm_shift = {
179 ABM_MASK_SH_LIST_DCE110(__SHIFT)
180 };
181
182 static const struct dce_abm_mask abm_mask = {
183 ABM_MASK_SH_LIST_DCE110(_MASK)
184 };
185
186 #define ipp_regs(id)\
187 [id] = {\
188 IPP_DCE110_REG_LIST_DCE_BASE(id)\
189 }
190
191 static const struct dce_ipp_registers ipp_regs[] = {
192 ipp_regs(0),
193 ipp_regs(1),
194 ipp_regs(2)
195 };
196
197 static const struct dce_ipp_shift ipp_shift = {
198 IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
199 };
200
201 static const struct dce_ipp_mask ipp_mask = {
202 IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
203 };
204
205 #define transform_regs(id)\
206 [id] = {\
207 XFM_COMMON_REG_LIST_DCE110(id)\
208 }
209
210 static const struct dce_transform_registers xfm_regs[] = {
211 transform_regs(0),
212 transform_regs(1),
213 transform_regs(2)
214 };
215
216 static const struct dce_transform_shift xfm_shift = {
217 XFM_COMMON_MASK_SH_LIST_DCE110(__SHIFT)
218 };
219
220 static const struct dce_transform_mask xfm_mask = {
221 XFM_COMMON_MASK_SH_LIST_DCE110(_MASK)
222 };
223
224 #define aux_regs(id)\
225 [id] = {\
226 AUX_REG_LIST(id)\
227 }
228
229 static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = {
230 aux_regs(0),
231 aux_regs(1),
232 aux_regs(2),
233 aux_regs(3),
234 aux_regs(4),
235 aux_regs(5)
236 };
237
238 #define hpd_regs(id)\
239 [id] = {\
240 HPD_REG_LIST(id)\
241 }
242
243 static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = {
244 hpd_regs(0),
245 hpd_regs(1),
246 hpd_regs(2),
247 hpd_regs(3),
248 hpd_regs(4),
249 hpd_regs(5)
250 };
251
252
253 #define link_regs(id)\
254 [id] = {\
255 LE_DCE110_REG_LIST(id)\
256 }
257
258 static const struct dce110_link_enc_registers link_enc_regs[] = {
259 link_regs(0),
260 link_regs(1),
261 link_regs(2),
262 link_regs(3),
263 link_regs(4),
264 link_regs(5),
265 link_regs(6),
266 };
267
268 #define stream_enc_regs(id)\
269 [id] = {\
270 SE_COMMON_REG_LIST(id),\
271 .TMDS_CNTL = 0,\
272 }
273
274 static const struct dce110_stream_enc_registers stream_enc_regs[] = {
275 stream_enc_regs(0),
276 stream_enc_regs(1),
277 stream_enc_regs(2)
278 };
279
280 static const struct dce_stream_encoder_shift se_shift = {
281 SE_COMMON_MASK_SH_LIST_DCE110(__SHIFT)
282 };
283
284 static const struct dce_stream_encoder_mask se_mask = {
285 SE_COMMON_MASK_SH_LIST_DCE110(_MASK)
286 };
287
288 #define opp_regs(id)\
289 [id] = {\
290 OPP_DCE_110_REG_LIST(id),\
291 }
292
293 static const struct dce_opp_registers opp_regs[] = {
294 opp_regs(0),
295 opp_regs(1),
296 opp_regs(2),
297 opp_regs(3),
298 opp_regs(4),
299 opp_regs(5)
300 };
301
302 static const struct dce_opp_shift opp_shift = {
303 OPP_COMMON_MASK_SH_LIST_DCE_110(__SHIFT)
304 };
305
306 static const struct dce_opp_mask opp_mask = {
307 OPP_COMMON_MASK_SH_LIST_DCE_110(_MASK)
308 };
309
310 #define aux_engine_regs(id)\
311 [id] = {\
312 AUX_COMMON_REG_LIST(id), \
313 .AUX_RESET_MASK = 0 \
314 }
315
316 static const struct dce110_aux_registers aux_engine_regs[] = {
317 aux_engine_regs(0),
318 aux_engine_regs(1),
319 aux_engine_regs(2),
320 aux_engine_regs(3),
321 aux_engine_regs(4),
322 aux_engine_regs(5)
323 };
324
325 #define audio_regs(id)\
326 [id] = {\
327 AUD_COMMON_REG_LIST(id)\
328 }
329
330 static const struct dce_audio_registers audio_regs[] = {
331 audio_regs(0),
332 audio_regs(1),
333 audio_regs(2),
334 audio_regs(3),
335 audio_regs(4),
336 audio_regs(5),
337 audio_regs(6),
338 };
339
340 static const struct dce_audio_shift audio_shift = {
341 AUD_COMMON_MASK_SH_LIST(__SHIFT)
342 };
343
344 static const struct dce_aduio_mask audio_mask = {
345 AUD_COMMON_MASK_SH_LIST(_MASK)
346 };
347
348 /* AG TBD Needs to be reduced back to 3 pipes once dce10 hw sequencer implemented. */
349
350
351 #define clk_src_regs(id)\
352 [id] = {\
353 CS_COMMON_REG_LIST_DCE_100_110(id),\
354 }
355
356 static const struct dce110_clk_src_regs clk_src_regs[] = {
357 clk_src_regs(0),
358 clk_src_regs(1),
359 clk_src_regs(2)
360 };
361
362 static const struct dce110_clk_src_shift cs_shift = {
363 CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
364 };
365
366 static const struct dce110_clk_src_mask cs_mask = {
367 CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
368 };
369
370 static const struct bios_registers bios_regs = {
371 .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6
372 };
373
374 static const struct resource_caps carrizo_resource_cap = {
375 .num_timing_generator = 3,
376 .num_video_plane = 1,
377 .num_audio = 3,
378 .num_stream_encoder = 3,
379 .num_pll = 2,
380 };
381
382 static const struct resource_caps stoney_resource_cap = {
383 .num_timing_generator = 2,
384 .num_video_plane = 1,
385 .num_audio = 3,
386 .num_stream_encoder = 3,
387 .num_pll = 2,
388 };
389
390 #define CTX ctx
391 #define REG(reg) mm ## reg
392
393 #ifndef mmCC_DC_HDMI_STRAPS
394 #define mmCC_DC_HDMI_STRAPS 0x4819
395 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE_MASK 0x40
396 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE__SHIFT 0x6
397 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER_MASK 0x700
398 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER__SHIFT 0x8
399 #endif
400
read_dce_straps(struct dc_context * ctx,struct resource_straps * straps)401 static void read_dce_straps(
402 struct dc_context *ctx,
403 struct resource_straps *straps)
404 {
405 REG_GET_2(CC_DC_HDMI_STRAPS,
406 HDMI_DISABLE, &straps->hdmi_disable,
407 AUDIO_STREAM_NUMBER, &straps->audio_stream_number);
408
409 REG_GET(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO, &straps->dc_pinstraps_audio);
410 }
411
create_audio(struct dc_context * ctx,unsigned int inst)412 static struct audio *create_audio(
413 struct dc_context *ctx, unsigned int inst)
414 {
415 return dce_audio_create(ctx, inst,
416 &audio_regs[inst], &audio_shift, &audio_mask);
417 }
418
dce110_timing_generator_create(struct dc_context * ctx,uint32_t instance,const struct dce110_timing_generator_offsets * offsets)419 static struct timing_generator *dce110_timing_generator_create(
420 struct dc_context *ctx,
421 uint32_t instance,
422 const struct dce110_timing_generator_offsets *offsets)
423 {
424 struct dce110_timing_generator *tg110 =
425 kzalloc(sizeof(struct dce110_timing_generator), GFP_KERNEL);
426
427 if (!tg110)
428 return NULL;
429
430 dce110_timing_generator_construct(tg110, ctx, instance, offsets);
431 return &tg110->base;
432 }
433
dce110_stream_encoder_create(enum engine_id eng_id,struct dc_context * ctx)434 static struct stream_encoder *dce110_stream_encoder_create(
435 enum engine_id eng_id,
436 struct dc_context *ctx)
437 {
438 struct dce110_stream_encoder *enc110 =
439 kzalloc(sizeof(struct dce110_stream_encoder), GFP_KERNEL);
440
441 if (!enc110)
442 return NULL;
443
444 dce110_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id,
445 &stream_enc_regs[eng_id],
446 &se_shift, &se_mask);
447 return &enc110->base;
448 }
449
450 #define SRII(reg_name, block, id)\
451 .reg_name[id] = mm ## block ## id ## _ ## reg_name
452
453 static const struct dce_hwseq_registers hwseq_stoney_reg = {
454 HWSEQ_ST_REG_LIST()
455 };
456
457 static const struct dce_hwseq_registers hwseq_cz_reg = {
458 HWSEQ_CZ_REG_LIST()
459 };
460
461 static const struct dce_hwseq_shift hwseq_shift = {
462 HWSEQ_DCE11_MASK_SH_LIST(__SHIFT),
463 };
464
465 static const struct dce_hwseq_mask hwseq_mask = {
466 HWSEQ_DCE11_MASK_SH_LIST(_MASK),
467 };
468
dce110_hwseq_create(struct dc_context * ctx)469 static struct dce_hwseq *dce110_hwseq_create(
470 struct dc_context *ctx)
471 {
472 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
473
474 if (hws) {
475 hws->ctx = ctx;
476 hws->regs = ASIC_REV_IS_STONEY(ctx->asic_id.hw_internal_rev) ?
477 &hwseq_stoney_reg : &hwseq_cz_reg;
478 hws->shifts = &hwseq_shift;
479 hws->masks = &hwseq_mask;
480 hws->wa.blnd_crtc_trigger = true;
481 }
482 return hws;
483 }
484
485 static const struct resource_create_funcs res_create_funcs = {
486 .read_dce_straps = read_dce_straps,
487 .create_audio = create_audio,
488 .create_stream_encoder = dce110_stream_encoder_create,
489 .create_hwseq = dce110_hwseq_create,
490 };
491
492 #define mi_inst_regs(id) { \
493 MI_DCE11_REG_LIST(id), \
494 .MC_HUB_RDREQ_DMIF_LIMIT = mmMC_HUB_RDREQ_DMIF_LIMIT \
495 }
496 static const struct dce_mem_input_registers mi_regs[] = {
497 mi_inst_regs(0),
498 mi_inst_regs(1),
499 mi_inst_regs(2),
500 };
501
502 static const struct dce_mem_input_shift mi_shifts = {
503 MI_DCE11_MASK_SH_LIST(__SHIFT),
504 .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE__SHIFT
505 };
506
507 static const struct dce_mem_input_mask mi_masks = {
508 MI_DCE11_MASK_SH_LIST(_MASK),
509 .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE_MASK
510 };
511
512
dce110_mem_input_create(struct dc_context * ctx,uint32_t inst)513 static struct mem_input *dce110_mem_input_create(
514 struct dc_context *ctx,
515 uint32_t inst)
516 {
517 struct dce_mem_input *dce_mi = kzalloc(sizeof(struct dce_mem_input),
518 GFP_KERNEL);
519
520 if (!dce_mi) {
521 BREAK_TO_DEBUGGER();
522 return NULL;
523 }
524
525 dce_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks);
526 dce_mi->wa.single_head_rdreq_dmif_limit = 3;
527 return &dce_mi->base;
528 }
529
dce110_transform_destroy(struct transform ** xfm)530 static void dce110_transform_destroy(struct transform **xfm)
531 {
532 kfree(TO_DCE_TRANSFORM(*xfm));
533 *xfm = NULL;
534 }
535
dce110_transform_create(struct dc_context * ctx,uint32_t inst)536 static struct transform *dce110_transform_create(
537 struct dc_context *ctx,
538 uint32_t inst)
539 {
540 struct dce_transform *transform =
541 kzalloc(sizeof(struct dce_transform), GFP_KERNEL);
542
543 if (!transform)
544 return NULL;
545
546 dce_transform_construct(transform, ctx, inst,
547 &xfm_regs[inst], &xfm_shift, &xfm_mask);
548 return &transform->base;
549 }
550
dce110_ipp_create(struct dc_context * ctx,uint32_t inst)551 static struct input_pixel_processor *dce110_ipp_create(
552 struct dc_context *ctx, uint32_t inst)
553 {
554 struct dce_ipp *ipp = kzalloc(sizeof(struct dce_ipp), GFP_KERNEL);
555
556 if (!ipp) {
557 BREAK_TO_DEBUGGER();
558 return NULL;
559 }
560
561 dce_ipp_construct(ipp, ctx, inst,
562 &ipp_regs[inst], &ipp_shift, &ipp_mask);
563 return &ipp->base;
564 }
565
566 static const struct encoder_feature_support link_enc_feature = {
567 .max_hdmi_deep_color = COLOR_DEPTH_121212,
568 .max_hdmi_pixel_clock = 594000,
569 .flags.bits.IS_HBR2_CAPABLE = true,
570 .flags.bits.IS_TPS3_CAPABLE = true,
571 .flags.bits.IS_YCBCR_CAPABLE = true
572 };
573
dce110_link_encoder_create(const struct encoder_init_data * enc_init_data)574 static struct link_encoder *dce110_link_encoder_create(
575 const struct encoder_init_data *enc_init_data)
576 {
577 struct dce110_link_encoder *enc110 =
578 kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL);
579
580 if (!enc110)
581 return NULL;
582
583 dce110_link_encoder_construct(enc110,
584 enc_init_data,
585 &link_enc_feature,
586 &link_enc_regs[enc_init_data->transmitter],
587 &link_enc_aux_regs[enc_init_data->channel - 1],
588 &link_enc_hpd_regs[enc_init_data->hpd_source]);
589 return &enc110->base;
590 }
591
dce110_opp_create(struct dc_context * ctx,uint32_t inst)592 static struct output_pixel_processor *dce110_opp_create(
593 struct dc_context *ctx,
594 uint32_t inst)
595 {
596 struct dce110_opp *opp =
597 kzalloc(sizeof(struct dce110_opp), GFP_KERNEL);
598
599 if (!opp)
600 return NULL;
601
602 dce110_opp_construct(opp,
603 ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask);
604 return &opp->base;
605 }
606
dce110_aux_engine_create(struct dc_context * ctx,uint32_t inst)607 struct aux_engine *dce110_aux_engine_create(
608 struct dc_context *ctx,
609 uint32_t inst)
610 {
611 struct aux_engine_dce110 *aux_engine =
612 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
613
614 if (!aux_engine)
615 return NULL;
616
617 dce110_aux_engine_construct(aux_engine, ctx, inst,
618 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
619 &aux_engine_regs[inst]);
620
621 return &aux_engine->base;
622 }
623
dce110_clock_source_create(struct dc_context * ctx,struct dc_bios * bios,enum clock_source_id id,const struct dce110_clk_src_regs * regs,bool dp_clk_src)624 struct clock_source *dce110_clock_source_create(
625 struct dc_context *ctx,
626 struct dc_bios *bios,
627 enum clock_source_id id,
628 const struct dce110_clk_src_regs *regs,
629 bool dp_clk_src)
630 {
631 struct dce110_clk_src *clk_src =
632 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
633
634 if (!clk_src)
635 return NULL;
636
637 if (dce110_clk_src_construct(clk_src, ctx, bios, id,
638 regs, &cs_shift, &cs_mask)) {
639 clk_src->base.dp_clk_src = dp_clk_src;
640 return &clk_src->base;
641 }
642
643 BREAK_TO_DEBUGGER();
644 return NULL;
645 }
646
dce110_clock_source_destroy(struct clock_source ** clk_src)647 void dce110_clock_source_destroy(struct clock_source **clk_src)
648 {
649 struct dce110_clk_src *dce110_clk_src;
650
651 if (!clk_src)
652 return;
653
654 dce110_clk_src = TO_DCE110_CLK_SRC(*clk_src);
655
656 kfree(dce110_clk_src->dp_ss_params);
657 kfree(dce110_clk_src->hdmi_ss_params);
658 kfree(dce110_clk_src->dvi_ss_params);
659
660 kfree(dce110_clk_src);
661 *clk_src = NULL;
662 }
663
destruct(struct dce110_resource_pool * pool)664 static void destruct(struct dce110_resource_pool *pool)
665 {
666 unsigned int i;
667
668 for (i = 0; i < pool->base.pipe_count; i++) {
669 if (pool->base.opps[i] != NULL)
670 dce110_opp_destroy(&pool->base.opps[i]);
671
672 if (pool->base.transforms[i] != NULL)
673 dce110_transform_destroy(&pool->base.transforms[i]);
674
675 if (pool->base.ipps[i] != NULL)
676 dce_ipp_destroy(&pool->base.ipps[i]);
677
678 if (pool->base.mis[i] != NULL) {
679 kfree(TO_DCE_MEM_INPUT(pool->base.mis[i]));
680 pool->base.mis[i] = NULL;
681 }
682
683 if (pool->base.timing_generators[i] != NULL) {
684 kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i]));
685 pool->base.timing_generators[i] = NULL;
686 }
687
688 if (pool->base.engines[i] != NULL)
689 dce110_engine_destroy(&pool->base.engines[i]);
690
691 }
692
693 for (i = 0; i < pool->base.stream_enc_count; i++) {
694 if (pool->base.stream_enc[i] != NULL)
695 kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i]));
696 }
697
698 for (i = 0; i < pool->base.clk_src_count; i++) {
699 if (pool->base.clock_sources[i] != NULL) {
700 dce110_clock_source_destroy(&pool->base.clock_sources[i]);
701 }
702 }
703
704 if (pool->base.dp_clock_source != NULL)
705 dce110_clock_source_destroy(&pool->base.dp_clock_source);
706
707 for (i = 0; i < pool->base.audio_count; i++) {
708 if (pool->base.audios[i] != NULL) {
709 dce_aud_destroy(&pool->base.audios[i]);
710 }
711 }
712
713 if (pool->base.abm != NULL)
714 dce_abm_destroy(&pool->base.abm);
715
716 if (pool->base.dmcu != NULL)
717 dce_dmcu_destroy(&pool->base.dmcu);
718
719 if (pool->base.dccg != NULL)
720 dce_dccg_destroy(&pool->base.dccg);
721
722 if (pool->base.irqs != NULL) {
723 dal_irq_service_destroy(&pool->base.irqs);
724 }
725 }
726
727
get_pixel_clock_parameters(const struct pipe_ctx * pipe_ctx,struct pixel_clk_params * pixel_clk_params)728 static void get_pixel_clock_parameters(
729 const struct pipe_ctx *pipe_ctx,
730 struct pixel_clk_params *pixel_clk_params)
731 {
732 const struct dc_stream_state *stream = pipe_ctx->stream;
733
734 /*TODO: is this halved for YCbCr 420? in that case we might want to move
735 * the pixel clock normalization for hdmi up to here instead of doing it
736 * in pll_adjust_pix_clk
737 */
738 pixel_clk_params->requested_pix_clk = stream->timing.pix_clk_khz;
739 pixel_clk_params->encoder_object_id = stream->sink->link->link_enc->id;
740 pixel_clk_params->signal_type = pipe_ctx->stream->signal;
741 pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1;
742 /* TODO: un-hardcode*/
743 pixel_clk_params->requested_sym_clk = LINK_RATE_LOW *
744 LINK_RATE_REF_FREQ_IN_KHZ;
745 pixel_clk_params->flags.ENABLE_SS = 0;
746 pixel_clk_params->color_depth =
747 stream->timing.display_color_depth;
748 pixel_clk_params->flags.DISPLAY_BLANKED = 1;
749 pixel_clk_params->flags.SUPPORT_YCBCR420 = (stream->timing.pixel_encoding ==
750 PIXEL_ENCODING_YCBCR420);
751 pixel_clk_params->pixel_encoding = stream->timing.pixel_encoding;
752 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422) {
753 pixel_clk_params->color_depth = COLOR_DEPTH_888;
754 }
755 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) {
756 pixel_clk_params->requested_pix_clk = pixel_clk_params->requested_pix_clk / 2;
757 }
758 }
759
dce110_resource_build_pipe_hw_param(struct pipe_ctx * pipe_ctx)760 void dce110_resource_build_pipe_hw_param(struct pipe_ctx *pipe_ctx)
761 {
762 get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params);
763 pipe_ctx->clock_source->funcs->get_pix_clk_dividers(
764 pipe_ctx->clock_source,
765 &pipe_ctx->stream_res.pix_clk_params,
766 &pipe_ctx->pll_settings);
767 resource_build_bit_depth_reduction_params(pipe_ctx->stream,
768 &pipe_ctx->stream->bit_depth_params);
769 pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->timing.pixel_encoding;
770 }
771
is_surface_pixel_format_supported(struct pipe_ctx * pipe_ctx,unsigned int underlay_idx)772 static bool is_surface_pixel_format_supported(struct pipe_ctx *pipe_ctx, unsigned int underlay_idx)
773 {
774 if (pipe_ctx->pipe_idx != underlay_idx)
775 return true;
776 if (!pipe_ctx->plane_state)
777 return false;
778 if (pipe_ctx->plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
779 return false;
780 return true;
781 }
782
build_mapped_resource(const struct dc * dc,struct dc_state * context,struct dc_stream_state * stream)783 static enum dc_status build_mapped_resource(
784 const struct dc *dc,
785 struct dc_state *context,
786 struct dc_stream_state *stream)
787 {
788 struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream);
789
790 if (!pipe_ctx)
791 return DC_ERROR_UNEXPECTED;
792
793 if (!is_surface_pixel_format_supported(pipe_ctx,
794 dc->res_pool->underlay_pipe_index))
795 return DC_SURFACE_PIXEL_FORMAT_UNSUPPORTED;
796
797 dce110_resource_build_pipe_hw_param(pipe_ctx);
798
799 /* TODO: validate audio ASIC caps, encoder */
800
801 resource_build_info_frame(pipe_ctx);
802
803 return DC_OK;
804 }
805
dce110_validate_bandwidth(struct dc * dc,struct dc_state * context)806 static bool dce110_validate_bandwidth(
807 struct dc *dc,
808 struct dc_state *context)
809 {
810 bool result = false;
811
812 DC_LOG_BANDWIDTH_CALCS(
813 "%s: start",
814 __func__);
815
816 if (bw_calcs(
817 dc->ctx,
818 dc->bw_dceip,
819 dc->bw_vbios,
820 context->res_ctx.pipe_ctx,
821 dc->res_pool->pipe_count,
822 &context->bw.dce))
823 result = true;
824
825 if (!result)
826 DC_LOG_BANDWIDTH_VALIDATION("%s: %dx%d@%d Bandwidth validation failed!\n",
827 __func__,
828 context->streams[0]->timing.h_addressable,
829 context->streams[0]->timing.v_addressable,
830 context->streams[0]->timing.pix_clk_khz);
831
832 if (memcmp(&dc->current_state->bw.dce,
833 &context->bw.dce, sizeof(context->bw.dce))) {
834
835 DC_LOG_BANDWIDTH_CALCS(
836 "%s: finish,\n"
837 "nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n"
838 "stutMark_b: %d stutMark_a: %d\n"
839 "nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n"
840 "stutMark_b: %d stutMark_a: %d\n"
841 "nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n"
842 "stutMark_b: %d stutMark_a: %d stutter_mode_enable: %d\n"
843 "cstate: %d pstate: %d nbpstate: %d sync: %d dispclk: %d\n"
844 "sclk: %d sclk_sleep: %d yclk: %d blackout_recovery_time_us: %d\n"
845 ,
846 __func__,
847 context->bw.dce.nbp_state_change_wm_ns[0].b_mark,
848 context->bw.dce.nbp_state_change_wm_ns[0].a_mark,
849 context->bw.dce.urgent_wm_ns[0].b_mark,
850 context->bw.dce.urgent_wm_ns[0].a_mark,
851 context->bw.dce.stutter_exit_wm_ns[0].b_mark,
852 context->bw.dce.stutter_exit_wm_ns[0].a_mark,
853 context->bw.dce.nbp_state_change_wm_ns[1].b_mark,
854 context->bw.dce.nbp_state_change_wm_ns[1].a_mark,
855 context->bw.dce.urgent_wm_ns[1].b_mark,
856 context->bw.dce.urgent_wm_ns[1].a_mark,
857 context->bw.dce.stutter_exit_wm_ns[1].b_mark,
858 context->bw.dce.stutter_exit_wm_ns[1].a_mark,
859 context->bw.dce.nbp_state_change_wm_ns[2].b_mark,
860 context->bw.dce.nbp_state_change_wm_ns[2].a_mark,
861 context->bw.dce.urgent_wm_ns[2].b_mark,
862 context->bw.dce.urgent_wm_ns[2].a_mark,
863 context->bw.dce.stutter_exit_wm_ns[2].b_mark,
864 context->bw.dce.stutter_exit_wm_ns[2].a_mark,
865 context->bw.dce.stutter_mode_enable,
866 context->bw.dce.cpuc_state_change_enable,
867 context->bw.dce.cpup_state_change_enable,
868 context->bw.dce.nbp_state_change_enable,
869 context->bw.dce.all_displays_in_sync,
870 context->bw.dce.dispclk_khz,
871 context->bw.dce.sclk_khz,
872 context->bw.dce.sclk_deep_sleep_khz,
873 context->bw.dce.yclk_khz,
874 context->bw.dce.blackout_recovery_time_us);
875 }
876 return result;
877 }
878
dce110_validate_plane(const struct dc_plane_state * plane_state,struct dc_caps * caps)879 enum dc_status dce110_validate_plane(const struct dc_plane_state *plane_state,
880 struct dc_caps *caps)
881 {
882 if (((plane_state->dst_rect.width * 2) < plane_state->src_rect.width) ||
883 ((plane_state->dst_rect.height * 2) < plane_state->src_rect.height))
884 return DC_FAIL_SURFACE_VALIDATE;
885
886 return DC_OK;
887 }
888
dce110_validate_surface_sets(struct dc_state * context)889 static bool dce110_validate_surface_sets(
890 struct dc_state *context)
891 {
892 int i, j;
893
894 for (i = 0; i < context->stream_count; i++) {
895 if (context->stream_status[i].plane_count == 0)
896 continue;
897
898 if (context->stream_status[i].plane_count > 2)
899 return false;
900
901 for (j = 0; j < context->stream_status[i].plane_count; j++) {
902 struct dc_plane_state *plane =
903 context->stream_status[i].plane_states[j];
904
905 /* underlay validation */
906 if (plane->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
907
908 if ((plane->src_rect.width > 1920 ||
909 plane->src_rect.height > 1080))
910 return false;
911
912 /* we don't have the logic to support underlay
913 * only yet so block the use case where we get
914 * NV12 plane as top layer
915 */
916 if (j == 0)
917 return false;
918
919 /* irrespective of plane format,
920 * stream should be RGB encoded
921 */
922 if (context->streams[i]->timing.pixel_encoding
923 != PIXEL_ENCODING_RGB)
924 return false;
925
926 }
927
928 }
929 }
930
931 return true;
932 }
933
dce110_validate_global(struct dc * dc,struct dc_state * context)934 enum dc_status dce110_validate_global(
935 struct dc *dc,
936 struct dc_state *context)
937 {
938 if (!dce110_validate_surface_sets(context))
939 return DC_FAIL_SURFACE_VALIDATE;
940
941 return DC_OK;
942 }
943
dce110_add_stream_to_ctx(struct dc * dc,struct dc_state * new_ctx,struct dc_stream_state * dc_stream)944 static enum dc_status dce110_add_stream_to_ctx(
945 struct dc *dc,
946 struct dc_state *new_ctx,
947 struct dc_stream_state *dc_stream)
948 {
949 enum dc_status result = DC_ERROR_UNEXPECTED;
950
951 result = resource_map_pool_resources(dc, new_ctx, dc_stream);
952
953 if (result == DC_OK)
954 result = resource_map_clock_resources(dc, new_ctx, dc_stream);
955
956
957 if (result == DC_OK)
958 result = build_mapped_resource(dc, new_ctx, dc_stream);
959
960 return result;
961 }
962
dce110_acquire_underlay(struct dc_state * context,const struct resource_pool * pool,struct dc_stream_state * stream)963 static struct pipe_ctx *dce110_acquire_underlay(
964 struct dc_state *context,
965 const struct resource_pool *pool,
966 struct dc_stream_state *stream)
967 {
968 struct dc *dc = stream->ctx->dc;
969 struct resource_context *res_ctx = &context->res_ctx;
970 unsigned int underlay_idx = pool->underlay_pipe_index;
971 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[underlay_idx];
972
973 if (res_ctx->pipe_ctx[underlay_idx].stream)
974 return NULL;
975
976 pipe_ctx->stream_res.tg = pool->timing_generators[underlay_idx];
977 pipe_ctx->plane_res.mi = pool->mis[underlay_idx];
978 /*pipe_ctx->plane_res.ipp = res_ctx->pool->ipps[underlay_idx];*/
979 pipe_ctx->plane_res.xfm = pool->transforms[underlay_idx];
980 pipe_ctx->stream_res.opp = pool->opps[underlay_idx];
981 pipe_ctx->pipe_idx = underlay_idx;
982
983 pipe_ctx->stream = stream;
984
985 if (!dc->current_state->res_ctx.pipe_ctx[underlay_idx].stream) {
986 struct tg_color black_color = {0};
987 struct dc_bios *dcb = dc->ctx->dc_bios;
988
989 dc->hwss.enable_display_power_gating(
990 dc,
991 pipe_ctx->stream_res.tg->inst,
992 dcb, PIPE_GATING_CONTROL_DISABLE);
993
994 /*
995 * This is for powering on underlay, so crtc does not
996 * need to be enabled
997 */
998
999 pipe_ctx->stream_res.tg->funcs->program_timing(pipe_ctx->stream_res.tg,
1000 &stream->timing,
1001 false);
1002
1003 pipe_ctx->stream_res.tg->funcs->enable_advanced_request(
1004 pipe_ctx->stream_res.tg,
1005 true,
1006 &stream->timing);
1007
1008 pipe_ctx->plane_res.mi->funcs->allocate_mem_input(pipe_ctx->plane_res.mi,
1009 stream->timing.h_total,
1010 stream->timing.v_total,
1011 stream->timing.pix_clk_khz,
1012 context->stream_count);
1013
1014 color_space_to_black_color(dc,
1015 COLOR_SPACE_YCBCR601, &black_color);
1016 pipe_ctx->stream_res.tg->funcs->set_blank_color(
1017 pipe_ctx->stream_res.tg,
1018 &black_color);
1019 }
1020
1021 return pipe_ctx;
1022 }
1023
dce110_destroy_resource_pool(struct resource_pool ** pool)1024 static void dce110_destroy_resource_pool(struct resource_pool **pool)
1025 {
1026 struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool);
1027
1028 destruct(dce110_pool);
1029 kfree(dce110_pool);
1030 *pool = NULL;
1031 }
1032
1033
1034 static const struct resource_funcs dce110_res_pool_funcs = {
1035 .destroy = dce110_destroy_resource_pool,
1036 .link_enc_create = dce110_link_encoder_create,
1037 .validate_bandwidth = dce110_validate_bandwidth,
1038 .validate_plane = dce110_validate_plane,
1039 .acquire_idle_pipe_for_layer = dce110_acquire_underlay,
1040 .add_stream_to_ctx = dce110_add_stream_to_ctx,
1041 .validate_global = dce110_validate_global
1042 };
1043
underlay_create(struct dc_context * ctx,struct resource_pool * pool)1044 static bool underlay_create(struct dc_context *ctx, struct resource_pool *pool)
1045 {
1046 struct dce110_timing_generator *dce110_tgv = kzalloc(sizeof(*dce110_tgv),
1047 GFP_KERNEL);
1048 struct dce_transform *dce110_xfmv = kzalloc(sizeof(*dce110_xfmv),
1049 GFP_KERNEL);
1050 struct dce_mem_input *dce110_miv = kzalloc(sizeof(*dce110_miv),
1051 GFP_KERNEL);
1052 struct dce110_opp *dce110_oppv = kzalloc(sizeof(*dce110_oppv),
1053 GFP_KERNEL);
1054
1055 if (!dce110_tgv || !dce110_xfmv || !dce110_miv || !dce110_oppv) {
1056 kfree(dce110_tgv);
1057 kfree(dce110_xfmv);
1058 kfree(dce110_miv);
1059 kfree(dce110_oppv);
1060 return false;
1061 }
1062
1063 dce110_opp_v_construct(dce110_oppv, ctx);
1064
1065 dce110_timing_generator_v_construct(dce110_tgv, ctx);
1066 dce110_mem_input_v_construct(dce110_miv, ctx);
1067 dce110_transform_v_construct(dce110_xfmv, ctx);
1068
1069 pool->opps[pool->pipe_count] = &dce110_oppv->base;
1070 pool->timing_generators[pool->pipe_count] = &dce110_tgv->base;
1071 pool->mis[pool->pipe_count] = &dce110_miv->base;
1072 pool->transforms[pool->pipe_count] = &dce110_xfmv->base;
1073 pool->pipe_count++;
1074
1075 /* update the public caps to indicate an underlay is available */
1076 ctx->dc->caps.max_slave_planes = 1;
1077 ctx->dc->caps.max_slave_planes = 1;
1078
1079 return true;
1080 }
1081
bw_calcs_data_update_from_pplib(struct dc * dc)1082 static void bw_calcs_data_update_from_pplib(struct dc *dc)
1083 {
1084 struct dm_pp_clock_levels clks = {0};
1085
1086 /*do system clock*/
1087 dm_pp_get_clock_levels_by_type(
1088 dc->ctx,
1089 DM_PP_CLOCK_TYPE_ENGINE_CLK,
1090 &clks);
1091 /* convert all the clock fro kHz to fix point mHz */
1092 dc->bw_vbios->high_sclk = bw_frc_to_fixed(
1093 clks.clocks_in_khz[clks.num_levels-1], 1000);
1094 dc->bw_vbios->mid1_sclk = bw_frc_to_fixed(
1095 clks.clocks_in_khz[clks.num_levels/8], 1000);
1096 dc->bw_vbios->mid2_sclk = bw_frc_to_fixed(
1097 clks.clocks_in_khz[clks.num_levels*2/8], 1000);
1098 dc->bw_vbios->mid3_sclk = bw_frc_to_fixed(
1099 clks.clocks_in_khz[clks.num_levels*3/8], 1000);
1100 dc->bw_vbios->mid4_sclk = bw_frc_to_fixed(
1101 clks.clocks_in_khz[clks.num_levels*4/8], 1000);
1102 dc->bw_vbios->mid5_sclk = bw_frc_to_fixed(
1103 clks.clocks_in_khz[clks.num_levels*5/8], 1000);
1104 dc->bw_vbios->mid6_sclk = bw_frc_to_fixed(
1105 clks.clocks_in_khz[clks.num_levels*6/8], 1000);
1106 dc->bw_vbios->low_sclk = bw_frc_to_fixed(
1107 clks.clocks_in_khz[0], 1000);
1108 dc->sclk_lvls = clks;
1109
1110 /*do display clock*/
1111 dm_pp_get_clock_levels_by_type(
1112 dc->ctx,
1113 DM_PP_CLOCK_TYPE_DISPLAY_CLK,
1114 &clks);
1115 dc->bw_vbios->high_voltage_max_dispclk = bw_frc_to_fixed(
1116 clks.clocks_in_khz[clks.num_levels-1], 1000);
1117 dc->bw_vbios->mid_voltage_max_dispclk = bw_frc_to_fixed(
1118 clks.clocks_in_khz[clks.num_levels>>1], 1000);
1119 dc->bw_vbios->low_voltage_max_dispclk = bw_frc_to_fixed(
1120 clks.clocks_in_khz[0], 1000);
1121
1122 /*do memory clock*/
1123 dm_pp_get_clock_levels_by_type(
1124 dc->ctx,
1125 DM_PP_CLOCK_TYPE_MEMORY_CLK,
1126 &clks);
1127
1128 dc->bw_vbios->low_yclk = bw_frc_to_fixed(
1129 clks.clocks_in_khz[0] * MEMORY_TYPE_MULTIPLIER, 1000);
1130 dc->bw_vbios->mid_yclk = bw_frc_to_fixed(
1131 clks.clocks_in_khz[clks.num_levels>>1] * MEMORY_TYPE_MULTIPLIER,
1132 1000);
1133 dc->bw_vbios->high_yclk = bw_frc_to_fixed(
1134 clks.clocks_in_khz[clks.num_levels-1] * MEMORY_TYPE_MULTIPLIER,
1135 1000);
1136 }
1137
dce110_resource_cap(struct hw_asic_id * asic_id)1138 const struct resource_caps *dce110_resource_cap(
1139 struct hw_asic_id *asic_id)
1140 {
1141 if (ASIC_REV_IS_STONEY(asic_id->hw_internal_rev))
1142 return &stoney_resource_cap;
1143 else
1144 return &carrizo_resource_cap;
1145 }
1146
construct(uint8_t num_virtual_links,struct dc * dc,struct dce110_resource_pool * pool,struct hw_asic_id asic_id)1147 static bool construct(
1148 uint8_t num_virtual_links,
1149 struct dc *dc,
1150 struct dce110_resource_pool *pool,
1151 struct hw_asic_id asic_id)
1152 {
1153 unsigned int i;
1154 struct dc_context *ctx = dc->ctx;
1155 struct dc_firmware_info info;
1156 struct dc_bios *bp;
1157 struct dm_pp_static_clock_info static_clk_info = {0};
1158
1159 ctx->dc_bios->regs = &bios_regs;
1160
1161 pool->base.res_cap = dce110_resource_cap(&ctx->asic_id);
1162 pool->base.funcs = &dce110_res_pool_funcs;
1163
1164 /*************************************************
1165 * Resource + asic cap harcoding *
1166 *************************************************/
1167
1168 pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
1169 pool->base.underlay_pipe_index = pool->base.pipe_count;
1170 pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator;
1171 dc->caps.max_downscale_ratio = 150;
1172 dc->caps.i2c_speed_in_khz = 100;
1173 dc->caps.max_cursor_size = 128;
1174 dc->caps.is_apu = true;
1175
1176 /*************************************************
1177 * Create resources *
1178 *************************************************/
1179
1180 bp = ctx->dc_bios;
1181
1182 if ((bp->funcs->get_firmware_info(bp, &info) == BP_RESULT_OK) &&
1183 info.external_clock_source_frequency_for_dp != 0) {
1184 pool->base.dp_clock_source =
1185 dce110_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true);
1186
1187 pool->base.clock_sources[0] =
1188 dce110_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0,
1189 &clk_src_regs[0], false);
1190 pool->base.clock_sources[1] =
1191 dce110_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1,
1192 &clk_src_regs[1], false);
1193
1194 pool->base.clk_src_count = 2;
1195
1196 /* TODO: find out if CZ support 3 PLLs */
1197 }
1198
1199 if (pool->base.dp_clock_source == NULL) {
1200 dm_error("DC: failed to create dp clock source!\n");
1201 BREAK_TO_DEBUGGER();
1202 goto res_create_fail;
1203 }
1204
1205 for (i = 0; i < pool->base.clk_src_count; i++) {
1206 if (pool->base.clock_sources[i] == NULL) {
1207 dm_error("DC: failed to create clock sources!\n");
1208 BREAK_TO_DEBUGGER();
1209 goto res_create_fail;
1210 }
1211 }
1212
1213 pool->base.dccg = dce110_dccg_create(ctx,
1214 &disp_clk_regs,
1215 &disp_clk_shift,
1216 &disp_clk_mask);
1217 if (pool->base.dccg == NULL) {
1218 dm_error("DC: failed to create display clock!\n");
1219 BREAK_TO_DEBUGGER();
1220 goto res_create_fail;
1221 }
1222
1223 pool->base.dmcu = dce_dmcu_create(ctx,
1224 &dmcu_regs,
1225 &dmcu_shift,
1226 &dmcu_mask);
1227 if (pool->base.dmcu == NULL) {
1228 dm_error("DC: failed to create dmcu!\n");
1229 BREAK_TO_DEBUGGER();
1230 goto res_create_fail;
1231 }
1232
1233 pool->base.abm = dce_abm_create(ctx,
1234 &abm_regs,
1235 &abm_shift,
1236 &abm_mask);
1237 if (pool->base.abm == NULL) {
1238 dm_error("DC: failed to create abm!\n");
1239 BREAK_TO_DEBUGGER();
1240 goto res_create_fail;
1241 }
1242
1243 /* get static clock information for PPLIB or firmware, save
1244 * max_clock_state
1245 */
1246 if (dm_pp_get_static_clocks(ctx, &static_clk_info))
1247 pool->base.dccg->max_clks_state =
1248 static_clk_info.max_clocks_state;
1249
1250 {
1251 struct irq_service_init_data init_data;
1252 init_data.ctx = dc->ctx;
1253 pool->base.irqs = dal_irq_service_dce110_create(&init_data);
1254 if (!pool->base.irqs)
1255 goto res_create_fail;
1256 }
1257
1258 for (i = 0; i < pool->base.pipe_count; i++) {
1259 pool->base.timing_generators[i] = dce110_timing_generator_create(
1260 ctx, i, &dce110_tg_offsets[i]);
1261 if (pool->base.timing_generators[i] == NULL) {
1262 BREAK_TO_DEBUGGER();
1263 dm_error("DC: failed to create tg!\n");
1264 goto res_create_fail;
1265 }
1266
1267 pool->base.mis[i] = dce110_mem_input_create(ctx, i);
1268 if (pool->base.mis[i] == NULL) {
1269 BREAK_TO_DEBUGGER();
1270 dm_error(
1271 "DC: failed to create memory input!\n");
1272 goto res_create_fail;
1273 }
1274
1275 pool->base.ipps[i] = dce110_ipp_create(ctx, i);
1276 if (pool->base.ipps[i] == NULL) {
1277 BREAK_TO_DEBUGGER();
1278 dm_error(
1279 "DC: failed to create input pixel processor!\n");
1280 goto res_create_fail;
1281 }
1282
1283 pool->base.transforms[i] = dce110_transform_create(ctx, i);
1284 if (pool->base.transforms[i] == NULL) {
1285 BREAK_TO_DEBUGGER();
1286 dm_error(
1287 "DC: failed to create transform!\n");
1288 goto res_create_fail;
1289 }
1290
1291 pool->base.opps[i] = dce110_opp_create(ctx, i);
1292 if (pool->base.opps[i] == NULL) {
1293 BREAK_TO_DEBUGGER();
1294 dm_error(
1295 "DC: failed to create output pixel processor!\n");
1296 goto res_create_fail;
1297 }
1298
1299 pool->base.engines[i] = dce110_aux_engine_create(ctx, i);
1300 if (pool->base.engines[i] == NULL) {
1301 BREAK_TO_DEBUGGER();
1302 dm_error(
1303 "DC:failed to create aux engine!!\n");
1304 goto res_create_fail;
1305 }
1306 }
1307
1308 dc->fbc_compressor = dce110_compressor_create(ctx);
1309
1310 if (!underlay_create(ctx, &pool->base))
1311 goto res_create_fail;
1312
1313 if (!resource_construct(num_virtual_links, dc, &pool->base,
1314 &res_create_funcs))
1315 goto res_create_fail;
1316
1317 /* Create hardware sequencer */
1318 dce110_hw_sequencer_construct(dc);
1319
1320 dc->caps.max_planes = pool->base.pipe_count;
1321
1322 bw_calcs_init(dc->bw_dceip, dc->bw_vbios, dc->ctx->asic_id);
1323
1324 bw_calcs_data_update_from_pplib(dc);
1325
1326 return true;
1327
1328 res_create_fail:
1329 destruct(pool);
1330 return false;
1331 }
1332
dce110_create_resource_pool(uint8_t num_virtual_links,struct dc * dc,struct hw_asic_id asic_id)1333 struct resource_pool *dce110_create_resource_pool(
1334 uint8_t num_virtual_links,
1335 struct dc *dc,
1336 struct hw_asic_id asic_id)
1337 {
1338 struct dce110_resource_pool *pool =
1339 kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL);
1340
1341 if (!pool)
1342 return NULL;
1343
1344 if (construct(num_virtual_links, dc, pool, asic_id))
1345 return &pool->base;
1346
1347 BREAK_TO_DEBUGGER();
1348 return NULL;
1349 }
1350
