1 /*
2 * Copyright 2012-15 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25 #include "dm_services.h"
26
27 #include "link_encoder.h"
28 #include "stream_encoder.h"
29
30 #include "resource.h"
31 #include "include/irq_service_interface.h"
32 #include "../virtual/virtual_stream_encoder.h"
33 #include "dce110/dce110_resource.h"
34 #include "dce110/dce110_timing_generator.h"
35 #include "irq/dce110/irq_service_dce110.h"
36 #include "dce/dce_link_encoder.h"
37 #include "dce/dce_stream_encoder.h"
38
39 #include "dce/dce_mem_input.h"
40 #include "dce/dce_ipp.h"
41 #include "dce/dce_transform.h"
42 #include "dce/dce_opp.h"
43 #include "dce/dce_clocks.h"
44 #include "dce/dce_clock_source.h"
45 #include "dce/dce_audio.h"
46 #include "dce/dce_hwseq.h"
47 #include "dce100/dce100_hw_sequencer.h"
48
49 #include "reg_helper.h"
50
51 #include "dce/dce_10_0_d.h"
52 #include "dce/dce_10_0_sh_mask.h"
53
54 #include "dce/dce_dmcu.h"
55 #include "dce/dce_aux.h"
56 #include "dce/dce_abm.h"
57
58 #ifndef mmMC_HUB_RDREQ_DMIF_LIMIT
59 #include "gmc/gmc_8_2_d.h"
60 #include "gmc/gmc_8_2_sh_mask.h"
61 #endif
62
63 #ifndef mmDP_DPHY_INTERNAL_CTRL
64 #define mmDP_DPHY_INTERNAL_CTRL 0x4aa7
65 #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x4aa7
66 #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x4ba7
67 #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x4ca7
68 #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x4da7
69 #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x4ea7
70 #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x4fa7
71 #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x54a7
72 #define mmDP7_DP_DPHY_INTERNAL_CTRL 0x56a7
73 #define mmDP8_DP_DPHY_INTERNAL_CTRL 0x57a7
74 #endif
75
76 #ifndef mmBIOS_SCRATCH_2
77 #define mmBIOS_SCRATCH_2 0x05CB
78 #define mmBIOS_SCRATCH_6 0x05CF
79 #endif
80
81 #ifndef mmDP_DPHY_BS_SR_SWAP_CNTL
82 #define mmDP_DPHY_BS_SR_SWAP_CNTL 0x4ADC
83 #define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL 0x4ADC
84 #define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL 0x4BDC
85 #define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL 0x4CDC
86 #define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL 0x4DDC
87 #define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL 0x4EDC
88 #define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL 0x4FDC
89 #define mmDP6_DP_DPHY_BS_SR_SWAP_CNTL 0x54DC
90 #endif
91
92 #ifndef mmDP_DPHY_FAST_TRAINING
93 #define mmDP_DPHY_FAST_TRAINING 0x4ABC
94 #define mmDP0_DP_DPHY_FAST_TRAINING 0x4ABC
95 #define mmDP1_DP_DPHY_FAST_TRAINING 0x4BBC
96 #define mmDP2_DP_DPHY_FAST_TRAINING 0x4CBC
97 #define mmDP3_DP_DPHY_FAST_TRAINING 0x4DBC
98 #define mmDP4_DP_DPHY_FAST_TRAINING 0x4EBC
99 #define mmDP5_DP_DPHY_FAST_TRAINING 0x4FBC
100 #define mmDP6_DP_DPHY_FAST_TRAINING 0x54BC
101 #endif
102
103 static const struct dce110_timing_generator_offsets dce100_tg_offsets[] = {
104 {
105 .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL),
106 .dcp = (mmDCP0_GRPH_CONTROL - mmGRPH_CONTROL),
107 },
108 {
109 .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL),
110 .dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL),
111 },
112 {
113 .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL),
114 .dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL),
115 },
116 {
117 .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL),
118 .dcp = (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL),
119 },
120 {
121 .crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC_CONTROL),
122 .dcp = (mmDCP4_GRPH_CONTROL - mmGRPH_CONTROL),
123 },
124 {
125 .crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC_CONTROL),
126 .dcp = (mmDCP5_GRPH_CONTROL - mmGRPH_CONTROL),
127 }
128 };
129
130 /* set register offset */
131 #define SR(reg_name)\
132 .reg_name = mm ## reg_name
133
134 /* set register offset with instance */
135 #define SRI(reg_name, block, id)\
136 .reg_name = mm ## block ## id ## _ ## reg_name
137
138
139 static const struct dccg_registers disp_clk_regs = {
140 CLK_COMMON_REG_LIST_DCE_BASE()
141 };
142
143 static const struct dccg_shift disp_clk_shift = {
144 CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
145 };
146
147 static const struct dccg_mask disp_clk_mask = {
148 CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
149 };
150
151 #define ipp_regs(id)\
152 [id] = {\
153 IPP_DCE100_REG_LIST_DCE_BASE(id)\
154 }
155
156 static const struct dce_ipp_registers ipp_regs[] = {
157 ipp_regs(0),
158 ipp_regs(1),
159 ipp_regs(2),
160 ipp_regs(3),
161 ipp_regs(4),
162 ipp_regs(5)
163 };
164
165 static const struct dce_ipp_shift ipp_shift = {
166 IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
167 };
168
169 static const struct dce_ipp_mask ipp_mask = {
170 IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
171 };
172
173 #define transform_regs(id)\
174 [id] = {\
175 XFM_COMMON_REG_LIST_DCE100(id)\
176 }
177
178 static const struct dce_transform_registers xfm_regs[] = {
179 transform_regs(0),
180 transform_regs(1),
181 transform_regs(2),
182 transform_regs(3),
183 transform_regs(4),
184 transform_regs(5)
185 };
186
187 static const struct dce_transform_shift xfm_shift = {
188 XFM_COMMON_MASK_SH_LIST_DCE110(__SHIFT)
189 };
190
191 static const struct dce_transform_mask xfm_mask = {
192 XFM_COMMON_MASK_SH_LIST_DCE110(_MASK)
193 };
194
195 #define aux_regs(id)\
196 [id] = {\
197 AUX_REG_LIST(id)\
198 }
199
200 static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = {
201 aux_regs(0),
202 aux_regs(1),
203 aux_regs(2),
204 aux_regs(3),
205 aux_regs(4),
206 aux_regs(5)
207 };
208
209 #define hpd_regs(id)\
210 [id] = {\
211 HPD_REG_LIST(id)\
212 }
213
214 static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = {
215 hpd_regs(0),
216 hpd_regs(1),
217 hpd_regs(2),
218 hpd_regs(3),
219 hpd_regs(4),
220 hpd_regs(5)
221 };
222
223 #define link_regs(id)\
224 [id] = {\
225 LE_DCE100_REG_LIST(id)\
226 }
227
228 static const struct dce110_link_enc_registers link_enc_regs[] = {
229 link_regs(0),
230 link_regs(1),
231 link_regs(2),
232 link_regs(3),
233 link_regs(4),
234 link_regs(5),
235 link_regs(6),
236 };
237
238 #define stream_enc_regs(id)\
239 [id] = {\
240 SE_COMMON_REG_LIST_DCE_BASE(id),\
241 .AFMT_CNTL = 0,\
242 }
243
244 static const struct dce110_stream_enc_registers stream_enc_regs[] = {
245 stream_enc_regs(0),
246 stream_enc_regs(1),
247 stream_enc_regs(2),
248 stream_enc_regs(3),
249 stream_enc_regs(4),
250 stream_enc_regs(5),
251 stream_enc_regs(6)
252 };
253
254 static const struct dce_stream_encoder_shift se_shift = {
255 SE_COMMON_MASK_SH_LIST_DCE80_100(__SHIFT)
256 };
257
258 static const struct dce_stream_encoder_mask se_mask = {
259 SE_COMMON_MASK_SH_LIST_DCE80_100(_MASK)
260 };
261
262 #define opp_regs(id)\
263 [id] = {\
264 OPP_DCE_100_REG_LIST(id),\
265 }
266
267 static const struct dce_opp_registers opp_regs[] = {
268 opp_regs(0),
269 opp_regs(1),
270 opp_regs(2),
271 opp_regs(3),
272 opp_regs(4),
273 opp_regs(5)
274 };
275
276 static const struct dce_opp_shift opp_shift = {
277 OPP_COMMON_MASK_SH_LIST_DCE_100(__SHIFT)
278 };
279
280 static const struct dce_opp_mask opp_mask = {
281 OPP_COMMON_MASK_SH_LIST_DCE_100(_MASK)
282 };
283 #define aux_engine_regs(id)\
284 [id] = {\
285 AUX_COMMON_REG_LIST(id), \
286 .AUX_RESET_MASK = 0 \
287 }
288
289 static const struct dce110_aux_registers aux_engine_regs[] = {
290 aux_engine_regs(0),
291 aux_engine_regs(1),
292 aux_engine_regs(2),
293 aux_engine_regs(3),
294 aux_engine_regs(4),
295 aux_engine_regs(5)
296 };
297
298 #define audio_regs(id)\
299 [id] = {\
300 AUD_COMMON_REG_LIST(id)\
301 }
302
303 static const struct dce_audio_registers audio_regs[] = {
304 audio_regs(0),
305 audio_regs(1),
306 audio_regs(2),
307 audio_regs(3),
308 audio_regs(4),
309 audio_regs(5),
310 audio_regs(6),
311 };
312
313 static const struct dce_audio_shift audio_shift = {
314 AUD_COMMON_MASK_SH_LIST(__SHIFT)
315 };
316
317 static const struct dce_aduio_mask audio_mask = {
318 AUD_COMMON_MASK_SH_LIST(_MASK)
319 };
320
321 #define clk_src_regs(id)\
322 [id] = {\
323 CS_COMMON_REG_LIST_DCE_100_110(id),\
324 }
325
326 static const struct dce110_clk_src_regs clk_src_regs[] = {
327 clk_src_regs(0),
328 clk_src_regs(1),
329 clk_src_regs(2)
330 };
331
332 static const struct dce110_clk_src_shift cs_shift = {
333 CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
334 };
335
336 static const struct dce110_clk_src_mask cs_mask = {
337 CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
338 };
339
340 static const struct dce_dmcu_registers dmcu_regs = {
341 DMCU_DCE110_COMMON_REG_LIST()
342 };
343
344 static const struct dce_dmcu_shift dmcu_shift = {
345 DMCU_MASK_SH_LIST_DCE110(__SHIFT)
346 };
347
348 static const struct dce_dmcu_mask dmcu_mask = {
349 DMCU_MASK_SH_LIST_DCE110(_MASK)
350 };
351
352 static const struct dce_abm_registers abm_regs = {
353 ABM_DCE110_COMMON_REG_LIST()
354 };
355
356 static const struct dce_abm_shift abm_shift = {
357 ABM_MASK_SH_LIST_DCE110(__SHIFT)
358 };
359
360 static const struct dce_abm_mask abm_mask = {
361 ABM_MASK_SH_LIST_DCE110(_MASK)
362 };
363
364 #define DCFE_MEM_PWR_CTRL_REG_BASE 0x1b03
365
366 static const struct bios_registers bios_regs = {
367 .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6
368 };
369
370 static const struct resource_caps res_cap = {
371 .num_timing_generator = 6,
372 .num_audio = 6,
373 .num_stream_encoder = 6,
374 .num_pll = 3
375 };
376
377 #define CTX ctx
378 #define REG(reg) mm ## reg
379
380 #ifndef mmCC_DC_HDMI_STRAPS
381 #define mmCC_DC_HDMI_STRAPS 0x1918
382 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE_MASK 0x40
383 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE__SHIFT 0x6
384 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER_MASK 0x700
385 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER__SHIFT 0x8
386 #endif
387
read_dce_straps(struct dc_context * ctx,struct resource_straps * straps)388 static void read_dce_straps(
389 struct dc_context *ctx,
390 struct resource_straps *straps)
391 {
392 REG_GET_2(CC_DC_HDMI_STRAPS,
393 HDMI_DISABLE, &straps->hdmi_disable,
394 AUDIO_STREAM_NUMBER, &straps->audio_stream_number);
395
396 REG_GET(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO, &straps->dc_pinstraps_audio);
397 }
398
create_audio(struct dc_context * ctx,unsigned int inst)399 static struct audio *create_audio(
400 struct dc_context *ctx, unsigned int inst)
401 {
402 return dce_audio_create(ctx, inst,
403 &audio_regs[inst], &audio_shift, &audio_mask);
404 }
405
dce100_timing_generator_create(struct dc_context * ctx,uint32_t instance,const struct dce110_timing_generator_offsets * offsets)406 static struct timing_generator *dce100_timing_generator_create(
407 struct dc_context *ctx,
408 uint32_t instance,
409 const struct dce110_timing_generator_offsets *offsets)
410 {
411 struct dce110_timing_generator *tg110 =
412 kzalloc(sizeof(struct dce110_timing_generator), GFP_KERNEL);
413
414 if (!tg110)
415 return NULL;
416
417 dce110_timing_generator_construct(tg110, ctx, instance, offsets);
418 return &tg110->base;
419 }
420
dce100_stream_encoder_create(enum engine_id eng_id,struct dc_context * ctx)421 static struct stream_encoder *dce100_stream_encoder_create(
422 enum engine_id eng_id,
423 struct dc_context *ctx)
424 {
425 struct dce110_stream_encoder *enc110 =
426 kzalloc(sizeof(struct dce110_stream_encoder), GFP_KERNEL);
427
428 if (!enc110)
429 return NULL;
430
431 dce110_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id,
432 &stream_enc_regs[eng_id], &se_shift, &se_mask);
433 return &enc110->base;
434 }
435
436 #define SRII(reg_name, block, id)\
437 .reg_name[id] = mm ## block ## id ## _ ## reg_name
438
439 static const struct dce_hwseq_registers hwseq_reg = {
440 HWSEQ_DCE10_REG_LIST()
441 };
442
443 static const struct dce_hwseq_shift hwseq_shift = {
444 HWSEQ_DCE10_MASK_SH_LIST(__SHIFT)
445 };
446
447 static const struct dce_hwseq_mask hwseq_mask = {
448 HWSEQ_DCE10_MASK_SH_LIST(_MASK)
449 };
450
dce100_hwseq_create(struct dc_context * ctx)451 static struct dce_hwseq *dce100_hwseq_create(
452 struct dc_context *ctx)
453 {
454 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
455
456 if (hws) {
457 hws->ctx = ctx;
458 hws->regs = &hwseq_reg;
459 hws->shifts = &hwseq_shift;
460 hws->masks = &hwseq_mask;
461 }
462 return hws;
463 }
464
465 static const struct resource_create_funcs res_create_funcs = {
466 .read_dce_straps = read_dce_straps,
467 .create_audio = create_audio,
468 .create_stream_encoder = dce100_stream_encoder_create,
469 .create_hwseq = dce100_hwseq_create,
470 };
471
472 #define mi_inst_regs(id) { \
473 MI_DCE8_REG_LIST(id), \
474 .MC_HUB_RDREQ_DMIF_LIMIT = mmMC_HUB_RDREQ_DMIF_LIMIT \
475 }
476 static const struct dce_mem_input_registers mi_regs[] = {
477 mi_inst_regs(0),
478 mi_inst_regs(1),
479 mi_inst_regs(2),
480 mi_inst_regs(3),
481 mi_inst_regs(4),
482 mi_inst_regs(5),
483 };
484
485 static const struct dce_mem_input_shift mi_shifts = {
486 MI_DCE8_MASK_SH_LIST(__SHIFT),
487 .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE__SHIFT
488 };
489
490 static const struct dce_mem_input_mask mi_masks = {
491 MI_DCE8_MASK_SH_LIST(_MASK),
492 .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE_MASK
493 };
494
dce100_mem_input_create(struct dc_context * ctx,uint32_t inst)495 static struct mem_input *dce100_mem_input_create(
496 struct dc_context *ctx,
497 uint32_t inst)
498 {
499 struct dce_mem_input *dce_mi = kzalloc(sizeof(struct dce_mem_input),
500 GFP_KERNEL);
501
502 if (!dce_mi) {
503 BREAK_TO_DEBUGGER();
504 return NULL;
505 }
506
507 dce_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks);
508 dce_mi->wa.single_head_rdreq_dmif_limit = 2;
509 return &dce_mi->base;
510 }
511
dce100_transform_destroy(struct transform ** xfm)512 static void dce100_transform_destroy(struct transform **xfm)
513 {
514 kfree(TO_DCE_TRANSFORM(*xfm));
515 *xfm = NULL;
516 }
517
dce100_transform_create(struct dc_context * ctx,uint32_t inst)518 static struct transform *dce100_transform_create(
519 struct dc_context *ctx,
520 uint32_t inst)
521 {
522 struct dce_transform *transform =
523 kzalloc(sizeof(struct dce_transform), GFP_KERNEL);
524
525 if (!transform)
526 return NULL;
527
528 dce_transform_construct(transform, ctx, inst,
529 &xfm_regs[inst], &xfm_shift, &xfm_mask);
530 return &transform->base;
531 }
532
dce100_ipp_create(struct dc_context * ctx,uint32_t inst)533 static struct input_pixel_processor *dce100_ipp_create(
534 struct dc_context *ctx, uint32_t inst)
535 {
536 struct dce_ipp *ipp = kzalloc(sizeof(struct dce_ipp), GFP_KERNEL);
537
538 if (!ipp) {
539 BREAK_TO_DEBUGGER();
540 return NULL;
541 }
542
543 dce_ipp_construct(ipp, ctx, inst,
544 &ipp_regs[inst], &ipp_shift, &ipp_mask);
545 return &ipp->base;
546 }
547
548 static const struct encoder_feature_support link_enc_feature = {
549 .max_hdmi_deep_color = COLOR_DEPTH_121212,
550 .max_hdmi_pixel_clock = 300000,
551 .flags.bits.IS_HBR2_CAPABLE = true,
552 .flags.bits.IS_TPS3_CAPABLE = true,
553 .flags.bits.IS_YCBCR_CAPABLE = true
554 };
555
dce100_link_encoder_create(const struct encoder_init_data * enc_init_data)556 struct link_encoder *dce100_link_encoder_create(
557 const struct encoder_init_data *enc_init_data)
558 {
559 struct dce110_link_encoder *enc110 =
560 kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL);
561
562 if (!enc110)
563 return NULL;
564
565 dce110_link_encoder_construct(enc110,
566 enc_init_data,
567 &link_enc_feature,
568 &link_enc_regs[enc_init_data->transmitter],
569 &link_enc_aux_regs[enc_init_data->channel - 1],
570 &link_enc_hpd_regs[enc_init_data->hpd_source]);
571 return &enc110->base;
572 }
573
dce100_opp_create(struct dc_context * ctx,uint32_t inst)574 struct output_pixel_processor *dce100_opp_create(
575 struct dc_context *ctx,
576 uint32_t inst)
577 {
578 struct dce110_opp *opp =
579 kzalloc(sizeof(struct dce110_opp), GFP_KERNEL);
580
581 if (!opp)
582 return NULL;
583
584 dce110_opp_construct(opp,
585 ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask);
586 return &opp->base;
587 }
588
dce100_aux_engine_create(struct dc_context * ctx,uint32_t inst)589 struct aux_engine *dce100_aux_engine_create(
590 struct dc_context *ctx,
591 uint32_t inst)
592 {
593 struct aux_engine_dce110 *aux_engine =
594 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
595
596 if (!aux_engine)
597 return NULL;
598
599 dce110_aux_engine_construct(aux_engine, ctx, inst,
600 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
601 &aux_engine_regs[inst]);
602
603 return &aux_engine->base;
604 }
605
dce100_clock_source_create(struct dc_context * ctx,struct dc_bios * bios,enum clock_source_id id,const struct dce110_clk_src_regs * regs,bool dp_clk_src)606 struct clock_source *dce100_clock_source_create(
607 struct dc_context *ctx,
608 struct dc_bios *bios,
609 enum clock_source_id id,
610 const struct dce110_clk_src_regs *regs,
611 bool dp_clk_src)
612 {
613 struct dce110_clk_src *clk_src =
614 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
615
616 if (!clk_src)
617 return NULL;
618
619 if (dce110_clk_src_construct(clk_src, ctx, bios, id,
620 regs, &cs_shift, &cs_mask)) {
621 clk_src->base.dp_clk_src = dp_clk_src;
622 return &clk_src->base;
623 }
624
625 BREAK_TO_DEBUGGER();
626 return NULL;
627 }
628
dce100_clock_source_destroy(struct clock_source ** clk_src)629 void dce100_clock_source_destroy(struct clock_source **clk_src)
630 {
631 kfree(TO_DCE110_CLK_SRC(*clk_src));
632 *clk_src = NULL;
633 }
634
destruct(struct dce110_resource_pool * pool)635 static void destruct(struct dce110_resource_pool *pool)
636 {
637 unsigned int i;
638
639 for (i = 0; i < pool->base.pipe_count; i++) {
640 if (pool->base.opps[i] != NULL)
641 dce110_opp_destroy(&pool->base.opps[i]);
642
643 if (pool->base.transforms[i] != NULL)
644 dce100_transform_destroy(&pool->base.transforms[i]);
645
646 if (pool->base.ipps[i] != NULL)
647 dce_ipp_destroy(&pool->base.ipps[i]);
648
649 if (pool->base.mis[i] != NULL) {
650 kfree(TO_DCE_MEM_INPUT(pool->base.mis[i]));
651 pool->base.mis[i] = NULL;
652 }
653
654 if (pool->base.timing_generators[i] != NULL) {
655 kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i]));
656 pool->base.timing_generators[i] = NULL;
657 }
658
659 if (pool->base.engines[i] != NULL)
660 dce110_engine_destroy(&pool->base.engines[i]);
661
662 }
663
664 for (i = 0; i < pool->base.stream_enc_count; i++) {
665 if (pool->base.stream_enc[i] != NULL)
666 kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i]));
667 }
668
669 for (i = 0; i < pool->base.clk_src_count; i++) {
670 if (pool->base.clock_sources[i] != NULL)
671 dce100_clock_source_destroy(&pool->base.clock_sources[i]);
672 }
673
674 if (pool->base.dp_clock_source != NULL)
675 dce100_clock_source_destroy(&pool->base.dp_clock_source);
676
677 for (i = 0; i < pool->base.audio_count; i++) {
678 if (pool->base.audios[i] != NULL)
679 dce_aud_destroy(&pool->base.audios[i]);
680 }
681
682 if (pool->base.dccg != NULL)
683 dce_dccg_destroy(&pool->base.dccg);
684
685 if (pool->base.abm != NULL)
686 dce_abm_destroy(&pool->base.abm);
687
688 if (pool->base.dmcu != NULL)
689 dce_dmcu_destroy(&pool->base.dmcu);
690
691 if (pool->base.irqs != NULL)
692 dal_irq_service_destroy(&pool->base.irqs);
693 }
694
build_mapped_resource(const struct dc * dc,struct dc_state * context,struct dc_stream_state * stream)695 static enum dc_status build_mapped_resource(
696 const struct dc *dc,
697 struct dc_state *context,
698 struct dc_stream_state *stream)
699 {
700 struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream);
701
702 if (!pipe_ctx)
703 return DC_ERROR_UNEXPECTED;
704
705 dce110_resource_build_pipe_hw_param(pipe_ctx);
706
707 resource_build_info_frame(pipe_ctx);
708
709 return DC_OK;
710 }
711
dce100_validate_bandwidth(struct dc * dc,struct dc_state * context)712 bool dce100_validate_bandwidth(
713 struct dc *dc,
714 struct dc_state *context)
715 {
716 int i;
717 bool at_least_one_pipe = false;
718
719 for (i = 0; i < dc->res_pool->pipe_count; i++) {
720 if (context->res_ctx.pipe_ctx[i].stream)
721 at_least_one_pipe = true;
722 }
723
724 if (at_least_one_pipe) {
725 /* TODO implement when needed but for now hardcode max value*/
726 context->bw.dce.dispclk_khz = 681000;
727 context->bw.dce.yclk_khz = 250000 * MEMORY_TYPE_MULTIPLIER;
728 } else {
729 context->bw.dce.dispclk_khz = 0;
730 context->bw.dce.yclk_khz = 0;
731 }
732
733 return true;
734 }
735
dce100_validate_surface_sets(struct dc_state * context)736 static bool dce100_validate_surface_sets(
737 struct dc_state *context)
738 {
739 int i;
740
741 for (i = 0; i < context->stream_count; i++) {
742 if (context->stream_status[i].plane_count == 0)
743 continue;
744
745 if (context->stream_status[i].plane_count > 1)
746 return false;
747
748 if (context->stream_status[i].plane_states[0]->format
749 >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
750 return false;
751 }
752
753 return true;
754 }
755
dce100_validate_global(struct dc * dc,struct dc_state * context)756 enum dc_status dce100_validate_global(
757 struct dc *dc,
758 struct dc_state *context)
759 {
760 if (!dce100_validate_surface_sets(context))
761 return DC_FAIL_SURFACE_VALIDATE;
762
763 return DC_OK;
764 }
765
dce100_add_stream_to_ctx(struct dc * dc,struct dc_state * new_ctx,struct dc_stream_state * dc_stream)766 enum dc_status dce100_add_stream_to_ctx(
767 struct dc *dc,
768 struct dc_state *new_ctx,
769 struct dc_stream_state *dc_stream)
770 {
771 enum dc_status result = DC_ERROR_UNEXPECTED;
772
773 result = resource_map_pool_resources(dc, new_ctx, dc_stream);
774
775 if (result == DC_OK)
776 result = resource_map_clock_resources(dc, new_ctx, dc_stream);
777
778 if (result == DC_OK)
779 result = build_mapped_resource(dc, new_ctx, dc_stream);
780
781 return result;
782 }
783
dce100_destroy_resource_pool(struct resource_pool ** pool)784 static void dce100_destroy_resource_pool(struct resource_pool **pool)
785 {
786 struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool);
787
788 destruct(dce110_pool);
789 kfree(dce110_pool);
790 *pool = NULL;
791 }
792
dce100_validate_plane(const struct dc_plane_state * plane_state,struct dc_caps * caps)793 enum dc_status dce100_validate_plane(const struct dc_plane_state *plane_state, struct dc_caps *caps)
794 {
795
796 if (plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
797 return DC_OK;
798
799 return DC_FAIL_SURFACE_VALIDATE;
800 }
801
802 static const struct resource_funcs dce100_res_pool_funcs = {
803 .destroy = dce100_destroy_resource_pool,
804 .link_enc_create = dce100_link_encoder_create,
805 .validate_bandwidth = dce100_validate_bandwidth,
806 .validate_plane = dce100_validate_plane,
807 .add_stream_to_ctx = dce100_add_stream_to_ctx,
808 .validate_global = dce100_validate_global
809 };
810
construct(uint8_t num_virtual_links,struct dc * dc,struct dce110_resource_pool * pool)811 static bool construct(
812 uint8_t num_virtual_links,
813 struct dc *dc,
814 struct dce110_resource_pool *pool)
815 {
816 unsigned int i;
817 struct dc_context *ctx = dc->ctx;
818 struct dc_firmware_info info;
819 struct dc_bios *bp;
820 struct dm_pp_static_clock_info static_clk_info = {0};
821
822 ctx->dc_bios->regs = &bios_regs;
823
824 pool->base.res_cap = &res_cap;
825 pool->base.funcs = &dce100_res_pool_funcs;
826 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
827
828 bp = ctx->dc_bios;
829
830 if ((bp->funcs->get_firmware_info(bp, &info) == BP_RESULT_OK) &&
831 info.external_clock_source_frequency_for_dp != 0) {
832 pool->base.dp_clock_source =
833 dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true);
834
835 pool->base.clock_sources[0] =
836 dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], false);
837 pool->base.clock_sources[1] =
838 dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
839 pool->base.clock_sources[2] =
840 dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
841 pool->base.clk_src_count = 3;
842
843 } else {
844 pool->base.dp_clock_source =
845 dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true);
846
847 pool->base.clock_sources[0] =
848 dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
849 pool->base.clock_sources[1] =
850 dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
851 pool->base.clk_src_count = 2;
852 }
853
854 if (pool->base.dp_clock_source == NULL) {
855 dm_error("DC: failed to create dp clock source!\n");
856 BREAK_TO_DEBUGGER();
857 goto res_create_fail;
858 }
859
860 for (i = 0; i < pool->base.clk_src_count; i++) {
861 if (pool->base.clock_sources[i] == NULL) {
862 dm_error("DC: failed to create clock sources!\n");
863 BREAK_TO_DEBUGGER();
864 goto res_create_fail;
865 }
866 }
867
868 pool->base.dccg = dce_dccg_create(ctx,
869 &disp_clk_regs,
870 &disp_clk_shift,
871 &disp_clk_mask);
872 if (pool->base.dccg == NULL) {
873 dm_error("DC: failed to create display clock!\n");
874 BREAK_TO_DEBUGGER();
875 goto res_create_fail;
876 }
877
878 pool->base.dmcu = dce_dmcu_create(ctx,
879 &dmcu_regs,
880 &dmcu_shift,
881 &dmcu_mask);
882 if (pool->base.dmcu == NULL) {
883 dm_error("DC: failed to create dmcu!\n");
884 BREAK_TO_DEBUGGER();
885 goto res_create_fail;
886 }
887
888 pool->base.abm = dce_abm_create(ctx,
889 &abm_regs,
890 &abm_shift,
891 &abm_mask);
892 if (pool->base.abm == NULL) {
893 dm_error("DC: failed to create abm!\n");
894 BREAK_TO_DEBUGGER();
895 goto res_create_fail;
896 }
897
898 /* get static clock information for PPLIB or firmware, save
899 * max_clock_state
900 */
901 if (dm_pp_get_static_clocks(ctx, &static_clk_info))
902 pool->base.dccg->max_clks_state =
903 static_clk_info.max_clocks_state;
904 {
905 struct irq_service_init_data init_data;
906 init_data.ctx = dc->ctx;
907 pool->base.irqs = dal_irq_service_dce110_create(&init_data);
908 if (!pool->base.irqs)
909 goto res_create_fail;
910 }
911
912 /*************************************************
913 * Resource + asic cap harcoding *
914 *************************************************/
915 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
916 pool->base.pipe_count = res_cap.num_timing_generator;
917 pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator;
918 dc->caps.max_downscale_ratio = 200;
919 dc->caps.i2c_speed_in_khz = 40;
920 dc->caps.max_cursor_size = 128;
921 dc->caps.dual_link_dvi = true;
922 dc->caps.disable_dp_clk_share = true;
923 for (i = 0; i < pool->base.pipe_count; i++) {
924 pool->base.timing_generators[i] =
925 dce100_timing_generator_create(
926 ctx,
927 i,
928 &dce100_tg_offsets[i]);
929 if (pool->base.timing_generators[i] == NULL) {
930 BREAK_TO_DEBUGGER();
931 dm_error("DC: failed to create tg!\n");
932 goto res_create_fail;
933 }
934
935 pool->base.mis[i] = dce100_mem_input_create(ctx, i);
936 if (pool->base.mis[i] == NULL) {
937 BREAK_TO_DEBUGGER();
938 dm_error(
939 "DC: failed to create memory input!\n");
940 goto res_create_fail;
941 }
942
943 pool->base.ipps[i] = dce100_ipp_create(ctx, i);
944 if (pool->base.ipps[i] == NULL) {
945 BREAK_TO_DEBUGGER();
946 dm_error(
947 "DC: failed to create input pixel processor!\n");
948 goto res_create_fail;
949 }
950
951 pool->base.transforms[i] = dce100_transform_create(ctx, i);
952 if (pool->base.transforms[i] == NULL) {
953 BREAK_TO_DEBUGGER();
954 dm_error(
955 "DC: failed to create transform!\n");
956 goto res_create_fail;
957 }
958
959 pool->base.opps[i] = dce100_opp_create(ctx, i);
960 if (pool->base.opps[i] == NULL) {
961 BREAK_TO_DEBUGGER();
962 dm_error(
963 "DC: failed to create output pixel processor!\n");
964 goto res_create_fail;
965 }
966 pool->base.engines[i] = dce100_aux_engine_create(ctx, i);
967 if (pool->base.engines[i] == NULL) {
968 BREAK_TO_DEBUGGER();
969 dm_error(
970 "DC:failed to create aux engine!!\n");
971 goto res_create_fail;
972 }
973 }
974
975 dc->caps.max_planes = pool->base.pipe_count;
976
977 if (!resource_construct(num_virtual_links, dc, &pool->base,
978 &res_create_funcs))
979 goto res_create_fail;
980
981 /* Create hardware sequencer */
982 dce100_hw_sequencer_construct(dc);
983 return true;
984
985 res_create_fail:
986 destruct(pool);
987
988 return false;
989 }
990
dce100_create_resource_pool(uint8_t num_virtual_links,struct dc * dc)991 struct resource_pool *dce100_create_resource_pool(
992 uint8_t num_virtual_links,
993 struct dc *dc)
994 {
995 struct dce110_resource_pool *pool =
996 kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL);
997
998 if (!pool)
999 return NULL;
1000
1001 if (construct(num_virtual_links, dc, pool))
1002 return &pool->base;
1003
1004 BREAK_TO_DEBUGGER();
1005 return NULL;
1006 }
1007
1008
