1 /*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25 #include "dm_services.h"
26 #include "dc.h"
27 #include "core_types.h"
28 #include "clk_mgr.h"
29 #include "hw_sequencer.h"
30 #include "dce100_hw_sequencer.h"
31 #include "resource.h"
32
33 #include "dce110/dce110_hw_sequencer.h"
34
35 /* include DCE10 register header files */
36 #include "dce/dce_10_0_d.h"
37 #include "dce/dce_10_0_sh_mask.h"
38
39 struct dce100_hw_seq_reg_offsets {
40 uint32_t blnd;
41 uint32_t crtc;
42 };
43
44 static const struct dce100_hw_seq_reg_offsets reg_offsets[] = {
45 {
46 .crtc = (mmCRTC0_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
47 },
48 {
49 .crtc = (mmCRTC1_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
50 },
51 {
52 .crtc = (mmCRTC2_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
53 },
54 {
55 .crtc = (mmCRTC3_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
56 },
57 {
58 .crtc = (mmCRTC4_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
59 },
60 {
61 .crtc = (mmCRTC5_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
62 }
63 };
64
65 #define HW_REG_CRTC(reg, id)\
66 (reg + reg_offsets[id].crtc)
67
68 /*******************************************************************************
69 * Private definitions
70 ******************************************************************************/
71 /***************************PIPE_CONTROL***********************************/
72
dce100_enable_display_power_gating(struct dc * dc,uint8_t controller_id,struct dc_bios * dcb,enum pipe_gating_control power_gating)73 bool dce100_enable_display_power_gating(
74 struct dc *dc,
75 uint8_t controller_id,
76 struct dc_bios *dcb,
77 enum pipe_gating_control power_gating)
78 {
79 enum bp_result bp_result = BP_RESULT_OK;
80 enum bp_pipe_control_action cntl;
81 struct dc_context *ctx = dc->ctx;
82
83 if (power_gating == PIPE_GATING_CONTROL_INIT)
84 cntl = ASIC_PIPE_INIT;
85 else if (power_gating == PIPE_GATING_CONTROL_ENABLE)
86 cntl = ASIC_PIPE_ENABLE;
87 else
88 cntl = ASIC_PIPE_DISABLE;
89
90 if (!(power_gating == PIPE_GATING_CONTROL_INIT && controller_id != 0)){
91
92 bp_result = dcb->funcs->enable_disp_power_gating(
93 dcb, controller_id + 1, cntl);
94
95 /* Revert MASTER_UPDATE_MODE to 0 because bios sets it 2
96 * by default when command table is called
97 */
98 dm_write_reg(ctx,
99 HW_REG_CRTC(mmMASTER_UPDATE_MODE, controller_id),
100 0);
101 }
102
103 if (bp_result == BP_RESULT_OK)
104 return true;
105 else
106 return false;
107 }
108
dce100_prepare_bandwidth(struct dc * dc,struct dc_state * context)109 void dce100_prepare_bandwidth(
110 struct dc *dc,
111 struct dc_state *context)
112 {
113 dce110_set_safe_displaymarks(&context->res_ctx, dc->res_pool);
114
115 dc->clk_mgr->funcs->update_clocks(
116 dc->clk_mgr,
117 context,
118 false);
119 }
120
dce100_optimize_bandwidth(struct dc * dc,struct dc_state * context)121 void dce100_optimize_bandwidth(
122 struct dc *dc,
123 struct dc_state *context)
124 {
125 dce110_set_safe_displaymarks(&context->res_ctx, dc->res_pool);
126
127 dc->clk_mgr->funcs->update_clocks(
128 dc->clk_mgr,
129 context,
130 true);
131 }
132
133 /**************************************************************************/
134
dce100_hw_sequencer_construct(struct dc * dc)135 void dce100_hw_sequencer_construct(struct dc *dc)
136 {
137 dce110_hw_sequencer_construct(dc);
138
139 dc->hwss.enable_display_power_gating = dce100_enable_display_power_gating;
140 dc->hwss.prepare_bandwidth = dce100_prepare_bandwidth;
141 dc->hwss.optimize_bandwidth = dce100_optimize_bandwidth;
142 }
143
144
