1 /*
2 * Copyright 2012-15 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include <linux/slab.h>
27
28 #include "dm_services.h"
29 #include "atomfirmware.h"
30 #include "dm_helpers.h"
31 #include "dc.h"
32 #include "grph_object_id.h"
33 #include "gpio_service_interface.h"
34 #include "core_status.h"
35 #include "dc_link_dp.h"
36 #include "dc_link_dpia.h"
37 #include "dc_link_ddc.h"
38 #include "link_hwss.h"
39 #include "opp.h"
40
41 #include "link_encoder.h"
42 #include "hw_sequencer.h"
43 #include "resource.h"
44 #include "abm.h"
45 #include "fixed31_32.h"
46 #include "dpcd_defs.h"
47 #include "dmcu.h"
48 #include "hw/clk_mgr.h"
49 #include "dce/dmub_psr.h"
50 #include "dmub/dmub_srv.h"
51 #include "inc/hw/panel_cntl.h"
52 #include "inc/link_enc_cfg.h"
53 #include "inc/link_dpcd.h"
54 #include "link/link_dp_trace.h"
55
56 #include "dc/dcn30/dcn30_vpg.h"
57
58 #define DC_LOGGER_INIT(logger)
59
60 #define LINK_INFO(...) \
61 DC_LOG_HW_HOTPLUG( \
62 __VA_ARGS__)
63
64 #define RETIMER_REDRIVER_INFO(...) \
65 DC_LOG_RETIMER_REDRIVER( \
66 __VA_ARGS__)
67
68 /*******************************************************************************
69 * Private functions
70 ******************************************************************************/
dc_link_destruct(struct dc_link * link)71 static void dc_link_destruct(struct dc_link *link)
72 {
73 int i;
74
75 if (link->hpd_gpio) {
76 dal_gpio_destroy_irq(&link->hpd_gpio);
77 link->hpd_gpio = NULL;
78 }
79
80 if (link->ddc)
81 dal_ddc_service_destroy(&link->ddc);
82
83 if (link->panel_cntl)
84 link->panel_cntl->funcs->destroy(&link->panel_cntl);
85
86 if (link->link_enc) {
87 /* Update link encoder resource tracking variables. These are used for
88 * the dynamic assignment of link encoders to streams. Virtual links
89 * are not assigned encoder resources on creation.
90 */
91 if (link->link_id.id != CONNECTOR_ID_VIRTUAL) {
92 link->dc->res_pool->link_encoders[link->eng_id - ENGINE_ID_DIGA] = NULL;
93 link->dc->res_pool->dig_link_enc_count--;
94 }
95 link->link_enc->funcs->destroy(&link->link_enc);
96 }
97
98 if (link->local_sink)
99 dc_sink_release(link->local_sink);
100
101 for (i = 0; i < link->sink_count; ++i)
102 dc_sink_release(link->remote_sinks[i]);
103 }
104
get_hpd_gpio(struct dc_bios * dcb,struct graphics_object_id link_id,struct gpio_service * gpio_service)105 struct gpio *get_hpd_gpio(struct dc_bios *dcb,
106 struct graphics_object_id link_id,
107 struct gpio_service *gpio_service)
108 {
109 enum bp_result bp_result;
110 struct graphics_object_hpd_info hpd_info;
111 struct gpio_pin_info pin_info;
112
113 if (dcb->funcs->get_hpd_info(dcb, link_id, &hpd_info) != BP_RESULT_OK)
114 return NULL;
115
116 bp_result = dcb->funcs->get_gpio_pin_info(dcb,
117 hpd_info.hpd_int_gpio_uid, &pin_info);
118
119 if (bp_result != BP_RESULT_OK) {
120 ASSERT(bp_result == BP_RESULT_NORECORD);
121 return NULL;
122 }
123
124 return dal_gpio_service_create_irq(gpio_service,
125 pin_info.offset,
126 pin_info.mask);
127 }
128
129 /*
130 * Function: program_hpd_filter
131 *
132 * @brief
133 * Programs HPD filter on associated HPD line
134 *
135 * @param [in] delay_on_connect_in_ms: Connect filter timeout
136 * @param [in] delay_on_disconnect_in_ms: Disconnect filter timeout
137 *
138 * @return
139 * true on success, false otherwise
140 */
program_hpd_filter(const struct dc_link * link)141 static bool program_hpd_filter(const struct dc_link *link)
142 {
143 bool result = false;
144 struct gpio *hpd;
145 int delay_on_connect_in_ms = 0;
146 int delay_on_disconnect_in_ms = 0;
147
148 if (link->is_hpd_filter_disabled)
149 return false;
150 /* Verify feature is supported */
151 switch (link->connector_signal) {
152 case SIGNAL_TYPE_DVI_SINGLE_LINK:
153 case SIGNAL_TYPE_DVI_DUAL_LINK:
154 case SIGNAL_TYPE_HDMI_TYPE_A:
155 /* Program hpd filter */
156 delay_on_connect_in_ms = 500;
157 delay_on_disconnect_in_ms = 100;
158 break;
159 case SIGNAL_TYPE_DISPLAY_PORT:
160 case SIGNAL_TYPE_DISPLAY_PORT_MST:
161 /* Program hpd filter to allow DP signal to settle */
162 /* 500: not able to detect MST <-> SST switch as HPD is low for
163 * only 100ms on DELL U2413
164 * 0: some passive dongle still show aux mode instead of i2c
165 * 20-50: not enough to hide bouncing HPD with passive dongle.
166 * also see intermittent i2c read issues.
167 */
168 delay_on_connect_in_ms = 80;
169 delay_on_disconnect_in_ms = 0;
170 break;
171 case SIGNAL_TYPE_LVDS:
172 case SIGNAL_TYPE_EDP:
173 default:
174 /* Don't program hpd filter */
175 return false;
176 }
177
178 /* Obtain HPD handle */
179 hpd = get_hpd_gpio(link->ctx->dc_bios, link->link_id,
180 link->ctx->gpio_service);
181
182 if (!hpd)
183 return result;
184
185 /* Setup HPD filtering */
186 if (dal_gpio_open(hpd, GPIO_MODE_INTERRUPT) == GPIO_RESULT_OK) {
187 struct gpio_hpd_config config;
188
189 config.delay_on_connect = delay_on_connect_in_ms;
190 config.delay_on_disconnect = delay_on_disconnect_in_ms;
191
192 dal_irq_setup_hpd_filter(hpd, &config);
193
194 dal_gpio_close(hpd);
195
196 result = true;
197 } else {
198 ASSERT_CRITICAL(false);
199 }
200
201 /* Release HPD handle */
202 dal_gpio_destroy_irq(&hpd);
203
204 return result;
205 }
206
dc_link_wait_for_t12(struct dc_link * link)207 bool dc_link_wait_for_t12(struct dc_link *link)
208 {
209 if (link->connector_signal == SIGNAL_TYPE_EDP && link->dc->hwss.edp_wait_for_T12) {
210 link->dc->hwss.edp_wait_for_T12(link);
211
212 return true;
213 }
214
215 return false;
216 }
217
218 /**
219 * dc_link_detect_sink() - Determine if there is a sink connected
220 *
221 * @link: pointer to the dc link
222 * @type: Returned connection type
223 * Does not detect downstream devices, such as MST sinks
224 * or display connected through active dongles
225 */
dc_link_detect_sink(struct dc_link * link,enum dc_connection_type * type)226 bool dc_link_detect_sink(struct dc_link *link, enum dc_connection_type *type)
227 {
228 uint32_t is_hpd_high = 0;
229 struct gpio *hpd_pin;
230
231 if (link->connector_signal == SIGNAL_TYPE_LVDS) {
232 *type = dc_connection_single;
233 return true;
234 }
235
236 if (link->connector_signal == SIGNAL_TYPE_EDP) {
237 /*in case it is not on*/
238 if (!link->dc->config.edp_no_power_sequencing)
239 link->dc->hwss.edp_power_control(link, true);
240 link->dc->hwss.edp_wait_for_hpd_ready(link, true);
241 }
242
243 /* Link may not have physical HPD pin. */
244 if (link->ep_type != DISPLAY_ENDPOINT_PHY) {
245 if (link->is_hpd_pending || !dc_link_dpia_query_hpd_status(link))
246 *type = dc_connection_none;
247 else
248 *type = dc_connection_single;
249
250 return true;
251 }
252
253 /* todo: may need to lock gpio access */
254 hpd_pin = get_hpd_gpio(link->ctx->dc_bios, link->link_id,
255 link->ctx->gpio_service);
256 if (!hpd_pin)
257 goto hpd_gpio_failure;
258
259 dal_gpio_open(hpd_pin, GPIO_MODE_INTERRUPT);
260 dal_gpio_get_value(hpd_pin, &is_hpd_high);
261 dal_gpio_close(hpd_pin);
262 dal_gpio_destroy_irq(&hpd_pin);
263
264 if (is_hpd_high) {
265 *type = dc_connection_single;
266 /* TODO: need to do the actual detection */
267 } else {
268 *type = dc_connection_none;
269 }
270
271 return true;
272
273 hpd_gpio_failure:
274 return false;
275 }
276
get_ddc_transaction_type(enum signal_type sink_signal)277 static enum ddc_transaction_type get_ddc_transaction_type(enum signal_type sink_signal)
278 {
279 enum ddc_transaction_type transaction_type = DDC_TRANSACTION_TYPE_NONE;
280
281 switch (sink_signal) {
282 case SIGNAL_TYPE_DVI_SINGLE_LINK:
283 case SIGNAL_TYPE_DVI_DUAL_LINK:
284 case SIGNAL_TYPE_HDMI_TYPE_A:
285 case SIGNAL_TYPE_LVDS:
286 case SIGNAL_TYPE_RGB:
287 transaction_type = DDC_TRANSACTION_TYPE_I2C;
288 break;
289
290 case SIGNAL_TYPE_DISPLAY_PORT:
291 case SIGNAL_TYPE_EDP:
292 transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
293 break;
294
295 case SIGNAL_TYPE_DISPLAY_PORT_MST:
296 /* MST does not use I2COverAux, but there is the
297 * SPECIAL use case for "immediate dwnstrm device
298 * access" (EPR#370830).
299 */
300 transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
301 break;
302
303 default:
304 break;
305 }
306
307 return transaction_type;
308 }
309
get_basic_signal_type(struct graphics_object_id encoder,struct graphics_object_id downstream)310 static enum signal_type get_basic_signal_type(struct graphics_object_id encoder,
311 struct graphics_object_id downstream)
312 {
313 if (downstream.type == OBJECT_TYPE_CONNECTOR) {
314 switch (downstream.id) {
315 case CONNECTOR_ID_SINGLE_LINK_DVII:
316 switch (encoder.id) {
317 case ENCODER_ID_INTERNAL_DAC1:
318 case ENCODER_ID_INTERNAL_KLDSCP_DAC1:
319 case ENCODER_ID_INTERNAL_DAC2:
320 case ENCODER_ID_INTERNAL_KLDSCP_DAC2:
321 return SIGNAL_TYPE_RGB;
322 default:
323 return SIGNAL_TYPE_DVI_SINGLE_LINK;
324 }
325 break;
326 case CONNECTOR_ID_DUAL_LINK_DVII:
327 {
328 switch (encoder.id) {
329 case ENCODER_ID_INTERNAL_DAC1:
330 case ENCODER_ID_INTERNAL_KLDSCP_DAC1:
331 case ENCODER_ID_INTERNAL_DAC2:
332 case ENCODER_ID_INTERNAL_KLDSCP_DAC2:
333 return SIGNAL_TYPE_RGB;
334 default:
335 return SIGNAL_TYPE_DVI_DUAL_LINK;
336 }
337 }
338 break;
339 case CONNECTOR_ID_SINGLE_LINK_DVID:
340 return SIGNAL_TYPE_DVI_SINGLE_LINK;
341 case CONNECTOR_ID_DUAL_LINK_DVID:
342 return SIGNAL_TYPE_DVI_DUAL_LINK;
343 case CONNECTOR_ID_VGA:
344 return SIGNAL_TYPE_RGB;
345 case CONNECTOR_ID_HDMI_TYPE_A:
346 return SIGNAL_TYPE_HDMI_TYPE_A;
347 case CONNECTOR_ID_LVDS:
348 return SIGNAL_TYPE_LVDS;
349 case CONNECTOR_ID_DISPLAY_PORT:
350 case CONNECTOR_ID_USBC:
351 return SIGNAL_TYPE_DISPLAY_PORT;
352 case CONNECTOR_ID_EDP:
353 return SIGNAL_TYPE_EDP;
354 default:
355 return SIGNAL_TYPE_NONE;
356 }
357 } else if (downstream.type == OBJECT_TYPE_ENCODER) {
358 switch (downstream.id) {
359 case ENCODER_ID_EXTERNAL_NUTMEG:
360 case ENCODER_ID_EXTERNAL_TRAVIS:
361 return SIGNAL_TYPE_DISPLAY_PORT;
362 default:
363 return SIGNAL_TYPE_NONE;
364 }
365 }
366
367 return SIGNAL_TYPE_NONE;
368 }
369
370 /*
371 * dc_link_is_dp_sink_present() - Check if there is a native DP
372 * or passive DP-HDMI dongle connected
373 */
dc_link_is_dp_sink_present(struct dc_link * link)374 bool dc_link_is_dp_sink_present(struct dc_link *link)
375 {
376 enum gpio_result gpio_result;
377 uint32_t clock_pin = 0;
378 uint8_t retry = 0;
379 struct ddc *ddc;
380
381 enum connector_id connector_id =
382 dal_graphics_object_id_get_connector_id(link->link_id);
383
384 bool present =
385 ((connector_id == CONNECTOR_ID_DISPLAY_PORT) ||
386 (connector_id == CONNECTOR_ID_EDP) ||
387 (connector_id == CONNECTOR_ID_USBC));
388
389 ddc = dal_ddc_service_get_ddc_pin(link->ddc);
390
391 if (!ddc) {
392 BREAK_TO_DEBUGGER();
393 return present;
394 }
395
396 /* Open GPIO and set it to I2C mode */
397 /* Note: this GpioMode_Input will be converted
398 * to GpioConfigType_I2cAuxDualMode in GPIO component,
399 * which indicates we need additional delay
400 */
401
402 if (dal_ddc_open(ddc, GPIO_MODE_INPUT,
403 GPIO_DDC_CONFIG_TYPE_MODE_I2C) != GPIO_RESULT_OK) {
404 dal_ddc_close(ddc);
405
406 return present;
407 }
408
409 /*
410 * Read GPIO: DP sink is present if both clock and data pins are zero
411 *
412 * [W/A] plug-unplug DP cable, sometimes customer board has
413 * one short pulse on clk_pin(1V, < 1ms). DP will be config to HDMI/DVI
414 * then monitor can't br light up. Add retry 3 times
415 * But in real passive dongle, it need additional 3ms to detect
416 */
417 do {
418 gpio_result = dal_gpio_get_value(ddc->pin_clock, &clock_pin);
419 ASSERT(gpio_result == GPIO_RESULT_OK);
420 if (clock_pin)
421 udelay(1000);
422 else
423 break;
424 } while (retry++ < 3);
425
426 present = (gpio_result == GPIO_RESULT_OK) && !clock_pin;
427
428 dal_ddc_close(ddc);
429
430 return present;
431 }
432
433 /*
434 * @brief
435 * Detect output sink type
436 */
link_detect_sink(struct dc_link * link,enum dc_detect_reason reason)437 static enum signal_type link_detect_sink(struct dc_link *link,
438 enum dc_detect_reason reason)
439 {
440 enum signal_type result;
441 struct graphics_object_id enc_id;
442
443 if (link->is_dig_mapping_flexible)
444 enc_id = (struct graphics_object_id){.id = ENCODER_ID_UNKNOWN};
445 else
446 enc_id = link->link_enc->id;
447 result = get_basic_signal_type(enc_id, link->link_id);
448
449 /* Use basic signal type for link without physical connector. */
450 if (link->ep_type != DISPLAY_ENDPOINT_PHY)
451 return result;
452
453 /* Internal digital encoder will detect only dongles
454 * that require digital signal
455 */
456
457 /* Detection mechanism is different
458 * for different native connectors.
459 * LVDS connector supports only LVDS signal;
460 * PCIE is a bus slot, the actual connector needs to be detected first;
461 * eDP connector supports only eDP signal;
462 * HDMI should check straps for audio
463 */
464
465 /* PCIE detects the actual connector on add-on board */
466 if (link->link_id.id == CONNECTOR_ID_PCIE) {
467 /* ZAZTODO implement PCIE add-on card detection */
468 }
469
470 switch (link->link_id.id) {
471 case CONNECTOR_ID_HDMI_TYPE_A: {
472 /* check audio support:
473 * if native HDMI is not supported, switch to DVI
474 */
475 struct audio_support *aud_support =
476 &link->dc->res_pool->audio_support;
477
478 if (!aud_support->hdmi_audio_native)
479 if (link->link_id.id == CONNECTOR_ID_HDMI_TYPE_A)
480 result = SIGNAL_TYPE_DVI_SINGLE_LINK;
481 }
482 break;
483 case CONNECTOR_ID_DISPLAY_PORT:
484 case CONNECTOR_ID_USBC: {
485 /* DP HPD short pulse. Passive DP dongle will not
486 * have short pulse
487 */
488 if (reason != DETECT_REASON_HPDRX) {
489 /* Check whether DP signal detected: if not -
490 * we assume signal is DVI; it could be corrected
491 * to HDMI after dongle detection
492 */
493 if (!dm_helpers_is_dp_sink_present(link))
494 result = SIGNAL_TYPE_DVI_SINGLE_LINK;
495 }
496 }
497 break;
498 default:
499 break;
500 }
501
502 return result;
503 }
504
decide_signal_from_strap_and_dongle_type(enum display_dongle_type dongle_type,struct audio_support * audio_support)505 static enum signal_type decide_signal_from_strap_and_dongle_type(enum display_dongle_type dongle_type,
506 struct audio_support *audio_support)
507 {
508 enum signal_type signal = SIGNAL_TYPE_NONE;
509
510 switch (dongle_type) {
511 case DISPLAY_DONGLE_DP_HDMI_DONGLE:
512 if (audio_support->hdmi_audio_on_dongle)
513 signal = SIGNAL_TYPE_HDMI_TYPE_A;
514 else
515 signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
516 break;
517 case DISPLAY_DONGLE_DP_DVI_DONGLE:
518 signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
519 break;
520 case DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE:
521 if (audio_support->hdmi_audio_native)
522 signal = SIGNAL_TYPE_HDMI_TYPE_A;
523 else
524 signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
525 break;
526 default:
527 signal = SIGNAL_TYPE_NONE;
528 break;
529 }
530
531 return signal;
532 }
533
dp_passive_dongle_detection(struct ddc_service * ddc,struct display_sink_capability * sink_cap,struct audio_support * audio_support)534 static enum signal_type dp_passive_dongle_detection(struct ddc_service *ddc,
535 struct display_sink_capability *sink_cap,
536 struct audio_support *audio_support)
537 {
538 dal_ddc_service_i2c_query_dp_dual_mode_adaptor(ddc, sink_cap);
539
540 return decide_signal_from_strap_and_dongle_type(sink_cap->dongle_type,
541 audio_support);
542 }
543
link_disconnect_sink(struct dc_link * link)544 static void link_disconnect_sink(struct dc_link *link)
545 {
546 if (link->local_sink) {
547 dc_sink_release(link->local_sink);
548 link->local_sink = NULL;
549 }
550
551 link->dpcd_sink_count = 0;
552 //link->dpcd_caps.dpcd_rev.raw = 0;
553 }
554
link_disconnect_remap(struct dc_sink * prev_sink,struct dc_link * link)555 static void link_disconnect_remap(struct dc_sink *prev_sink, struct dc_link *link)
556 {
557 dc_sink_release(link->local_sink);
558 link->local_sink = prev_sink;
559 }
560
561 #if defined(CONFIG_DRM_AMD_DC_HDCP)
dc_link_is_hdcp14(struct dc_link * link,enum signal_type signal)562 bool dc_link_is_hdcp14(struct dc_link *link, enum signal_type signal)
563 {
564 bool ret = false;
565
566 switch (signal) {
567 case SIGNAL_TYPE_DISPLAY_PORT:
568 case SIGNAL_TYPE_DISPLAY_PORT_MST:
569 ret = link->hdcp_caps.bcaps.bits.HDCP_CAPABLE;
570 break;
571 case SIGNAL_TYPE_DVI_SINGLE_LINK:
572 case SIGNAL_TYPE_DVI_DUAL_LINK:
573 case SIGNAL_TYPE_HDMI_TYPE_A:
574 /* HDMI doesn't tell us its HDCP(1.4) capability, so assume to always be capable,
575 * we can poll for bksv but some displays have an issue with this. Since its so rare
576 * for a display to not be 1.4 capable, this assumtion is ok
577 */
578 ret = true;
579 break;
580 default:
581 break;
582 }
583 return ret;
584 }
585
dc_link_is_hdcp22(struct dc_link * link,enum signal_type signal)586 bool dc_link_is_hdcp22(struct dc_link *link, enum signal_type signal)
587 {
588 bool ret = false;
589
590 switch (signal) {
591 case SIGNAL_TYPE_DISPLAY_PORT:
592 case SIGNAL_TYPE_DISPLAY_PORT_MST:
593 ret = (link->hdcp_caps.bcaps.bits.HDCP_CAPABLE &&
594 link->hdcp_caps.rx_caps.fields.byte0.hdcp_capable &&
595 (link->hdcp_caps.rx_caps.fields.version == 0x2)) ? 1 : 0;
596 break;
597 case SIGNAL_TYPE_DVI_SINGLE_LINK:
598 case SIGNAL_TYPE_DVI_DUAL_LINK:
599 case SIGNAL_TYPE_HDMI_TYPE_A:
600 ret = (link->hdcp_caps.rx_caps.fields.version == 0x4) ? 1:0;
601 break;
602 default:
603 break;
604 }
605
606 return ret;
607 }
608
query_hdcp_capability(enum signal_type signal,struct dc_link * link)609 static void query_hdcp_capability(enum signal_type signal, struct dc_link *link)
610 {
611 struct hdcp_protection_message msg22;
612 struct hdcp_protection_message msg14;
613
614 memset(&msg22, 0, sizeof(struct hdcp_protection_message));
615 memset(&msg14, 0, sizeof(struct hdcp_protection_message));
616 memset(link->hdcp_caps.rx_caps.raw, 0,
617 sizeof(link->hdcp_caps.rx_caps.raw));
618
619 if ((link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT &&
620 link->ddc->transaction_type ==
621 DDC_TRANSACTION_TYPE_I2C_OVER_AUX) ||
622 link->connector_signal == SIGNAL_TYPE_EDP) {
623 msg22.data = link->hdcp_caps.rx_caps.raw;
624 msg22.length = sizeof(link->hdcp_caps.rx_caps.raw);
625 msg22.msg_id = HDCP_MESSAGE_ID_RX_CAPS;
626 } else {
627 msg22.data = &link->hdcp_caps.rx_caps.fields.version;
628 msg22.length = sizeof(link->hdcp_caps.rx_caps.fields.version);
629 msg22.msg_id = HDCP_MESSAGE_ID_HDCP2VERSION;
630 }
631 msg22.version = HDCP_VERSION_22;
632 msg22.link = HDCP_LINK_PRIMARY;
633 msg22.max_retries = 5;
634 dc_process_hdcp_msg(signal, link, &msg22);
635
636 if (signal == SIGNAL_TYPE_DISPLAY_PORT || signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
637 msg14.data = &link->hdcp_caps.bcaps.raw;
638 msg14.length = sizeof(link->hdcp_caps.bcaps.raw);
639 msg14.msg_id = HDCP_MESSAGE_ID_READ_BCAPS;
640 msg14.version = HDCP_VERSION_14;
641 msg14.link = HDCP_LINK_PRIMARY;
642 msg14.max_retries = 5;
643
644 dc_process_hdcp_msg(signal, link, &msg14);
645 }
646
647 }
648 #endif
649
read_current_link_settings_on_detect(struct dc_link * link)650 static void read_current_link_settings_on_detect(struct dc_link *link)
651 {
652 union lane_count_set lane_count_set = {0};
653 uint8_t link_bw_set;
654 uint8_t link_rate_set;
655 uint32_t read_dpcd_retry_cnt = 10;
656 enum dc_status status = DC_ERROR_UNEXPECTED;
657 int i;
658 union max_down_spread max_down_spread = {0};
659
660 // Read DPCD 00101h to find out the number of lanes currently set
661 for (i = 0; i < read_dpcd_retry_cnt; i++) {
662 status = core_link_read_dpcd(link,
663 DP_LANE_COUNT_SET,
664 &lane_count_set.raw,
665 sizeof(lane_count_set));
666 /* First DPCD read after VDD ON can fail if the particular board
667 * does not have HPD pin wired correctly. So if DPCD read fails,
668 * which it should never happen, retry a few times. Target worst
669 * case scenario of 80 ms.
670 */
671 if (status == DC_OK) {
672 link->cur_link_settings.lane_count =
673 lane_count_set.bits.LANE_COUNT_SET;
674 break;
675 }
676
677 msleep(8);
678 }
679
680 // Read DPCD 00100h to find if standard link rates are set
681 core_link_read_dpcd(link, DP_LINK_BW_SET,
682 &link_bw_set, sizeof(link_bw_set));
683
684 if (link_bw_set == 0) {
685 if (link->connector_signal == SIGNAL_TYPE_EDP) {
686 /* If standard link rates are not being used,
687 * Read DPCD 00115h to find the edp link rate set used
688 */
689 core_link_read_dpcd(link, DP_LINK_RATE_SET,
690 &link_rate_set, sizeof(link_rate_set));
691
692 // edp_supported_link_rates_count = 0 for DP
693 if (link_rate_set < link->dpcd_caps.edp_supported_link_rates_count) {
694 link->cur_link_settings.link_rate =
695 link->dpcd_caps.edp_supported_link_rates[link_rate_set];
696 link->cur_link_settings.link_rate_set = link_rate_set;
697 link->cur_link_settings.use_link_rate_set = true;
698 }
699 } else {
700 // Link Rate not found. Seamless boot may not work.
701 ASSERT(false);
702 }
703 } else {
704 link->cur_link_settings.link_rate = link_bw_set;
705 link->cur_link_settings.use_link_rate_set = false;
706 }
707 // Read DPCD 00003h to find the max down spread.
708 core_link_read_dpcd(link, DP_MAX_DOWNSPREAD,
709 &max_down_spread.raw, sizeof(max_down_spread));
710 link->cur_link_settings.link_spread =
711 max_down_spread.bits.MAX_DOWN_SPREAD ?
712 LINK_SPREAD_05_DOWNSPREAD_30KHZ : LINK_SPREAD_DISABLED;
713 }
714
detect_dp(struct dc_link * link,struct display_sink_capability * sink_caps,enum dc_detect_reason reason)715 static bool detect_dp(struct dc_link *link,
716 struct display_sink_capability *sink_caps,
717 enum dc_detect_reason reason)
718 {
719 struct audio_support *audio_support = &link->dc->res_pool->audio_support;
720
721 sink_caps->signal = link_detect_sink(link, reason);
722 sink_caps->transaction_type =
723 get_ddc_transaction_type(sink_caps->signal);
724
725 if (sink_caps->transaction_type == DDC_TRANSACTION_TYPE_I2C_OVER_AUX) {
726 sink_caps->signal = SIGNAL_TYPE_DISPLAY_PORT;
727 if (!detect_dp_sink_caps(link))
728 return false;
729
730 if (is_dp_branch_device(link))
731 /* DP SST branch */
732 link->type = dc_connection_sst_branch;
733 } else {
734 /* DP passive dongles */
735 sink_caps->signal = dp_passive_dongle_detection(link->ddc,
736 sink_caps,
737 audio_support);
738 link->dpcd_caps.dongle_type = sink_caps->dongle_type;
739 link->dpcd_caps.is_dongle_type_one = sink_caps->is_dongle_type_one;
740 link->dpcd_caps.dpcd_rev.raw = 0;
741 }
742
743 return true;
744 }
745
is_same_edid(struct dc_edid * old_edid,struct dc_edid * new_edid)746 static bool is_same_edid(struct dc_edid *old_edid, struct dc_edid *new_edid)
747 {
748 if (old_edid->length != new_edid->length)
749 return false;
750
751 if (new_edid->length == 0)
752 return false;
753
754 return (memcmp(old_edid->raw_edid,
755 new_edid->raw_edid, new_edid->length) == 0);
756 }
757
wait_for_entering_dp_alt_mode(struct dc_link * link)758 static bool wait_for_entering_dp_alt_mode(struct dc_link *link)
759 {
760 /**
761 * something is terribly wrong if time out is > 200ms. (5Hz)
762 * 500 microseconds * 400 tries us 200 ms
763 **/
764 unsigned int sleep_time_in_microseconds = 500;
765 unsigned int tries_allowed = 400;
766 bool is_in_alt_mode;
767 unsigned long long enter_timestamp;
768 unsigned long long finish_timestamp;
769 unsigned long long time_taken_in_ns;
770 int tries_taken;
771
772 DC_LOGGER_INIT(link->ctx->logger);
773
774 if (!link->link_enc->funcs->is_in_alt_mode)
775 return true;
776
777 is_in_alt_mode = link->link_enc->funcs->is_in_alt_mode(link->link_enc);
778 DC_LOG_WARNING("DP Alt mode state on HPD: %d\n", is_in_alt_mode);
779
780 if (is_in_alt_mode)
781 return true;
782
783 enter_timestamp = dm_get_timestamp(link->ctx);
784
785 for (tries_taken = 0; tries_taken < tries_allowed; tries_taken++) {
786 udelay(sleep_time_in_microseconds);
787 /* ask the link if alt mode is enabled, if so return ok */
788 if (link->link_enc->funcs->is_in_alt_mode(link->link_enc)) {
789 finish_timestamp = dm_get_timestamp(link->ctx);
790 time_taken_in_ns =
791 dm_get_elapse_time_in_ns(link->ctx,
792 finish_timestamp,
793 enter_timestamp);
794 DC_LOG_WARNING("Alt mode entered finished after %llu ms\n",
795 div_u64(time_taken_in_ns, 1000000));
796 return true;
797 }
798 }
799 finish_timestamp = dm_get_timestamp(link->ctx);
800 time_taken_in_ns = dm_get_elapse_time_in_ns(link->ctx, finish_timestamp,
801 enter_timestamp);
802 DC_LOG_WARNING("Alt mode has timed out after %llu ms\n",
803 div_u64(time_taken_in_ns, 1000000));
804 return false;
805 }
806
apply_dpia_mst_dsc_always_on_wa(struct dc_link * link)807 static void apply_dpia_mst_dsc_always_on_wa(struct dc_link *link)
808 {
809 /* Apply work around for tunneled MST on certain USB4 docks. Always use DSC if dock
810 * reports DSC support.
811 */
812 if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA &&
813 link->type == dc_connection_mst_branch &&
814 link->dpcd_caps.branch_dev_id == DP_BRANCH_DEVICE_ID_90CC24 &&
815 link->dpcd_caps.branch_hw_revision == DP_BRANCH_HW_REV_20 &&
816 link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_SUPPORT &&
817 !link->dc->debug.dpia_debug.bits.disable_mst_dsc_work_around)
818 link->wa_flags.dpia_mst_dsc_always_on = true;
819 }
820
revert_dpia_mst_dsc_always_on_wa(struct dc_link * link)821 static void revert_dpia_mst_dsc_always_on_wa(struct dc_link *link)
822 {
823 /* Disable work around which keeps DSC on for tunneled MST on certain USB4 docks. */
824 if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA)
825 link->wa_flags.dpia_mst_dsc_always_on = false;
826 }
827
discover_dp_mst_topology(struct dc_link * link,enum dc_detect_reason reason)828 static bool discover_dp_mst_topology(struct dc_link *link, enum dc_detect_reason reason)
829 {
830 DC_LOGGER_INIT(link->ctx->logger);
831
832 LINK_INFO("link=%d, mst branch is now Connected\n",
833 link->link_index);
834
835 link->type = dc_connection_mst_branch;
836 apply_dpia_mst_dsc_always_on_wa(link);
837
838 dm_helpers_dp_update_branch_info(link->ctx, link);
839 if (dm_helpers_dp_mst_start_top_mgr(link->ctx,
840 link, (reason == DETECT_REASON_BOOT || reason == DETECT_REASON_RESUMEFROMS3S4))) {
841 link_disconnect_sink(link);
842 } else {
843 link->type = dc_connection_sst_branch;
844 }
845
846 return link->type == dc_connection_mst_branch;
847 }
848
reset_cur_dp_mst_topology(struct dc_link * link)849 bool reset_cur_dp_mst_topology(struct dc_link *link)
850 {
851 DC_LOGGER_INIT(link->ctx->logger);
852
853 LINK_INFO("link=%d, mst branch is now Disconnected\n",
854 link->link_index);
855
856 revert_dpia_mst_dsc_always_on_wa(link);
857 return dm_helpers_dp_mst_stop_top_mgr(link->ctx, link);
858 }
859
should_prepare_phy_clocks_for_link_verification(const struct dc * dc,enum dc_detect_reason reason)860 static bool should_prepare_phy_clocks_for_link_verification(const struct dc *dc,
861 enum dc_detect_reason reason)
862 {
863 int i;
864 bool can_apply_seamless_boot = false;
865
866 for (i = 0; i < dc->current_state->stream_count; i++) {
867 if (dc->current_state->streams[i]->apply_seamless_boot_optimization) {
868 can_apply_seamless_boot = true;
869 break;
870 }
871 }
872
873 return !can_apply_seamless_boot && reason != DETECT_REASON_BOOT;
874 }
875
prepare_phy_clocks_for_destructive_link_verification(const struct dc * dc)876 static void prepare_phy_clocks_for_destructive_link_verification(const struct dc *dc)
877 {
878 dc_z10_restore(dc);
879 clk_mgr_exit_optimized_pwr_state(dc, dc->clk_mgr);
880 }
881
restore_phy_clocks_for_destructive_link_verification(const struct dc * dc)882 static void restore_phy_clocks_for_destructive_link_verification(const struct dc *dc)
883 {
884 clk_mgr_optimize_pwr_state(dc, dc->clk_mgr);
885 }
886
set_all_streams_dpms_off_for_link(struct dc_link * link)887 static void set_all_streams_dpms_off_for_link(struct dc_link *link)
888 {
889 int i;
890 struct pipe_ctx *pipe_ctx;
891 struct dc_stream_update stream_update;
892 bool dpms_off = true;
893 struct link_resource link_res = {0};
894
895 memset(&stream_update, 0, sizeof(stream_update));
896 stream_update.dpms_off = &dpms_off;
897
898 for (i = 0; i < MAX_PIPES; i++) {
899 pipe_ctx = &link->dc->current_state->res_ctx.pipe_ctx[i];
900 if (pipe_ctx && pipe_ctx->stream && !pipe_ctx->stream->dpms_off &&
901 pipe_ctx->stream->link == link && !pipe_ctx->prev_odm_pipe) {
902 stream_update.stream = pipe_ctx->stream;
903 dc_commit_updates_for_stream(link->ctx->dc, NULL, 0,
904 pipe_ctx->stream, &stream_update,
905 link->ctx->dc->current_state);
906 }
907 }
908
909 /* link can be also enabled by vbios. In this case it is not recorded
910 * in pipe_ctx. Disable link phy here to make sure it is completely off
911 */
912 dp_disable_link_phy(link, &link_res, link->connector_signal);
913 }
914
verify_link_capability_destructive(struct dc_link * link,struct dc_sink * sink,enum dc_detect_reason reason)915 static void verify_link_capability_destructive(struct dc_link *link,
916 struct dc_sink *sink,
917 enum dc_detect_reason reason)
918 {
919 bool should_prepare_phy_clocks =
920 should_prepare_phy_clocks_for_link_verification(link->dc, reason);
921
922 if (should_prepare_phy_clocks)
923 prepare_phy_clocks_for_destructive_link_verification(link->dc);
924
925 if (dc_is_dp_signal(link->local_sink->sink_signal)) {
926 struct dc_link_settings known_limit_link_setting =
927 dp_get_max_link_cap(link);
928 set_all_streams_dpms_off_for_link(link);
929 dp_verify_link_cap_with_retries(
930 link, &known_limit_link_setting,
931 LINK_TRAINING_MAX_VERIFY_RETRY);
932 } else {
933 ASSERT(0);
934 }
935
936 if (should_prepare_phy_clocks)
937 restore_phy_clocks_for_destructive_link_verification(link->dc);
938 }
939
verify_link_capability_non_destructive(struct dc_link * link)940 static void verify_link_capability_non_destructive(struct dc_link *link)
941 {
942 if (dc_is_dp_signal(link->local_sink->sink_signal)) {
943 if (dc_is_embedded_signal(link->local_sink->sink_signal) ||
944 link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA)
945 /* TODO - should we check link encoder's max link caps here?
946 * How do we know which link encoder to check from?
947 */
948 link->verified_link_cap = link->reported_link_cap;
949 else
950 link->verified_link_cap = dp_get_max_link_cap(link);
951 }
952 }
953
should_verify_link_capability_destructively(struct dc_link * link,enum dc_detect_reason reason)954 static bool should_verify_link_capability_destructively(struct dc_link *link,
955 enum dc_detect_reason reason)
956 {
957 bool destrictive = false;
958 struct dc_link_settings max_link_cap;
959 bool is_link_enc_unavailable = link->link_enc &&
960 link->dc->res_pool->funcs->link_encs_assign &&
961 !link_enc_cfg_is_link_enc_avail(
962 link->ctx->dc,
963 link->link_enc->preferred_engine,
964 link);
965
966 if (dc_is_dp_signal(link->local_sink->sink_signal)) {
967 max_link_cap = dp_get_max_link_cap(link);
968 destrictive = true;
969
970 if (link->dc->debug.skip_detection_link_training ||
971 dc_is_embedded_signal(link->local_sink->sink_signal) ||
972 link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) {
973 destrictive = false;
974 } else if (dp_get_link_encoding_format(&max_link_cap) ==
975 DP_8b_10b_ENCODING) {
976 if (link->dpcd_caps.is_mst_capable ||
977 is_link_enc_unavailable) {
978 destrictive = false;
979 }
980 }
981 }
982
983 return destrictive;
984 }
985
verify_link_capability(struct dc_link * link,struct dc_sink * sink,enum dc_detect_reason reason)986 static void verify_link_capability(struct dc_link *link, struct dc_sink *sink,
987 enum dc_detect_reason reason)
988 {
989 if (should_verify_link_capability_destructively(link, reason))
990 verify_link_capability_destructive(link, sink, reason);
991 else
992 verify_link_capability_non_destructive(link);
993 }
994
995
996 /**
997 * detect_link_and_local_sink() - Detect if a sink is attached to a given link
998 *
999 * link->local_sink is created or destroyed as needed.
1000 *
1001 * This does not create remote sinks.
1002 */
detect_link_and_local_sink(struct dc_link * link,enum dc_detect_reason reason)1003 static bool detect_link_and_local_sink(struct dc_link *link,
1004 enum dc_detect_reason reason)
1005 {
1006 struct dc_sink_init_data sink_init_data = { 0 };
1007 struct display_sink_capability sink_caps = { 0 };
1008 uint32_t i;
1009 bool converter_disable_audio = false;
1010 struct audio_support *aud_support = &link->dc->res_pool->audio_support;
1011 bool same_edid = false;
1012 enum dc_edid_status edid_status;
1013 struct dc_context *dc_ctx = link->ctx;
1014 struct dc *dc = dc_ctx->dc;
1015 struct dc_sink *sink = NULL;
1016 struct dc_sink *prev_sink = NULL;
1017 struct dpcd_caps prev_dpcd_caps;
1018 enum dc_connection_type new_connection_type = dc_connection_none;
1019 const uint32_t post_oui_delay = 30; // 30ms
1020
1021 DC_LOGGER_INIT(link->ctx->logger);
1022
1023 if (dc_is_virtual_signal(link->connector_signal))
1024 return false;
1025
1026 if (((link->connector_signal == SIGNAL_TYPE_LVDS ||
1027 link->connector_signal == SIGNAL_TYPE_EDP) &&
1028 (!link->dc->config.allow_edp_hotplug_detection)) &&
1029 link->local_sink) {
1030 // need to re-write OUI and brightness in resume case
1031 if (link->connector_signal == SIGNAL_TYPE_EDP &&
1032 (link->dpcd_sink_ext_caps.bits.oled == 1)) {
1033 dpcd_set_source_specific_data(link);
1034 msleep(post_oui_delay);
1035 dc_link_set_default_brightness_aux(link);
1036 //TODO: use cached
1037 }
1038
1039 return true;
1040 }
1041
1042 if (!dc_link_detect_sink(link, &new_connection_type)) {
1043 BREAK_TO_DEBUGGER();
1044 return false;
1045 }
1046
1047 prev_sink = link->local_sink;
1048 if (prev_sink) {
1049 dc_sink_retain(prev_sink);
1050 memcpy(&prev_dpcd_caps, &link->dpcd_caps, sizeof(struct dpcd_caps));
1051 }
1052
1053 link_disconnect_sink(link);
1054 if (new_connection_type != dc_connection_none) {
1055 link->type = new_connection_type;
1056 link->link_state_valid = false;
1057
1058 /* From Disconnected-to-Connected. */
1059 switch (link->connector_signal) {
1060 case SIGNAL_TYPE_HDMI_TYPE_A: {
1061 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
1062 if (aud_support->hdmi_audio_native)
1063 sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A;
1064 else
1065 sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
1066 break;
1067 }
1068
1069 case SIGNAL_TYPE_DVI_SINGLE_LINK: {
1070 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
1071 sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
1072 break;
1073 }
1074
1075 case SIGNAL_TYPE_DVI_DUAL_LINK: {
1076 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
1077 sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK;
1078 break;
1079 }
1080
1081 case SIGNAL_TYPE_LVDS: {
1082 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
1083 sink_caps.signal = SIGNAL_TYPE_LVDS;
1084 break;
1085 }
1086
1087 case SIGNAL_TYPE_EDP: {
1088 read_current_link_settings_on_detect(link);
1089
1090 detect_edp_sink_caps(link);
1091 read_current_link_settings_on_detect(link);
1092
1093 /* Disable power sequence on MIPI panel + converter
1094 */
1095 if (dc->config.enable_mipi_converter_optimization &&
1096 dc_ctx->dce_version == DCN_VERSION_3_01 &&
1097 link->dpcd_caps.sink_dev_id == DP_BRANCH_DEVICE_ID_0022B9 &&
1098 memcmp(&link->dpcd_caps.branch_dev_name, DP_SINK_BRANCH_DEV_NAME_7580,
1099 sizeof(link->dpcd_caps.branch_dev_name)) == 0) {
1100 dc->config.edp_no_power_sequencing = true;
1101
1102 if (!link->dpcd_caps.set_power_state_capable_edp)
1103 link->wa_flags.dp_keep_receiver_powered = true;
1104 }
1105
1106 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
1107 sink_caps.signal = SIGNAL_TYPE_EDP;
1108 break;
1109 }
1110
1111 case SIGNAL_TYPE_DISPLAY_PORT: {
1112 /* wa HPD high coming too early*/
1113 if (link->ep_type == DISPLAY_ENDPOINT_PHY &&
1114 link->link_enc->features.flags.bits.DP_IS_USB_C == 1) {
1115 /* if alt mode times out, return false */
1116 if (!wait_for_entering_dp_alt_mode(link))
1117 return false;
1118 }
1119
1120 if (!detect_dp(link, &sink_caps, reason)) {
1121 if (prev_sink)
1122 dc_sink_release(prev_sink);
1123 return false;
1124 }
1125
1126 /* Active SST downstream branch device unplug*/
1127 if (link->type == dc_connection_sst_branch &&
1128 link->dpcd_caps.sink_count.bits.SINK_COUNT == 0) {
1129 if (prev_sink)
1130 /* Downstream unplug */
1131 dc_sink_release(prev_sink);
1132 return true;
1133 }
1134
1135 /* disable audio for non DP to HDMI active sst converter */
1136 if (link->type == dc_connection_sst_branch &&
1137 is_dp_active_dongle(link) &&
1138 (link->dpcd_caps.dongle_type !=
1139 DISPLAY_DONGLE_DP_HDMI_CONVERTER))
1140 converter_disable_audio = true;
1141 break;
1142 }
1143
1144 default:
1145 DC_ERROR("Invalid connector type! signal:%d\n",
1146 link->connector_signal);
1147 if (prev_sink)
1148 dc_sink_release(prev_sink);
1149 return false;
1150 } /* switch() */
1151
1152 if (link->dpcd_caps.sink_count.bits.SINK_COUNT)
1153 link->dpcd_sink_count =
1154 link->dpcd_caps.sink_count.bits.SINK_COUNT;
1155 else
1156 link->dpcd_sink_count = 1;
1157
1158 dal_ddc_service_set_transaction_type(link->ddc,
1159 sink_caps.transaction_type);
1160
1161 link->aux_mode =
1162 dal_ddc_service_is_in_aux_transaction_mode(link->ddc);
1163
1164 sink_init_data.link = link;
1165 sink_init_data.sink_signal = sink_caps.signal;
1166
1167 sink = dc_sink_create(&sink_init_data);
1168 if (!sink) {
1169 DC_ERROR("Failed to create sink!\n");
1170 if (prev_sink)
1171 dc_sink_release(prev_sink);
1172 return false;
1173 }
1174
1175 sink->link->dongle_max_pix_clk = sink_caps.max_hdmi_pixel_clock;
1176 sink->converter_disable_audio = converter_disable_audio;
1177
1178 /* dc_sink_create returns a new reference */
1179 link->local_sink = sink;
1180
1181 edid_status = dm_helpers_read_local_edid(link->ctx,
1182 link, sink);
1183
1184 switch (edid_status) {
1185 case EDID_BAD_CHECKSUM:
1186 DC_LOG_ERROR("EDID checksum invalid.\n");
1187 break;
1188 case EDID_PARTIAL_VALID:
1189 DC_LOG_ERROR("Partial EDID valid, abandon invalid blocks.\n");
1190 break;
1191 case EDID_NO_RESPONSE:
1192 DC_LOG_ERROR("No EDID read.\n");
1193 /*
1194 * Abort detection for non-DP connectors if we have
1195 * no EDID
1196 *
1197 * DP needs to report as connected if HDP is high
1198 * even if we have no EDID in order to go to
1199 * fail-safe mode
1200 */
1201 if (dc_is_hdmi_signal(link->connector_signal) ||
1202 dc_is_dvi_signal(link->connector_signal)) {
1203 if (prev_sink)
1204 dc_sink_release(prev_sink);
1205
1206 return false;
1207 }
1208
1209 if (link->type == dc_connection_sst_branch &&
1210 link->dpcd_caps.dongle_type ==
1211 DISPLAY_DONGLE_DP_VGA_CONVERTER &&
1212 reason == DETECT_REASON_HPDRX) {
1213 /* Abort detection for DP-VGA adapters when EDID
1214 * can't be read and detection reason is VGA-side
1215 * hotplug
1216 */
1217 if (prev_sink)
1218 dc_sink_release(prev_sink);
1219 link_disconnect_sink(link);
1220
1221 return true;
1222 }
1223
1224 break;
1225 default:
1226 break;
1227 }
1228
1229 // Check if edid is the same
1230 if ((prev_sink) &&
1231 (edid_status == EDID_THE_SAME || edid_status == EDID_OK))
1232 same_edid = is_same_edid(&prev_sink->dc_edid,
1233 &sink->dc_edid);
1234
1235 if (sink->edid_caps.panel_patch.skip_scdc_overwrite)
1236 link->ctx->dc->debug.hdmi20_disable = true;
1237
1238 if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT &&
1239 sink_caps.transaction_type ==
1240 DDC_TRANSACTION_TYPE_I2C_OVER_AUX) {
1241 /*
1242 * TODO debug why Dell 2413 doesn't like
1243 * two link trainings
1244 */
1245 #if defined(CONFIG_DRM_AMD_DC_HDCP)
1246 query_hdcp_capability(sink->sink_signal, link);
1247 #endif
1248 } else {
1249 // If edid is the same, then discard new sink and revert back to original sink
1250 if (same_edid) {
1251 link_disconnect_remap(prev_sink, link);
1252 sink = prev_sink;
1253 prev_sink = NULL;
1254 }
1255 #if defined(CONFIG_DRM_AMD_DC_HDCP)
1256 query_hdcp_capability(sink->sink_signal, link);
1257 #endif
1258 }
1259
1260 /* HDMI-DVI Dongle */
1261 if (sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A &&
1262 !sink->edid_caps.edid_hdmi)
1263 sink->sink_signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
1264
1265 if (link->local_sink && dc_is_dp_signal(sink_caps.signal))
1266 dp_trace_init(link);
1267
1268 /* Connectivity log: detection */
1269 for (i = 0; i < sink->dc_edid.length / DC_EDID_BLOCK_SIZE; i++) {
1270 CONN_DATA_DETECT(link,
1271 &sink->dc_edid.raw_edid[i * DC_EDID_BLOCK_SIZE],
1272 DC_EDID_BLOCK_SIZE,
1273 "%s: [Block %d] ", sink->edid_caps.display_name, i);
1274 }
1275
1276 DC_LOG_DETECTION_EDID_PARSER("%s: "
1277 "manufacturer_id = %X, "
1278 "product_id = %X, "
1279 "serial_number = %X, "
1280 "manufacture_week = %d, "
1281 "manufacture_year = %d, "
1282 "display_name = %s, "
1283 "speaker_flag = %d, "
1284 "audio_mode_count = %d\n",
1285 __func__,
1286 sink->edid_caps.manufacturer_id,
1287 sink->edid_caps.product_id,
1288 sink->edid_caps.serial_number,
1289 sink->edid_caps.manufacture_week,
1290 sink->edid_caps.manufacture_year,
1291 sink->edid_caps.display_name,
1292 sink->edid_caps.speaker_flags,
1293 sink->edid_caps.audio_mode_count);
1294
1295 for (i = 0; i < sink->edid_caps.audio_mode_count; i++) {
1296 DC_LOG_DETECTION_EDID_PARSER("%s: mode number = %d, "
1297 "format_code = %d, "
1298 "channel_count = %d, "
1299 "sample_rate = %d, "
1300 "sample_size = %d\n",
1301 __func__,
1302 i,
1303 sink->edid_caps.audio_modes[i].format_code,
1304 sink->edid_caps.audio_modes[i].channel_count,
1305 sink->edid_caps.audio_modes[i].sample_rate,
1306 sink->edid_caps.audio_modes[i].sample_size);
1307 }
1308
1309 if (link->connector_signal == SIGNAL_TYPE_EDP) {
1310 /* Init dc_panel_config by HW config */
1311 if (dc_ctx->dc->res_pool->funcs->get_panel_config_defaults)
1312 dc_ctx->dc->res_pool->funcs->get_panel_config_defaults(&link->panel_config);
1313 /* Pickup base DM settings */
1314 dm_helpers_init_panel_settings(dc_ctx, &link->panel_config, sink);
1315 // Override dc_panel_config if system has specific settings
1316 dm_helpers_override_panel_settings(dc_ctx, &link->panel_config);
1317 }
1318
1319 } else {
1320 /* From Connected-to-Disconnected. */
1321 link->type = dc_connection_none;
1322 sink_caps.signal = SIGNAL_TYPE_NONE;
1323 /* When we unplug a passive DP-HDMI dongle connection, dongle_max_pix_clk
1324 * is not cleared. If we emulate a DP signal on this connection, it thinks
1325 * the dongle is still there and limits the number of modes we can emulate.
1326 * Clear dongle_max_pix_clk on disconnect to fix this
1327 */
1328 link->dongle_max_pix_clk = 0;
1329
1330 dc_link_clear_dprx_states(link);
1331 dp_trace_reset(link);
1332 }
1333
1334 LINK_INFO("link=%d, dc_sink_in=%p is now %s prev_sink=%p edid same=%d\n",
1335 link->link_index, sink,
1336 (sink_caps.signal ==
1337 SIGNAL_TYPE_NONE ? "Disconnected" : "Connected"),
1338 prev_sink, same_edid);
1339
1340 if (prev_sink)
1341 dc_sink_release(prev_sink);
1342
1343 return true;
1344 }
1345
dc_link_detect(struct dc_link * link,enum dc_detect_reason reason)1346 bool dc_link_detect(struct dc_link *link, enum dc_detect_reason reason)
1347 {
1348 bool is_local_sink_detect_success;
1349 bool is_delegated_to_mst_top_mgr = false;
1350 enum dc_connection_type pre_link_type = link->type;
1351
1352 is_local_sink_detect_success = detect_link_and_local_sink(link, reason);
1353
1354 if (is_local_sink_detect_success && link->local_sink)
1355 verify_link_capability(link, link->local_sink, reason);
1356
1357 if (is_local_sink_detect_success && link->local_sink &&
1358 dc_is_dp_signal(link->local_sink->sink_signal) &&
1359 link->dpcd_caps.is_mst_capable)
1360 is_delegated_to_mst_top_mgr = discover_dp_mst_topology(link, reason);
1361
1362 if (is_local_sink_detect_success &&
1363 pre_link_type == dc_connection_mst_branch &&
1364 link->type != dc_connection_mst_branch)
1365 is_delegated_to_mst_top_mgr = reset_cur_dp_mst_topology(link);
1366
1367 return is_local_sink_detect_success && !is_delegated_to_mst_top_mgr;
1368 }
1369
dc_link_get_hpd_state(struct dc_link * dc_link)1370 bool dc_link_get_hpd_state(struct dc_link *dc_link)
1371 {
1372 uint32_t state;
1373
1374 dal_gpio_lock_pin(dc_link->hpd_gpio);
1375 dal_gpio_get_value(dc_link->hpd_gpio, &state);
1376 dal_gpio_unlock_pin(dc_link->hpd_gpio);
1377
1378 return state;
1379 }
1380
get_hpd_line(struct dc_link * link)1381 static enum hpd_source_id get_hpd_line(struct dc_link *link)
1382 {
1383 struct gpio *hpd;
1384 enum hpd_source_id hpd_id;
1385
1386 hpd_id = HPD_SOURCEID_UNKNOWN;
1387
1388 hpd = get_hpd_gpio(link->ctx->dc_bios, link->link_id,
1389 link->ctx->gpio_service);
1390
1391 if (hpd) {
1392 switch (dal_irq_get_source(hpd)) {
1393 case DC_IRQ_SOURCE_HPD1:
1394 hpd_id = HPD_SOURCEID1;
1395 break;
1396 case DC_IRQ_SOURCE_HPD2:
1397 hpd_id = HPD_SOURCEID2;
1398 break;
1399 case DC_IRQ_SOURCE_HPD3:
1400 hpd_id = HPD_SOURCEID3;
1401 break;
1402 case DC_IRQ_SOURCE_HPD4:
1403 hpd_id = HPD_SOURCEID4;
1404 break;
1405 case DC_IRQ_SOURCE_HPD5:
1406 hpd_id = HPD_SOURCEID5;
1407 break;
1408 case DC_IRQ_SOURCE_HPD6:
1409 hpd_id = HPD_SOURCEID6;
1410 break;
1411 default:
1412 BREAK_TO_DEBUGGER();
1413 break;
1414 }
1415
1416 dal_gpio_destroy_irq(&hpd);
1417 }
1418
1419 return hpd_id;
1420 }
1421
get_ddc_line(struct dc_link * link)1422 static enum channel_id get_ddc_line(struct dc_link *link)
1423 {
1424 struct ddc *ddc;
1425 enum channel_id channel;
1426
1427 channel = CHANNEL_ID_UNKNOWN;
1428
1429 ddc = dal_ddc_service_get_ddc_pin(link->ddc);
1430
1431 if (ddc) {
1432 switch (dal_ddc_get_line(ddc)) {
1433 case GPIO_DDC_LINE_DDC1:
1434 channel = CHANNEL_ID_DDC1;
1435 break;
1436 case GPIO_DDC_LINE_DDC2:
1437 channel = CHANNEL_ID_DDC2;
1438 break;
1439 case GPIO_DDC_LINE_DDC3:
1440 channel = CHANNEL_ID_DDC3;
1441 break;
1442 case GPIO_DDC_LINE_DDC4:
1443 channel = CHANNEL_ID_DDC4;
1444 break;
1445 case GPIO_DDC_LINE_DDC5:
1446 channel = CHANNEL_ID_DDC5;
1447 break;
1448 case GPIO_DDC_LINE_DDC6:
1449 channel = CHANNEL_ID_DDC6;
1450 break;
1451 case GPIO_DDC_LINE_DDC_VGA:
1452 channel = CHANNEL_ID_DDC_VGA;
1453 break;
1454 case GPIO_DDC_LINE_I2C_PAD:
1455 channel = CHANNEL_ID_I2C_PAD;
1456 break;
1457 default:
1458 BREAK_TO_DEBUGGER();
1459 break;
1460 }
1461 }
1462
1463 return channel;
1464 }
1465
translate_encoder_to_transmitter(struct graphics_object_id encoder)1466 static enum transmitter translate_encoder_to_transmitter(struct graphics_object_id encoder)
1467 {
1468 switch (encoder.id) {
1469 case ENCODER_ID_INTERNAL_UNIPHY:
1470 switch (encoder.enum_id) {
1471 case ENUM_ID_1:
1472 return TRANSMITTER_UNIPHY_A;
1473 case ENUM_ID_2:
1474 return TRANSMITTER_UNIPHY_B;
1475 default:
1476 return TRANSMITTER_UNKNOWN;
1477 }
1478 break;
1479 case ENCODER_ID_INTERNAL_UNIPHY1:
1480 switch (encoder.enum_id) {
1481 case ENUM_ID_1:
1482 return TRANSMITTER_UNIPHY_C;
1483 case ENUM_ID_2:
1484 return TRANSMITTER_UNIPHY_D;
1485 default:
1486 return TRANSMITTER_UNKNOWN;
1487 }
1488 break;
1489 case ENCODER_ID_INTERNAL_UNIPHY2:
1490 switch (encoder.enum_id) {
1491 case ENUM_ID_1:
1492 return TRANSMITTER_UNIPHY_E;
1493 case ENUM_ID_2:
1494 return TRANSMITTER_UNIPHY_F;
1495 default:
1496 return TRANSMITTER_UNKNOWN;
1497 }
1498 break;
1499 case ENCODER_ID_INTERNAL_UNIPHY3:
1500 switch (encoder.enum_id) {
1501 case ENUM_ID_1:
1502 return TRANSMITTER_UNIPHY_G;
1503 default:
1504 return TRANSMITTER_UNKNOWN;
1505 }
1506 break;
1507 case ENCODER_ID_EXTERNAL_NUTMEG:
1508 switch (encoder.enum_id) {
1509 case ENUM_ID_1:
1510 return TRANSMITTER_NUTMEG_CRT;
1511 default:
1512 return TRANSMITTER_UNKNOWN;
1513 }
1514 break;
1515 case ENCODER_ID_EXTERNAL_TRAVIS:
1516 switch (encoder.enum_id) {
1517 case ENUM_ID_1:
1518 return TRANSMITTER_TRAVIS_CRT;
1519 case ENUM_ID_2:
1520 return TRANSMITTER_TRAVIS_LCD;
1521 default:
1522 return TRANSMITTER_UNKNOWN;
1523 }
1524 break;
1525 default:
1526 return TRANSMITTER_UNKNOWN;
1527 }
1528 }
1529
dc_link_construct_legacy(struct dc_link * link,const struct link_init_data * init_params)1530 static bool dc_link_construct_legacy(struct dc_link *link,
1531 const struct link_init_data *init_params)
1532 {
1533 uint8_t i;
1534 struct ddc_service_init_data ddc_service_init_data = { 0 };
1535 struct dc_context *dc_ctx = init_params->ctx;
1536 struct encoder_init_data enc_init_data = { 0 };
1537 struct panel_cntl_init_data panel_cntl_init_data = { 0 };
1538 struct integrated_info *info;
1539 struct dc_bios *bios = init_params->dc->ctx->dc_bios;
1540 const struct dc_vbios_funcs *bp_funcs = bios->funcs;
1541 struct bp_disp_connector_caps_info disp_connect_caps_info = { 0 };
1542
1543 DC_LOGGER_INIT(dc_ctx->logger);
1544
1545 info = kzalloc(sizeof(*info), GFP_KERNEL);
1546 if (!info)
1547 goto create_fail;
1548
1549 link->irq_source_hpd = DC_IRQ_SOURCE_INVALID;
1550 link->irq_source_hpd_rx = DC_IRQ_SOURCE_INVALID;
1551
1552 link->link_status.dpcd_caps = &link->dpcd_caps;
1553
1554 link->dc = init_params->dc;
1555 link->ctx = dc_ctx;
1556 link->link_index = init_params->link_index;
1557
1558 memset(&link->preferred_training_settings, 0,
1559 sizeof(struct dc_link_training_overrides));
1560 memset(&link->preferred_link_setting, 0,
1561 sizeof(struct dc_link_settings));
1562
1563 link->link_id =
1564 bios->funcs->get_connector_id(bios, init_params->connector_index);
1565
1566 link->ep_type = DISPLAY_ENDPOINT_PHY;
1567
1568 DC_LOG_DC("BIOS object table - link_id: %d", link->link_id.id);
1569
1570 if (bios->funcs->get_disp_connector_caps_info) {
1571 bios->funcs->get_disp_connector_caps_info(bios, link->link_id, &disp_connect_caps_info);
1572 link->is_internal_display = disp_connect_caps_info.INTERNAL_DISPLAY;
1573 DC_LOG_DC("BIOS object table - is_internal_display: %d", link->is_internal_display);
1574 }
1575
1576 if (link->link_id.type != OBJECT_TYPE_CONNECTOR) {
1577 dm_output_to_console("%s: Invalid Connector ObjectID from Adapter Service for connector index:%d! type %d expected %d\n",
1578 __func__, init_params->connector_index,
1579 link->link_id.type, OBJECT_TYPE_CONNECTOR);
1580 goto create_fail;
1581 }
1582
1583 if (link->dc->res_pool->funcs->link_init)
1584 link->dc->res_pool->funcs->link_init(link);
1585
1586 link->hpd_gpio = get_hpd_gpio(link->ctx->dc_bios, link->link_id,
1587 link->ctx->gpio_service);
1588
1589 if (link->hpd_gpio) {
1590 dal_gpio_open(link->hpd_gpio, GPIO_MODE_INTERRUPT);
1591 dal_gpio_unlock_pin(link->hpd_gpio);
1592 link->irq_source_hpd = dal_irq_get_source(link->hpd_gpio);
1593
1594 DC_LOG_DC("BIOS object table - hpd_gpio id: %d", link->hpd_gpio->id);
1595 DC_LOG_DC("BIOS object table - hpd_gpio en: %d", link->hpd_gpio->en);
1596 }
1597
1598 switch (link->link_id.id) {
1599 case CONNECTOR_ID_HDMI_TYPE_A:
1600 link->connector_signal = SIGNAL_TYPE_HDMI_TYPE_A;
1601
1602 break;
1603 case CONNECTOR_ID_SINGLE_LINK_DVID:
1604 case CONNECTOR_ID_SINGLE_LINK_DVII:
1605 link->connector_signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
1606 break;
1607 case CONNECTOR_ID_DUAL_LINK_DVID:
1608 case CONNECTOR_ID_DUAL_LINK_DVII:
1609 link->connector_signal = SIGNAL_TYPE_DVI_DUAL_LINK;
1610 break;
1611 case CONNECTOR_ID_DISPLAY_PORT:
1612 case CONNECTOR_ID_USBC:
1613 link->connector_signal = SIGNAL_TYPE_DISPLAY_PORT;
1614
1615 if (link->hpd_gpio)
1616 link->irq_source_hpd_rx =
1617 dal_irq_get_rx_source(link->hpd_gpio);
1618
1619 break;
1620 case CONNECTOR_ID_EDP:
1621 link->connector_signal = SIGNAL_TYPE_EDP;
1622
1623 if (link->hpd_gpio) {
1624 if (!link->dc->config.allow_edp_hotplug_detection)
1625 link->irq_source_hpd = DC_IRQ_SOURCE_INVALID;
1626
1627 switch (link->dc->config.allow_edp_hotplug_detection) {
1628 case 1: // only the 1st eDP handles hotplug
1629 if (link->link_index == 0)
1630 link->irq_source_hpd_rx =
1631 dal_irq_get_rx_source(link->hpd_gpio);
1632 else
1633 link->irq_source_hpd = DC_IRQ_SOURCE_INVALID;
1634 break;
1635 case 2: // only the 2nd eDP handles hotplug
1636 if (link->link_index == 1)
1637 link->irq_source_hpd_rx =
1638 dal_irq_get_rx_source(link->hpd_gpio);
1639 else
1640 link->irq_source_hpd = DC_IRQ_SOURCE_INVALID;
1641 break;
1642 default:
1643 break;
1644 }
1645 }
1646
1647 break;
1648 case CONNECTOR_ID_LVDS:
1649 link->connector_signal = SIGNAL_TYPE_LVDS;
1650 break;
1651 default:
1652 DC_LOG_WARNING("Unsupported Connector type:%d!\n",
1653 link->link_id.id);
1654 goto create_fail;
1655 }
1656
1657 /* TODO: #DAL3 Implement id to str function.*/
1658 LINK_INFO("Connector[%d] description:"
1659 "signal %d\n",
1660 init_params->connector_index,
1661 link->connector_signal);
1662
1663 ddc_service_init_data.ctx = link->ctx;
1664 ddc_service_init_data.id = link->link_id;
1665 ddc_service_init_data.link = link;
1666 link->ddc = dal_ddc_service_create(&ddc_service_init_data);
1667
1668 if (!link->ddc) {
1669 DC_ERROR("Failed to create ddc_service!\n");
1670 goto ddc_create_fail;
1671 }
1672
1673 if (!link->ddc->ddc_pin) {
1674 DC_ERROR("Failed to get I2C info for connector!\n");
1675 goto ddc_create_fail;
1676 }
1677
1678 link->ddc_hw_inst =
1679 dal_ddc_get_line(dal_ddc_service_get_ddc_pin(link->ddc));
1680
1681
1682 if (link->dc->res_pool->funcs->panel_cntl_create &&
1683 (link->link_id.id == CONNECTOR_ID_EDP ||
1684 link->link_id.id == CONNECTOR_ID_LVDS)) {
1685 panel_cntl_init_data.ctx = dc_ctx;
1686 panel_cntl_init_data.inst =
1687 panel_cntl_init_data.ctx->dc_edp_id_count;
1688 link->panel_cntl =
1689 link->dc->res_pool->funcs->panel_cntl_create(
1690 &panel_cntl_init_data);
1691 panel_cntl_init_data.ctx->dc_edp_id_count++;
1692
1693 if (link->panel_cntl == NULL) {
1694 DC_ERROR("Failed to create link panel_cntl!\n");
1695 goto panel_cntl_create_fail;
1696 }
1697 }
1698
1699 enc_init_data.ctx = dc_ctx;
1700 bp_funcs->get_src_obj(dc_ctx->dc_bios, link->link_id, 0,
1701 &enc_init_data.encoder);
1702 enc_init_data.connector = link->link_id;
1703 enc_init_data.channel = get_ddc_line(link);
1704 enc_init_data.hpd_source = get_hpd_line(link);
1705
1706 link->hpd_src = enc_init_data.hpd_source;
1707
1708 enc_init_data.transmitter =
1709 translate_encoder_to_transmitter(enc_init_data.encoder);
1710 link->link_enc =
1711 link->dc->res_pool->funcs->link_enc_create(dc_ctx, &enc_init_data);
1712
1713 if (!link->link_enc) {
1714 DC_ERROR("Failed to create link encoder!\n");
1715 goto link_enc_create_fail;
1716 }
1717
1718 DC_LOG_DC("BIOS object table - DP_IS_USB_C: %d", link->link_enc->features.flags.bits.DP_IS_USB_C);
1719 DC_LOG_DC("BIOS object table - IS_DP2_CAPABLE: %d", link->link_enc->features.flags.bits.IS_DP2_CAPABLE);
1720
1721 /* Update link encoder tracking variables. These are used for the dynamic
1722 * assignment of link encoders to streams.
1723 */
1724 link->eng_id = link->link_enc->preferred_engine;
1725 link->dc->res_pool->link_encoders[link->eng_id - ENGINE_ID_DIGA] = link->link_enc;
1726 link->dc->res_pool->dig_link_enc_count++;
1727
1728 link->link_enc_hw_inst = link->link_enc->transmitter;
1729
1730 for (i = 0; i < 4; i++) {
1731 if (bp_funcs->get_device_tag(dc_ctx->dc_bios,
1732 link->link_id, i,
1733 &link->device_tag) != BP_RESULT_OK) {
1734 DC_ERROR("Failed to find device tag!\n");
1735 goto device_tag_fail;
1736 }
1737
1738 /* Look for device tag that matches connector signal,
1739 * CRT for rgb, LCD for other supported signal tyes
1740 */
1741 if (!bp_funcs->is_device_id_supported(dc_ctx->dc_bios,
1742 link->device_tag.dev_id))
1743 continue;
1744 if (link->device_tag.dev_id.device_type == DEVICE_TYPE_CRT &&
1745 link->connector_signal != SIGNAL_TYPE_RGB)
1746 continue;
1747 if (link->device_tag.dev_id.device_type == DEVICE_TYPE_LCD &&
1748 link->connector_signal == SIGNAL_TYPE_RGB)
1749 continue;
1750
1751 DC_LOG_DC("BIOS object table - device_tag.acpi_device: %d", link->device_tag.acpi_device);
1752 DC_LOG_DC("BIOS object table - device_tag.dev_id.device_type: %d", link->device_tag.dev_id.device_type);
1753 DC_LOG_DC("BIOS object table - device_tag.dev_id.enum_id: %d", link->device_tag.dev_id.enum_id);
1754 break;
1755 }
1756
1757 if (bios->integrated_info)
1758 memcpy(info, bios->integrated_info, sizeof(*info));
1759
1760 /* Look for channel mapping corresponding to connector and device tag */
1761 for (i = 0; i < MAX_NUMBER_OF_EXT_DISPLAY_PATH; i++) {
1762 struct external_display_path *path =
1763 &info->ext_disp_conn_info.path[i];
1764
1765 if (path->device_connector_id.enum_id == link->link_id.enum_id &&
1766 path->device_connector_id.id == link->link_id.id &&
1767 path->device_connector_id.type == link->link_id.type) {
1768 if (link->device_tag.acpi_device != 0 &&
1769 path->device_acpi_enum == link->device_tag.acpi_device) {
1770 link->ddi_channel_mapping = path->channel_mapping;
1771 link->chip_caps = path->caps;
1772 DC_LOG_DC("BIOS object table - ddi_channel_mapping: 0x%04X", link->ddi_channel_mapping.raw);
1773 DC_LOG_DC("BIOS object table - chip_caps: %d", link->chip_caps);
1774 } else if (path->device_tag ==
1775 link->device_tag.dev_id.raw_device_tag) {
1776 link->ddi_channel_mapping = path->channel_mapping;
1777 link->chip_caps = path->caps;
1778 DC_LOG_DC("BIOS object table - ddi_channel_mapping: 0x%04X", link->ddi_channel_mapping.raw);
1779 DC_LOG_DC("BIOS object table - chip_caps: %d", link->chip_caps);
1780 }
1781
1782 if (link->chip_caps & EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN) {
1783 link->bios_forced_drive_settings.VOLTAGE_SWING =
1784 (info->ext_disp_conn_info.fixdpvoltageswing & 0x3);
1785 link->bios_forced_drive_settings.PRE_EMPHASIS =
1786 ((info->ext_disp_conn_info.fixdpvoltageswing >> 2) & 0x3);
1787 }
1788
1789 break;
1790 }
1791 }
1792
1793 if (bios->funcs->get_atom_dc_golden_table)
1794 bios->funcs->get_atom_dc_golden_table(bios);
1795
1796 /*
1797 * TODO check if GPIO programmed correctly
1798 *
1799 * If GPIO isn't programmed correctly HPD might not rise or drain
1800 * fast enough, leading to bounces.
1801 */
1802 program_hpd_filter(link);
1803
1804 link->psr_settings.psr_vtotal_control_support = false;
1805 link->psr_settings.psr_version = DC_PSR_VERSION_UNSUPPORTED;
1806
1807 DC_LOG_DC("BIOS object table - %s finished successfully.\n", __func__);
1808 kfree(info);
1809 return true;
1810 device_tag_fail:
1811 link->link_enc->funcs->destroy(&link->link_enc);
1812 link_enc_create_fail:
1813 if (link->panel_cntl != NULL)
1814 link->panel_cntl->funcs->destroy(&link->panel_cntl);
1815 panel_cntl_create_fail:
1816 dal_ddc_service_destroy(&link->ddc);
1817 ddc_create_fail:
1818 create_fail:
1819
1820 if (link->hpd_gpio) {
1821 dal_gpio_destroy_irq(&link->hpd_gpio);
1822 link->hpd_gpio = NULL;
1823 }
1824
1825 DC_LOG_DC("BIOS object table - %s failed.\n", __func__);
1826 kfree(info);
1827
1828 return false;
1829 }
1830
dc_link_construct_dpia(struct dc_link * link,const struct link_init_data * init_params)1831 static bool dc_link_construct_dpia(struct dc_link *link,
1832 const struct link_init_data *init_params)
1833 {
1834 struct ddc_service_init_data ddc_service_init_data = { 0 };
1835 struct dc_context *dc_ctx = init_params->ctx;
1836
1837 DC_LOGGER_INIT(dc_ctx->logger);
1838
1839 /* Initialized irq source for hpd and hpd rx */
1840 link->irq_source_hpd = DC_IRQ_SOURCE_INVALID;
1841 link->irq_source_hpd_rx = DC_IRQ_SOURCE_INVALID;
1842 link->link_status.dpcd_caps = &link->dpcd_caps;
1843
1844 link->dc = init_params->dc;
1845 link->ctx = dc_ctx;
1846 link->link_index = init_params->link_index;
1847
1848 memset(&link->preferred_training_settings, 0,
1849 sizeof(struct dc_link_training_overrides));
1850 memset(&link->preferred_link_setting, 0,
1851 sizeof(struct dc_link_settings));
1852
1853 /* Dummy Init for linkid */
1854 link->link_id.type = OBJECT_TYPE_CONNECTOR;
1855 link->link_id.id = CONNECTOR_ID_DISPLAY_PORT;
1856 link->link_id.enum_id = ENUM_ID_1 + init_params->connector_index;
1857 link->is_internal_display = false;
1858 link->connector_signal = SIGNAL_TYPE_DISPLAY_PORT;
1859 LINK_INFO("Connector[%d] description:signal %d\n",
1860 init_params->connector_index,
1861 link->connector_signal);
1862
1863 link->ep_type = DISPLAY_ENDPOINT_USB4_DPIA;
1864 link->is_dig_mapping_flexible = true;
1865
1866 /* TODO: Initialize link : funcs->link_init */
1867
1868 ddc_service_init_data.ctx = link->ctx;
1869 ddc_service_init_data.id = link->link_id;
1870 ddc_service_init_data.link = link;
1871 /* Set indicator for dpia link so that ddc won't be created */
1872 ddc_service_init_data.is_dpia_link = true;
1873
1874 link->ddc = dal_ddc_service_create(&ddc_service_init_data);
1875 if (!link->ddc) {
1876 DC_ERROR("Failed to create ddc_service!\n");
1877 goto ddc_create_fail;
1878 }
1879
1880 /* Set dpia port index : 0 to number of dpia ports */
1881 link->ddc_hw_inst = init_params->connector_index;
1882
1883 /* TODO: Create link encoder */
1884
1885 link->psr_settings.psr_version = DC_PSR_VERSION_UNSUPPORTED;
1886
1887 /* Some docks seem to NAK I2C writes to segment pointer with mot=0. */
1888 link->wa_flags.dp_mot_reset_segment = true;
1889
1890 return true;
1891
1892 ddc_create_fail:
1893 return false;
1894 }
1895
dc_link_construct(struct dc_link * link,const struct link_init_data * init_params)1896 static bool dc_link_construct(struct dc_link *link,
1897 const struct link_init_data *init_params)
1898 {
1899 /* Handle dpia case */
1900 if (init_params->is_dpia_link)
1901 return dc_link_construct_dpia(link, init_params);
1902 else
1903 return dc_link_construct_legacy(link, init_params);
1904 }
1905 /*******************************************************************************
1906 * Public functions
1907 ******************************************************************************/
link_create(const struct link_init_data * init_params)1908 struct dc_link *link_create(const struct link_init_data *init_params)
1909 {
1910 struct dc_link *link =
1911 kzalloc(sizeof(*link), GFP_KERNEL);
1912
1913 if (NULL == link)
1914 goto alloc_fail;
1915
1916 if (false == dc_link_construct(link, init_params))
1917 goto construct_fail;
1918
1919 /*
1920 * Must use preferred_link_setting, not reported_link_cap or verified_link_cap,
1921 * since struct preferred_link_setting won't be reset after S3.
1922 */
1923 link->preferred_link_setting.dpcd_source_device_specific_field_support = true;
1924
1925 return link;
1926
1927 construct_fail:
1928 kfree(link);
1929
1930 alloc_fail:
1931 return NULL;
1932 }
1933
link_destroy(struct dc_link ** link)1934 void link_destroy(struct dc_link **link)
1935 {
1936 dc_link_destruct(*link);
1937 kfree(*link);
1938 *link = NULL;
1939 }
1940
enable_stream_features(struct pipe_ctx * pipe_ctx)1941 static void enable_stream_features(struct pipe_ctx *pipe_ctx)
1942 {
1943 struct dc_stream_state *stream = pipe_ctx->stream;
1944
1945 if (pipe_ctx->stream->signal != SIGNAL_TYPE_DISPLAY_PORT_MST) {
1946 struct dc_link *link = stream->link;
1947 union down_spread_ctrl old_downspread;
1948 union down_spread_ctrl new_downspread;
1949
1950 memset(&old_downspread, 0, sizeof(old_downspread));
1951
1952 core_link_read_dpcd(link, DP_DOWNSPREAD_CTRL,
1953 &old_downspread.raw, sizeof(old_downspread));
1954
1955 new_downspread.raw = old_downspread.raw;
1956
1957 new_downspread.bits.IGNORE_MSA_TIMING_PARAM =
1958 (stream->ignore_msa_timing_param) ? 1 : 0;
1959
1960 if (new_downspread.raw != old_downspread.raw) {
1961 core_link_write_dpcd(link, DP_DOWNSPREAD_CTRL,
1962 &new_downspread.raw, sizeof(new_downspread));
1963 }
1964
1965 } else {
1966 dm_helpers_mst_enable_stream_features(stream);
1967 }
1968 }
1969
enable_link_dp(struct dc_state * state,struct pipe_ctx * pipe_ctx)1970 static enum dc_status enable_link_dp(struct dc_state *state,
1971 struct pipe_ctx *pipe_ctx)
1972 {
1973 struct dc_stream_state *stream = pipe_ctx->stream;
1974 enum dc_status status;
1975 bool skip_video_pattern;
1976 struct dc_link *link = stream->link;
1977 const struct dc_link_settings *link_settings =
1978 &pipe_ctx->link_config.dp_link_settings;
1979 bool fec_enable;
1980 int i;
1981 bool apply_seamless_boot_optimization = false;
1982 uint32_t bl_oled_enable_delay = 50; // in ms
1983 uint32_t post_oui_delay = 30; // 30ms
1984 /* Reduce link bandwidth between failed link training attempts. */
1985 bool do_fallback = false;
1986
1987 // check for seamless boot
1988 for (i = 0; i < state->stream_count; i++) {
1989 if (state->streams[i]->apply_seamless_boot_optimization) {
1990 apply_seamless_boot_optimization = true;
1991 break;
1992 }
1993 }
1994
1995 /* Train with fallback when enabling DPIA link. Conventional links are
1996 * trained with fallback during sink detection.
1997 */
1998 if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA)
1999 do_fallback = true;
2000
2001 /*
2002 * Temporary w/a to get DP2.0 link rates to work with SST.
2003 * TODO DP2.0 - Workaround: Remove w/a if and when the issue is resolved.
2004 */
2005 if (dp_get_link_encoding_format(link_settings) == DP_128b_132b_ENCODING &&
2006 pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT &&
2007 link->dc->debug.set_mst_en_for_sst) {
2008 dp_enable_mst_on_sink(link, true);
2009 }
2010
2011 if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP) {
2012 /*in case it is not on*/
2013 if (!link->dc->config.edp_no_power_sequencing)
2014 link->dc->hwss.edp_power_control(link, true);
2015 link->dc->hwss.edp_wait_for_hpd_ready(link, true);
2016 }
2017
2018 if (dp_get_link_encoding_format(link_settings) == DP_128b_132b_ENCODING) {
2019 /* TODO - DP2.0 HW: calculate 32 symbol clock for HPO encoder */
2020 } else {
2021 pipe_ctx->stream_res.pix_clk_params.requested_sym_clk =
2022 link_settings->link_rate * LINK_RATE_REF_FREQ_IN_KHZ;
2023 if (state->clk_mgr && !apply_seamless_boot_optimization)
2024 state->clk_mgr->funcs->update_clocks(state->clk_mgr,
2025 state, false);
2026 }
2027
2028 // during mode switch we do DP_SET_POWER off then on, and OUI is lost
2029 dpcd_set_source_specific_data(link);
2030 if (link->dpcd_sink_ext_caps.raw != 0) {
2031 post_oui_delay += link->panel_config.pps.extra_post_OUI_ms;
2032 msleep(post_oui_delay);
2033 }
2034
2035 // similarly, mode switch can cause loss of cable ID
2036 dpcd_write_cable_id_to_dprx(link);
2037
2038 skip_video_pattern = true;
2039
2040 if (link_settings->link_rate == LINK_RATE_LOW)
2041 skip_video_pattern = false;
2042
2043 if (perform_link_training_with_retries(link_settings,
2044 skip_video_pattern,
2045 LINK_TRAINING_ATTEMPTS,
2046 pipe_ctx,
2047 pipe_ctx->stream->signal,
2048 do_fallback)) {
2049 status = DC_OK;
2050 } else {
2051 status = DC_FAIL_DP_LINK_TRAINING;
2052 }
2053
2054 if (link->preferred_training_settings.fec_enable)
2055 fec_enable = *link->preferred_training_settings.fec_enable;
2056 else
2057 fec_enable = true;
2058
2059 if (dp_get_link_encoding_format(link_settings) == DP_8b_10b_ENCODING)
2060 dp_set_fec_enable(link, fec_enable);
2061
2062 // during mode set we do DP_SET_POWER off then on, aux writes are lost
2063 if (link->dpcd_sink_ext_caps.bits.oled == 1 ||
2064 link->dpcd_sink_ext_caps.bits.sdr_aux_backlight_control == 1 ||
2065 link->dpcd_sink_ext_caps.bits.hdr_aux_backlight_control == 1) {
2066 dc_link_set_default_brightness_aux(link); // TODO: use cached if known
2067 if (link->dpcd_sink_ext_caps.bits.oled == 1)
2068 msleep(bl_oled_enable_delay);
2069 dc_link_backlight_enable_aux(link, true);
2070 }
2071
2072 return status;
2073 }
2074
enable_link_edp(struct dc_state * state,struct pipe_ctx * pipe_ctx)2075 static enum dc_status enable_link_edp(
2076 struct dc_state *state,
2077 struct pipe_ctx *pipe_ctx)
2078 {
2079 return enable_link_dp(state, pipe_ctx);
2080 }
2081
enable_link_dp_mst(struct dc_state * state,struct pipe_ctx * pipe_ctx)2082 static enum dc_status enable_link_dp_mst(
2083 struct dc_state *state,
2084 struct pipe_ctx *pipe_ctx)
2085 {
2086 struct dc_link *link = pipe_ctx->stream->link;
2087
2088 /* sink signal type after MST branch is MST. Multiple MST sinks
2089 * share one link. Link DP PHY is enable or training only once.
2090 */
2091 if (link->link_status.link_active)
2092 return DC_OK;
2093
2094 /* clear payload table */
2095 dm_helpers_dp_mst_clear_payload_allocation_table(link->ctx, link);
2096
2097 /* to make sure the pending down rep can be processed
2098 * before enabling the link
2099 */
2100 dm_helpers_dp_mst_poll_pending_down_reply(link->ctx, link);
2101
2102 /* set the sink to MST mode before enabling the link */
2103 dp_enable_mst_on_sink(link, true);
2104
2105 return enable_link_dp(state, pipe_ctx);
2106 }
2107
dc_link_blank_all_dp_displays(struct dc * dc)2108 void dc_link_blank_all_dp_displays(struct dc *dc)
2109 {
2110 unsigned int i;
2111 uint8_t dpcd_power_state = '\0';
2112 enum dc_status status = DC_ERROR_UNEXPECTED;
2113
2114 for (i = 0; i < dc->link_count; i++) {
2115 if ((dc->links[i]->connector_signal != SIGNAL_TYPE_DISPLAY_PORT) ||
2116 (dc->links[i]->priv == NULL) || (dc->links[i]->local_sink == NULL))
2117 continue;
2118
2119 /* DP 2.0 spec requires that we read LTTPR caps first */
2120 dp_retrieve_lttpr_cap(dc->links[i]);
2121 /* if any of the displays are lit up turn them off */
2122 status = core_link_read_dpcd(dc->links[i], DP_SET_POWER,
2123 &dpcd_power_state, sizeof(dpcd_power_state));
2124
2125 if (status == DC_OK && dpcd_power_state == DP_POWER_STATE_D0)
2126 dc_link_blank_dp_stream(dc->links[i], true);
2127 }
2128
2129 }
2130
dc_link_blank_all_edp_displays(struct dc * dc)2131 void dc_link_blank_all_edp_displays(struct dc *dc)
2132 {
2133 unsigned int i;
2134 uint8_t dpcd_power_state = '\0';
2135 enum dc_status status = DC_ERROR_UNEXPECTED;
2136
2137 for (i = 0; i < dc->link_count; i++) {
2138 if ((dc->links[i]->connector_signal != SIGNAL_TYPE_EDP) ||
2139 (!dc->links[i]->edp_sink_present))
2140 continue;
2141
2142 /* if any of the displays are lit up turn them off */
2143 status = core_link_read_dpcd(dc->links[i], DP_SET_POWER,
2144 &dpcd_power_state, sizeof(dpcd_power_state));
2145
2146 if (status == DC_OK && dpcd_power_state == DP_POWER_STATE_D0)
2147 dc_link_blank_dp_stream(dc->links[i], true);
2148 }
2149 }
2150
dc_link_blank_dp_stream(struct dc_link * link,bool hw_init)2151 void dc_link_blank_dp_stream(struct dc_link *link, bool hw_init)
2152 {
2153 unsigned int j;
2154 struct dc *dc = link->ctx->dc;
2155 enum signal_type signal = link->connector_signal;
2156
2157 if ((signal == SIGNAL_TYPE_EDP) ||
2158 (signal == SIGNAL_TYPE_DISPLAY_PORT)) {
2159 if (link->ep_type == DISPLAY_ENDPOINT_PHY &&
2160 link->link_enc->funcs->get_dig_frontend &&
2161 link->link_enc->funcs->is_dig_enabled(link->link_enc)) {
2162 unsigned int fe = link->link_enc->funcs->get_dig_frontend(link->link_enc);
2163
2164 if (fe != ENGINE_ID_UNKNOWN)
2165 for (j = 0; j < dc->res_pool->stream_enc_count; j++) {
2166 if (fe == dc->res_pool->stream_enc[j]->id) {
2167 dc->res_pool->stream_enc[j]->funcs->dp_blank(link,
2168 dc->res_pool->stream_enc[j]);
2169 break;
2170 }
2171 }
2172 }
2173
2174 if ((!link->wa_flags.dp_keep_receiver_powered) || hw_init)
2175 dp_receiver_power_ctrl(link, false);
2176 }
2177 }
2178
get_ext_hdmi_settings(struct pipe_ctx * pipe_ctx,enum engine_id eng_id,struct ext_hdmi_settings * settings)2179 static bool get_ext_hdmi_settings(struct pipe_ctx *pipe_ctx,
2180 enum engine_id eng_id,
2181 struct ext_hdmi_settings *settings)
2182 {
2183 bool result = false;
2184 int i = 0;
2185 struct integrated_info *integrated_info =
2186 pipe_ctx->stream->ctx->dc_bios->integrated_info;
2187
2188 if (integrated_info == NULL)
2189 return false;
2190
2191 /*
2192 * Get retimer settings from sbios for passing SI eye test for DCE11
2193 * The setting values are varied based on board revision and port id
2194 * Therefore the setting values of each ports is passed by sbios.
2195 */
2196
2197 // Check if current bios contains ext Hdmi settings
2198 if (integrated_info->gpu_cap_info & 0x20) {
2199 switch (eng_id) {
2200 case ENGINE_ID_DIGA:
2201 settings->slv_addr = integrated_info->dp0_ext_hdmi_slv_addr;
2202 settings->reg_num = integrated_info->dp0_ext_hdmi_6g_reg_num;
2203 settings->reg_num_6g = integrated_info->dp0_ext_hdmi_6g_reg_num;
2204 memmove(settings->reg_settings,
2205 integrated_info->dp0_ext_hdmi_reg_settings,
2206 sizeof(integrated_info->dp0_ext_hdmi_reg_settings));
2207 memmove(settings->reg_settings_6g,
2208 integrated_info->dp0_ext_hdmi_6g_reg_settings,
2209 sizeof(integrated_info->dp0_ext_hdmi_6g_reg_settings));
2210 result = true;
2211 break;
2212 case ENGINE_ID_DIGB:
2213 settings->slv_addr = integrated_info->dp1_ext_hdmi_slv_addr;
2214 settings->reg_num = integrated_info->dp1_ext_hdmi_6g_reg_num;
2215 settings->reg_num_6g = integrated_info->dp1_ext_hdmi_6g_reg_num;
2216 memmove(settings->reg_settings,
2217 integrated_info->dp1_ext_hdmi_reg_settings,
2218 sizeof(integrated_info->dp1_ext_hdmi_reg_settings));
2219 memmove(settings->reg_settings_6g,
2220 integrated_info->dp1_ext_hdmi_6g_reg_settings,
2221 sizeof(integrated_info->dp1_ext_hdmi_6g_reg_settings));
2222 result = true;
2223 break;
2224 case ENGINE_ID_DIGC:
2225 settings->slv_addr = integrated_info->dp2_ext_hdmi_slv_addr;
2226 settings->reg_num = integrated_info->dp2_ext_hdmi_6g_reg_num;
2227 settings->reg_num_6g = integrated_info->dp2_ext_hdmi_6g_reg_num;
2228 memmove(settings->reg_settings,
2229 integrated_info->dp2_ext_hdmi_reg_settings,
2230 sizeof(integrated_info->dp2_ext_hdmi_reg_settings));
2231 memmove(settings->reg_settings_6g,
2232 integrated_info->dp2_ext_hdmi_6g_reg_settings,
2233 sizeof(integrated_info->dp2_ext_hdmi_6g_reg_settings));
2234 result = true;
2235 break;
2236 case ENGINE_ID_DIGD:
2237 settings->slv_addr = integrated_info->dp3_ext_hdmi_slv_addr;
2238 settings->reg_num = integrated_info->dp3_ext_hdmi_6g_reg_num;
2239 settings->reg_num_6g = integrated_info->dp3_ext_hdmi_6g_reg_num;
2240 memmove(settings->reg_settings,
2241 integrated_info->dp3_ext_hdmi_reg_settings,
2242 sizeof(integrated_info->dp3_ext_hdmi_reg_settings));
2243 memmove(settings->reg_settings_6g,
2244 integrated_info->dp3_ext_hdmi_6g_reg_settings,
2245 sizeof(integrated_info->dp3_ext_hdmi_6g_reg_settings));
2246 result = true;
2247 break;
2248 default:
2249 break;
2250 }
2251
2252 if (result == true) {
2253 // Validate settings from bios integrated info table
2254 if (settings->slv_addr == 0)
2255 return false;
2256 if (settings->reg_num > 9)
2257 return false;
2258 if (settings->reg_num_6g > 3)
2259 return false;
2260
2261 for (i = 0; i < settings->reg_num; i++) {
2262 if (settings->reg_settings[i].i2c_reg_index > 0x20)
2263 return false;
2264 }
2265
2266 for (i = 0; i < settings->reg_num_6g; i++) {
2267 if (settings->reg_settings_6g[i].i2c_reg_index > 0x20)
2268 return false;
2269 }
2270 }
2271 }
2272
2273 return result;
2274 }
2275
i2c_write(struct pipe_ctx * pipe_ctx,uint8_t address,uint8_t * buffer,uint32_t length)2276 static bool i2c_write(struct pipe_ctx *pipe_ctx,
2277 uint8_t address, uint8_t *buffer, uint32_t length)
2278 {
2279 struct i2c_command cmd = {0};
2280 struct i2c_payload payload = {0};
2281
2282 memset(&payload, 0, sizeof(payload));
2283 memset(&cmd, 0, sizeof(cmd));
2284
2285 cmd.number_of_payloads = 1;
2286 cmd.engine = I2C_COMMAND_ENGINE_DEFAULT;
2287 cmd.speed = pipe_ctx->stream->ctx->dc->caps.i2c_speed_in_khz;
2288
2289 payload.address = address;
2290 payload.data = buffer;
2291 payload.length = length;
2292 payload.write = true;
2293 cmd.payloads = &payload;
2294
2295 if (dm_helpers_submit_i2c(pipe_ctx->stream->ctx,
2296 pipe_ctx->stream->link, &cmd))
2297 return true;
2298
2299 return false;
2300 }
2301
write_i2c_retimer_setting(struct pipe_ctx * pipe_ctx,bool is_vga_mode,bool is_over_340mhz,struct ext_hdmi_settings * settings)2302 static void write_i2c_retimer_setting(
2303 struct pipe_ctx *pipe_ctx,
2304 bool is_vga_mode,
2305 bool is_over_340mhz,
2306 struct ext_hdmi_settings *settings)
2307 {
2308 uint8_t slave_address = (settings->slv_addr >> 1);
2309 uint8_t buffer[2];
2310 const uint8_t apply_rx_tx_change = 0x4;
2311 uint8_t offset = 0xA;
2312 uint8_t value = 0;
2313 int i = 0;
2314 bool i2c_success = false;
2315 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
2316
2317 memset(&buffer, 0, sizeof(buffer));
2318
2319 /* Start Ext-Hdmi programming*/
2320
2321 for (i = 0; i < settings->reg_num; i++) {
2322 /* Apply 3G settings */
2323 if (settings->reg_settings[i].i2c_reg_index <= 0x20) {
2324
2325 buffer[0] = settings->reg_settings[i].i2c_reg_index;
2326 buffer[1] = settings->reg_settings[i].i2c_reg_val;
2327 i2c_success = i2c_write(pipe_ctx, slave_address,
2328 buffer, sizeof(buffer));
2329 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
2330 offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n",
2331 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2332
2333 if (!i2c_success)
2334 goto i2c_write_fail;
2335
2336 /* Based on DP159 specs, APPLY_RX_TX_CHANGE bit in 0x0A
2337 * needs to be set to 1 on every 0xA-0xC write.
2338 */
2339 if (settings->reg_settings[i].i2c_reg_index == 0xA ||
2340 settings->reg_settings[i].i2c_reg_index == 0xB ||
2341 settings->reg_settings[i].i2c_reg_index == 0xC) {
2342
2343 /* Query current value from offset 0xA */
2344 if (settings->reg_settings[i].i2c_reg_index == 0xA)
2345 value = settings->reg_settings[i].i2c_reg_val;
2346 else {
2347 i2c_success =
2348 dal_ddc_service_query_ddc_data(
2349 pipe_ctx->stream->link->ddc,
2350 slave_address, &offset, 1, &value, 1);
2351 if (!i2c_success)
2352 goto i2c_write_fail;
2353 }
2354
2355 buffer[0] = offset;
2356 /* Set APPLY_RX_TX_CHANGE bit to 1 */
2357 buffer[1] = value | apply_rx_tx_change;
2358 i2c_success = i2c_write(pipe_ctx, slave_address,
2359 buffer, sizeof(buffer));
2360 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
2361 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2362 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2363 if (!i2c_success)
2364 goto i2c_write_fail;
2365 }
2366 }
2367 }
2368
2369 /* Apply 3G settings */
2370 if (is_over_340mhz) {
2371 for (i = 0; i < settings->reg_num_6g; i++) {
2372 /* Apply 3G settings */
2373 if (settings->reg_settings[i].i2c_reg_index <= 0x20) {
2374
2375 buffer[0] = settings->reg_settings_6g[i].i2c_reg_index;
2376 buffer[1] = settings->reg_settings_6g[i].i2c_reg_val;
2377 i2c_success = i2c_write(pipe_ctx, slave_address,
2378 buffer, sizeof(buffer));
2379 RETIMER_REDRIVER_INFO("above 340Mhz: retimer write to slave_address = 0x%x,\
2380 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2381 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2382
2383 if (!i2c_success)
2384 goto i2c_write_fail;
2385
2386 /* Based on DP159 specs, APPLY_RX_TX_CHANGE bit in 0x0A
2387 * needs to be set to 1 on every 0xA-0xC write.
2388 */
2389 if (settings->reg_settings_6g[i].i2c_reg_index == 0xA ||
2390 settings->reg_settings_6g[i].i2c_reg_index == 0xB ||
2391 settings->reg_settings_6g[i].i2c_reg_index == 0xC) {
2392
2393 /* Query current value from offset 0xA */
2394 if (settings->reg_settings_6g[i].i2c_reg_index == 0xA)
2395 value = settings->reg_settings_6g[i].i2c_reg_val;
2396 else {
2397 i2c_success =
2398 dal_ddc_service_query_ddc_data(
2399 pipe_ctx->stream->link->ddc,
2400 slave_address, &offset, 1, &value, 1);
2401 if (!i2c_success)
2402 goto i2c_write_fail;
2403 }
2404
2405 buffer[0] = offset;
2406 /* Set APPLY_RX_TX_CHANGE bit to 1 */
2407 buffer[1] = value | apply_rx_tx_change;
2408 i2c_success = i2c_write(pipe_ctx, slave_address,
2409 buffer, sizeof(buffer));
2410 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
2411 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2412 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2413 if (!i2c_success)
2414 goto i2c_write_fail;
2415 }
2416 }
2417 }
2418 }
2419
2420 if (is_vga_mode) {
2421 /* Program additional settings if using 640x480 resolution */
2422
2423 /* Write offset 0xFF to 0x01 */
2424 buffer[0] = 0xff;
2425 buffer[1] = 0x01;
2426 i2c_success = i2c_write(pipe_ctx, slave_address,
2427 buffer, sizeof(buffer));
2428 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
2429 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2430 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2431 if (!i2c_success)
2432 goto i2c_write_fail;
2433
2434 /* Write offset 0x00 to 0x23 */
2435 buffer[0] = 0x00;
2436 buffer[1] = 0x23;
2437 i2c_success = i2c_write(pipe_ctx, slave_address,
2438 buffer, sizeof(buffer));
2439 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
2440 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2441 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2442 if (!i2c_success)
2443 goto i2c_write_fail;
2444
2445 /* Write offset 0xff to 0x00 */
2446 buffer[0] = 0xff;
2447 buffer[1] = 0x00;
2448 i2c_success = i2c_write(pipe_ctx, slave_address,
2449 buffer, sizeof(buffer));
2450 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
2451 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2452 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2453 if (!i2c_success)
2454 goto i2c_write_fail;
2455
2456 }
2457
2458 return;
2459
2460 i2c_write_fail:
2461 DC_LOG_DEBUG("Set retimer failed");
2462 }
2463
write_i2c_default_retimer_setting(struct pipe_ctx * pipe_ctx,bool is_vga_mode,bool is_over_340mhz)2464 static void write_i2c_default_retimer_setting(
2465 struct pipe_ctx *pipe_ctx,
2466 bool is_vga_mode,
2467 bool is_over_340mhz)
2468 {
2469 uint8_t slave_address = (0xBA >> 1);
2470 uint8_t buffer[2];
2471 bool i2c_success = false;
2472 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
2473
2474 memset(&buffer, 0, sizeof(buffer));
2475
2476 /* Program Slave Address for tuning single integrity */
2477 /* Write offset 0x0A to 0x13 */
2478 buffer[0] = 0x0A;
2479 buffer[1] = 0x13;
2480 i2c_success = i2c_write(pipe_ctx, slave_address,
2481 buffer, sizeof(buffer));
2482 RETIMER_REDRIVER_INFO("retimer writes default setting to slave_address = 0x%x,\
2483 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2484 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2485 if (!i2c_success)
2486 goto i2c_write_fail;
2487
2488 /* Write offset 0x0A to 0x17 */
2489 buffer[0] = 0x0A;
2490 buffer[1] = 0x17;
2491 i2c_success = i2c_write(pipe_ctx, slave_address,
2492 buffer, sizeof(buffer));
2493 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
2494 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2495 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2496 if (!i2c_success)
2497 goto i2c_write_fail;
2498
2499 /* Write offset 0x0B to 0xDA or 0xD8 */
2500 buffer[0] = 0x0B;
2501 buffer[1] = is_over_340mhz ? 0xDA : 0xD8;
2502 i2c_success = i2c_write(pipe_ctx, slave_address,
2503 buffer, sizeof(buffer));
2504 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
2505 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2506 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2507 if (!i2c_success)
2508 goto i2c_write_fail;
2509
2510 /* Write offset 0x0A to 0x17 */
2511 buffer[0] = 0x0A;
2512 buffer[1] = 0x17;
2513 i2c_success = i2c_write(pipe_ctx, slave_address,
2514 buffer, sizeof(buffer));
2515 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
2516 offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n",
2517 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2518 if (!i2c_success)
2519 goto i2c_write_fail;
2520
2521 /* Write offset 0x0C to 0x1D or 0x91 */
2522 buffer[0] = 0x0C;
2523 buffer[1] = is_over_340mhz ? 0x1D : 0x91;
2524 i2c_success = i2c_write(pipe_ctx, slave_address,
2525 buffer, sizeof(buffer));
2526 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
2527 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2528 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2529 if (!i2c_success)
2530 goto i2c_write_fail;
2531
2532 /* Write offset 0x0A to 0x17 */
2533 buffer[0] = 0x0A;
2534 buffer[1] = 0x17;
2535 i2c_success = i2c_write(pipe_ctx, slave_address,
2536 buffer, sizeof(buffer));
2537 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
2538 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2539 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2540 if (!i2c_success)
2541 goto i2c_write_fail;
2542
2543
2544 if (is_vga_mode) {
2545 /* Program additional settings if using 640x480 resolution */
2546
2547 /* Write offset 0xFF to 0x01 */
2548 buffer[0] = 0xff;
2549 buffer[1] = 0x01;
2550 i2c_success = i2c_write(pipe_ctx, slave_address,
2551 buffer, sizeof(buffer));
2552 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
2553 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2554 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2555 if (!i2c_success)
2556 goto i2c_write_fail;
2557
2558 /* Write offset 0x00 to 0x23 */
2559 buffer[0] = 0x00;
2560 buffer[1] = 0x23;
2561 i2c_success = i2c_write(pipe_ctx, slave_address,
2562 buffer, sizeof(buffer));
2563 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
2564 offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n",
2565 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2566 if (!i2c_success)
2567 goto i2c_write_fail;
2568
2569 /* Write offset 0xff to 0x00 */
2570 buffer[0] = 0xff;
2571 buffer[1] = 0x00;
2572 i2c_success = i2c_write(pipe_ctx, slave_address,
2573 buffer, sizeof(buffer));
2574 RETIMER_REDRIVER_INFO("retimer write default setting to slave_addr = 0x%x,\
2575 offset = 0x%x, reg_val= 0x%x, i2c_success = %d end here\n",
2576 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2577 if (!i2c_success)
2578 goto i2c_write_fail;
2579 }
2580
2581 return;
2582
2583 i2c_write_fail:
2584 DC_LOG_DEBUG("Set default retimer failed");
2585 }
2586
write_i2c_redriver_setting(struct pipe_ctx * pipe_ctx,bool is_over_340mhz)2587 static void write_i2c_redriver_setting(
2588 struct pipe_ctx *pipe_ctx,
2589 bool is_over_340mhz)
2590 {
2591 uint8_t slave_address = (0xF0 >> 1);
2592 uint8_t buffer[16];
2593 bool i2c_success = false;
2594 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
2595
2596 memset(&buffer, 0, sizeof(buffer));
2597
2598 // Program Slave Address for tuning single integrity
2599 buffer[3] = 0x4E;
2600 buffer[4] = 0x4E;
2601 buffer[5] = 0x4E;
2602 buffer[6] = is_over_340mhz ? 0x4E : 0x4A;
2603
2604 i2c_success = i2c_write(pipe_ctx, slave_address,
2605 buffer, sizeof(buffer));
2606 RETIMER_REDRIVER_INFO("redriver write 0 to all 16 reg offset expect following:\n\
2607 \t slave_addr = 0x%x, offset[3] = 0x%x, offset[4] = 0x%x,\
2608 offset[5] = 0x%x,offset[6] is_over_340mhz = 0x%x,\
2609 i2c_success = %d\n",
2610 slave_address, buffer[3], buffer[4], buffer[5], buffer[6], i2c_success?1:0);
2611
2612 if (!i2c_success)
2613 DC_LOG_DEBUG("Set redriver failed");
2614 }
2615
disable_link(struct dc_link * link,const struct link_resource * link_res,enum signal_type signal)2616 static void disable_link(struct dc_link *link, const struct link_resource *link_res,
2617 enum signal_type signal)
2618 {
2619 /*
2620 * TODO: implement call for dp_set_hw_test_pattern
2621 * it is needed for compliance testing
2622 */
2623
2624 /* Here we need to specify that encoder output settings
2625 * need to be calculated as for the set mode,
2626 * it will lead to querying dynamic link capabilities
2627 * which should be done before enable output
2628 */
2629
2630 if (dc_is_dp_signal(signal)) {
2631 /* SST DP, eDP */
2632 struct dc_link_settings link_settings = link->cur_link_settings;
2633 if (dc_is_dp_sst_signal(signal))
2634 dp_disable_link_phy(link, link_res, signal);
2635 else
2636 dp_disable_link_phy_mst(link, link_res, signal);
2637
2638 if (dc_is_dp_sst_signal(signal) ||
2639 link->mst_stream_alloc_table.stream_count == 0) {
2640 if (dp_get_link_encoding_format(&link_settings) == DP_8b_10b_ENCODING) {
2641 dp_set_fec_enable(link, false);
2642 dp_set_fec_ready(link, link_res, false);
2643 }
2644 }
2645 } else if (signal != SIGNAL_TYPE_VIRTUAL) {
2646 link->dc->hwss.disable_link_output(link, link_res, signal);
2647 }
2648
2649 if (signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
2650 /* MST disable link only when no stream use the link */
2651 if (link->mst_stream_alloc_table.stream_count <= 0)
2652 link->link_status.link_active = false;
2653 } else {
2654 link->link_status.link_active = false;
2655 }
2656 }
2657
enable_link_hdmi(struct pipe_ctx * pipe_ctx)2658 static void enable_link_hdmi(struct pipe_ctx *pipe_ctx)
2659 {
2660 struct dc_stream_state *stream = pipe_ctx->stream;
2661 struct dc_link *link = stream->link;
2662 enum dc_color_depth display_color_depth;
2663 enum engine_id eng_id;
2664 struct ext_hdmi_settings settings = {0};
2665 bool is_over_340mhz = false;
2666 bool is_vga_mode = (stream->timing.h_addressable == 640)
2667 && (stream->timing.v_addressable == 480);
2668 struct dc *dc = pipe_ctx->stream->ctx->dc;
2669
2670 if (stream->phy_pix_clk == 0)
2671 stream->phy_pix_clk = stream->timing.pix_clk_100hz / 10;
2672 if (stream->phy_pix_clk > 340000)
2673 is_over_340mhz = true;
2674
2675 if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) {
2676 unsigned short masked_chip_caps = pipe_ctx->stream->link->chip_caps &
2677 EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK;
2678 if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT) {
2679 /* DP159, Retimer settings */
2680 eng_id = pipe_ctx->stream_res.stream_enc->id;
2681
2682 if (get_ext_hdmi_settings(pipe_ctx, eng_id, &settings)) {
2683 write_i2c_retimer_setting(pipe_ctx,
2684 is_vga_mode, is_over_340mhz, &settings);
2685 } else {
2686 write_i2c_default_retimer_setting(pipe_ctx,
2687 is_vga_mode, is_over_340mhz);
2688 }
2689 } else if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204) {
2690 /* PI3EQX1204, Redriver settings */
2691 write_i2c_redriver_setting(pipe_ctx, is_over_340mhz);
2692 }
2693 }
2694
2695 if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
2696 dal_ddc_service_write_scdc_data(
2697 stream->link->ddc,
2698 stream->phy_pix_clk,
2699 stream->timing.flags.LTE_340MCSC_SCRAMBLE);
2700
2701 memset(&stream->link->cur_link_settings, 0,
2702 sizeof(struct dc_link_settings));
2703
2704 display_color_depth = stream->timing.display_color_depth;
2705 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
2706 display_color_depth = COLOR_DEPTH_888;
2707
2708 dc->hwss.enable_tmds_link_output(
2709 link,
2710 &pipe_ctx->link_res,
2711 pipe_ctx->stream->signal,
2712 pipe_ctx->clock_source->id,
2713 display_color_depth,
2714 stream->phy_pix_clk);
2715
2716 if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
2717 dal_ddc_service_read_scdc_data(link->ddc);
2718 }
2719
enable_link_lvds(struct pipe_ctx * pipe_ctx)2720 static void enable_link_lvds(struct pipe_ctx *pipe_ctx)
2721 {
2722 struct dc_stream_state *stream = pipe_ctx->stream;
2723 struct dc_link *link = stream->link;
2724 struct dc *dc = stream->ctx->dc;
2725
2726 if (stream->phy_pix_clk == 0)
2727 stream->phy_pix_clk = stream->timing.pix_clk_100hz / 10;
2728
2729 memset(&stream->link->cur_link_settings, 0,
2730 sizeof(struct dc_link_settings));
2731 dc->hwss.enable_lvds_link_output(
2732 link,
2733 &pipe_ctx->link_res,
2734 pipe_ctx->clock_source->id,
2735 stream->phy_pix_clk);
2736
2737 }
2738
dc_power_alpm_dpcd_enable(struct dc_link * link,bool enable)2739 bool dc_power_alpm_dpcd_enable(struct dc_link *link, bool enable)
2740 {
2741 bool ret = false;
2742 union dpcd_alpm_configuration alpm_config;
2743
2744 if (link->psr_settings.psr_version == DC_PSR_VERSION_SU_1) {
2745 memset(&alpm_config, 0, sizeof(alpm_config));
2746
2747 alpm_config.bits.ENABLE = (enable ? true : false);
2748 ret = dm_helpers_dp_write_dpcd(link->ctx, link,
2749 DP_RECEIVER_ALPM_CONFIG, &alpm_config.raw,
2750 sizeof(alpm_config.raw));
2751 }
2752 return ret;
2753 }
2754
2755 /****************************enable_link***********************************/
enable_link(struct dc_state * state,struct pipe_ctx * pipe_ctx)2756 static enum dc_status enable_link(
2757 struct dc_state *state,
2758 struct pipe_ctx *pipe_ctx)
2759 {
2760 enum dc_status status = DC_ERROR_UNEXPECTED;
2761 struct dc_stream_state *stream = pipe_ctx->stream;
2762 struct dc_link *link = stream->link;
2763
2764 /* There's some scenarios where driver is unloaded with display
2765 * still enabled. When driver is reloaded, it may cause a display
2766 * to not light up if there is a mismatch between old and new
2767 * link settings. Need to call disable first before enabling at
2768 * new link settings.
2769 */
2770 if (link->link_status.link_active) {
2771 disable_link(link, &pipe_ctx->link_res, pipe_ctx->stream->signal);
2772 }
2773
2774 switch (pipe_ctx->stream->signal) {
2775 case SIGNAL_TYPE_DISPLAY_PORT:
2776 status = enable_link_dp(state, pipe_ctx);
2777 break;
2778 case SIGNAL_TYPE_EDP:
2779 status = enable_link_edp(state, pipe_ctx);
2780 break;
2781 case SIGNAL_TYPE_DISPLAY_PORT_MST:
2782 status = enable_link_dp_mst(state, pipe_ctx);
2783 msleep(200);
2784 break;
2785 case SIGNAL_TYPE_DVI_SINGLE_LINK:
2786 case SIGNAL_TYPE_DVI_DUAL_LINK:
2787 case SIGNAL_TYPE_HDMI_TYPE_A:
2788 enable_link_hdmi(pipe_ctx);
2789 status = DC_OK;
2790 break;
2791 case SIGNAL_TYPE_LVDS:
2792 enable_link_lvds(pipe_ctx);
2793 status = DC_OK;
2794 break;
2795 case SIGNAL_TYPE_VIRTUAL:
2796 status = DC_OK;
2797 break;
2798 default:
2799 break;
2800 }
2801
2802 if (status == DC_OK)
2803 pipe_ctx->stream->link->link_status.link_active = true;
2804
2805 return status;
2806 }
2807
get_timing_pixel_clock_100hz(const struct dc_crtc_timing * timing)2808 static uint32_t get_timing_pixel_clock_100hz(const struct dc_crtc_timing *timing)
2809 {
2810
2811 uint32_t pxl_clk = timing->pix_clk_100hz;
2812
2813 if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
2814 pxl_clk /= 2;
2815 else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422)
2816 pxl_clk = pxl_clk * 2 / 3;
2817
2818 if (timing->display_color_depth == COLOR_DEPTH_101010)
2819 pxl_clk = pxl_clk * 10 / 8;
2820 else if (timing->display_color_depth == COLOR_DEPTH_121212)
2821 pxl_clk = pxl_clk * 12 / 8;
2822
2823 return pxl_clk;
2824 }
2825
dp_active_dongle_validate_timing(const struct dc_crtc_timing * timing,const struct dpcd_caps * dpcd_caps)2826 static bool dp_active_dongle_validate_timing(
2827 const struct dc_crtc_timing *timing,
2828 const struct dpcd_caps *dpcd_caps)
2829 {
2830 const struct dc_dongle_caps *dongle_caps = &dpcd_caps->dongle_caps;
2831
2832 switch (dpcd_caps->dongle_type) {
2833 case DISPLAY_DONGLE_DP_VGA_CONVERTER:
2834 case DISPLAY_DONGLE_DP_DVI_CONVERTER:
2835 case DISPLAY_DONGLE_DP_DVI_DONGLE:
2836 if (timing->pixel_encoding == PIXEL_ENCODING_RGB)
2837 return true;
2838 else
2839 return false;
2840 default:
2841 break;
2842 }
2843
2844 if (dpcd_caps->dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER &&
2845 dongle_caps->extendedCapValid == true) {
2846 /* Check Pixel Encoding */
2847 switch (timing->pixel_encoding) {
2848 case PIXEL_ENCODING_RGB:
2849 case PIXEL_ENCODING_YCBCR444:
2850 break;
2851 case PIXEL_ENCODING_YCBCR422:
2852 if (!dongle_caps->is_dp_hdmi_ycbcr422_pass_through)
2853 return false;
2854 break;
2855 case PIXEL_ENCODING_YCBCR420:
2856 if (!dongle_caps->is_dp_hdmi_ycbcr420_pass_through)
2857 return false;
2858 break;
2859 default:
2860 /* Invalid Pixel Encoding*/
2861 return false;
2862 }
2863
2864 switch (timing->display_color_depth) {
2865 case COLOR_DEPTH_666:
2866 case COLOR_DEPTH_888:
2867 /*888 and 666 should always be supported*/
2868 break;
2869 case COLOR_DEPTH_101010:
2870 if (dongle_caps->dp_hdmi_max_bpc < 10)
2871 return false;
2872 break;
2873 case COLOR_DEPTH_121212:
2874 if (dongle_caps->dp_hdmi_max_bpc < 12)
2875 return false;
2876 break;
2877 case COLOR_DEPTH_141414:
2878 case COLOR_DEPTH_161616:
2879 default:
2880 /* These color depths are currently not supported */
2881 return false;
2882 }
2883
2884 /* Check 3D format */
2885 switch (timing->timing_3d_format) {
2886 case TIMING_3D_FORMAT_NONE:
2887 case TIMING_3D_FORMAT_FRAME_ALTERNATE:
2888 /*Only frame alternate 3D is supported on active dongle*/
2889 break;
2890 default:
2891 /*other 3D formats are not supported due to bad infoframe translation */
2892 return false;
2893 }
2894
2895 #if defined(CONFIG_DRM_AMD_DC_DCN)
2896 if (dongle_caps->dp_hdmi_frl_max_link_bw_in_kbps > 0) { // DP to HDMI FRL converter
2897 struct dc_crtc_timing outputTiming = *timing;
2898
2899 if (timing->flags.DSC && !timing->dsc_cfg.is_frl)
2900 /* DP input has DSC, HDMI FRL output doesn't have DSC, remove DSC from output timing */
2901 outputTiming.flags.DSC = 0;
2902 if (dc_bandwidth_in_kbps_from_timing(&outputTiming) > dongle_caps->dp_hdmi_frl_max_link_bw_in_kbps)
2903 return false;
2904 } else { // DP to HDMI TMDS converter
2905 if (get_timing_pixel_clock_100hz(timing) > (dongle_caps->dp_hdmi_max_pixel_clk_in_khz * 10))
2906 return false;
2907 }
2908 #else
2909 if (get_timing_pixel_clock_100hz(timing) > (dongle_caps->dp_hdmi_max_pixel_clk_in_khz * 10))
2910 return false;
2911 #endif
2912 }
2913
2914 if (dpcd_caps->channel_coding_cap.bits.DP_128b_132b_SUPPORTED == 0 &&
2915 dpcd_caps->dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_PASSTHROUGH_SUPPORT == 0 &&
2916 dongle_caps->dfp_cap_ext.supported) {
2917
2918 if (dongle_caps->dfp_cap_ext.max_pixel_rate_in_mps < (timing->pix_clk_100hz / 10000))
2919 return false;
2920
2921 if (dongle_caps->dfp_cap_ext.max_video_h_active_width < timing->h_addressable)
2922 return false;
2923
2924 if (dongle_caps->dfp_cap_ext.max_video_v_active_height < timing->v_addressable)
2925 return false;
2926
2927 if (timing->pixel_encoding == PIXEL_ENCODING_RGB) {
2928 if (!dongle_caps->dfp_cap_ext.encoding_format_caps.support_rgb)
2929 return false;
2930 if (timing->display_color_depth == COLOR_DEPTH_666 &&
2931 !dongle_caps->dfp_cap_ext.rgb_color_depth_caps.support_6bpc)
2932 return false;
2933 else if (timing->display_color_depth == COLOR_DEPTH_888 &&
2934 !dongle_caps->dfp_cap_ext.rgb_color_depth_caps.support_8bpc)
2935 return false;
2936 else if (timing->display_color_depth == COLOR_DEPTH_101010 &&
2937 !dongle_caps->dfp_cap_ext.rgb_color_depth_caps.support_10bpc)
2938 return false;
2939 else if (timing->display_color_depth == COLOR_DEPTH_121212 &&
2940 !dongle_caps->dfp_cap_ext.rgb_color_depth_caps.support_12bpc)
2941 return false;
2942 else if (timing->display_color_depth == COLOR_DEPTH_161616 &&
2943 !dongle_caps->dfp_cap_ext.rgb_color_depth_caps.support_16bpc)
2944 return false;
2945 } else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR444) {
2946 if (!dongle_caps->dfp_cap_ext.encoding_format_caps.support_rgb)
2947 return false;
2948 if (timing->display_color_depth == COLOR_DEPTH_888 &&
2949 !dongle_caps->dfp_cap_ext.ycbcr444_color_depth_caps.support_8bpc)
2950 return false;
2951 else if (timing->display_color_depth == COLOR_DEPTH_101010 &&
2952 !dongle_caps->dfp_cap_ext.ycbcr444_color_depth_caps.support_10bpc)
2953 return false;
2954 else if (timing->display_color_depth == COLOR_DEPTH_121212 &&
2955 !dongle_caps->dfp_cap_ext.ycbcr444_color_depth_caps.support_12bpc)
2956 return false;
2957 else if (timing->display_color_depth == COLOR_DEPTH_161616 &&
2958 !dongle_caps->dfp_cap_ext.ycbcr444_color_depth_caps.support_16bpc)
2959 return false;
2960 } else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) {
2961 if (!dongle_caps->dfp_cap_ext.encoding_format_caps.support_rgb)
2962 return false;
2963 if (timing->display_color_depth == COLOR_DEPTH_888 &&
2964 !dongle_caps->dfp_cap_ext.ycbcr422_color_depth_caps.support_8bpc)
2965 return false;
2966 else if (timing->display_color_depth == COLOR_DEPTH_101010 &&
2967 !dongle_caps->dfp_cap_ext.ycbcr422_color_depth_caps.support_10bpc)
2968 return false;
2969 else if (timing->display_color_depth == COLOR_DEPTH_121212 &&
2970 !dongle_caps->dfp_cap_ext.ycbcr422_color_depth_caps.support_12bpc)
2971 return false;
2972 else if (timing->display_color_depth == COLOR_DEPTH_161616 &&
2973 !dongle_caps->dfp_cap_ext.ycbcr422_color_depth_caps.support_16bpc)
2974 return false;
2975 } else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420) {
2976 if (!dongle_caps->dfp_cap_ext.encoding_format_caps.support_rgb)
2977 return false;
2978 if (timing->display_color_depth == COLOR_DEPTH_888 &&
2979 !dongle_caps->dfp_cap_ext.ycbcr420_color_depth_caps.support_8bpc)
2980 return false;
2981 else if (timing->display_color_depth == COLOR_DEPTH_101010 &&
2982 !dongle_caps->dfp_cap_ext.ycbcr420_color_depth_caps.support_10bpc)
2983 return false;
2984 else if (timing->display_color_depth == COLOR_DEPTH_121212 &&
2985 !dongle_caps->dfp_cap_ext.ycbcr420_color_depth_caps.support_12bpc)
2986 return false;
2987 else if (timing->display_color_depth == COLOR_DEPTH_161616 &&
2988 !dongle_caps->dfp_cap_ext.ycbcr420_color_depth_caps.support_16bpc)
2989 return false;
2990 }
2991 }
2992
2993 return true;
2994 }
2995
dc_link_validate_mode_timing(const struct dc_stream_state * stream,struct dc_link * link,const struct dc_crtc_timing * timing)2996 enum dc_status dc_link_validate_mode_timing(
2997 const struct dc_stream_state *stream,
2998 struct dc_link *link,
2999 const struct dc_crtc_timing *timing)
3000 {
3001 uint32_t max_pix_clk = stream->link->dongle_max_pix_clk * 10;
3002 struct dpcd_caps *dpcd_caps = &link->dpcd_caps;
3003
3004 /* A hack to avoid failing any modes for EDID override feature on
3005 * topology change such as lower quality cable for DP or different dongle
3006 */
3007 if (link->remote_sinks[0] && link->remote_sinks[0]->sink_signal == SIGNAL_TYPE_VIRTUAL)
3008 return DC_OK;
3009
3010 /* Passive Dongle */
3011 if (max_pix_clk != 0 && get_timing_pixel_clock_100hz(timing) > max_pix_clk)
3012 return DC_EXCEED_DONGLE_CAP;
3013
3014 /* Active Dongle*/
3015 if (!dp_active_dongle_validate_timing(timing, dpcd_caps))
3016 return DC_EXCEED_DONGLE_CAP;
3017
3018 switch (stream->signal) {
3019 case SIGNAL_TYPE_EDP:
3020 case SIGNAL_TYPE_DISPLAY_PORT:
3021 if (!dp_validate_mode_timing(
3022 link,
3023 timing))
3024 return DC_NO_DP_LINK_BANDWIDTH;
3025 break;
3026
3027 default:
3028 break;
3029 }
3030
3031 return DC_OK;
3032 }
3033
get_abm_from_stream_res(const struct dc_link * link)3034 static struct abm *get_abm_from_stream_res(const struct dc_link *link)
3035 {
3036 int i;
3037 struct dc *dc = NULL;
3038 struct abm *abm = NULL;
3039
3040 if (!link || !link->ctx)
3041 return NULL;
3042
3043 dc = link->ctx->dc;
3044
3045 for (i = 0; i < MAX_PIPES; i++) {
3046 struct pipe_ctx pipe_ctx = dc->current_state->res_ctx.pipe_ctx[i];
3047 struct dc_stream_state *stream = pipe_ctx.stream;
3048
3049 if (stream && stream->link == link) {
3050 abm = pipe_ctx.stream_res.abm;
3051 break;
3052 }
3053 }
3054 return abm;
3055 }
3056
dc_link_get_backlight_level(const struct dc_link * link)3057 int dc_link_get_backlight_level(const struct dc_link *link)
3058 {
3059 struct abm *abm = get_abm_from_stream_res(link);
3060 struct panel_cntl *panel_cntl = link->panel_cntl;
3061 struct dc *dc = link->ctx->dc;
3062 struct dmcu *dmcu = dc->res_pool->dmcu;
3063 bool fw_set_brightness = true;
3064
3065 if (dmcu)
3066 fw_set_brightness = dmcu->funcs->is_dmcu_initialized(dmcu);
3067
3068 if (!fw_set_brightness && panel_cntl->funcs->get_current_backlight)
3069 return panel_cntl->funcs->get_current_backlight(panel_cntl);
3070 else if (abm != NULL && abm->funcs->get_current_backlight != NULL)
3071 return (int) abm->funcs->get_current_backlight(abm);
3072 else
3073 return DC_ERROR_UNEXPECTED;
3074 }
3075
dc_link_get_target_backlight_pwm(const struct dc_link * link)3076 int dc_link_get_target_backlight_pwm(const struct dc_link *link)
3077 {
3078 struct abm *abm = get_abm_from_stream_res(link);
3079
3080 if (abm == NULL || abm->funcs->get_target_backlight == NULL)
3081 return DC_ERROR_UNEXPECTED;
3082
3083 return (int) abm->funcs->get_target_backlight(abm);
3084 }
3085
get_pipe_from_link(const struct dc_link * link)3086 static struct pipe_ctx *get_pipe_from_link(const struct dc_link *link)
3087 {
3088 int i;
3089 struct dc *dc = link->ctx->dc;
3090 struct pipe_ctx *pipe_ctx = NULL;
3091
3092 for (i = 0; i < MAX_PIPES; i++) {
3093 if (dc->current_state->res_ctx.pipe_ctx[i].stream) {
3094 if (dc->current_state->res_ctx.pipe_ctx[i].stream->link == link) {
3095 pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
3096 break;
3097 }
3098 }
3099 }
3100
3101 return pipe_ctx;
3102 }
3103
dc_link_set_backlight_level(const struct dc_link * link,uint32_t backlight_pwm_u16_16,uint32_t frame_ramp)3104 bool dc_link_set_backlight_level(const struct dc_link *link,
3105 uint32_t backlight_pwm_u16_16,
3106 uint32_t frame_ramp)
3107 {
3108 struct dc *dc = link->ctx->dc;
3109
3110 DC_LOGGER_INIT(link->ctx->logger);
3111 DC_LOG_BACKLIGHT("New Backlight level: %d (0x%X)\n",
3112 backlight_pwm_u16_16, backlight_pwm_u16_16);
3113
3114 if (dc_is_embedded_signal(link->connector_signal)) {
3115 struct pipe_ctx *pipe_ctx = get_pipe_from_link(link);
3116
3117 if (pipe_ctx) {
3118 /* Disable brightness ramping when the display is blanked
3119 * as it can hang the DMCU
3120 */
3121 if (pipe_ctx->plane_state == NULL)
3122 frame_ramp = 0;
3123 } else {
3124 return false;
3125 }
3126
3127 dc->hwss.set_backlight_level(
3128 pipe_ctx,
3129 backlight_pwm_u16_16,
3130 frame_ramp);
3131 }
3132 return true;
3133 }
3134
dc_link_set_psr_allow_active(struct dc_link * link,const bool * allow_active,bool wait,bool force_static,const unsigned int * power_opts)3135 bool dc_link_set_psr_allow_active(struct dc_link *link, const bool *allow_active,
3136 bool wait, bool force_static, const unsigned int *power_opts)
3137 {
3138 struct dc *dc = link->ctx->dc;
3139 struct dmcu *dmcu = dc->res_pool->dmcu;
3140 struct dmub_psr *psr = dc->res_pool->psr;
3141 unsigned int panel_inst;
3142
3143 if (psr == NULL && force_static)
3144 return false;
3145
3146 if (!dc_get_edp_link_panel_inst(dc, link, &panel_inst))
3147 return false;
3148
3149 if ((allow_active != NULL) && (*allow_active == true) && (link->type == dc_connection_none)) {
3150 // Don't enter PSR if panel is not connected
3151 return false;
3152 }
3153
3154 /* Set power optimization flag */
3155 if (power_opts && link->psr_settings.psr_power_opt != *power_opts) {
3156 link->psr_settings.psr_power_opt = *power_opts;
3157
3158 if (psr != NULL && link->psr_settings.psr_feature_enabled && psr->funcs->psr_set_power_opt)
3159 psr->funcs->psr_set_power_opt(psr, link->psr_settings.psr_power_opt, panel_inst);
3160 }
3161
3162 if (psr != NULL && link->psr_settings.psr_feature_enabled &&
3163 force_static && psr->funcs->psr_force_static)
3164 psr->funcs->psr_force_static(psr, panel_inst);
3165
3166 /* Enable or Disable PSR */
3167 if (allow_active && link->psr_settings.psr_allow_active != *allow_active) {
3168 link->psr_settings.psr_allow_active = *allow_active;
3169
3170 if (!link->psr_settings.psr_allow_active)
3171 dc_z10_restore(dc);
3172
3173 if (psr != NULL && link->psr_settings.psr_feature_enabled) {
3174 psr->funcs->psr_enable(psr, link->psr_settings.psr_allow_active, wait, panel_inst);
3175 } else if ((dmcu != NULL && dmcu->funcs->is_dmcu_initialized(dmcu)) &&
3176 link->psr_settings.psr_feature_enabled)
3177 dmcu->funcs->set_psr_enable(dmcu, link->psr_settings.psr_allow_active, wait);
3178 else
3179 return false;
3180 }
3181
3182 return true;
3183 }
3184
dc_link_get_psr_state(const struct dc_link * link,enum dc_psr_state * state)3185 bool dc_link_get_psr_state(const struct dc_link *link, enum dc_psr_state *state)
3186 {
3187 struct dc *dc = link->ctx->dc;
3188 struct dmcu *dmcu = dc->res_pool->dmcu;
3189 struct dmub_psr *psr = dc->res_pool->psr;
3190 unsigned int panel_inst;
3191
3192 if (!dc_get_edp_link_panel_inst(dc, link, &panel_inst))
3193 return false;
3194
3195 if (psr != NULL && link->psr_settings.psr_feature_enabled)
3196 psr->funcs->psr_get_state(psr, state, panel_inst);
3197 else if (dmcu != NULL && link->psr_settings.psr_feature_enabled)
3198 dmcu->funcs->get_psr_state(dmcu, state);
3199
3200 return true;
3201 }
3202
3203 static inline enum physical_phy_id
transmitter_to_phy_id(enum transmitter transmitter_value)3204 transmitter_to_phy_id(enum transmitter transmitter_value)
3205 {
3206 switch (transmitter_value) {
3207 case TRANSMITTER_UNIPHY_A:
3208 return PHYLD_0;
3209 case TRANSMITTER_UNIPHY_B:
3210 return PHYLD_1;
3211 case TRANSMITTER_UNIPHY_C:
3212 return PHYLD_2;
3213 case TRANSMITTER_UNIPHY_D:
3214 return PHYLD_3;
3215 case TRANSMITTER_UNIPHY_E:
3216 return PHYLD_4;
3217 case TRANSMITTER_UNIPHY_F:
3218 return PHYLD_5;
3219 case TRANSMITTER_NUTMEG_CRT:
3220 return PHYLD_6;
3221 case TRANSMITTER_TRAVIS_CRT:
3222 return PHYLD_7;
3223 case TRANSMITTER_TRAVIS_LCD:
3224 return PHYLD_8;
3225 case TRANSMITTER_UNIPHY_G:
3226 return PHYLD_9;
3227 case TRANSMITTER_COUNT:
3228 return PHYLD_COUNT;
3229 case TRANSMITTER_UNKNOWN:
3230 return PHYLD_UNKNOWN;
3231 default:
3232 WARN_ONCE(1, "Unknown transmitter value %d\n",
3233 transmitter_value);
3234 return PHYLD_UNKNOWN;
3235 }
3236 }
3237
dc_link_setup_psr(struct dc_link * link,const struct dc_stream_state * stream,struct psr_config * psr_config,struct psr_context * psr_context)3238 bool dc_link_setup_psr(struct dc_link *link,
3239 const struct dc_stream_state *stream, struct psr_config *psr_config,
3240 struct psr_context *psr_context)
3241 {
3242 struct dc *dc;
3243 struct dmcu *dmcu;
3244 struct dmub_psr *psr;
3245 int i;
3246 unsigned int panel_inst;
3247 /* updateSinkPsrDpcdConfig*/
3248 union dpcd_psr_configuration psr_configuration;
3249 union dpcd_sink_active_vtotal_control_mode vtotal_control = {0};
3250
3251 psr_context->controllerId = CONTROLLER_ID_UNDEFINED;
3252
3253 if (!link)
3254 return false;
3255
3256 dc = link->ctx->dc;
3257 dmcu = dc->res_pool->dmcu;
3258 psr = dc->res_pool->psr;
3259
3260 if (!dmcu && !psr)
3261 return false;
3262
3263 if (!dc_get_edp_link_panel_inst(dc, link, &panel_inst))
3264 return false;
3265
3266
3267 memset(&psr_configuration, 0, sizeof(psr_configuration));
3268
3269 psr_configuration.bits.ENABLE = 1;
3270 psr_configuration.bits.CRC_VERIFICATION = 1;
3271 psr_configuration.bits.FRAME_CAPTURE_INDICATION =
3272 psr_config->psr_frame_capture_indication_req;
3273
3274 /* Check for PSR v2*/
3275 if (link->psr_settings.psr_version == DC_PSR_VERSION_SU_1) {
3276 /* For PSR v2 selective update.
3277 * Indicates whether sink should start capturing
3278 * immediately following active scan line,
3279 * or starting with the 2nd active scan line.
3280 */
3281 psr_configuration.bits.LINE_CAPTURE_INDICATION = 0;
3282 /*For PSR v2, determines whether Sink should generate
3283 * IRQ_HPD when CRC mismatch is detected.
3284 */
3285 psr_configuration.bits.IRQ_HPD_WITH_CRC_ERROR = 1;
3286 /* For PSR v2, set the bit when the Source device will
3287 * be enabling PSR2 operation.
3288 */
3289 psr_configuration.bits.ENABLE_PSR2 = 1;
3290 /* For PSR v2, the Sink device must be able to receive
3291 * SU region updates early in the frame time.
3292 */
3293 psr_configuration.bits.EARLY_TRANSPORT_ENABLE = 1;
3294 }
3295
3296 dm_helpers_dp_write_dpcd(
3297 link->ctx,
3298 link,
3299 368,
3300 &psr_configuration.raw,
3301 sizeof(psr_configuration.raw));
3302
3303 if (link->psr_settings.psr_version == DC_PSR_VERSION_SU_1) {
3304 dc_power_alpm_dpcd_enable(link, true);
3305 psr_context->su_granularity_required =
3306 psr_config->su_granularity_required;
3307 psr_context->su_y_granularity =
3308 psr_config->su_y_granularity;
3309 psr_context->line_time_in_us =
3310 psr_config->line_time_in_us;
3311
3312 if (link->psr_settings.psr_vtotal_control_support) {
3313 psr_context->rate_control_caps = psr_config->rate_control_caps;
3314 vtotal_control.bits.ENABLE = true;
3315 core_link_write_dpcd(link, DP_SINK_PSR_ACTIVE_VTOTAL_CONTROL_MODE,
3316 &vtotal_control.raw, sizeof(vtotal_control.raw));
3317 }
3318 }
3319
3320 psr_context->channel = link->ddc->ddc_pin->hw_info.ddc_channel;
3321 psr_context->transmitterId = link->link_enc->transmitter;
3322 psr_context->engineId = link->link_enc->preferred_engine;
3323
3324 for (i = 0; i < MAX_PIPES; i++) {
3325 if (dc->current_state->res_ctx.pipe_ctx[i].stream
3326 == stream) {
3327 /* dmcu -1 for all controller id values,
3328 * therefore +1 here
3329 */
3330 psr_context->controllerId =
3331 dc->current_state->res_ctx.
3332 pipe_ctx[i].stream_res.tg->inst + 1;
3333 break;
3334 }
3335 }
3336
3337 /* Hardcoded for now. Can be Pcie or Uniphy (or Unknown)*/
3338 psr_context->phyType = PHY_TYPE_UNIPHY;
3339 /*PhyId is associated with the transmitter id*/
3340 psr_context->smuPhyId =
3341 transmitter_to_phy_id(link->link_enc->transmitter);
3342
3343 psr_context->crtcTimingVerticalTotal = stream->timing.v_total;
3344 psr_context->vsync_rate_hz = div64_u64(div64_u64((stream->
3345 timing.pix_clk_100hz * 100),
3346 stream->timing.v_total),
3347 stream->timing.h_total);
3348
3349 psr_context->psrSupportedDisplayConfig = true;
3350 psr_context->psrExitLinkTrainingRequired =
3351 psr_config->psr_exit_link_training_required;
3352 psr_context->sdpTransmitLineNumDeadline =
3353 psr_config->psr_sdp_transmit_line_num_deadline;
3354 psr_context->psrFrameCaptureIndicationReq =
3355 psr_config->psr_frame_capture_indication_req;
3356
3357 psr_context->skipPsrWaitForPllLock = 0; /* only = 1 in KV */
3358
3359 psr_context->numberOfControllers =
3360 link->dc->res_pool->timing_generator_count;
3361
3362 psr_context->rfb_update_auto_en = true;
3363
3364 /* 2 frames before enter PSR. */
3365 psr_context->timehyst_frames = 2;
3366 /* half a frame
3367 * (units in 100 lines, i.e. a value of 1 represents 100 lines)
3368 */
3369 psr_context->hyst_lines = stream->timing.v_total / 2 / 100;
3370 psr_context->aux_repeats = 10;
3371
3372 psr_context->psr_level.u32all = 0;
3373
3374 /*skip power down the single pipe since it blocks the cstate*/
3375 #if defined(CONFIG_DRM_AMD_DC_DCN)
3376 if (link->ctx->asic_id.chip_family >= FAMILY_RV) {
3377 switch(link->ctx->asic_id.chip_family) {
3378 case FAMILY_YELLOW_CARP:
3379 case AMDGPU_FAMILY_GC_10_3_6:
3380 case AMDGPU_FAMILY_GC_11_0_1:
3381 if (dc->debug.disable_z10)
3382 psr_context->psr_level.bits.SKIP_CRTC_DISABLE = true;
3383 break;
3384 default:
3385 psr_context->psr_level.bits.SKIP_CRTC_DISABLE = true;
3386 break;
3387 }
3388 }
3389 #else
3390 if (link->ctx->asic_id.chip_family >= FAMILY_RV)
3391 psr_context->psr_level.bits.SKIP_CRTC_DISABLE = true;
3392 #endif
3393
3394 /* SMU will perform additional powerdown sequence.
3395 * For unsupported ASICs, set psr_level flag to skip PSR
3396 * static screen notification to SMU.
3397 * (Always set for DAL2, did not check ASIC)
3398 */
3399 psr_context->allow_smu_optimizations = psr_config->allow_smu_optimizations;
3400 psr_context->allow_multi_disp_optimizations = psr_config->allow_multi_disp_optimizations;
3401
3402 /* Complete PSR entry before aborting to prevent intermittent
3403 * freezes on certain eDPs
3404 */
3405 psr_context->psr_level.bits.DISABLE_PSR_ENTRY_ABORT = 1;
3406
3407 /* enable ALPM */
3408 psr_context->psr_level.bits.DISABLE_ALPM = 0;
3409 psr_context->psr_level.bits.ALPM_DEFAULT_PD_MODE = 1;
3410
3411 /* Controls additional delay after remote frame capture before
3412 * continuing power down, default = 0
3413 */
3414 psr_context->frame_delay = 0;
3415
3416 if (psr) {
3417 link->psr_settings.psr_feature_enabled = psr->funcs->psr_copy_settings(psr,
3418 link, psr_context, panel_inst);
3419 link->psr_settings.psr_power_opt = 0;
3420 link->psr_settings.psr_allow_active = 0;
3421 }
3422 else
3423 link->psr_settings.psr_feature_enabled = dmcu->funcs->setup_psr(dmcu, link, psr_context);
3424
3425 /* psr_enabled == 0 indicates setup_psr did not succeed, but this
3426 * should not happen since firmware should be running at this point
3427 */
3428 if (link->psr_settings.psr_feature_enabled == 0)
3429 ASSERT(0);
3430
3431 return true;
3432
3433 }
3434
dc_link_get_psr_residency(const struct dc_link * link,uint32_t * residency)3435 void dc_link_get_psr_residency(const struct dc_link *link, uint32_t *residency)
3436 {
3437 struct dc *dc = link->ctx->dc;
3438 struct dmub_psr *psr = dc->res_pool->psr;
3439 unsigned int panel_inst;
3440
3441 if (!dc_get_edp_link_panel_inst(dc, link, &panel_inst))
3442 return;
3443
3444 /* PSR residency measurements only supported on DMCUB */
3445 if (psr != NULL && link->psr_settings.psr_feature_enabled)
3446 psr->funcs->psr_get_residency(psr, residency, panel_inst);
3447 else
3448 *residency = 0;
3449 }
3450
dc_link_set_sink_vtotal_in_psr_active(const struct dc_link * link,uint16_t psr_vtotal_idle,uint16_t psr_vtotal_su)3451 bool dc_link_set_sink_vtotal_in_psr_active(const struct dc_link *link, uint16_t psr_vtotal_idle, uint16_t psr_vtotal_su)
3452 {
3453 struct dc *dc = link->ctx->dc;
3454 struct dmub_psr *psr = dc->res_pool->psr;
3455
3456 if (psr == NULL || !link->psr_settings.psr_feature_enabled || !link->psr_settings.psr_vtotal_control_support)
3457 return false;
3458
3459 psr->funcs->psr_set_sink_vtotal_in_psr_active(psr, psr_vtotal_idle, psr_vtotal_su);
3460
3461 return true;
3462 }
3463
dc_link_get_status(const struct dc_link * link)3464 const struct dc_link_status *dc_link_get_status(const struct dc_link *link)
3465 {
3466 return &link->link_status;
3467 }
3468
core_link_resume(struct dc_link * link)3469 void core_link_resume(struct dc_link *link)
3470 {
3471 if (link->connector_signal != SIGNAL_TYPE_VIRTUAL)
3472 program_hpd_filter(link);
3473 }
3474
get_pbn_per_slot(struct dc_stream_state * stream)3475 static struct fixed31_32 get_pbn_per_slot(struct dc_stream_state *stream)
3476 {
3477 struct fixed31_32 mbytes_per_sec;
3478 uint32_t link_rate_in_mbytes_per_sec = dc_link_bandwidth_kbps(stream->link,
3479 &stream->link->cur_link_settings);
3480 link_rate_in_mbytes_per_sec /= 8000; /* Kbits to MBytes */
3481
3482 mbytes_per_sec = dc_fixpt_from_int(link_rate_in_mbytes_per_sec);
3483
3484 return dc_fixpt_div_int(mbytes_per_sec, 54);
3485 }
3486
get_pbn_from_bw_in_kbps(uint64_t kbps)3487 static struct fixed31_32 get_pbn_from_bw_in_kbps(uint64_t kbps)
3488 {
3489 struct fixed31_32 peak_kbps;
3490 uint32_t numerator = 0;
3491 uint32_t denominator = 1;
3492
3493 /*
3494 * margin 5300ppm + 300ppm ~ 0.6% as per spec, factor is 1.006
3495 * The unit of 54/64Mbytes/sec is an arbitrary unit chosen based on
3496 * common multiplier to render an integer PBN for all link rate/lane
3497 * counts combinations
3498 * calculate
3499 * peak_kbps *= (1006/1000)
3500 * peak_kbps *= (64/54)
3501 * peak_kbps *= 8 convert to bytes
3502 */
3503
3504 numerator = 64 * PEAK_FACTOR_X1000;
3505 denominator = 54 * 8 * 1000 * 1000;
3506 kbps *= numerator;
3507 peak_kbps = dc_fixpt_from_fraction(kbps, denominator);
3508
3509 return peak_kbps;
3510 }
3511
get_pbn_from_timing(struct pipe_ctx * pipe_ctx)3512 static struct fixed31_32 get_pbn_from_timing(struct pipe_ctx *pipe_ctx)
3513 {
3514 uint64_t kbps;
3515
3516 kbps = dc_bandwidth_in_kbps_from_timing(&pipe_ctx->stream->timing);
3517 return get_pbn_from_bw_in_kbps(kbps);
3518 }
3519
update_mst_stream_alloc_table(struct dc_link * link,struct stream_encoder * stream_enc,struct hpo_dp_stream_encoder * hpo_dp_stream_enc,const struct dc_dp_mst_stream_allocation_table * proposed_table)3520 static void update_mst_stream_alloc_table(
3521 struct dc_link *link,
3522 struct stream_encoder *stream_enc,
3523 struct hpo_dp_stream_encoder *hpo_dp_stream_enc, // TODO: Rename stream_enc to dio_stream_enc?
3524 const struct dc_dp_mst_stream_allocation_table *proposed_table)
3525 {
3526 struct link_mst_stream_allocation work_table[MAX_CONTROLLER_NUM] = { 0 };
3527 struct link_mst_stream_allocation *dc_alloc;
3528
3529 int i;
3530 int j;
3531
3532 /* if DRM proposed_table has more than one new payload */
3533 ASSERT(proposed_table->stream_count -
3534 link->mst_stream_alloc_table.stream_count < 2);
3535
3536 /* copy proposed_table to link, add stream encoder */
3537 for (i = 0; i < proposed_table->stream_count; i++) {
3538
3539 for (j = 0; j < link->mst_stream_alloc_table.stream_count; j++) {
3540 dc_alloc =
3541 &link->mst_stream_alloc_table.stream_allocations[j];
3542
3543 if (dc_alloc->vcp_id ==
3544 proposed_table->stream_allocations[i].vcp_id) {
3545
3546 work_table[i] = *dc_alloc;
3547 work_table[i].slot_count = proposed_table->stream_allocations[i].slot_count;
3548 break; /* exit j loop */
3549 }
3550 }
3551
3552 /* new vcp_id */
3553 if (j == link->mst_stream_alloc_table.stream_count) {
3554 work_table[i].vcp_id =
3555 proposed_table->stream_allocations[i].vcp_id;
3556 work_table[i].slot_count =
3557 proposed_table->stream_allocations[i].slot_count;
3558 work_table[i].stream_enc = stream_enc;
3559 work_table[i].hpo_dp_stream_enc = hpo_dp_stream_enc;
3560 }
3561 }
3562
3563 /* update link->mst_stream_alloc_table with work_table */
3564 link->mst_stream_alloc_table.stream_count =
3565 proposed_table->stream_count;
3566 for (i = 0; i < MAX_CONTROLLER_NUM; i++)
3567 link->mst_stream_alloc_table.stream_allocations[i] =
3568 work_table[i];
3569 }
3570
remove_stream_from_alloc_table(struct dc_link * link,struct stream_encoder * dio_stream_enc,struct hpo_dp_stream_encoder * hpo_dp_stream_enc)3571 static void remove_stream_from_alloc_table(
3572 struct dc_link *link,
3573 struct stream_encoder *dio_stream_enc,
3574 struct hpo_dp_stream_encoder *hpo_dp_stream_enc)
3575 {
3576 int i = 0;
3577 struct link_mst_stream_allocation_table *table =
3578 &link->mst_stream_alloc_table;
3579
3580 if (hpo_dp_stream_enc) {
3581 for (; i < table->stream_count; i++)
3582 if (hpo_dp_stream_enc == table->stream_allocations[i].hpo_dp_stream_enc)
3583 break;
3584 } else {
3585 for (; i < table->stream_count; i++)
3586 if (dio_stream_enc == table->stream_allocations[i].stream_enc)
3587 break;
3588 }
3589
3590 if (i < table->stream_count) {
3591 i++;
3592 for (; i < table->stream_count; i++)
3593 table->stream_allocations[i-1] = table->stream_allocations[i];
3594 memset(&table->stream_allocations[table->stream_count-1], 0,
3595 sizeof(struct link_mst_stream_allocation));
3596 table->stream_count--;
3597 }
3598 }
3599
dc_log_vcp_x_y(const struct dc_link * link,struct fixed31_32 avg_time_slots_per_mtp)3600 static void dc_log_vcp_x_y(const struct dc_link *link, struct fixed31_32 avg_time_slots_per_mtp)
3601 {
3602 const uint32_t VCP_Y_PRECISION = 1000;
3603 uint64_t vcp_x, vcp_y;
3604
3605 // Add 0.5*(1/VCP_Y_PRECISION) to round up to decimal precision
3606 avg_time_slots_per_mtp = dc_fixpt_add(
3607 avg_time_slots_per_mtp, dc_fixpt_from_fraction(1, 2 * VCP_Y_PRECISION));
3608
3609 vcp_x = dc_fixpt_floor(avg_time_slots_per_mtp);
3610 vcp_y = dc_fixpt_floor(
3611 dc_fixpt_mul_int(
3612 dc_fixpt_sub_int(avg_time_slots_per_mtp, dc_fixpt_floor(avg_time_slots_per_mtp)),
3613 VCP_Y_PRECISION));
3614
3615 if (link->type == dc_connection_mst_branch)
3616 DC_LOG_DP2("MST Update Payload: set_throttled_vcp_size slot X.Y for MST stream "
3617 "X: %lld Y: %lld/%d", vcp_x, vcp_y, VCP_Y_PRECISION);
3618 else
3619 DC_LOG_DP2("SST Update Payload: set_throttled_vcp_size slot X.Y for SST stream "
3620 "X: %lld Y: %lld/%d", vcp_x, vcp_y, VCP_Y_PRECISION);
3621 }
3622
3623 /*
3624 * Payload allocation/deallocation for SST introduced in DP2.0
3625 */
dc_link_update_sst_payload(struct pipe_ctx * pipe_ctx,bool allocate)3626 static enum dc_status dc_link_update_sst_payload(struct pipe_ctx *pipe_ctx,
3627 bool allocate)
3628 {
3629 struct dc_stream_state *stream = pipe_ctx->stream;
3630 struct dc_link *link = stream->link;
3631 struct link_mst_stream_allocation_table proposed_table = {0};
3632 struct fixed31_32 avg_time_slots_per_mtp;
3633 const struct dc_link_settings empty_link_settings = {0};
3634 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res);
3635 DC_LOGGER_INIT(link->ctx->logger);
3636
3637 /* slot X.Y for SST payload deallocate */
3638 if (!allocate) {
3639 avg_time_slots_per_mtp = dc_fixpt_from_int(0);
3640
3641 dc_log_vcp_x_y(link, avg_time_slots_per_mtp);
3642
3643 if (link_hwss->ext.set_throttled_vcp_size)
3644 link_hwss->ext.set_throttled_vcp_size(pipe_ctx,
3645 avg_time_slots_per_mtp);
3646 if (link_hwss->ext.set_hblank_min_symbol_width)
3647 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx,
3648 &empty_link_settings,
3649 avg_time_slots_per_mtp);
3650 }
3651
3652 /* calculate VC payload and update branch with new payload allocation table*/
3653 if (!dpcd_write_128b_132b_sst_payload_allocation_table(
3654 stream,
3655 link,
3656 &proposed_table,
3657 allocate)) {
3658 DC_LOG_ERROR("SST Update Payload: Failed to update "
3659 "allocation table for "
3660 "pipe idx: %d\n",
3661 pipe_ctx->pipe_idx);
3662 return DC_FAIL_DP_PAYLOAD_ALLOCATION;
3663 }
3664
3665 proposed_table.stream_allocations[0].hpo_dp_stream_enc = pipe_ctx->stream_res.hpo_dp_stream_enc;
3666
3667 ASSERT(proposed_table.stream_count == 1);
3668
3669 //TODO - DP2.0 Logging: Instead of hpo_dp_stream_enc pointer, log instance id
3670 DC_LOG_DP2("SST Update Payload: hpo_dp_stream_enc: %p "
3671 "vcp_id: %d "
3672 "slot_count: %d\n",
3673 (void *) proposed_table.stream_allocations[0].hpo_dp_stream_enc,
3674 proposed_table.stream_allocations[0].vcp_id,
3675 proposed_table.stream_allocations[0].slot_count);
3676
3677 /* program DP source TX for payload */
3678 link_hwss->ext.update_stream_allocation_table(link, &pipe_ctx->link_res,
3679 &proposed_table);
3680
3681 /* poll for ACT handled */
3682 if (!dpcd_poll_for_allocation_change_trigger(link)) {
3683 // Failures will result in blackscreen and errors logged
3684 BREAK_TO_DEBUGGER();
3685 }
3686
3687 /* slot X.Y for SST payload allocate */
3688 if (allocate && dp_get_link_encoding_format(&link->cur_link_settings) ==
3689 DP_128b_132b_ENCODING) {
3690 avg_time_slots_per_mtp = calculate_sst_avg_time_slots_per_mtp(stream, link);
3691
3692 dc_log_vcp_x_y(link, avg_time_slots_per_mtp);
3693
3694 if (link_hwss->ext.set_throttled_vcp_size)
3695 link_hwss->ext.set_throttled_vcp_size(pipe_ctx,
3696 avg_time_slots_per_mtp);
3697 if (link_hwss->ext.set_hblank_min_symbol_width)
3698 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx,
3699 &link->cur_link_settings,
3700 avg_time_slots_per_mtp);
3701 }
3702
3703 /* Always return DC_OK.
3704 * If part of sequence fails, log failure(s) and show blackscreen
3705 */
3706 return DC_OK;
3707 }
3708
3709 /* convert link_mst_stream_alloc_table to dm dp_mst_stream_alloc_table
3710 * because stream_encoder is not exposed to dm
3711 */
dc_link_allocate_mst_payload(struct pipe_ctx * pipe_ctx)3712 enum dc_status dc_link_allocate_mst_payload(struct pipe_ctx *pipe_ctx)
3713 {
3714 struct dc_stream_state *stream = pipe_ctx->stream;
3715 struct dc_link *link = stream->link;
3716 struct dc_dp_mst_stream_allocation_table proposed_table = {0};
3717 struct fixed31_32 avg_time_slots_per_mtp;
3718 struct fixed31_32 pbn;
3719 struct fixed31_32 pbn_per_slot;
3720 int i;
3721 enum act_return_status ret;
3722 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res);
3723 DC_LOGGER_INIT(link->ctx->logger);
3724
3725 /* enable_link_dp_mst already check link->enabled_stream_count
3726 * and stream is in link->stream[]. This is called during set mode,
3727 * stream_enc is available.
3728 */
3729
3730 /* get calculate VC payload for stream: stream_alloc */
3731 if (dm_helpers_dp_mst_write_payload_allocation_table(
3732 stream->ctx,
3733 stream,
3734 &proposed_table,
3735 true))
3736 update_mst_stream_alloc_table(
3737 link,
3738 pipe_ctx->stream_res.stream_enc,
3739 pipe_ctx->stream_res.hpo_dp_stream_enc,
3740 &proposed_table);
3741 else
3742 DC_LOG_WARNING("Failed to update"
3743 "MST allocation table for"
3744 "pipe idx:%d\n",
3745 pipe_ctx->pipe_idx);
3746
3747 DC_LOG_MST("%s "
3748 "stream_count: %d: \n ",
3749 __func__,
3750 link->mst_stream_alloc_table.stream_count);
3751
3752 for (i = 0; i < MAX_CONTROLLER_NUM; i++) {
3753 DC_LOG_MST("stream_enc[%d]: %p "
3754 "stream[%d].hpo_dp_stream_enc: %p "
3755 "stream[%d].vcp_id: %d "
3756 "stream[%d].slot_count: %d\n",
3757 i,
3758 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc,
3759 i,
3760 (void *) link->mst_stream_alloc_table.stream_allocations[i].hpo_dp_stream_enc,
3761 i,
3762 link->mst_stream_alloc_table.stream_allocations[i].vcp_id,
3763 i,
3764 link->mst_stream_alloc_table.stream_allocations[i].slot_count);
3765 }
3766
3767 ASSERT(proposed_table.stream_count > 0);
3768
3769 /* program DP source TX for payload */
3770 if (link_hwss->ext.update_stream_allocation_table == NULL ||
3771 dp_get_link_encoding_format(&link->cur_link_settings) == DP_UNKNOWN_ENCODING) {
3772 DC_LOG_ERROR("Failure: unknown encoding format\n");
3773 return DC_ERROR_UNEXPECTED;
3774 }
3775
3776 link_hwss->ext.update_stream_allocation_table(link,
3777 &pipe_ctx->link_res,
3778 &link->mst_stream_alloc_table);
3779
3780 /* send down message */
3781 ret = dm_helpers_dp_mst_poll_for_allocation_change_trigger(
3782 stream->ctx,
3783 stream);
3784
3785 if (ret != ACT_LINK_LOST) {
3786 dm_helpers_dp_mst_send_payload_allocation(
3787 stream->ctx,
3788 stream,
3789 true);
3790 }
3791
3792 /* slot X.Y for only current stream */
3793 pbn_per_slot = get_pbn_per_slot(stream);
3794 if (pbn_per_slot.value == 0) {
3795 DC_LOG_ERROR("Failure: pbn_per_slot==0 not allowed. Cannot continue, returning DC_UNSUPPORTED_VALUE.\n");
3796 return DC_UNSUPPORTED_VALUE;
3797 }
3798 pbn = get_pbn_from_timing(pipe_ctx);
3799 avg_time_slots_per_mtp = dc_fixpt_div(pbn, pbn_per_slot);
3800
3801 dc_log_vcp_x_y(link, avg_time_slots_per_mtp);
3802
3803 if (link_hwss->ext.set_throttled_vcp_size)
3804 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp);
3805 if (link_hwss->ext.set_hblank_min_symbol_width)
3806 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx,
3807 &link->cur_link_settings,
3808 avg_time_slots_per_mtp);
3809
3810 return DC_OK;
3811
3812 }
3813
dc_link_reduce_mst_payload(struct pipe_ctx * pipe_ctx,uint32_t bw_in_kbps)3814 enum dc_status dc_link_reduce_mst_payload(struct pipe_ctx *pipe_ctx, uint32_t bw_in_kbps)
3815 {
3816 struct dc_stream_state *stream = pipe_ctx->stream;
3817 struct dc_link *link = stream->link;
3818 struct fixed31_32 avg_time_slots_per_mtp;
3819 struct fixed31_32 pbn;
3820 struct fixed31_32 pbn_per_slot;
3821 struct dc_dp_mst_stream_allocation_table proposed_table = {0};
3822 uint8_t i;
3823 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res);
3824 DC_LOGGER_INIT(link->ctx->logger);
3825
3826 /* decrease throttled vcp size */
3827 pbn_per_slot = get_pbn_per_slot(stream);
3828 pbn = get_pbn_from_bw_in_kbps(bw_in_kbps);
3829 avg_time_slots_per_mtp = dc_fixpt_div(pbn, pbn_per_slot);
3830
3831 if (link_hwss->ext.set_throttled_vcp_size)
3832 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp);
3833 if (link_hwss->ext.set_hblank_min_symbol_width)
3834 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx,
3835 &link->cur_link_settings,
3836 avg_time_slots_per_mtp);
3837
3838 /* send ALLOCATE_PAYLOAD sideband message with updated pbn */
3839 dm_helpers_dp_mst_send_payload_allocation(
3840 stream->ctx,
3841 stream,
3842 true);
3843
3844 /* notify immediate branch device table update */
3845 if (dm_helpers_dp_mst_write_payload_allocation_table(
3846 stream->ctx,
3847 stream,
3848 &proposed_table,
3849 true)) {
3850 /* update mst stream allocation table software state */
3851 update_mst_stream_alloc_table(
3852 link,
3853 pipe_ctx->stream_res.stream_enc,
3854 pipe_ctx->stream_res.hpo_dp_stream_enc,
3855 &proposed_table);
3856 } else {
3857 DC_LOG_WARNING("Failed to update"
3858 "MST allocation table for"
3859 "pipe idx:%d\n",
3860 pipe_ctx->pipe_idx);
3861 }
3862
3863 DC_LOG_MST("%s "
3864 "stream_count: %d: \n ",
3865 __func__,
3866 link->mst_stream_alloc_table.stream_count);
3867
3868 for (i = 0; i < MAX_CONTROLLER_NUM; i++) {
3869 DC_LOG_MST("stream_enc[%d]: %p "
3870 "stream[%d].hpo_dp_stream_enc: %p "
3871 "stream[%d].vcp_id: %d "
3872 "stream[%d].slot_count: %d\n",
3873 i,
3874 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc,
3875 i,
3876 (void *) link->mst_stream_alloc_table.stream_allocations[i].hpo_dp_stream_enc,
3877 i,
3878 link->mst_stream_alloc_table.stream_allocations[i].vcp_id,
3879 i,
3880 link->mst_stream_alloc_table.stream_allocations[i].slot_count);
3881 }
3882
3883 ASSERT(proposed_table.stream_count > 0);
3884
3885 /* update mst stream allocation table hardware state */
3886 if (link_hwss->ext.update_stream_allocation_table == NULL ||
3887 dp_get_link_encoding_format(&link->cur_link_settings) == DP_UNKNOWN_ENCODING) {
3888 DC_LOG_ERROR("Failure: unknown encoding format\n");
3889 return DC_ERROR_UNEXPECTED;
3890 }
3891
3892 link_hwss->ext.update_stream_allocation_table(link, &pipe_ctx->link_res,
3893 &link->mst_stream_alloc_table);
3894
3895 /* poll for immediate branch device ACT handled */
3896 dm_helpers_dp_mst_poll_for_allocation_change_trigger(
3897 stream->ctx,
3898 stream);
3899
3900 return DC_OK;
3901 }
3902
dc_link_increase_mst_payload(struct pipe_ctx * pipe_ctx,uint32_t bw_in_kbps)3903 enum dc_status dc_link_increase_mst_payload(struct pipe_ctx *pipe_ctx, uint32_t bw_in_kbps)
3904 {
3905 struct dc_stream_state *stream = pipe_ctx->stream;
3906 struct dc_link *link = stream->link;
3907 struct fixed31_32 avg_time_slots_per_mtp;
3908 struct fixed31_32 pbn;
3909 struct fixed31_32 pbn_per_slot;
3910 struct dc_dp_mst_stream_allocation_table proposed_table = {0};
3911 uint8_t i;
3912 enum act_return_status ret;
3913 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res);
3914 DC_LOGGER_INIT(link->ctx->logger);
3915
3916 /* notify immediate branch device table update */
3917 if (dm_helpers_dp_mst_write_payload_allocation_table(
3918 stream->ctx,
3919 stream,
3920 &proposed_table,
3921 true)) {
3922 /* update mst stream allocation table software state */
3923 update_mst_stream_alloc_table(
3924 link,
3925 pipe_ctx->stream_res.stream_enc,
3926 pipe_ctx->stream_res.hpo_dp_stream_enc,
3927 &proposed_table);
3928 }
3929
3930 DC_LOG_MST("%s "
3931 "stream_count: %d: \n ",
3932 __func__,
3933 link->mst_stream_alloc_table.stream_count);
3934
3935 for (i = 0; i < MAX_CONTROLLER_NUM; i++) {
3936 DC_LOG_MST("stream_enc[%d]: %p "
3937 "stream[%d].hpo_dp_stream_enc: %p "
3938 "stream[%d].vcp_id: %d "
3939 "stream[%d].slot_count: %d\n",
3940 i,
3941 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc,
3942 i,
3943 (void *) link->mst_stream_alloc_table.stream_allocations[i].hpo_dp_stream_enc,
3944 i,
3945 link->mst_stream_alloc_table.stream_allocations[i].vcp_id,
3946 i,
3947 link->mst_stream_alloc_table.stream_allocations[i].slot_count);
3948 }
3949
3950 ASSERT(proposed_table.stream_count > 0);
3951
3952 /* update mst stream allocation table hardware state */
3953 if (link_hwss->ext.update_stream_allocation_table == NULL ||
3954 dp_get_link_encoding_format(&link->cur_link_settings) == DP_UNKNOWN_ENCODING) {
3955 DC_LOG_ERROR("Failure: unknown encoding format\n");
3956 return DC_ERROR_UNEXPECTED;
3957 }
3958
3959 link_hwss->ext.update_stream_allocation_table(link, &pipe_ctx->link_res,
3960 &link->mst_stream_alloc_table);
3961
3962 /* poll for immediate branch device ACT handled */
3963 ret = dm_helpers_dp_mst_poll_for_allocation_change_trigger(
3964 stream->ctx,
3965 stream);
3966
3967 if (ret != ACT_LINK_LOST) {
3968 /* send ALLOCATE_PAYLOAD sideband message with updated pbn */
3969 dm_helpers_dp_mst_send_payload_allocation(
3970 stream->ctx,
3971 stream,
3972 true);
3973 }
3974
3975 /* increase throttled vcp size */
3976 pbn = get_pbn_from_bw_in_kbps(bw_in_kbps);
3977 pbn_per_slot = get_pbn_per_slot(stream);
3978 avg_time_slots_per_mtp = dc_fixpt_div(pbn, pbn_per_slot);
3979
3980 if (link_hwss->ext.set_throttled_vcp_size)
3981 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp);
3982 if (link_hwss->ext.set_hblank_min_symbol_width)
3983 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx,
3984 &link->cur_link_settings,
3985 avg_time_slots_per_mtp);
3986
3987 return DC_OK;
3988 }
3989
deallocate_mst_payload(struct pipe_ctx * pipe_ctx)3990 static enum dc_status deallocate_mst_payload(struct pipe_ctx *pipe_ctx)
3991 {
3992 struct dc_stream_state *stream = pipe_ctx->stream;
3993 struct dc_link *link = stream->link;
3994 struct dc_dp_mst_stream_allocation_table proposed_table = {0};
3995 struct fixed31_32 avg_time_slots_per_mtp = dc_fixpt_from_int(0);
3996 int i;
3997 bool mst_mode = (link->type == dc_connection_mst_branch);
3998 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res);
3999 const struct dc_link_settings empty_link_settings = {0};
4000 DC_LOGGER_INIT(link->ctx->logger);
4001
4002 /* deallocate_mst_payload is called before disable link. When mode or
4003 * disable/enable monitor, new stream is created which is not in link
4004 * stream[] yet. For this, payload is not allocated yet, so de-alloc
4005 * should not done. For new mode set, map_resources will get engine
4006 * for new stream, so stream_enc->id should be validated until here.
4007 */
4008
4009 /* slot X.Y */
4010 if (link_hwss->ext.set_throttled_vcp_size)
4011 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp);
4012 if (link_hwss->ext.set_hblank_min_symbol_width)
4013 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx,
4014 &empty_link_settings,
4015 avg_time_slots_per_mtp);
4016
4017 if (mst_mode) {
4018 /* when link is in mst mode, reply on mst manager to remove
4019 * payload
4020 */
4021 if (dm_helpers_dp_mst_write_payload_allocation_table(
4022 stream->ctx,
4023 stream,
4024 &proposed_table,
4025 false))
4026
4027 update_mst_stream_alloc_table(
4028 link,
4029 pipe_ctx->stream_res.stream_enc,
4030 pipe_ctx->stream_res.hpo_dp_stream_enc,
4031 &proposed_table);
4032 else
4033 DC_LOG_WARNING("Failed to update"
4034 "MST allocation table for"
4035 "pipe idx:%d\n",
4036 pipe_ctx->pipe_idx);
4037 } else {
4038 /* when link is no longer in mst mode (mst hub unplugged),
4039 * remove payload with default dc logic
4040 */
4041 remove_stream_from_alloc_table(link, pipe_ctx->stream_res.stream_enc,
4042 pipe_ctx->stream_res.hpo_dp_stream_enc);
4043 }
4044
4045 DC_LOG_MST("%s"
4046 "stream_count: %d: ",
4047 __func__,
4048 link->mst_stream_alloc_table.stream_count);
4049
4050 for (i = 0; i < MAX_CONTROLLER_NUM; i++) {
4051 DC_LOG_MST("stream_enc[%d]: %p "
4052 "stream[%d].hpo_dp_stream_enc: %p "
4053 "stream[%d].vcp_id: %d "
4054 "stream[%d].slot_count: %d\n",
4055 i,
4056 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc,
4057 i,
4058 (void *) link->mst_stream_alloc_table.stream_allocations[i].hpo_dp_stream_enc,
4059 i,
4060 link->mst_stream_alloc_table.stream_allocations[i].vcp_id,
4061 i,
4062 link->mst_stream_alloc_table.stream_allocations[i].slot_count);
4063 }
4064
4065 /* update mst stream allocation table hardware state */
4066 if (link_hwss->ext.update_stream_allocation_table == NULL ||
4067 dp_get_link_encoding_format(&link->cur_link_settings) == DP_UNKNOWN_ENCODING) {
4068 DC_LOG_DEBUG("Unknown encoding format\n");
4069 return DC_ERROR_UNEXPECTED;
4070 }
4071
4072 link_hwss->ext.update_stream_allocation_table(link, &pipe_ctx->link_res,
4073 &link->mst_stream_alloc_table);
4074
4075 if (mst_mode) {
4076 dm_helpers_dp_mst_poll_for_allocation_change_trigger(
4077 stream->ctx,
4078 stream);
4079
4080 dm_helpers_dp_mst_send_payload_allocation(
4081 stream->ctx,
4082 stream,
4083 false);
4084 }
4085
4086 return DC_OK;
4087 }
4088
4089
4090 #if defined(CONFIG_DRM_AMD_DC_HDCP)
update_psp_stream_config(struct pipe_ctx * pipe_ctx,bool dpms_off)4091 static void update_psp_stream_config(struct pipe_ctx *pipe_ctx, bool dpms_off)
4092 {
4093 struct cp_psp *cp_psp = &pipe_ctx->stream->ctx->cp_psp;
4094 struct link_encoder *link_enc = NULL;
4095 struct cp_psp_stream_config config = {0};
4096 enum dp_panel_mode panel_mode =
4097 dp_get_panel_mode(pipe_ctx->stream->link);
4098
4099 if (cp_psp == NULL || cp_psp->funcs.update_stream_config == NULL)
4100 return;
4101
4102 link_enc = link_enc_cfg_get_link_enc(pipe_ctx->stream->link);
4103 ASSERT(link_enc);
4104 if (link_enc == NULL)
4105 return;
4106
4107 /* otg instance */
4108 config.otg_inst = (uint8_t) pipe_ctx->stream_res.tg->inst;
4109
4110 /* dig front end */
4111 config.dig_fe = (uint8_t) pipe_ctx->stream_res.stream_enc->stream_enc_inst;
4112
4113 /* stream encoder index */
4114 config.stream_enc_idx = pipe_ctx->stream_res.stream_enc->id - ENGINE_ID_DIGA;
4115 if (is_dp_128b_132b_signal(pipe_ctx))
4116 config.stream_enc_idx =
4117 pipe_ctx->stream_res.hpo_dp_stream_enc->id - ENGINE_ID_HPO_DP_0;
4118
4119 /* dig back end */
4120 config.dig_be = pipe_ctx->stream->link->link_enc_hw_inst;
4121
4122 /* link encoder index */
4123 config.link_enc_idx = link_enc->transmitter - TRANSMITTER_UNIPHY_A;
4124 if (is_dp_128b_132b_signal(pipe_ctx))
4125 config.link_enc_idx = pipe_ctx->link_res.hpo_dp_link_enc->inst;
4126
4127 /* dio output index is dpia index for DPIA endpoint & dcio index by default */
4128 if (pipe_ctx->stream->link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA)
4129 config.dio_output_idx = pipe_ctx->stream->link->link_id.enum_id - ENUM_ID_1;
4130 else
4131 config.dio_output_idx = link_enc->transmitter - TRANSMITTER_UNIPHY_A;
4132
4133
4134 /* phy index */
4135 config.phy_idx = resource_transmitter_to_phy_idx(
4136 pipe_ctx->stream->link->dc, link_enc->transmitter);
4137 if (pipe_ctx->stream->link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA)
4138 /* USB4 DPIA doesn't use PHY in our soc, initialize it to 0 */
4139 config.phy_idx = 0;
4140
4141 /* stream properties */
4142 config.assr_enabled = (panel_mode == DP_PANEL_MODE_EDP) ? 1 : 0;
4143 config.mst_enabled = (pipe_ctx->stream->signal ==
4144 SIGNAL_TYPE_DISPLAY_PORT_MST) ? 1 : 0;
4145 config.dp2_enabled = is_dp_128b_132b_signal(pipe_ctx) ? 1 : 0;
4146 config.usb4_enabled = (pipe_ctx->stream->link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) ?
4147 1 : 0;
4148 config.dpms_off = dpms_off;
4149
4150 /* dm stream context */
4151 config.dm_stream_ctx = pipe_ctx->stream->dm_stream_context;
4152
4153 cp_psp->funcs.update_stream_config(cp_psp->handle, &config);
4154 }
4155 #endif
4156
fpga_dp_hpo_enable_link_and_stream(struct dc_state * state,struct pipe_ctx * pipe_ctx)4157 static void fpga_dp_hpo_enable_link_and_stream(struct dc_state *state, struct pipe_ctx *pipe_ctx)
4158 {
4159 struct dc *dc = pipe_ctx->stream->ctx->dc;
4160 struct dc_stream_state *stream = pipe_ctx->stream;
4161 struct link_mst_stream_allocation_table proposed_table = {0};
4162 struct fixed31_32 avg_time_slots_per_mtp;
4163 uint8_t req_slot_count = 0;
4164 uint8_t vc_id = 1; /// VC ID always 1 for SST
4165 struct dc_link_settings link_settings = pipe_ctx->link_config.dp_link_settings;
4166 const struct link_hwss *link_hwss = get_link_hwss(stream->link, &pipe_ctx->link_res);
4167 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
4168
4169 stream->link->cur_link_settings = link_settings;
4170
4171 if (link_hwss->ext.enable_dp_link_output)
4172 link_hwss->ext.enable_dp_link_output(stream->link, &pipe_ctx->link_res,
4173 stream->signal, pipe_ctx->clock_source->id,
4174 &link_settings);
4175
4176 #ifdef DIAGS_BUILD
4177 /* Workaround for FPGA HPO capture DP link data:
4178 * HPO capture will set link to active mode
4179 * This workaround is required to get a capture from start of frame
4180 */
4181 if (!dc->debug.fpga_hpo_capture_en) {
4182 struct encoder_set_dp_phy_pattern_param params = {0};
4183 params.dp_phy_pattern = DP_TEST_PATTERN_VIDEO_MODE;
4184
4185 /* Set link active */
4186 stream->link->hpo_dp_link_enc->funcs->set_link_test_pattern(
4187 stream->link->hpo_dp_link_enc,
4188 ¶ms);
4189 }
4190 #endif
4191
4192 /* Enable DP_STREAM_ENC */
4193 dc->hwss.enable_stream(pipe_ctx);
4194
4195 /* Set DPS PPS SDP (AKA "info frames") */
4196 if (pipe_ctx->stream->timing.flags.DSC) {
4197 dp_set_dsc_pps_sdp(pipe_ctx, true, true);
4198 }
4199
4200 /* Allocate Payload */
4201 if ((stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) && (state->stream_count > 1)) {
4202 // MST case
4203 uint8_t i;
4204
4205 proposed_table.stream_count = state->stream_count;
4206 for (i = 0; i < state->stream_count; i++) {
4207 avg_time_slots_per_mtp = calculate_sst_avg_time_slots_per_mtp(state->streams[i], state->streams[i]->link);
4208 req_slot_count = dc_fixpt_ceil(avg_time_slots_per_mtp);
4209 proposed_table.stream_allocations[i].slot_count = req_slot_count;
4210 proposed_table.stream_allocations[i].vcp_id = i+1;
4211 /* NOTE: This makes assumption that pipe_ctx index is same as stream index */
4212 proposed_table.stream_allocations[i].hpo_dp_stream_enc = state->res_ctx.pipe_ctx[i].stream_res.hpo_dp_stream_enc;
4213 }
4214 } else {
4215 // SST case
4216 avg_time_slots_per_mtp = calculate_sst_avg_time_slots_per_mtp(stream, stream->link);
4217 req_slot_count = dc_fixpt_ceil(avg_time_slots_per_mtp);
4218 proposed_table.stream_count = 1; /// Always 1 stream for SST
4219 proposed_table.stream_allocations[0].slot_count = req_slot_count;
4220 proposed_table.stream_allocations[0].vcp_id = vc_id;
4221 proposed_table.stream_allocations[0].hpo_dp_stream_enc = pipe_ctx->stream_res.hpo_dp_stream_enc;
4222 }
4223
4224 link_hwss->ext.update_stream_allocation_table(stream->link,
4225 &pipe_ctx->link_res,
4226 &proposed_table);
4227
4228 if (link_hwss->ext.set_throttled_vcp_size)
4229 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp);
4230
4231 dc->hwss.unblank_stream(pipe_ctx, &stream->link->cur_link_settings);
4232 }
4233
core_link_enable_stream(struct dc_state * state,struct pipe_ctx * pipe_ctx)4234 void core_link_enable_stream(
4235 struct dc_state *state,
4236 struct pipe_ctx *pipe_ctx)
4237 {
4238 struct dc *dc = pipe_ctx->stream->ctx->dc;
4239 struct dc_stream_state *stream = pipe_ctx->stream;
4240 struct dc_link *link = stream->sink->link;
4241 enum dc_status status;
4242 struct link_encoder *link_enc;
4243 enum otg_out_mux_dest otg_out_dest = OUT_MUX_DIO;
4244 struct vpg *vpg = pipe_ctx->stream_res.stream_enc->vpg;
4245 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res);
4246
4247 if (is_dp_128b_132b_signal(pipe_ctx))
4248 vpg = pipe_ctx->stream_res.hpo_dp_stream_enc->vpg;
4249
4250 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
4251
4252 if (pipe_ctx->stream->sink) {
4253 if (pipe_ctx->stream->sink->sink_signal != SIGNAL_TYPE_VIRTUAL &&
4254 pipe_ctx->stream->sink->sink_signal != SIGNAL_TYPE_NONE) {
4255 DC_LOG_DC("%s pipe_ctx dispname=%s signal=%x\n", __func__,
4256 pipe_ctx->stream->sink->edid_caps.display_name,
4257 pipe_ctx->stream->signal);
4258 }
4259 }
4260
4261 if (!IS_DIAG_DC(dc->ctx->dce_environment) &&
4262 dc_is_virtual_signal(pipe_ctx->stream->signal))
4263 return;
4264
4265 link_enc = link_enc_cfg_get_link_enc(link);
4266 ASSERT(link_enc);
4267
4268 if (!dc_is_virtual_signal(pipe_ctx->stream->signal)
4269 && !is_dp_128b_132b_signal(pipe_ctx)) {
4270 if (link_enc)
4271 link_enc->funcs->setup(
4272 link_enc,
4273 pipe_ctx->stream->signal);
4274 }
4275
4276 pipe_ctx->stream->link->link_state_valid = true;
4277
4278 if (pipe_ctx->stream_res.tg->funcs->set_out_mux) {
4279 if (is_dp_128b_132b_signal(pipe_ctx))
4280 otg_out_dest = OUT_MUX_HPO_DP;
4281 else
4282 otg_out_dest = OUT_MUX_DIO;
4283 pipe_ctx->stream_res.tg->funcs->set_out_mux(pipe_ctx->stream_res.tg, otg_out_dest);
4284 }
4285
4286 link_hwss->setup_stream_attribute(pipe_ctx);
4287
4288 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
4289 bool apply_edp_fast_boot_optimization =
4290 pipe_ctx->stream->apply_edp_fast_boot_optimization;
4291
4292 pipe_ctx->stream->apply_edp_fast_boot_optimization = false;
4293
4294 // Enable VPG before building infoframe
4295 if (vpg && vpg->funcs->vpg_poweron)
4296 vpg->funcs->vpg_poweron(vpg);
4297
4298 resource_build_info_frame(pipe_ctx);
4299 dc->hwss.update_info_frame(pipe_ctx);
4300
4301 if (dc_is_dp_signal(pipe_ctx->stream->signal))
4302 dp_source_sequence_trace(link, DPCD_SOURCE_SEQ_AFTER_UPDATE_INFO_FRAME);
4303
4304 /* Do not touch link on seamless boot optimization. */
4305 if (pipe_ctx->stream->apply_seamless_boot_optimization) {
4306 pipe_ctx->stream->dpms_off = false;
4307
4308 /* Still enable stream features & audio on seamless boot for DP external displays */
4309 if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT) {
4310 enable_stream_features(pipe_ctx);
4311 if (pipe_ctx->stream_res.audio != NULL) {
4312 pipe_ctx->stream_res.stream_enc->funcs->dp_audio_enable(pipe_ctx->stream_res.stream_enc);
4313 dc->hwss.enable_audio_stream(pipe_ctx);
4314 }
4315 }
4316
4317 #if defined(CONFIG_DRM_AMD_DC_HDCP)
4318 update_psp_stream_config(pipe_ctx, false);
4319 #endif
4320 return;
4321 }
4322
4323 /* eDP lit up by bios already, no need to enable again. */
4324 if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP &&
4325 apply_edp_fast_boot_optimization &&
4326 !pipe_ctx->stream->timing.flags.DSC &&
4327 !pipe_ctx->next_odm_pipe) {
4328 pipe_ctx->stream->dpms_off = false;
4329 #if defined(CONFIG_DRM_AMD_DC_HDCP)
4330 update_psp_stream_config(pipe_ctx, false);
4331 #endif
4332 return;
4333 }
4334
4335 if (pipe_ctx->stream->dpms_off)
4336 return;
4337
4338 /* Have to setup DSC before DIG FE and BE are connected (which happens before the
4339 * link training). This is to make sure the bandwidth sent to DIG BE won't be
4340 * bigger than what the link and/or DIG BE can handle. VBID[6]/CompressedStream_flag
4341 * will be automatically set at a later time when the video is enabled
4342 * (DP_VID_STREAM_EN = 1).
4343 */
4344 if (pipe_ctx->stream->timing.flags.DSC) {
4345 if (dc_is_dp_signal(pipe_ctx->stream->signal) ||
4346 dc_is_virtual_signal(pipe_ctx->stream->signal))
4347 dp_set_dsc_enable(pipe_ctx, true);
4348
4349 }
4350
4351 status = enable_link(state, pipe_ctx);
4352
4353 if (status != DC_OK) {
4354 DC_LOG_WARNING("enabling link %u failed: %d\n",
4355 pipe_ctx->stream->link->link_index,
4356 status);
4357
4358 /* Abort stream enable *unless* the failure was due to
4359 * DP link training - some DP monitors will recover and
4360 * show the stream anyway. But MST displays can't proceed
4361 * without link training.
4362 */
4363 if (status != DC_FAIL_DP_LINK_TRAINING ||
4364 pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
4365 if (false == stream->link->link_status.link_active)
4366 disable_link(stream->link, &pipe_ctx->link_res,
4367 pipe_ctx->stream->signal);
4368 BREAK_TO_DEBUGGER();
4369 return;
4370 }
4371 }
4372
4373 /* turn off otg test pattern if enable */
4374 if (pipe_ctx->stream_res.tg->funcs->set_test_pattern)
4375 pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,
4376 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
4377 COLOR_DEPTH_UNDEFINED);
4378
4379 /* This second call is needed to reconfigure the DIG
4380 * as a workaround for the incorrect value being applied
4381 * from transmitter control.
4382 */
4383 if (!(dc_is_virtual_signal(pipe_ctx->stream->signal) ||
4384 is_dp_128b_132b_signal(pipe_ctx)))
4385 if (link_enc)
4386 link_enc->funcs->setup(
4387 link_enc,
4388 pipe_ctx->stream->signal);
4389
4390 dc->hwss.enable_stream(pipe_ctx);
4391
4392 /* Set DPS PPS SDP (AKA "info frames") */
4393 if (pipe_ctx->stream->timing.flags.DSC) {
4394 if (dc_is_dp_signal(pipe_ctx->stream->signal) ||
4395 dc_is_virtual_signal(pipe_ctx->stream->signal)) {
4396 dp_set_dsc_on_rx(pipe_ctx, true);
4397 dp_set_dsc_pps_sdp(pipe_ctx, true, true);
4398 }
4399 }
4400
4401 if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
4402 dc_link_allocate_mst_payload(pipe_ctx);
4403 else if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT &&
4404 is_dp_128b_132b_signal(pipe_ctx))
4405 dc_link_update_sst_payload(pipe_ctx, true);
4406
4407 dc->hwss.unblank_stream(pipe_ctx,
4408 &pipe_ctx->stream->link->cur_link_settings);
4409
4410 if (stream->sink_patches.delay_ignore_msa > 0)
4411 msleep(stream->sink_patches.delay_ignore_msa);
4412
4413 if (dc_is_dp_signal(pipe_ctx->stream->signal))
4414 enable_stream_features(pipe_ctx);
4415 #if defined(CONFIG_DRM_AMD_DC_HDCP)
4416 update_psp_stream_config(pipe_ctx, false);
4417 #endif
4418
4419 dc->hwss.enable_audio_stream(pipe_ctx);
4420
4421 } else { // if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
4422 if (is_dp_128b_132b_signal(pipe_ctx))
4423 fpga_dp_hpo_enable_link_and_stream(state, pipe_ctx);
4424 if (dc_is_dp_signal(pipe_ctx->stream->signal) ||
4425 dc_is_virtual_signal(pipe_ctx->stream->signal))
4426 dp_set_dsc_enable(pipe_ctx, true);
4427 }
4428
4429 if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) {
4430 core_link_set_avmute(pipe_ctx, false);
4431 }
4432 }
4433
core_link_disable_stream(struct pipe_ctx * pipe_ctx)4434 void core_link_disable_stream(struct pipe_ctx *pipe_ctx)
4435 {
4436 struct dc *dc = pipe_ctx->stream->ctx->dc;
4437 struct dc_stream_state *stream = pipe_ctx->stream;
4438 struct dc_link *link = stream->sink->link;
4439 struct vpg *vpg = pipe_ctx->stream_res.stream_enc->vpg;
4440
4441 if (is_dp_128b_132b_signal(pipe_ctx))
4442 vpg = pipe_ctx->stream_res.hpo_dp_stream_enc->vpg;
4443
4444 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
4445
4446 if (pipe_ctx->stream->sink) {
4447 if (pipe_ctx->stream->sink->sink_signal != SIGNAL_TYPE_VIRTUAL &&
4448 pipe_ctx->stream->sink->sink_signal != SIGNAL_TYPE_NONE) {
4449 DC_LOG_DC("%s pipe_ctx dispname=%s signal=%x\n", __func__,
4450 pipe_ctx->stream->sink->edid_caps.display_name,
4451 pipe_ctx->stream->signal);
4452 }
4453 }
4454
4455 if (!IS_DIAG_DC(dc->ctx->dce_environment) &&
4456 dc_is_virtual_signal(pipe_ctx->stream->signal))
4457 return;
4458
4459 if (!pipe_ctx->stream->sink->edid_caps.panel_patch.skip_avmute) {
4460 if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
4461 core_link_set_avmute(pipe_ctx, true);
4462 }
4463
4464 dc->hwss.disable_audio_stream(pipe_ctx);
4465
4466 #if defined(CONFIG_DRM_AMD_DC_HDCP)
4467 update_psp_stream_config(pipe_ctx, true);
4468 #endif
4469 dc->hwss.blank_stream(pipe_ctx);
4470
4471 if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
4472 deallocate_mst_payload(pipe_ctx);
4473 else if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT &&
4474 is_dp_128b_132b_signal(pipe_ctx))
4475 dc_link_update_sst_payload(pipe_ctx, false);
4476
4477 if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) {
4478 struct ext_hdmi_settings settings = {0};
4479 enum engine_id eng_id = pipe_ctx->stream_res.stream_enc->id;
4480
4481 unsigned short masked_chip_caps = link->chip_caps &
4482 EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK;
4483 //Need to inform that sink is going to use legacy HDMI mode.
4484 dal_ddc_service_write_scdc_data(
4485 link->ddc,
4486 165000,//vbios only handles 165Mhz.
4487 false);
4488 if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT) {
4489 /* DP159, Retimer settings */
4490 if (get_ext_hdmi_settings(pipe_ctx, eng_id, &settings))
4491 write_i2c_retimer_setting(pipe_ctx,
4492 false, false, &settings);
4493 else
4494 write_i2c_default_retimer_setting(pipe_ctx,
4495 false, false);
4496 } else if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204) {
4497 /* PI3EQX1204, Redriver settings */
4498 write_i2c_redriver_setting(pipe_ctx, false);
4499 }
4500 }
4501
4502 if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT &&
4503 !is_dp_128b_132b_signal(pipe_ctx)) {
4504
4505 /* In DP1.x SST mode, our encoder will go to TPS1
4506 * when link is on but stream is off.
4507 * Disabling link before stream will avoid exposing TPS1 pattern
4508 * during the disable sequence as it will confuse some receivers
4509 * state machine.
4510 * In DP2 or MST mode, our encoder will stay video active
4511 */
4512 disable_link(pipe_ctx->stream->link, &pipe_ctx->link_res, pipe_ctx->stream->signal);
4513 dc->hwss.disable_stream(pipe_ctx);
4514 } else {
4515 dc->hwss.disable_stream(pipe_ctx);
4516 disable_link(pipe_ctx->stream->link, &pipe_ctx->link_res, pipe_ctx->stream->signal);
4517 }
4518
4519 if (pipe_ctx->stream->timing.flags.DSC) {
4520 if (dc_is_dp_signal(pipe_ctx->stream->signal))
4521 dp_set_dsc_enable(pipe_ctx, false);
4522 }
4523 if (is_dp_128b_132b_signal(pipe_ctx)) {
4524 if (pipe_ctx->stream_res.tg->funcs->set_out_mux)
4525 pipe_ctx->stream_res.tg->funcs->set_out_mux(pipe_ctx->stream_res.tg, OUT_MUX_DIO);
4526 }
4527
4528 if (vpg && vpg->funcs->vpg_powerdown)
4529 vpg->funcs->vpg_powerdown(vpg);
4530 }
4531
core_link_set_avmute(struct pipe_ctx * pipe_ctx,bool enable)4532 void core_link_set_avmute(struct pipe_ctx *pipe_ctx, bool enable)
4533 {
4534 struct dc *dc = pipe_ctx->stream->ctx->dc;
4535
4536 if (!dc_is_hdmi_signal(pipe_ctx->stream->signal))
4537 return;
4538
4539 dc->hwss.set_avmute(pipe_ctx, enable);
4540 }
4541
4542 /**
4543 * dc_link_enable_hpd_filter:
4544 * If enable is true, programs HPD filter on associated HPD line using
4545 * delay_on_disconnect/delay_on_connect values dependent on
4546 * link->connector_signal
4547 *
4548 * If enable is false, programs HPD filter on associated HPD line with no
4549 * delays on connect or disconnect
4550 *
4551 * @link: pointer to the dc link
4552 * @enable: boolean specifying whether to enable hbd
4553 */
dc_link_enable_hpd_filter(struct dc_link * link,bool enable)4554 void dc_link_enable_hpd_filter(struct dc_link *link, bool enable)
4555 {
4556 struct gpio *hpd;
4557
4558 if (enable) {
4559 link->is_hpd_filter_disabled = false;
4560 program_hpd_filter(link);
4561 } else {
4562 link->is_hpd_filter_disabled = true;
4563 /* Obtain HPD handle */
4564 hpd = get_hpd_gpio(link->ctx->dc_bios, link->link_id, link->ctx->gpio_service);
4565
4566 if (!hpd)
4567 return;
4568
4569 /* Setup HPD filtering */
4570 if (dal_gpio_open(hpd, GPIO_MODE_INTERRUPT) == GPIO_RESULT_OK) {
4571 struct gpio_hpd_config config;
4572
4573 config.delay_on_connect = 0;
4574 config.delay_on_disconnect = 0;
4575
4576 dal_irq_setup_hpd_filter(hpd, &config);
4577
4578 dal_gpio_close(hpd);
4579 } else {
4580 ASSERT_CRITICAL(false);
4581 }
4582 /* Release HPD handle */
4583 dal_gpio_destroy_irq(&hpd);
4584 }
4585 }
4586
dc_link_set_drive_settings(struct dc * dc,struct link_training_settings * lt_settings,const struct dc_link * link)4587 void dc_link_set_drive_settings(struct dc *dc,
4588 struct link_training_settings *lt_settings,
4589 const struct dc_link *link)
4590 {
4591
4592 int i;
4593 struct link_resource link_res;
4594
4595 for (i = 0; i < dc->link_count; i++)
4596 if (dc->links[i] == link)
4597 break;
4598
4599 if (i >= dc->link_count)
4600 ASSERT_CRITICAL(false);
4601
4602 dc_link_get_cur_link_res(link, &link_res);
4603 dc_link_dp_set_drive_settings(dc->links[i], &link_res, lt_settings);
4604 }
4605
dc_link_set_preferred_link_settings(struct dc * dc,struct dc_link_settings * link_setting,struct dc_link * link)4606 void dc_link_set_preferred_link_settings(struct dc *dc,
4607 struct dc_link_settings *link_setting,
4608 struct dc_link *link)
4609 {
4610 int i;
4611 struct pipe_ctx *pipe;
4612 struct dc_stream_state *link_stream;
4613 struct dc_link_settings store_settings = *link_setting;
4614
4615 link->preferred_link_setting = store_settings;
4616
4617 /* Retrain with preferred link settings only relevant for
4618 * DP signal type
4619 * Check for non-DP signal or if passive dongle present
4620 */
4621 if (!dc_is_dp_signal(link->connector_signal) ||
4622 link->dongle_max_pix_clk > 0)
4623 return;
4624
4625 for (i = 0; i < MAX_PIPES; i++) {
4626 pipe = &dc->current_state->res_ctx.pipe_ctx[i];
4627 if (pipe->stream && pipe->stream->link) {
4628 if (pipe->stream->link == link) {
4629 link_stream = pipe->stream;
4630 break;
4631 }
4632 }
4633 }
4634
4635 /* Stream not found */
4636 if (i == MAX_PIPES)
4637 return;
4638
4639 /* Cannot retrain link if backend is off */
4640 if (link_stream->dpms_off)
4641 return;
4642
4643 if (decide_link_settings(link_stream, &store_settings))
4644 dp_retrain_link_dp_test(link, &store_settings, false);
4645 }
4646
dc_link_set_preferred_training_settings(struct dc * dc,struct dc_link_settings * link_setting,struct dc_link_training_overrides * lt_overrides,struct dc_link * link,bool skip_immediate_retrain)4647 void dc_link_set_preferred_training_settings(struct dc *dc,
4648 struct dc_link_settings *link_setting,
4649 struct dc_link_training_overrides *lt_overrides,
4650 struct dc_link *link,
4651 bool skip_immediate_retrain)
4652 {
4653 if (lt_overrides != NULL)
4654 link->preferred_training_settings = *lt_overrides;
4655 else
4656 memset(&link->preferred_training_settings, 0, sizeof(link->preferred_training_settings));
4657
4658 if (link_setting != NULL) {
4659 link->preferred_link_setting = *link_setting;
4660 if (dp_get_link_encoding_format(link_setting) == DP_128b_132b_ENCODING)
4661 /* TODO: add dc update for acquiring link res */
4662 skip_immediate_retrain = true;
4663 } else {
4664 link->preferred_link_setting.lane_count = LANE_COUNT_UNKNOWN;
4665 link->preferred_link_setting.link_rate = LINK_RATE_UNKNOWN;
4666 }
4667
4668 /* Retrain now, or wait until next stream update to apply */
4669 if (skip_immediate_retrain == false)
4670 dc_link_set_preferred_link_settings(dc, &link->preferred_link_setting, link);
4671 }
4672
dc_link_enable_hpd(const struct dc_link * link)4673 void dc_link_enable_hpd(const struct dc_link *link)
4674 {
4675 dc_link_dp_enable_hpd(link);
4676 }
4677
dc_link_disable_hpd(const struct dc_link * link)4678 void dc_link_disable_hpd(const struct dc_link *link)
4679 {
4680 dc_link_dp_disable_hpd(link);
4681 }
4682
dc_link_set_test_pattern(struct dc_link * link,enum dp_test_pattern test_pattern,enum dp_test_pattern_color_space test_pattern_color_space,const struct link_training_settings * p_link_settings,const unsigned char * p_custom_pattern,unsigned int cust_pattern_size)4683 void dc_link_set_test_pattern(struct dc_link *link,
4684 enum dp_test_pattern test_pattern,
4685 enum dp_test_pattern_color_space test_pattern_color_space,
4686 const struct link_training_settings *p_link_settings,
4687 const unsigned char *p_custom_pattern,
4688 unsigned int cust_pattern_size)
4689 {
4690 if (link != NULL)
4691 dc_link_dp_set_test_pattern(
4692 link,
4693 test_pattern,
4694 test_pattern_color_space,
4695 p_link_settings,
4696 p_custom_pattern,
4697 cust_pattern_size);
4698 }
4699
dc_link_bandwidth_kbps(const struct dc_link * link,const struct dc_link_settings * link_setting)4700 uint32_t dc_link_bandwidth_kbps(
4701 const struct dc_link *link,
4702 const struct dc_link_settings *link_setting)
4703 {
4704 uint32_t total_data_bw_efficiency_x10000 = 0;
4705 uint32_t link_rate_per_lane_kbps = 0;
4706
4707 switch (dp_get_link_encoding_format(link_setting)) {
4708 case DP_8b_10b_ENCODING:
4709 /* For 8b/10b encoding:
4710 * link rate is defined in the unit of LINK_RATE_REF_FREQ_IN_KHZ per DP byte per lane.
4711 * data bandwidth efficiency is 80% with additional 3% overhead if FEC is supported.
4712 */
4713 link_rate_per_lane_kbps = link_setting->link_rate * LINK_RATE_REF_FREQ_IN_KHZ * BITS_PER_DP_BYTE;
4714 total_data_bw_efficiency_x10000 = DATA_EFFICIENCY_8b_10b_x10000;
4715 if (dc_link_should_enable_fec(link)) {
4716 total_data_bw_efficiency_x10000 /= 100;
4717 total_data_bw_efficiency_x10000 *= DATA_EFFICIENCY_8b_10b_FEC_EFFICIENCY_x100;
4718 }
4719 break;
4720 case DP_128b_132b_ENCODING:
4721 /* For 128b/132b encoding:
4722 * link rate is defined in the unit of 10mbps per lane.
4723 * total data bandwidth efficiency is always 96.71%.
4724 */
4725 link_rate_per_lane_kbps = link_setting->link_rate * 10000;
4726 total_data_bw_efficiency_x10000 = DATA_EFFICIENCY_128b_132b_x10000;
4727 break;
4728 default:
4729 break;
4730 }
4731
4732 /* overall effective link bandwidth = link rate per lane * lane count * total data bandwidth efficiency */
4733 return link_rate_per_lane_kbps * link_setting->lane_count / 10000 * total_data_bw_efficiency_x10000;
4734 }
4735
dc_link_get_link_cap(const struct dc_link * link)4736 const struct dc_link_settings *dc_link_get_link_cap(
4737 const struct dc_link *link)
4738 {
4739 if (link->preferred_link_setting.lane_count != LANE_COUNT_UNKNOWN &&
4740 link->preferred_link_setting.link_rate != LINK_RATE_UNKNOWN)
4741 return &link->preferred_link_setting;
4742 return &link->verified_link_cap;
4743 }
4744
dc_link_overwrite_extended_receiver_cap(struct dc_link * link)4745 void dc_link_overwrite_extended_receiver_cap(
4746 struct dc_link *link)
4747 {
4748 dp_overwrite_extended_receiver_cap(link);
4749 }
4750
dc_link_is_fec_supported(const struct dc_link * link)4751 bool dc_link_is_fec_supported(const struct dc_link *link)
4752 {
4753 /* TODO - use asic cap instead of link_enc->features
4754 * we no longer know which link enc to use for this link before commit
4755 */
4756 struct link_encoder *link_enc = NULL;
4757
4758 link_enc = link_enc_cfg_get_link_enc(link);
4759 ASSERT(link_enc);
4760
4761 return (dc_is_dp_signal(link->connector_signal) && link_enc &&
4762 link_enc->features.fec_supported &&
4763 link->dpcd_caps.fec_cap.bits.FEC_CAPABLE &&
4764 !IS_FPGA_MAXIMUS_DC(link->ctx->dce_environment));
4765 }
4766
dc_link_should_enable_fec(const struct dc_link * link)4767 bool dc_link_should_enable_fec(const struct dc_link *link)
4768 {
4769 bool force_disable = false;
4770
4771 if (link->fec_state == dc_link_fec_enabled)
4772 force_disable = false;
4773 else if (link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT_MST &&
4774 link->local_sink &&
4775 link->local_sink->edid_caps.panel_patch.disable_fec)
4776 force_disable = true;
4777 else if (link->connector_signal == SIGNAL_TYPE_EDP
4778 && (link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.
4779 dsc_support.DSC_SUPPORT == false
4780 || link->panel_config.dsc.disable_dsc_edp
4781 || !link->dc->caps.edp_dsc_support))
4782 force_disable = true;
4783
4784 return !force_disable && dc_link_is_fec_supported(link);
4785 }
4786
dc_bandwidth_in_kbps_from_timing(const struct dc_crtc_timing * timing)4787 uint32_t dc_bandwidth_in_kbps_from_timing(
4788 const struct dc_crtc_timing *timing)
4789 {
4790 uint32_t bits_per_channel = 0;
4791 uint32_t kbps;
4792
4793 #if defined(CONFIG_DRM_AMD_DC_DCN)
4794 if (timing->flags.DSC)
4795 return dc_dsc_stream_bandwidth_in_kbps(timing,
4796 timing->dsc_cfg.bits_per_pixel,
4797 timing->dsc_cfg.num_slices_h,
4798 timing->dsc_cfg.is_dp);
4799 #endif /* CONFIG_DRM_AMD_DC_DCN */
4800
4801 switch (timing->display_color_depth) {
4802 case COLOR_DEPTH_666:
4803 bits_per_channel = 6;
4804 break;
4805 case COLOR_DEPTH_888:
4806 bits_per_channel = 8;
4807 break;
4808 case COLOR_DEPTH_101010:
4809 bits_per_channel = 10;
4810 break;
4811 case COLOR_DEPTH_121212:
4812 bits_per_channel = 12;
4813 break;
4814 case COLOR_DEPTH_141414:
4815 bits_per_channel = 14;
4816 break;
4817 case COLOR_DEPTH_161616:
4818 bits_per_channel = 16;
4819 break;
4820 default:
4821 ASSERT(bits_per_channel != 0);
4822 bits_per_channel = 8;
4823 break;
4824 }
4825
4826 kbps = timing->pix_clk_100hz / 10;
4827 kbps *= bits_per_channel;
4828
4829 if (timing->flags.Y_ONLY != 1) {
4830 /*Only YOnly make reduce bandwidth by 1/3 compares to RGB*/
4831 kbps *= 3;
4832 if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
4833 kbps /= 2;
4834 else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422)
4835 kbps = kbps * 2 / 3;
4836 }
4837
4838 return kbps;
4839
4840 }
4841
dc_link_get_cur_link_res(const struct dc_link * link,struct link_resource * link_res)4842 void dc_link_get_cur_link_res(const struct dc_link *link,
4843 struct link_resource *link_res)
4844 {
4845 int i;
4846 struct pipe_ctx *pipe = NULL;
4847
4848 memset(link_res, 0, sizeof(*link_res));
4849
4850 for (i = 0; i < MAX_PIPES; i++) {
4851 pipe = &link->dc->current_state->res_ctx.pipe_ctx[i];
4852 if (pipe->stream && pipe->stream->link && pipe->top_pipe == NULL) {
4853 if (pipe->stream->link == link) {
4854 *link_res = pipe->link_res;
4855 break;
4856 }
4857 }
4858 }
4859
4860 }
4861
4862 /**
4863 * dc_get_cur_link_res_map() - take a snapshot of current link resource allocation state
4864 * @dc: pointer to dc of the dm calling this
4865 * @map: a dc link resource snapshot defined internally to dc.
4866 *
4867 * DM needs to capture a snapshot of current link resource allocation mapping
4868 * and store it in its persistent storage.
4869 *
4870 * Some of the link resource is using first come first serve policy.
4871 * The allocation mapping depends on original hotplug order. This information
4872 * is lost after driver is loaded next time. The snapshot is used in order to
4873 * restore link resource to its previous state so user will get consistent
4874 * link capability allocation across reboot.
4875 *
4876 * Return: none (void function)
4877 *
4878 */
dc_get_cur_link_res_map(const struct dc * dc,uint32_t * map)4879 void dc_get_cur_link_res_map(const struct dc *dc, uint32_t *map)
4880 {
4881 struct dc_link *link;
4882 uint32_t i;
4883 uint32_t hpo_dp_recycle_map = 0;
4884
4885 *map = 0;
4886
4887 if (dc->caps.dp_hpo) {
4888 for (i = 0; i < dc->caps.max_links; i++) {
4889 link = dc->links[i];
4890 if (link->link_status.link_active &&
4891 dp_get_link_encoding_format(&link->reported_link_cap) == DP_128b_132b_ENCODING &&
4892 dp_get_link_encoding_format(&link->cur_link_settings) != DP_128b_132b_ENCODING)
4893 /* hpo dp link encoder is considered as recycled, when RX reports 128b/132b encoding capability
4894 * but current link doesn't use it.
4895 */
4896 hpo_dp_recycle_map |= (1 << i);
4897 }
4898 *map |= (hpo_dp_recycle_map << LINK_RES_HPO_DP_REC_MAP__SHIFT);
4899 }
4900 }
4901
4902 /**
4903 * dc_restore_link_res_map() - restore link resource allocation state from a snapshot
4904 * @dc: pointer to dc of the dm calling this
4905 * @map: a dc link resource snapshot defined internally to dc.
4906 *
4907 * DM needs to call this function after initial link detection on boot and
4908 * before first commit streams to restore link resource allocation state
4909 * from previous boot session.
4910 *
4911 * Some of the link resource is using first come first serve policy.
4912 * The allocation mapping depends on original hotplug order. This information
4913 * is lost after driver is loaded next time. The snapshot is used in order to
4914 * restore link resource to its previous state so user will get consistent
4915 * link capability allocation across reboot.
4916 *
4917 * Return: none (void function)
4918 *
4919 */
dc_restore_link_res_map(const struct dc * dc,uint32_t * map)4920 void dc_restore_link_res_map(const struct dc *dc, uint32_t *map)
4921 {
4922 struct dc_link *link;
4923 uint32_t i;
4924 unsigned int available_hpo_dp_count;
4925 uint32_t hpo_dp_recycle_map = (*map & LINK_RES_HPO_DP_REC_MAP__MASK)
4926 >> LINK_RES_HPO_DP_REC_MAP__SHIFT;
4927
4928 if (dc->caps.dp_hpo) {
4929 available_hpo_dp_count = dc->res_pool->hpo_dp_link_enc_count;
4930 /* remove excess 128b/132b encoding support for not recycled links */
4931 for (i = 0; i < dc->caps.max_links; i++) {
4932 if ((hpo_dp_recycle_map & (1 << i)) == 0) {
4933 link = dc->links[i];
4934 if (link->type != dc_connection_none &&
4935 dp_get_link_encoding_format(&link->verified_link_cap) == DP_128b_132b_ENCODING) {
4936 if (available_hpo_dp_count > 0)
4937 available_hpo_dp_count--;
4938 else
4939 /* remove 128b/132b encoding capability by limiting verified link rate to HBR3 */
4940 link->verified_link_cap.link_rate = LINK_RATE_HIGH3;
4941 }
4942 }
4943 }
4944 /* remove excess 128b/132b encoding support for recycled links */
4945 for (i = 0; i < dc->caps.max_links; i++) {
4946 if ((hpo_dp_recycle_map & (1 << i)) != 0) {
4947 link = dc->links[i];
4948 if (link->type != dc_connection_none &&
4949 dp_get_link_encoding_format(&link->verified_link_cap) == DP_128b_132b_ENCODING) {
4950 if (available_hpo_dp_count > 0)
4951 available_hpo_dp_count--;
4952 else
4953 /* remove 128b/132b encoding capability by limiting verified link rate to HBR3 */
4954 link->verified_link_cap.link_rate = LINK_RATE_HIGH3;
4955 }
4956 }
4957 }
4958 }
4959 }
4960
