1 /*
2 * Copyright 2012-15 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include "dm_services.h"
27 #include "dm_helpers.h"
28 #include "gpio_service_interface.h"
29 #include "include/ddc_service_types.h"
30 #include "include/grph_object_id.h"
31 #include "include/dpcd_defs.h"
32 #include "include/logger_interface.h"
33 #include "include/vector.h"
34 #include "core_types.h"
35 #include "dc_link_ddc.h"
36 #include "aux_engine.h"
37
38 #define AUX_POWER_UP_WA_DELAY 500
39 #define I2C_OVER_AUX_DEFER_WA_DELAY 70
40
41 /* CV smart dongle slave address for retrieving supported HDTV modes*/
42 #define CV_SMART_DONGLE_ADDRESS 0x20
43 /* DVI-HDMI dongle slave address for retrieving dongle signature*/
44 #define DVI_HDMI_DONGLE_ADDRESS 0x68
45 static const int8_t dvi_hdmi_dongle_signature_str[] = "6140063500G";
46 struct dvi_hdmi_dongle_signature_data {
47 int8_t vendor[3];/* "AMD" */
48 uint8_t version[2];
49 uint8_t size;
50 int8_t id[11];/* "6140063500G"*/
51 };
52 /* DP-HDMI dongle slave address for retrieving dongle signature*/
53 #define DP_HDMI_DONGLE_ADDRESS 0x40
54 static const uint8_t dp_hdmi_dongle_signature_str[] = "DP-HDMI ADAPTOR";
55 #define DP_HDMI_DONGLE_SIGNATURE_EOT 0x04
56
57 struct dp_hdmi_dongle_signature_data {
58 int8_t id[15];/* "DP-HDMI ADAPTOR"*/
59 uint8_t eot;/* end of transmition '\x4' */
60 };
61
62 /* SCDC Address defines (HDMI 2.0)*/
63 #define HDMI_SCDC_WRITE_UPDATE_0_ARRAY 3
64 #define HDMI_SCDC_ADDRESS 0x54
65 #define HDMI_SCDC_SINK_VERSION 0x01
66 #define HDMI_SCDC_SOURCE_VERSION 0x02
67 #define HDMI_SCDC_UPDATE_0 0x10
68 #define HDMI_SCDC_TMDS_CONFIG 0x20
69 #define HDMI_SCDC_SCRAMBLER_STATUS 0x21
70 #define HDMI_SCDC_CONFIG_0 0x30
71 #define HDMI_SCDC_STATUS_FLAGS 0x40
72 #define HDMI_SCDC_ERR_DETECT 0x50
73 #define HDMI_SCDC_TEST_CONFIG 0xC0
74
75 union hdmi_scdc_update_read_data {
76 uint8_t byte[2];
77 struct {
78 uint8_t STATUS_UPDATE:1;
79 uint8_t CED_UPDATE:1;
80 uint8_t RR_TEST:1;
81 uint8_t RESERVED:5;
82 uint8_t RESERVED2:8;
83 } fields;
84 };
85
86 union hdmi_scdc_status_flags_data {
87 uint8_t byte[2];
88 struct {
89 uint8_t CLOCK_DETECTED:1;
90 uint8_t CH0_LOCKED:1;
91 uint8_t CH1_LOCKED:1;
92 uint8_t CH2_LOCKED:1;
93 uint8_t RESERVED:4;
94 uint8_t RESERVED2:8;
95 } fields;
96 };
97
98 union hdmi_scdc_ced_data {
99 uint8_t byte[7];
100 struct {
101 uint8_t CH0_8LOW:8;
102 uint8_t CH0_7HIGH:7;
103 uint8_t CH0_VALID:1;
104 uint8_t CH1_8LOW:8;
105 uint8_t CH1_7HIGH:7;
106 uint8_t CH1_VALID:1;
107 uint8_t CH2_8LOW:8;
108 uint8_t CH2_7HIGH:7;
109 uint8_t CH2_VALID:1;
110 uint8_t CHECKSUM:8;
111 } fields;
112 };
113
114 union hdmi_scdc_test_config_Data {
115 uint8_t byte;
116 struct {
117 uint8_t TEST_READ_REQUEST_DELAY:7;
118 uint8_t TEST_READ_REQUEST: 1;
119 } fields;
120 };
121
122 struct i2c_payloads {
123 struct vector payloads;
124 };
125
126 struct aux_payloads {
127 struct vector payloads;
128 };
129
dal_ddc_i2c_payloads_create(struct dc_context * ctx,uint32_t count)130 static struct i2c_payloads *dal_ddc_i2c_payloads_create(struct dc_context *ctx, uint32_t count)
131 {
132 struct i2c_payloads *payloads;
133
134 payloads = kzalloc(sizeof(struct i2c_payloads), GFP_KERNEL);
135
136 if (!payloads)
137 return NULL;
138
139 if (dal_vector_construct(
140 &payloads->payloads, ctx, count, sizeof(struct i2c_payload)))
141 return payloads;
142
143 kfree(payloads);
144 return NULL;
145
146 }
147
dal_ddc_i2c_payloads_get(struct i2c_payloads * p)148 static struct i2c_payload *dal_ddc_i2c_payloads_get(struct i2c_payloads *p)
149 {
150 return (struct i2c_payload *)p->payloads.container;
151 }
152
dal_ddc_i2c_payloads_get_count(struct i2c_payloads * p)153 static uint32_t dal_ddc_i2c_payloads_get_count(struct i2c_payloads *p)
154 {
155 return p->payloads.count;
156 }
157
dal_ddc_i2c_payloads_destroy(struct i2c_payloads ** p)158 static void dal_ddc_i2c_payloads_destroy(struct i2c_payloads **p)
159 {
160 if (!p || !*p)
161 return;
162 dal_vector_destruct(&(*p)->payloads);
163 kfree(*p);
164 *p = NULL;
165
166 }
167
dal_ddc_aux_payloads_create(struct dc_context * ctx,uint32_t count)168 static struct aux_payloads *dal_ddc_aux_payloads_create(struct dc_context *ctx, uint32_t count)
169 {
170 struct aux_payloads *payloads;
171
172 payloads = kzalloc(sizeof(struct aux_payloads), GFP_KERNEL);
173
174 if (!payloads)
175 return NULL;
176
177 if (dal_vector_construct(
178 &payloads->payloads, ctx, count, sizeof(struct aux_payload)))
179 return payloads;
180
181 kfree(payloads);
182 return NULL;
183 }
184
dal_ddc_aux_payloads_get(struct aux_payloads * p)185 static struct aux_payload *dal_ddc_aux_payloads_get(struct aux_payloads *p)
186 {
187 return (struct aux_payload *)p->payloads.container;
188 }
189
dal_ddc_aux_payloads_get_count(struct aux_payloads * p)190 static uint32_t dal_ddc_aux_payloads_get_count(struct aux_payloads *p)
191 {
192 return p->payloads.count;
193 }
194
dal_ddc_aux_payloads_destroy(struct aux_payloads ** p)195 static void dal_ddc_aux_payloads_destroy(struct aux_payloads **p)
196 {
197 if (!p || !*p)
198 return;
199
200 dal_vector_destruct(&(*p)->payloads);
201 kfree(*p);
202 *p = NULL;
203 }
204
205 #define DDC_MIN(a, b) (((a) < (b)) ? (a) : (b))
206
dal_ddc_i2c_payloads_add(struct i2c_payloads * payloads,uint32_t address,uint32_t len,uint8_t * data,bool write)207 void dal_ddc_i2c_payloads_add(
208 struct i2c_payloads *payloads,
209 uint32_t address,
210 uint32_t len,
211 uint8_t *data,
212 bool write)
213 {
214 uint32_t payload_size = EDID_SEGMENT_SIZE;
215 uint32_t pos;
216
217 for (pos = 0; pos < len; pos += payload_size) {
218 struct i2c_payload payload = {
219 .write = write,
220 .address = address,
221 .length = DDC_MIN(payload_size, len - pos),
222 .data = data + pos };
223 dal_vector_append(&payloads->payloads, &payload);
224 }
225
226 }
227
dal_ddc_aux_payloads_add(struct aux_payloads * payloads,uint32_t address,uint32_t len,uint8_t * data,bool write)228 void dal_ddc_aux_payloads_add(
229 struct aux_payloads *payloads,
230 uint32_t address,
231 uint32_t len,
232 uint8_t *data,
233 bool write)
234 {
235 uint32_t payload_size = DEFAULT_AUX_MAX_DATA_SIZE;
236 uint32_t pos;
237
238 for (pos = 0; pos < len; pos += payload_size) {
239 struct aux_payload payload = {
240 .i2c_over_aux = true,
241 .write = write,
242 .address = address,
243 .length = DDC_MIN(payload_size, len - pos),
244 .data = data + pos };
245 dal_vector_append(&payloads->payloads, &payload);
246 }
247 }
248
construct(struct ddc_service * ddc_service,struct ddc_service_init_data * init_data)249 static void construct(
250 struct ddc_service *ddc_service,
251 struct ddc_service_init_data *init_data)
252 {
253 enum connector_id connector_id =
254 dal_graphics_object_id_get_connector_id(init_data->id);
255
256 struct gpio_service *gpio_service = init_data->ctx->gpio_service;
257 struct graphics_object_i2c_info i2c_info;
258 struct gpio_ddc_hw_info hw_info;
259 struct dc_bios *dcb = init_data->ctx->dc_bios;
260
261 ddc_service->link = init_data->link;
262 ddc_service->ctx = init_data->ctx;
263
264 if (BP_RESULT_OK != dcb->funcs->get_i2c_info(dcb, init_data->id, &i2c_info)) {
265 ddc_service->ddc_pin = NULL;
266 } else {
267 hw_info.ddc_channel = i2c_info.i2c_line;
268 hw_info.hw_supported = i2c_info.i2c_hw_assist;
269
270 ddc_service->ddc_pin = dal_gpio_create_ddc(
271 gpio_service,
272 i2c_info.gpio_info.clk_a_register_index,
273 1 << i2c_info.gpio_info.clk_a_shift,
274 &hw_info);
275 }
276
277 ddc_service->flags.EDID_QUERY_DONE_ONCE = false;
278 ddc_service->flags.FORCE_READ_REPEATED_START = false;
279 ddc_service->flags.EDID_STRESS_READ = false;
280
281 ddc_service->flags.IS_INTERNAL_DISPLAY =
282 connector_id == CONNECTOR_ID_EDP ||
283 connector_id == CONNECTOR_ID_LVDS;
284
285 ddc_service->wa.raw = 0;
286 }
287
dal_ddc_service_create(struct ddc_service_init_data * init_data)288 struct ddc_service *dal_ddc_service_create(
289 struct ddc_service_init_data *init_data)
290 {
291 struct ddc_service *ddc_service;
292
293 ddc_service = kzalloc(sizeof(struct ddc_service), GFP_KERNEL);
294
295 if (!ddc_service)
296 return NULL;
297
298 construct(ddc_service, init_data);
299 return ddc_service;
300 }
301
destruct(struct ddc_service * ddc)302 static void destruct(struct ddc_service *ddc)
303 {
304 if (ddc->ddc_pin)
305 dal_gpio_destroy_ddc(&ddc->ddc_pin);
306 }
307
dal_ddc_service_destroy(struct ddc_service ** ddc)308 void dal_ddc_service_destroy(struct ddc_service **ddc)
309 {
310 if (!ddc || !*ddc) {
311 BREAK_TO_DEBUGGER();
312 return;
313 }
314 destruct(*ddc);
315 kfree(*ddc);
316 *ddc = NULL;
317 }
318
dal_ddc_service_get_type(struct ddc_service * ddc)319 enum ddc_service_type dal_ddc_service_get_type(struct ddc_service *ddc)
320 {
321 return DDC_SERVICE_TYPE_CONNECTOR;
322 }
323
dal_ddc_service_set_transaction_type(struct ddc_service * ddc,enum ddc_transaction_type type)324 void dal_ddc_service_set_transaction_type(
325 struct ddc_service *ddc,
326 enum ddc_transaction_type type)
327 {
328 ddc->transaction_type = type;
329 }
330
dal_ddc_service_is_in_aux_transaction_mode(struct ddc_service * ddc)331 bool dal_ddc_service_is_in_aux_transaction_mode(struct ddc_service *ddc)
332 {
333 switch (ddc->transaction_type) {
334 case DDC_TRANSACTION_TYPE_I2C_OVER_AUX:
335 case DDC_TRANSACTION_TYPE_I2C_OVER_AUX_WITH_DEFER:
336 case DDC_TRANSACTION_TYPE_I2C_OVER_AUX_RETRY_DEFER:
337 return true;
338 default:
339 break;
340 }
341 return false;
342 }
343
ddc_service_set_dongle_type(struct ddc_service * ddc,enum display_dongle_type dongle_type)344 void ddc_service_set_dongle_type(struct ddc_service *ddc,
345 enum display_dongle_type dongle_type)
346 {
347 ddc->dongle_type = dongle_type;
348 }
349
defer_delay_converter_wa(struct ddc_service * ddc,uint32_t defer_delay)350 static uint32_t defer_delay_converter_wa(
351 struct ddc_service *ddc,
352 uint32_t defer_delay)
353 {
354 struct dc_link *link = ddc->link;
355
356 if (link->dpcd_caps.branch_dev_id == DP_BRANCH_DEVICE_ID_4 &&
357 !memcmp(link->dpcd_caps.branch_dev_name,
358 DP_DVI_CONVERTER_ID_4,
359 sizeof(link->dpcd_caps.branch_dev_name)))
360 return defer_delay > I2C_OVER_AUX_DEFER_WA_DELAY ?
361 defer_delay : I2C_OVER_AUX_DEFER_WA_DELAY;
362
363 return defer_delay;
364 }
365
366 #define DP_TRANSLATOR_DELAY 5
367
get_defer_delay(struct ddc_service * ddc)368 uint32_t get_defer_delay(struct ddc_service *ddc)
369 {
370 uint32_t defer_delay = 0;
371
372 switch (ddc->transaction_type) {
373 case DDC_TRANSACTION_TYPE_I2C_OVER_AUX:
374 if ((DISPLAY_DONGLE_DP_VGA_CONVERTER == ddc->dongle_type) ||
375 (DISPLAY_DONGLE_DP_DVI_CONVERTER == ddc->dongle_type) ||
376 (DISPLAY_DONGLE_DP_HDMI_CONVERTER ==
377 ddc->dongle_type)) {
378
379 defer_delay = DP_TRANSLATOR_DELAY;
380
381 defer_delay =
382 defer_delay_converter_wa(ddc, defer_delay);
383
384 } else /*sink has a delay different from an Active Converter*/
385 defer_delay = 0;
386 break;
387 case DDC_TRANSACTION_TYPE_I2C_OVER_AUX_WITH_DEFER:
388 defer_delay = DP_TRANSLATOR_DELAY;
389 break;
390 default:
391 break;
392 }
393 return defer_delay;
394 }
395
i2c_read(struct ddc_service * ddc,uint32_t address,uint8_t * buffer,uint32_t len)396 static bool i2c_read(
397 struct ddc_service *ddc,
398 uint32_t address,
399 uint8_t *buffer,
400 uint32_t len)
401 {
402 uint8_t offs_data = 0;
403 struct i2c_payload payloads[2] = {
404 {
405 .write = true,
406 .address = address,
407 .length = 1,
408 .data = &offs_data },
409 {
410 .write = false,
411 .address = address,
412 .length = len,
413 .data = buffer } };
414
415 struct i2c_command command = {
416 .payloads = payloads,
417 .number_of_payloads = 2,
418 .engine = DDC_I2C_COMMAND_ENGINE,
419 .speed = ddc->ctx->dc->caps.i2c_speed_in_khz };
420
421 return dm_helpers_submit_i2c(
422 ddc->ctx,
423 ddc->link,
424 &command);
425 }
426
dal_ddc_service_i2c_query_dp_dual_mode_adaptor(struct ddc_service * ddc,struct display_sink_capability * sink_cap)427 void dal_ddc_service_i2c_query_dp_dual_mode_adaptor(
428 struct ddc_service *ddc,
429 struct display_sink_capability *sink_cap)
430 {
431 uint8_t i;
432 bool is_valid_hdmi_signature;
433 enum display_dongle_type *dongle = &sink_cap->dongle_type;
434 uint8_t type2_dongle_buf[DP_ADAPTOR_TYPE2_SIZE];
435 bool is_type2_dongle = false;
436 struct dp_hdmi_dongle_signature_data *dongle_signature;
437
438 /* Assume we have no valid DP passive dongle connected */
439 *dongle = DISPLAY_DONGLE_NONE;
440 sink_cap->max_hdmi_pixel_clock = DP_ADAPTOR_HDMI_SAFE_MAX_TMDS_CLK;
441
442 /* Read DP-HDMI dongle I2c (no response interpreted as DP-DVI dongle)*/
443 if (!i2c_read(
444 ddc,
445 DP_HDMI_DONGLE_ADDRESS,
446 type2_dongle_buf,
447 sizeof(type2_dongle_buf))) {
448 *dongle = DISPLAY_DONGLE_DP_DVI_DONGLE;
449 sink_cap->max_hdmi_pixel_clock = DP_ADAPTOR_DVI_MAX_TMDS_CLK;
450
451 CONN_DATA_DETECT(ddc->link, type2_dongle_buf, sizeof(type2_dongle_buf),
452 "DP-DVI passive dongle %dMhz: ",
453 DP_ADAPTOR_DVI_MAX_TMDS_CLK / 1000);
454 return;
455 }
456
457 /* Check if Type 2 dongle.*/
458 if (type2_dongle_buf[DP_ADAPTOR_TYPE2_REG_ID] == DP_ADAPTOR_TYPE2_ID)
459 is_type2_dongle = true;
460
461 dongle_signature =
462 (struct dp_hdmi_dongle_signature_data *)type2_dongle_buf;
463
464 is_valid_hdmi_signature = true;
465
466 /* Check EOT */
467 if (dongle_signature->eot != DP_HDMI_DONGLE_SIGNATURE_EOT) {
468 is_valid_hdmi_signature = false;
469 }
470
471 /* Check signature */
472 for (i = 0; i < sizeof(dongle_signature->id); ++i) {
473 /* If its not the right signature,
474 * skip mismatch in subversion byte.*/
475 if (dongle_signature->id[i] !=
476 dp_hdmi_dongle_signature_str[i] && i != 3) {
477
478 if (is_type2_dongle) {
479 is_valid_hdmi_signature = false;
480 break;
481 }
482
483 }
484 }
485
486 if (is_type2_dongle) {
487 uint32_t max_tmds_clk =
488 type2_dongle_buf[DP_ADAPTOR_TYPE2_REG_MAX_TMDS_CLK];
489
490 max_tmds_clk = max_tmds_clk * 2 + max_tmds_clk / 2;
491
492 if (0 == max_tmds_clk ||
493 max_tmds_clk < DP_ADAPTOR_TYPE2_MIN_TMDS_CLK ||
494 max_tmds_clk > DP_ADAPTOR_TYPE2_MAX_TMDS_CLK) {
495 *dongle = DISPLAY_DONGLE_DP_DVI_DONGLE;
496
497 CONN_DATA_DETECT(ddc->link, type2_dongle_buf,
498 sizeof(type2_dongle_buf),
499 "DP-DVI passive dongle %dMhz: ",
500 DP_ADAPTOR_DVI_MAX_TMDS_CLK / 1000);
501 } else {
502 if (is_valid_hdmi_signature == true) {
503 *dongle = DISPLAY_DONGLE_DP_HDMI_DONGLE;
504
505 CONN_DATA_DETECT(ddc->link, type2_dongle_buf,
506 sizeof(type2_dongle_buf),
507 "Type 2 DP-HDMI passive dongle %dMhz: ",
508 max_tmds_clk);
509 } else {
510 *dongle = DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE;
511
512 CONN_DATA_DETECT(ddc->link, type2_dongle_buf,
513 sizeof(type2_dongle_buf),
514 "Type 2 DP-HDMI passive dongle (no signature) %dMhz: ",
515 max_tmds_clk);
516
517 }
518
519 /* Multiply by 1000 to convert to kHz. */
520 sink_cap->max_hdmi_pixel_clock =
521 max_tmds_clk * 1000;
522 }
523
524 } else {
525 if (is_valid_hdmi_signature == true) {
526 *dongle = DISPLAY_DONGLE_DP_HDMI_DONGLE;
527
528 CONN_DATA_DETECT(ddc->link, type2_dongle_buf,
529 sizeof(type2_dongle_buf),
530 "Type 1 DP-HDMI passive dongle %dMhz: ",
531 sink_cap->max_hdmi_pixel_clock / 1000);
532 } else {
533 *dongle = DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE;
534
535 CONN_DATA_DETECT(ddc->link, type2_dongle_buf,
536 sizeof(type2_dongle_buf),
537 "Type 1 DP-HDMI passive dongle (no signature) %dMhz: ",
538 sink_cap->max_hdmi_pixel_clock / 1000);
539 }
540 }
541
542 return;
543 }
544
545 enum {
546 DP_SINK_CAP_SIZE =
547 DP_EDP_CONFIGURATION_CAP - DP_DPCD_REV + 1
548 };
549
dal_ddc_service_query_ddc_data(struct ddc_service * ddc,uint32_t address,uint8_t * write_buf,uint32_t write_size,uint8_t * read_buf,uint32_t read_size)550 bool dal_ddc_service_query_ddc_data(
551 struct ddc_service *ddc,
552 uint32_t address,
553 uint8_t *write_buf,
554 uint32_t write_size,
555 uint8_t *read_buf,
556 uint32_t read_size)
557 {
558 bool ret;
559 uint32_t payload_size =
560 dal_ddc_service_is_in_aux_transaction_mode(ddc) ?
561 DEFAULT_AUX_MAX_DATA_SIZE : EDID_SEGMENT_SIZE;
562
563 uint32_t write_payloads =
564 (write_size + payload_size - 1) / payload_size;
565
566 uint32_t read_payloads =
567 (read_size + payload_size - 1) / payload_size;
568
569 uint32_t payloads_num = write_payloads + read_payloads;
570
571 if (write_size > EDID_SEGMENT_SIZE || read_size > EDID_SEGMENT_SIZE)
572 return false;
573
574 /*TODO: len of payload data for i2c and aux is uint8!!!!,
575 * but we want to read 256 over i2c!!!!*/
576 if (dal_ddc_service_is_in_aux_transaction_mode(ddc)) {
577
578 struct aux_payloads *payloads =
579 dal_ddc_aux_payloads_create(ddc->ctx, payloads_num);
580
581 struct aux_command command = {
582 .payloads = dal_ddc_aux_payloads_get(payloads),
583 .number_of_payloads = 0,
584 .defer_delay = get_defer_delay(ddc),
585 .max_defer_write_retry = 0 };
586
587 dal_ddc_aux_payloads_add(
588 payloads, address, write_size, write_buf, true);
589
590 dal_ddc_aux_payloads_add(
591 payloads, address, read_size, read_buf, false);
592
593 command.number_of_payloads =
594 dal_ddc_aux_payloads_get_count(payloads);
595
596 ret = dal_i2caux_submit_aux_command(
597 ddc->ctx->i2caux,
598 ddc->ddc_pin,
599 &command);
600
601 dal_ddc_aux_payloads_destroy(&payloads);
602
603 } else {
604 struct i2c_payloads *payloads =
605 dal_ddc_i2c_payloads_create(ddc->ctx, payloads_num);
606
607 struct i2c_command command = {
608 .payloads = dal_ddc_i2c_payloads_get(payloads),
609 .number_of_payloads = 0,
610 .engine = DDC_I2C_COMMAND_ENGINE,
611 .speed = ddc->ctx->dc->caps.i2c_speed_in_khz };
612
613 dal_ddc_i2c_payloads_add(
614 payloads, address, write_size, write_buf, true);
615
616 dal_ddc_i2c_payloads_add(
617 payloads, address, read_size, read_buf, false);
618
619 command.number_of_payloads =
620 dal_ddc_i2c_payloads_get_count(payloads);
621
622 ret = dm_helpers_submit_i2c(
623 ddc->ctx,
624 ddc->link,
625 &command);
626
627 dal_ddc_i2c_payloads_destroy(&payloads);
628 }
629
630 return ret;
631 }
632
dc_link_aux_transfer(struct ddc_service * ddc,unsigned int address,uint8_t * reply,void * buffer,unsigned int size,enum aux_transaction_type type,enum i2caux_transaction_action action)633 int dc_link_aux_transfer(struct ddc_service *ddc,
634 unsigned int address,
635 uint8_t *reply,
636 void *buffer,
637 unsigned int size,
638 enum aux_transaction_type type,
639 enum i2caux_transaction_action action)
640 {
641 struct ddc *ddc_pin = ddc->ddc_pin;
642 struct aux_engine *aux_engine;
643 enum aux_channel_operation_result operation_result;
644 struct aux_request_transaction_data aux_req;
645 struct aux_reply_transaction_data aux_rep;
646 uint8_t returned_bytes = 0;
647 int res = -1;
648 uint32_t status;
649
650 memset(&aux_req, 0, sizeof(aux_req));
651 memset(&aux_rep, 0, sizeof(aux_rep));
652
653 aux_engine = ddc->ctx->dc->res_pool->engines[ddc_pin->pin_data->en];
654 aux_engine->funcs->acquire(aux_engine, ddc_pin);
655
656 aux_req.type = type;
657 aux_req.action = action;
658
659 aux_req.address = address;
660 aux_req.delay = 0;
661 aux_req.length = size;
662 aux_req.data = buffer;
663
664 aux_engine->funcs->submit_channel_request(aux_engine, &aux_req);
665 operation_result = aux_engine->funcs->get_channel_status(aux_engine, &returned_bytes);
666
667 switch (operation_result) {
668 case AUX_CHANNEL_OPERATION_SUCCEEDED:
669 res = returned_bytes;
670
671 if (res <= size && res >= 0)
672 res = aux_engine->funcs->read_channel_reply(aux_engine, size,
673 buffer, reply,
674 &status);
675
676 break;
677 case AUX_CHANNEL_OPERATION_FAILED_HPD_DISCON:
678 res = 0;
679 break;
680 case AUX_CHANNEL_OPERATION_FAILED_REASON_UNKNOWN:
681 case AUX_CHANNEL_OPERATION_FAILED_INVALID_REPLY:
682 case AUX_CHANNEL_OPERATION_FAILED_TIMEOUT:
683 res = -1;
684 break;
685 }
686 aux_engine->funcs->release_engine(aux_engine);
687 return res;
688 }
689
690 /*test only function*/
dal_ddc_service_set_ddc_pin(struct ddc_service * ddc_service,struct ddc * ddc)691 void dal_ddc_service_set_ddc_pin(
692 struct ddc_service *ddc_service,
693 struct ddc *ddc)
694 {
695 ddc_service->ddc_pin = ddc;
696 }
697
dal_ddc_service_get_ddc_pin(struct ddc_service * ddc_service)698 struct ddc *dal_ddc_service_get_ddc_pin(struct ddc_service *ddc_service)
699 {
700 return ddc_service->ddc_pin;
701 }
702
dal_ddc_service_write_scdc_data(struct ddc_service * ddc_service,uint32_t pix_clk,bool lte_340_scramble)703 void dal_ddc_service_write_scdc_data(struct ddc_service *ddc_service,
704 uint32_t pix_clk,
705 bool lte_340_scramble)
706 {
707 bool over_340_mhz = pix_clk > 340000 ? 1 : 0;
708 uint8_t slave_address = HDMI_SCDC_ADDRESS;
709 uint8_t offset = HDMI_SCDC_SINK_VERSION;
710 uint8_t sink_version = 0;
711 uint8_t write_buffer[2] = {0};
712 /*Lower than 340 Scramble bit from SCDC caps*/
713
714 dal_ddc_service_query_ddc_data(ddc_service, slave_address, &offset,
715 sizeof(offset), &sink_version, sizeof(sink_version));
716 if (sink_version == 1) {
717 /*Source Version = 1*/
718 write_buffer[0] = HDMI_SCDC_SOURCE_VERSION;
719 write_buffer[1] = 1;
720 dal_ddc_service_query_ddc_data(ddc_service, slave_address,
721 write_buffer, sizeof(write_buffer), NULL, 0);
722 /*Read Request from SCDC caps*/
723 }
724 write_buffer[0] = HDMI_SCDC_TMDS_CONFIG;
725
726 if (over_340_mhz) {
727 write_buffer[1] = 3;
728 } else if (lte_340_scramble) {
729 write_buffer[1] = 1;
730 } else {
731 write_buffer[1] = 0;
732 }
733 dal_ddc_service_query_ddc_data(ddc_service, slave_address, write_buffer,
734 sizeof(write_buffer), NULL, 0);
735 }
736
dal_ddc_service_read_scdc_data(struct ddc_service * ddc_service)737 void dal_ddc_service_read_scdc_data(struct ddc_service *ddc_service)
738 {
739 uint8_t slave_address = HDMI_SCDC_ADDRESS;
740 uint8_t offset = HDMI_SCDC_TMDS_CONFIG;
741 uint8_t tmds_config = 0;
742
743 dal_ddc_service_query_ddc_data(ddc_service, slave_address, &offset,
744 sizeof(offset), &tmds_config, sizeof(tmds_config));
745 if (tmds_config & 0x1) {
746 union hdmi_scdc_status_flags_data status_data = { {0} };
747 uint8_t scramble_status = 0;
748
749 offset = HDMI_SCDC_SCRAMBLER_STATUS;
750 dal_ddc_service_query_ddc_data(ddc_service, slave_address,
751 &offset, sizeof(offset), &scramble_status,
752 sizeof(scramble_status));
753 offset = HDMI_SCDC_STATUS_FLAGS;
754 dal_ddc_service_query_ddc_data(ddc_service, slave_address,
755 &offset, sizeof(offset), status_data.byte,
756 sizeof(status_data.byte));
757 }
758 }
759
760
