1 /*
2 * Copyright 2012-15 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include <linux/slab.h>
27
28 #include "dm_services.h"
29
30 #include "include/logger_interface.h"
31
32 #include "irq_service_dce110.h"
33
34 #include "dce/dce_11_0_d.h"
35 #include "dce/dce_11_0_sh_mask.h"
36
37 #include "ivsrcid/ivsrcid_vislands30.h"
38
39 #include "dc.h"
40 #include "core_types.h"
41 #define DC_LOGGER \
42 irq_service->ctx->logger
43
hpd_ack(struct irq_service * irq_service,const struct irq_source_info * info)44 static bool hpd_ack(struct irq_service *irq_service,
45 const struct irq_source_info *info)
46 {
47 uint32_t addr = info->status_reg;
48 uint32_t value = dm_read_reg(irq_service->ctx, addr);
49 uint32_t current_status = get_reg_field_value(value,
50 DC_HPD_INT_STATUS,
51 DC_HPD_SENSE_DELAYED);
52
53 dal_irq_service_ack_generic(irq_service, info);
54
55 value = dm_read_reg(irq_service->ctx, info->enable_reg);
56
57 set_reg_field_value(value, current_status ? 0 : 1,
58 DC_HPD_INT_CONTROL,
59 DC_HPD_INT_POLARITY);
60
61 dm_write_reg(irq_service->ctx, info->enable_reg, value);
62
63 return true;
64 }
65
66 static const struct irq_source_info_funcs hpd_irq_info_funcs = {
67 .set = NULL,
68 .ack = hpd_ack
69 };
70
71 static const struct irq_source_info_funcs hpd_rx_irq_info_funcs = {
72 .set = NULL,
73 .ack = NULL
74 };
75
76 static const struct irq_source_info_funcs pflip_irq_info_funcs = {
77 .set = NULL,
78 .ack = NULL
79 };
80
81 static const struct irq_source_info_funcs vblank_irq_info_funcs = {
82 .set = dce110_vblank_set,
83 .ack = NULL
84 };
85
86 static const struct irq_source_info_funcs vupdate_irq_info_funcs = {
87 .set = NULL,
88 .ack = NULL
89 };
90
91 #define hpd_int_entry(reg_num)\
92 [DC_IRQ_SOURCE_HPD1 + reg_num] = {\
93 .enable_reg = mmHPD ## reg_num ## _DC_HPD_INT_CONTROL,\
94 .enable_mask = DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK,\
95 .enable_value = {\
96 DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK,\
97 ~DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK\
98 },\
99 .ack_reg = mmHPD ## reg_num ## _DC_HPD_INT_CONTROL,\
100 .ack_mask = DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK,\
101 .ack_value = DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK,\
102 .status_reg = mmHPD ## reg_num ## _DC_HPD_INT_STATUS,\
103 .funcs = &hpd_irq_info_funcs\
104 }
105
106 #define hpd_rx_int_entry(reg_num)\
107 [DC_IRQ_SOURCE_HPD1RX + reg_num] = {\
108 .enable_reg = mmHPD ## reg_num ## _DC_HPD_INT_CONTROL,\
109 .enable_mask = DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK,\
110 .enable_value = {\
111 DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK,\
112 ~DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK },\
113 .ack_reg = mmHPD ## reg_num ## _DC_HPD_INT_CONTROL,\
114 .ack_mask = DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK,\
115 .ack_value = DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK,\
116 .status_reg = mmHPD ## reg_num ## _DC_HPD_INT_STATUS,\
117 .funcs = &hpd_rx_irq_info_funcs\
118 }
119 #define pflip_int_entry(reg_num)\
120 [DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\
121 .enable_reg = mmDCP ## reg_num ## _GRPH_INTERRUPT_CONTROL,\
122 .enable_mask =\
123 GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK,\
124 .enable_value = {\
125 GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK,\
126 ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK},\
127 .ack_reg = mmDCP ## reg_num ## _GRPH_INTERRUPT_STATUS,\
128 .ack_mask = GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK,\
129 .ack_value = GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK,\
130 .status_reg = mmDCP ## reg_num ##_GRPH_INTERRUPT_STATUS,\
131 .funcs = &pflip_irq_info_funcs\
132 }
133
134 #define vupdate_int_entry(reg_num)\
135 [DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
136 .enable_reg = mmCRTC ## reg_num ## _CRTC_INTERRUPT_CONTROL,\
137 .enable_mask =\
138 CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK_MASK,\
139 .enable_value = {\
140 CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK_MASK,\
141 ~CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK_MASK},\
142 .ack_reg = mmCRTC ## reg_num ## _CRTC_V_UPDATE_INT_STATUS,\
143 .ack_mask =\
144 CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR_MASK,\
145 .ack_value =\
146 CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR_MASK,\
147 .funcs = &vupdate_irq_info_funcs\
148 }
149
150 #define vblank_int_entry(reg_num)\
151 [DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\
152 .enable_reg = mmCRTC ## reg_num ## _CRTC_VERTICAL_INTERRUPT0_CONTROL,\
153 .enable_mask =\
154 CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK,\
155 .enable_value = {\
156 CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK,\
157 ~CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK},\
158 .ack_reg = mmCRTC ## reg_num ## _CRTC_VERTICAL_INTERRUPT0_CONTROL,\
159 .ack_mask =\
160 CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR_MASK,\
161 .ack_value =\
162 CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR_MASK,\
163 .funcs = &vblank_irq_info_funcs,\
164 .src_id = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0 + reg_num\
165 }
166
167 #define dummy_irq_entry() \
168 {\
169 .funcs = &dummy_irq_info_funcs\
170 }
171
172 #define i2c_int_entry(reg_num) \
173 [DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry()
174
175 #define dp_sink_int_entry(reg_num) \
176 [DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry()
177
178 #define gpio_pad_int_entry(reg_num) \
179 [DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry()
180
181 #define dc_underflow_int_entry(reg_num) \
182 [DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry()
183
dal_irq_service_dummy_set(struct irq_service * irq_service,const struct irq_source_info * info,bool enable)184 bool dal_irq_service_dummy_set(struct irq_service *irq_service,
185 const struct irq_source_info *info,
186 bool enable)
187 {
188 DC_LOG_ERROR("%s: called for non-implemented irq source\n",
189 __func__);
190 return false;
191 }
192
dal_irq_service_dummy_ack(struct irq_service * irq_service,const struct irq_source_info * info)193 bool dal_irq_service_dummy_ack(struct irq_service *irq_service,
194 const struct irq_source_info *info)
195 {
196 DC_LOG_ERROR("%s: called for non-implemented irq source\n",
197 __func__);
198 return false;
199 }
200
201
dce110_vblank_set(struct irq_service * irq_service,const struct irq_source_info * info,bool enable)202 bool dce110_vblank_set(struct irq_service *irq_service,
203 const struct irq_source_info *info,
204 bool enable)
205 {
206 struct dc_context *dc_ctx = irq_service->ctx;
207 struct dc *core_dc = irq_service->ctx->dc;
208 enum dc_irq_source dal_irq_src =
209 dc_interrupt_to_irq_source(irq_service->ctx->dc,
210 info->src_id,
211 info->ext_id);
212 uint8_t pipe_offset = dal_irq_src - IRQ_TYPE_VBLANK;
213
214 struct timing_generator *tg =
215 core_dc->current_state->res_ctx.pipe_ctx[pipe_offset].stream_res.tg;
216
217 if (enable) {
218 if (!tg || !tg->funcs->arm_vert_intr(tg, 2)) {
219 DC_ERROR("Failed to get VBLANK!\n");
220 return false;
221 }
222 }
223
224 dal_irq_service_set_generic(irq_service, info, enable);
225 return true;
226 }
227
228 static const struct irq_source_info_funcs dummy_irq_info_funcs = {
229 .set = dal_irq_service_dummy_set,
230 .ack = dal_irq_service_dummy_ack
231 };
232
233 static const struct irq_source_info
234 irq_source_info_dce110[DAL_IRQ_SOURCES_NUMBER] = {
235 [DC_IRQ_SOURCE_INVALID] = dummy_irq_entry(),
236 hpd_int_entry(0),
237 hpd_int_entry(1),
238 hpd_int_entry(2),
239 hpd_int_entry(3),
240 hpd_int_entry(4),
241 hpd_int_entry(5),
242 hpd_rx_int_entry(0),
243 hpd_rx_int_entry(1),
244 hpd_rx_int_entry(2),
245 hpd_rx_int_entry(3),
246 hpd_rx_int_entry(4),
247 hpd_rx_int_entry(5),
248 i2c_int_entry(1),
249 i2c_int_entry(2),
250 i2c_int_entry(3),
251 i2c_int_entry(4),
252 i2c_int_entry(5),
253 i2c_int_entry(6),
254 dp_sink_int_entry(1),
255 dp_sink_int_entry(2),
256 dp_sink_int_entry(3),
257 dp_sink_int_entry(4),
258 dp_sink_int_entry(5),
259 dp_sink_int_entry(6),
260 [DC_IRQ_SOURCE_TIMER] = dummy_irq_entry(),
261 pflip_int_entry(0),
262 pflip_int_entry(1),
263 pflip_int_entry(2),
264 pflip_int_entry(3),
265 pflip_int_entry(4),
266 pflip_int_entry(5),
267 [DC_IRQ_SOURCE_PFLIP_UNDERLAY0] = dummy_irq_entry(),
268 gpio_pad_int_entry(0),
269 gpio_pad_int_entry(1),
270 gpio_pad_int_entry(2),
271 gpio_pad_int_entry(3),
272 gpio_pad_int_entry(4),
273 gpio_pad_int_entry(5),
274 gpio_pad_int_entry(6),
275 gpio_pad_int_entry(7),
276 gpio_pad_int_entry(8),
277 gpio_pad_int_entry(9),
278 gpio_pad_int_entry(10),
279 gpio_pad_int_entry(11),
280 gpio_pad_int_entry(12),
281 gpio_pad_int_entry(13),
282 gpio_pad_int_entry(14),
283 gpio_pad_int_entry(15),
284 gpio_pad_int_entry(16),
285 gpio_pad_int_entry(17),
286 gpio_pad_int_entry(18),
287 gpio_pad_int_entry(19),
288 gpio_pad_int_entry(20),
289 gpio_pad_int_entry(21),
290 gpio_pad_int_entry(22),
291 gpio_pad_int_entry(23),
292 gpio_pad_int_entry(24),
293 gpio_pad_int_entry(25),
294 gpio_pad_int_entry(26),
295 gpio_pad_int_entry(27),
296 gpio_pad_int_entry(28),
297 gpio_pad_int_entry(29),
298 gpio_pad_int_entry(30),
299 dc_underflow_int_entry(1),
300 dc_underflow_int_entry(2),
301 dc_underflow_int_entry(3),
302 dc_underflow_int_entry(4),
303 dc_underflow_int_entry(5),
304 dc_underflow_int_entry(6),
305 [DC_IRQ_SOURCE_DMCU_SCP] = dummy_irq_entry(),
306 [DC_IRQ_SOURCE_VBIOS_SW] = dummy_irq_entry(),
307 vupdate_int_entry(0),
308 vupdate_int_entry(1),
309 vupdate_int_entry(2),
310 vupdate_int_entry(3),
311 vupdate_int_entry(4),
312 vupdate_int_entry(5),
313 vblank_int_entry(0),
314 vblank_int_entry(1),
315 vblank_int_entry(2),
316 vblank_int_entry(3),
317 vblank_int_entry(4),
318 vblank_int_entry(5),
319
320 };
321
to_dal_irq_source_dce110(struct irq_service * irq_service,uint32_t src_id,uint32_t ext_id)322 enum dc_irq_source to_dal_irq_source_dce110(
323 struct irq_service *irq_service,
324 uint32_t src_id,
325 uint32_t ext_id)
326 {
327 switch (src_id) {
328 case VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0:
329 return DC_IRQ_SOURCE_VBLANK1;
330 case VISLANDS30_IV_SRCID_D2_VERTICAL_INTERRUPT0:
331 return DC_IRQ_SOURCE_VBLANK2;
332 case VISLANDS30_IV_SRCID_D3_VERTICAL_INTERRUPT0:
333 return DC_IRQ_SOURCE_VBLANK3;
334 case VISLANDS30_IV_SRCID_D4_VERTICAL_INTERRUPT0:
335 return DC_IRQ_SOURCE_VBLANK4;
336 case VISLANDS30_IV_SRCID_D5_VERTICAL_INTERRUPT0:
337 return DC_IRQ_SOURCE_VBLANK5;
338 case VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0:
339 return DC_IRQ_SOURCE_VBLANK6;
340 case VISLANDS30_IV_SRCID_D1_V_UPDATE_INT:
341 return DC_IRQ_SOURCE_VUPDATE1;
342 case VISLANDS30_IV_SRCID_D2_V_UPDATE_INT:
343 return DC_IRQ_SOURCE_VUPDATE2;
344 case VISLANDS30_IV_SRCID_D3_V_UPDATE_INT:
345 return DC_IRQ_SOURCE_VUPDATE3;
346 case VISLANDS30_IV_SRCID_D4_V_UPDATE_INT:
347 return DC_IRQ_SOURCE_VUPDATE4;
348 case VISLANDS30_IV_SRCID_D5_V_UPDATE_INT:
349 return DC_IRQ_SOURCE_VUPDATE5;
350 case VISLANDS30_IV_SRCID_D6_V_UPDATE_INT:
351 return DC_IRQ_SOURCE_VUPDATE6;
352 case VISLANDS30_IV_SRCID_D1_GRPH_PFLIP:
353 return DC_IRQ_SOURCE_PFLIP1;
354 case VISLANDS30_IV_SRCID_D2_GRPH_PFLIP:
355 return DC_IRQ_SOURCE_PFLIP2;
356 case VISLANDS30_IV_SRCID_D3_GRPH_PFLIP:
357 return DC_IRQ_SOURCE_PFLIP3;
358 case VISLANDS30_IV_SRCID_D4_GRPH_PFLIP:
359 return DC_IRQ_SOURCE_PFLIP4;
360 case VISLANDS30_IV_SRCID_D5_GRPH_PFLIP:
361 return DC_IRQ_SOURCE_PFLIP5;
362 case VISLANDS30_IV_SRCID_D6_GRPH_PFLIP:
363 return DC_IRQ_SOURCE_PFLIP6;
364
365 case VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A:
366 /* generic src_id for all HPD and HPDRX interrupts */
367 switch (ext_id) {
368 case VISLANDS30_IV_EXTID_HOTPLUG_DETECT_A:
369 return DC_IRQ_SOURCE_HPD1;
370 case VISLANDS30_IV_EXTID_HOTPLUG_DETECT_B:
371 return DC_IRQ_SOURCE_HPD2;
372 case VISLANDS30_IV_EXTID_HOTPLUG_DETECT_C:
373 return DC_IRQ_SOURCE_HPD3;
374 case VISLANDS30_IV_EXTID_HOTPLUG_DETECT_D:
375 return DC_IRQ_SOURCE_HPD4;
376 case VISLANDS30_IV_EXTID_HOTPLUG_DETECT_E:
377 return DC_IRQ_SOURCE_HPD5;
378 case VISLANDS30_IV_EXTID_HOTPLUG_DETECT_F:
379 return DC_IRQ_SOURCE_HPD6;
380 case VISLANDS30_IV_EXTID_HPD_RX_A:
381 return DC_IRQ_SOURCE_HPD1RX;
382 case VISLANDS30_IV_EXTID_HPD_RX_B:
383 return DC_IRQ_SOURCE_HPD2RX;
384 case VISLANDS30_IV_EXTID_HPD_RX_C:
385 return DC_IRQ_SOURCE_HPD3RX;
386 case VISLANDS30_IV_EXTID_HPD_RX_D:
387 return DC_IRQ_SOURCE_HPD4RX;
388 case VISLANDS30_IV_EXTID_HPD_RX_E:
389 return DC_IRQ_SOURCE_HPD5RX;
390 case VISLANDS30_IV_EXTID_HPD_RX_F:
391 return DC_IRQ_SOURCE_HPD6RX;
392 default:
393 return DC_IRQ_SOURCE_INVALID;
394 }
395 break;
396
397 default:
398 return DC_IRQ_SOURCE_INVALID;
399 }
400 }
401
402 static const struct irq_service_funcs irq_service_funcs_dce110 = {
403 .to_dal_irq_source = to_dal_irq_source_dce110
404 };
405
construct(struct irq_service * irq_service,struct irq_service_init_data * init_data)406 static void construct(struct irq_service *irq_service,
407 struct irq_service_init_data *init_data)
408 {
409 dal_irq_service_construct(irq_service, init_data);
410
411 irq_service->info = irq_source_info_dce110;
412 irq_service->funcs = &irq_service_funcs_dce110;
413 }
414
415 struct irq_service *
dal_irq_service_dce110_create(struct irq_service_init_data * init_data)416 dal_irq_service_dce110_create(struct irq_service_init_data *init_data)
417 {
418 struct irq_service *irq_service = kzalloc(sizeof(*irq_service),
419 GFP_KERNEL);
420
421 if (!irq_service)
422 return NULL;
423
424 construct(irq_service, init_data);
425 return irq_service;
426 }
427
