1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Copyright 2014 IBM Corp.
4 */
5
6 #include <linux/pci_regs.h>
7 #include <linux/pci_ids.h>
8 #include <linux/device.h>
9 #include <linux/module.h>
10 #include <linux/kernel.h>
11 #include <linux/slab.h>
12 #include <linux/sort.h>
13 #include <linux/pci.h>
14 #include <linux/of.h>
15 #include <linux/delay.h>
16 #include <asm/opal.h>
17 #include <asm/msi_bitmap.h>
18 #include <asm/pnv-pci.h>
19 #include <asm/io.h>
20 #include <asm/reg.h>
21
22 #include "cxl.h"
23 #include <misc/cxl.h>
24
25
26 #define CXL_PCI_VSEC_ID 0x1280
27 #define CXL_VSEC_MIN_SIZE 0x80
28
29 #define CXL_READ_VSEC_LENGTH(dev, vsec, dest) \
30 { \
31 pci_read_config_word(dev, vsec + 0x6, dest); \
32 *dest >>= 4; \
33 }
34 #define CXL_READ_VSEC_NAFUS(dev, vsec, dest) \
35 pci_read_config_byte(dev, vsec + 0x8, dest)
36
37 #define CXL_READ_VSEC_STATUS(dev, vsec, dest) \
38 pci_read_config_byte(dev, vsec + 0x9, dest)
39 #define CXL_STATUS_SECOND_PORT 0x80
40 #define CXL_STATUS_MSI_X_FULL 0x40
41 #define CXL_STATUS_MSI_X_SINGLE 0x20
42 #define CXL_STATUS_FLASH_RW 0x08
43 #define CXL_STATUS_FLASH_RO 0x04
44 #define CXL_STATUS_LOADABLE_AFU 0x02
45 #define CXL_STATUS_LOADABLE_PSL 0x01
46 /* If we see these features we won't try to use the card */
47 #define CXL_UNSUPPORTED_FEATURES \
48 (CXL_STATUS_MSI_X_FULL | CXL_STATUS_MSI_X_SINGLE)
49
50 #define CXL_READ_VSEC_MODE_CONTROL(dev, vsec, dest) \
51 pci_read_config_byte(dev, vsec + 0xa, dest)
52 #define CXL_WRITE_VSEC_MODE_CONTROL(dev, vsec, val) \
53 pci_write_config_byte(dev, vsec + 0xa, val)
54 #define CXL_VSEC_PROTOCOL_MASK 0xe0
55 #define CXL_VSEC_PROTOCOL_1024TB 0x80
56 #define CXL_VSEC_PROTOCOL_512TB 0x40
57 #define CXL_VSEC_PROTOCOL_256TB 0x20 /* Power 8/9 uses this */
58 #define CXL_VSEC_PROTOCOL_ENABLE 0x01
59
60 #define CXL_READ_VSEC_PSL_REVISION(dev, vsec, dest) \
61 pci_read_config_word(dev, vsec + 0xc, dest)
62 #define CXL_READ_VSEC_CAIA_MINOR(dev, vsec, dest) \
63 pci_read_config_byte(dev, vsec + 0xe, dest)
64 #define CXL_READ_VSEC_CAIA_MAJOR(dev, vsec, dest) \
65 pci_read_config_byte(dev, vsec + 0xf, dest)
66 #define CXL_READ_VSEC_BASE_IMAGE(dev, vsec, dest) \
67 pci_read_config_word(dev, vsec + 0x10, dest)
68
69 #define CXL_READ_VSEC_IMAGE_STATE(dev, vsec, dest) \
70 pci_read_config_byte(dev, vsec + 0x13, dest)
71 #define CXL_WRITE_VSEC_IMAGE_STATE(dev, vsec, val) \
72 pci_write_config_byte(dev, vsec + 0x13, val)
73 #define CXL_VSEC_USER_IMAGE_LOADED 0x80 /* RO */
74 #define CXL_VSEC_PERST_LOADS_IMAGE 0x20 /* RW */
75 #define CXL_VSEC_PERST_SELECT_USER 0x10 /* RW */
76
77 #define CXL_READ_VSEC_AFU_DESC_OFF(dev, vsec, dest) \
78 pci_read_config_dword(dev, vsec + 0x20, dest)
79 #define CXL_READ_VSEC_AFU_DESC_SIZE(dev, vsec, dest) \
80 pci_read_config_dword(dev, vsec + 0x24, dest)
81 #define CXL_READ_VSEC_PS_OFF(dev, vsec, dest) \
82 pci_read_config_dword(dev, vsec + 0x28, dest)
83 #define CXL_READ_VSEC_PS_SIZE(dev, vsec, dest) \
84 pci_read_config_dword(dev, vsec + 0x2c, dest)
85
86
87 /* This works a little different than the p1/p2 register accesses to make it
88 * easier to pull out individual fields */
89 #define AFUD_READ(afu, off) in_be64(afu->native->afu_desc_mmio + off)
90 #define AFUD_READ_LE(afu, off) in_le64(afu->native->afu_desc_mmio + off)
91 #define EXTRACT_PPC_BIT(val, bit) (!!(val & PPC_BIT(bit)))
92 #define EXTRACT_PPC_BITS(val, bs, be) ((val & PPC_BITMASK(bs, be)) >> PPC_BITLSHIFT(be))
93
94 #define AFUD_READ_INFO(afu) AFUD_READ(afu, 0x0)
95 #define AFUD_NUM_INTS_PER_PROC(val) EXTRACT_PPC_BITS(val, 0, 15)
96 #define AFUD_NUM_PROCS(val) EXTRACT_PPC_BITS(val, 16, 31)
97 #define AFUD_NUM_CRS(val) EXTRACT_PPC_BITS(val, 32, 47)
98 #define AFUD_MULTIMODE(val) EXTRACT_PPC_BIT(val, 48)
99 #define AFUD_PUSH_BLOCK_TRANSFER(val) EXTRACT_PPC_BIT(val, 55)
100 #define AFUD_DEDICATED_PROCESS(val) EXTRACT_PPC_BIT(val, 59)
101 #define AFUD_AFU_DIRECTED(val) EXTRACT_PPC_BIT(val, 61)
102 #define AFUD_TIME_SLICED(val) EXTRACT_PPC_BIT(val, 63)
103 #define AFUD_READ_CR(afu) AFUD_READ(afu, 0x20)
104 #define AFUD_CR_LEN(val) EXTRACT_PPC_BITS(val, 8, 63)
105 #define AFUD_READ_CR_OFF(afu) AFUD_READ(afu, 0x28)
106 #define AFUD_READ_PPPSA(afu) AFUD_READ(afu, 0x30)
107 #define AFUD_PPPSA_PP(val) EXTRACT_PPC_BIT(val, 6)
108 #define AFUD_PPPSA_PSA(val) EXTRACT_PPC_BIT(val, 7)
109 #define AFUD_PPPSA_LEN(val) EXTRACT_PPC_BITS(val, 8, 63)
110 #define AFUD_READ_PPPSA_OFF(afu) AFUD_READ(afu, 0x38)
111 #define AFUD_READ_EB(afu) AFUD_READ(afu, 0x40)
112 #define AFUD_EB_LEN(val) EXTRACT_PPC_BITS(val, 8, 63)
113 #define AFUD_READ_EB_OFF(afu) AFUD_READ(afu, 0x48)
114
115 static const struct pci_device_id cxl_pci_tbl[] = {
116 { PCI_DEVICE(PCI_VENDOR_ID_IBM, 0x0477), },
117 { PCI_DEVICE(PCI_VENDOR_ID_IBM, 0x044b), },
118 { PCI_DEVICE(PCI_VENDOR_ID_IBM, 0x04cf), },
119 { PCI_DEVICE(PCI_VENDOR_ID_IBM, 0x0601), },
120 { PCI_DEVICE(PCI_VENDOR_ID_IBM, 0x0623), },
121 { PCI_DEVICE(PCI_VENDOR_ID_IBM, 0x0628), },
122 { }
123 };
124 MODULE_DEVICE_TABLE(pci, cxl_pci_tbl);
125
126
127 /*
128 * Mostly using these wrappers to avoid confusion:
129 * priv 1 is BAR2, while priv 2 is BAR0
130 */
p1_base(struct pci_dev * dev)131 static inline resource_size_t p1_base(struct pci_dev *dev)
132 {
133 return pci_resource_start(dev, 2);
134 }
135
p1_size(struct pci_dev * dev)136 static inline resource_size_t p1_size(struct pci_dev *dev)
137 {
138 return pci_resource_len(dev, 2);
139 }
140
p2_base(struct pci_dev * dev)141 static inline resource_size_t p2_base(struct pci_dev *dev)
142 {
143 return pci_resource_start(dev, 0);
144 }
145
p2_size(struct pci_dev * dev)146 static inline resource_size_t p2_size(struct pci_dev *dev)
147 {
148 return pci_resource_len(dev, 0);
149 }
150
find_cxl_vsec(struct pci_dev * dev)151 static int find_cxl_vsec(struct pci_dev *dev)
152 {
153 return pci_find_vsec_capability(dev, PCI_VENDOR_ID_IBM, CXL_PCI_VSEC_ID);
154 }
155
dump_cxl_config_space(struct pci_dev * dev)156 static void dump_cxl_config_space(struct pci_dev *dev)
157 {
158 int vsec;
159 u32 val;
160
161 dev_info(&dev->dev, "dump_cxl_config_space\n");
162
163 pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &val);
164 dev_info(&dev->dev, "BAR0: %#.8x\n", val);
165 pci_read_config_dword(dev, PCI_BASE_ADDRESS_1, &val);
166 dev_info(&dev->dev, "BAR1: %#.8x\n", val);
167 pci_read_config_dword(dev, PCI_BASE_ADDRESS_2, &val);
168 dev_info(&dev->dev, "BAR2: %#.8x\n", val);
169 pci_read_config_dword(dev, PCI_BASE_ADDRESS_3, &val);
170 dev_info(&dev->dev, "BAR3: %#.8x\n", val);
171 pci_read_config_dword(dev, PCI_BASE_ADDRESS_4, &val);
172 dev_info(&dev->dev, "BAR4: %#.8x\n", val);
173 pci_read_config_dword(dev, PCI_BASE_ADDRESS_5, &val);
174 dev_info(&dev->dev, "BAR5: %#.8x\n", val);
175
176 dev_info(&dev->dev, "p1 regs: %#llx, len: %#llx\n",
177 p1_base(dev), p1_size(dev));
178 dev_info(&dev->dev, "p2 regs: %#llx, len: %#llx\n",
179 p2_base(dev), p2_size(dev));
180 dev_info(&dev->dev, "BAR 4/5: %#llx, len: %#llx\n",
181 pci_resource_start(dev, 4), pci_resource_len(dev, 4));
182
183 if (!(vsec = find_cxl_vsec(dev)))
184 return;
185
186 #define show_reg(name, what) \
187 dev_info(&dev->dev, "cxl vsec: %30s: %#x\n", name, what)
188
189 pci_read_config_dword(dev, vsec + 0x0, &val);
190 show_reg("Cap ID", (val >> 0) & 0xffff);
191 show_reg("Cap Ver", (val >> 16) & 0xf);
192 show_reg("Next Cap Ptr", (val >> 20) & 0xfff);
193 pci_read_config_dword(dev, vsec + 0x4, &val);
194 show_reg("VSEC ID", (val >> 0) & 0xffff);
195 show_reg("VSEC Rev", (val >> 16) & 0xf);
196 show_reg("VSEC Length", (val >> 20) & 0xfff);
197 pci_read_config_dword(dev, vsec + 0x8, &val);
198 show_reg("Num AFUs", (val >> 0) & 0xff);
199 show_reg("Status", (val >> 8) & 0xff);
200 show_reg("Mode Control", (val >> 16) & 0xff);
201 show_reg("Reserved", (val >> 24) & 0xff);
202 pci_read_config_dword(dev, vsec + 0xc, &val);
203 show_reg("PSL Rev", (val >> 0) & 0xffff);
204 show_reg("CAIA Ver", (val >> 16) & 0xffff);
205 pci_read_config_dword(dev, vsec + 0x10, &val);
206 show_reg("Base Image Rev", (val >> 0) & 0xffff);
207 show_reg("Reserved", (val >> 16) & 0x0fff);
208 show_reg("Image Control", (val >> 28) & 0x3);
209 show_reg("Reserved", (val >> 30) & 0x1);
210 show_reg("Image Loaded", (val >> 31) & 0x1);
211
212 pci_read_config_dword(dev, vsec + 0x14, &val);
213 show_reg("Reserved", val);
214 pci_read_config_dword(dev, vsec + 0x18, &val);
215 show_reg("Reserved", val);
216 pci_read_config_dword(dev, vsec + 0x1c, &val);
217 show_reg("Reserved", val);
218
219 pci_read_config_dword(dev, vsec + 0x20, &val);
220 show_reg("AFU Descriptor Offset", val);
221 pci_read_config_dword(dev, vsec + 0x24, &val);
222 show_reg("AFU Descriptor Size", val);
223 pci_read_config_dword(dev, vsec + 0x28, &val);
224 show_reg("Problem State Offset", val);
225 pci_read_config_dword(dev, vsec + 0x2c, &val);
226 show_reg("Problem State Size", val);
227
228 pci_read_config_dword(dev, vsec + 0x30, &val);
229 show_reg("Reserved", val);
230 pci_read_config_dword(dev, vsec + 0x34, &val);
231 show_reg("Reserved", val);
232 pci_read_config_dword(dev, vsec + 0x38, &val);
233 show_reg("Reserved", val);
234 pci_read_config_dword(dev, vsec + 0x3c, &val);
235 show_reg("Reserved", val);
236
237 pci_read_config_dword(dev, vsec + 0x40, &val);
238 show_reg("PSL Programming Port", val);
239 pci_read_config_dword(dev, vsec + 0x44, &val);
240 show_reg("PSL Programming Control", val);
241
242 pci_read_config_dword(dev, vsec + 0x48, &val);
243 show_reg("Reserved", val);
244 pci_read_config_dword(dev, vsec + 0x4c, &val);
245 show_reg("Reserved", val);
246
247 pci_read_config_dword(dev, vsec + 0x50, &val);
248 show_reg("Flash Address Register", val);
249 pci_read_config_dword(dev, vsec + 0x54, &val);
250 show_reg("Flash Size Register", val);
251 pci_read_config_dword(dev, vsec + 0x58, &val);
252 show_reg("Flash Status/Control Register", val);
253 pci_read_config_dword(dev, vsec + 0x58, &val);
254 show_reg("Flash Data Port", val);
255
256 #undef show_reg
257 }
258
dump_afu_descriptor(struct cxl_afu * afu)259 static void dump_afu_descriptor(struct cxl_afu *afu)
260 {
261 u64 val, afu_cr_num, afu_cr_off, afu_cr_len;
262 int i;
263
264 #define show_reg(name, what) \
265 dev_info(&afu->dev, "afu desc: %30s: %#llx\n", name, what)
266
267 val = AFUD_READ_INFO(afu);
268 show_reg("num_ints_per_process", AFUD_NUM_INTS_PER_PROC(val));
269 show_reg("num_of_processes", AFUD_NUM_PROCS(val));
270 show_reg("num_of_afu_CRs", AFUD_NUM_CRS(val));
271 show_reg("req_prog_mode", val & 0xffffULL);
272 afu_cr_num = AFUD_NUM_CRS(val);
273
274 val = AFUD_READ(afu, 0x8);
275 show_reg("Reserved", val);
276 val = AFUD_READ(afu, 0x10);
277 show_reg("Reserved", val);
278 val = AFUD_READ(afu, 0x18);
279 show_reg("Reserved", val);
280
281 val = AFUD_READ_CR(afu);
282 show_reg("Reserved", (val >> (63-7)) & 0xff);
283 show_reg("AFU_CR_len", AFUD_CR_LEN(val));
284 afu_cr_len = AFUD_CR_LEN(val) * 256;
285
286 val = AFUD_READ_CR_OFF(afu);
287 afu_cr_off = val;
288 show_reg("AFU_CR_offset", val);
289
290 val = AFUD_READ_PPPSA(afu);
291 show_reg("PerProcessPSA_control", (val >> (63-7)) & 0xff);
292 show_reg("PerProcessPSA Length", AFUD_PPPSA_LEN(val));
293
294 val = AFUD_READ_PPPSA_OFF(afu);
295 show_reg("PerProcessPSA_offset", val);
296
297 val = AFUD_READ_EB(afu);
298 show_reg("Reserved", (val >> (63-7)) & 0xff);
299 show_reg("AFU_EB_len", AFUD_EB_LEN(val));
300
301 val = AFUD_READ_EB_OFF(afu);
302 show_reg("AFU_EB_offset", val);
303
304 for (i = 0; i < afu_cr_num; i++) {
305 val = AFUD_READ_LE(afu, afu_cr_off + i * afu_cr_len);
306 show_reg("CR Vendor", val & 0xffff);
307 show_reg("CR Device", (val >> 16) & 0xffff);
308 }
309 #undef show_reg
310 }
311
312 #define P8_CAPP_UNIT0_ID 0xBA
313 #define P8_CAPP_UNIT1_ID 0XBE
314 #define P9_CAPP_UNIT0_ID 0xC0
315 #define P9_CAPP_UNIT1_ID 0xE0
316
get_phb_index(struct device_node * np,u32 * phb_index)317 static int get_phb_index(struct device_node *np, u32 *phb_index)
318 {
319 if (of_property_read_u32(np, "ibm,phb-index", phb_index))
320 return -ENODEV;
321 return 0;
322 }
323
get_capp_unit_id(struct device_node * np,u32 phb_index)324 static u64 get_capp_unit_id(struct device_node *np, u32 phb_index)
325 {
326 /*
327 * POWER 8:
328 * - For chips other than POWER8NVL, we only have CAPP 0,
329 * irrespective of which PHB is used.
330 * - For POWER8NVL, assume CAPP 0 is attached to PHB0 and
331 * CAPP 1 is attached to PHB1.
332 */
333 if (cxl_is_power8()) {
334 if (!pvr_version_is(PVR_POWER8NVL))
335 return P8_CAPP_UNIT0_ID;
336
337 if (phb_index == 0)
338 return P8_CAPP_UNIT0_ID;
339
340 if (phb_index == 1)
341 return P8_CAPP_UNIT1_ID;
342 }
343
344 /*
345 * POWER 9:
346 * PEC0 (PHB0). Capp ID = CAPP0 (0b1100_0000)
347 * PEC1 (PHB1 - PHB2). No capi mode
348 * PEC2 (PHB3 - PHB4 - PHB5): Capi mode on PHB3 only. Capp ID = CAPP1 (0b1110_0000)
349 */
350 if (cxl_is_power9()) {
351 if (phb_index == 0)
352 return P9_CAPP_UNIT0_ID;
353
354 if (phb_index == 3)
355 return P9_CAPP_UNIT1_ID;
356 }
357
358 return 0;
359 }
360
cxl_calc_capp_routing(struct pci_dev * dev,u64 * chipid,u32 * phb_index,u64 * capp_unit_id)361 int cxl_calc_capp_routing(struct pci_dev *dev, u64 *chipid,
362 u32 *phb_index, u64 *capp_unit_id)
363 {
364 int rc;
365 struct device_node *np;
366 const __be32 *prop;
367
368 if (!(np = pnv_pci_get_phb_node(dev)))
369 return -ENODEV;
370
371 while (np && !(prop = of_get_property(np, "ibm,chip-id", NULL)))
372 np = of_get_next_parent(np);
373 if (!np)
374 return -ENODEV;
375
376 *chipid = be32_to_cpup(prop);
377
378 rc = get_phb_index(np, phb_index);
379 if (rc) {
380 pr_err("cxl: invalid phb index\n");
381 of_node_put(np);
382 return rc;
383 }
384
385 *capp_unit_id = get_capp_unit_id(np, *phb_index);
386 of_node_put(np);
387 if (!*capp_unit_id) {
388 pr_err("cxl: No capp unit found for PHB[%lld,%d]. Make sure the adapter is on a capi-compatible slot\n",
389 *chipid, *phb_index);
390 return -ENODEV;
391 }
392
393 return 0;
394 }
395
396 static DEFINE_MUTEX(indications_mutex);
397
get_phb_indications(struct pci_dev * dev,u64 * capiind,u64 * asnind,u64 * nbwind)398 static int get_phb_indications(struct pci_dev *dev, u64 *capiind, u64 *asnind,
399 u64 *nbwind)
400 {
401 static u64 nbw, asn, capi = 0;
402 struct device_node *np;
403 const __be32 *prop;
404
405 mutex_lock(&indications_mutex);
406 if (!capi) {
407 if (!(np = pnv_pci_get_phb_node(dev))) {
408 mutex_unlock(&indications_mutex);
409 return -ENODEV;
410 }
411
412 prop = of_get_property(np, "ibm,phb-indications", NULL);
413 if (!prop) {
414 nbw = 0x0300UL; /* legacy values */
415 asn = 0x0400UL;
416 capi = 0x0200UL;
417 } else {
418 nbw = (u64)be32_to_cpu(prop[2]);
419 asn = (u64)be32_to_cpu(prop[1]);
420 capi = (u64)be32_to_cpu(prop[0]);
421 }
422 of_node_put(np);
423 }
424 *capiind = capi;
425 *asnind = asn;
426 *nbwind = nbw;
427 mutex_unlock(&indications_mutex);
428 return 0;
429 }
430
cxl_get_xsl9_dsnctl(struct pci_dev * dev,u64 capp_unit_id,u64 * reg)431 int cxl_get_xsl9_dsnctl(struct pci_dev *dev, u64 capp_unit_id, u64 *reg)
432 {
433 u64 xsl_dsnctl;
434 u64 capiind, asnind, nbwind;
435
436 /*
437 * CAPI Identifier bits [0:7]
438 * bit 61:60 MSI bits --> 0
439 * bit 59 TVT selector --> 0
440 */
441 if (get_phb_indications(dev, &capiind, &asnind, &nbwind))
442 return -ENODEV;
443
444 /*
445 * Tell XSL where to route data to.
446 * The field chipid should match the PHB CAPI_CMPM register
447 */
448 xsl_dsnctl = (capiind << (63-15)); /* Bit 57 */
449 xsl_dsnctl |= (capp_unit_id << (63-15));
450
451 /* nMMU_ID Defaults to: b’000001001’*/
452 xsl_dsnctl |= ((u64)0x09 << (63-28));
453
454 /*
455 * Used to identify CAPI packets which should be sorted into
456 * the Non-Blocking queues by the PHB. This field should match
457 * the PHB PBL_NBW_CMPM register
458 * nbwind=0x03, bits [57:58], must include capi indicator.
459 * Not supported on P9 DD1.
460 */
461 xsl_dsnctl |= (nbwind << (63-55));
462
463 /*
464 * Upper 16b address bits of ASB_Notify messages sent to the
465 * system. Need to match the PHB’s ASN Compare/Mask Register.
466 * Not supported on P9 DD1.
467 */
468 xsl_dsnctl |= asnind;
469
470 *reg = xsl_dsnctl;
471 return 0;
472 }
473
init_implementation_adapter_regs_psl9(struct cxl * adapter,struct pci_dev * dev)474 static int init_implementation_adapter_regs_psl9(struct cxl *adapter,
475 struct pci_dev *dev)
476 {
477 u64 xsl_dsnctl, psl_fircntl;
478 u64 chipid;
479 u32 phb_index;
480 u64 capp_unit_id;
481 u64 psl_debug;
482 int rc;
483
484 rc = cxl_calc_capp_routing(dev, &chipid, &phb_index, &capp_unit_id);
485 if (rc)
486 return rc;
487
488 rc = cxl_get_xsl9_dsnctl(dev, capp_unit_id, &xsl_dsnctl);
489 if (rc)
490 return rc;
491
492 cxl_p1_write(adapter, CXL_XSL9_DSNCTL, xsl_dsnctl);
493
494 /* Set fir_cntl to recommended value for production env */
495 psl_fircntl = (0x2ULL << (63-3)); /* ce_report */
496 psl_fircntl |= (0x1ULL << (63-6)); /* FIR_report */
497 psl_fircntl |= 0x1ULL; /* ce_thresh */
498 cxl_p1_write(adapter, CXL_PSL9_FIR_CNTL, psl_fircntl);
499
500 /* Setup the PSL to transmit packets on the PCIe before the
501 * CAPP is enabled. Make sure that CAPP virtual machines are disabled
502 */
503 cxl_p1_write(adapter, CXL_PSL9_DSNDCTL, 0x0001001000012A10ULL);
504
505 /*
506 * A response to an ASB_Notify request is returned by the
507 * system as an MMIO write to the address defined in
508 * the PSL_TNR_ADDR register.
509 * keep the Reset Value: 0x00020000E0000000
510 */
511
512 /* Enable XSL rty limit */
513 cxl_p1_write(adapter, CXL_XSL9_DEF, 0x51F8000000000005ULL);
514
515 /* Change XSL_INV dummy read threshold */
516 cxl_p1_write(adapter, CXL_XSL9_INV, 0x0000040007FFC200ULL);
517
518 if (phb_index == 3) {
519 /* disable machines 31-47 and 20-27 for DMA */
520 cxl_p1_write(adapter, CXL_PSL9_APCDEDTYPE, 0x40000FF3FFFF0000ULL);
521 }
522
523 /* Snoop machines */
524 cxl_p1_write(adapter, CXL_PSL9_APCDEDALLOC, 0x800F000200000000ULL);
525
526 /* Enable NORST and DD2 features */
527 cxl_p1_write(adapter, CXL_PSL9_DEBUG, 0xC000000000000000ULL);
528
529 /*
530 * Check if PSL has data-cache. We need to flush adapter datacache
531 * when as its about to be removed.
532 */
533 psl_debug = cxl_p1_read(adapter, CXL_PSL9_DEBUG);
534 if (psl_debug & CXL_PSL_DEBUG_CDC) {
535 dev_dbg(&dev->dev, "No data-cache present\n");
536 adapter->native->no_data_cache = true;
537 }
538
539 return 0;
540 }
541
init_implementation_adapter_regs_psl8(struct cxl * adapter,struct pci_dev * dev)542 static int init_implementation_adapter_regs_psl8(struct cxl *adapter, struct pci_dev *dev)
543 {
544 u64 psl_dsnctl, psl_fircntl;
545 u64 chipid;
546 u32 phb_index;
547 u64 capp_unit_id;
548 int rc;
549
550 rc = cxl_calc_capp_routing(dev, &chipid, &phb_index, &capp_unit_id);
551 if (rc)
552 return rc;
553
554 psl_dsnctl = 0x0000900000000000ULL; /* pteupd ttype, scdone */
555 psl_dsnctl |= (0x2ULL << (63-38)); /* MMIO hang pulse: 256 us */
556 /* Tell PSL where to route data to */
557 psl_dsnctl |= (chipid << (63-5));
558 psl_dsnctl |= (capp_unit_id << (63-13));
559
560 cxl_p1_write(adapter, CXL_PSL_DSNDCTL, psl_dsnctl);
561 cxl_p1_write(adapter, CXL_PSL_RESLCKTO, 0x20000000200ULL);
562 /* snoop write mask */
563 cxl_p1_write(adapter, CXL_PSL_SNWRALLOC, 0x00000000FFFFFFFFULL);
564 /* set fir_cntl to recommended value for production env */
565 psl_fircntl = (0x2ULL << (63-3)); /* ce_report */
566 psl_fircntl |= (0x1ULL << (63-6)); /* FIR_report */
567 psl_fircntl |= 0x1ULL; /* ce_thresh */
568 cxl_p1_write(adapter, CXL_PSL_FIR_CNTL, psl_fircntl);
569 /* for debugging with trace arrays */
570 cxl_p1_write(adapter, CXL_PSL_TRACE, 0x0000FF7C00000000ULL);
571
572 return 0;
573 }
574
575 /* PSL */
576 #define TBSYNC_CAL(n) (((u64)n & 0x7) << (63-3))
577 #define TBSYNC_CNT(n) (((u64)n & 0x7) << (63-6))
578 /* For the PSL this is a multiple for 0 < n <= 7: */
579 #define PSL_2048_250MHZ_CYCLES 1
580
write_timebase_ctrl_psl8(struct cxl * adapter)581 static void write_timebase_ctrl_psl8(struct cxl *adapter)
582 {
583 cxl_p1_write(adapter, CXL_PSL_TB_CTLSTAT,
584 TBSYNC_CNT(2 * PSL_2048_250MHZ_CYCLES));
585 }
586
timebase_read_psl9(struct cxl * adapter)587 static u64 timebase_read_psl9(struct cxl *adapter)
588 {
589 return cxl_p1_read(adapter, CXL_PSL9_Timebase);
590 }
591
timebase_read_psl8(struct cxl * adapter)592 static u64 timebase_read_psl8(struct cxl *adapter)
593 {
594 return cxl_p1_read(adapter, CXL_PSL_Timebase);
595 }
596
cxl_setup_psl_timebase(struct cxl * adapter,struct pci_dev * dev)597 static void cxl_setup_psl_timebase(struct cxl *adapter, struct pci_dev *dev)
598 {
599 struct device_node *np;
600
601 adapter->psl_timebase_synced = false;
602
603 if (!(np = pnv_pci_get_phb_node(dev)))
604 return;
605
606 /* Do not fail when CAPP timebase sync is not supported by OPAL */
607 of_node_get(np);
608 if (! of_get_property(np, "ibm,capp-timebase-sync", NULL)) {
609 of_node_put(np);
610 dev_info(&dev->dev, "PSL timebase inactive: OPAL support missing\n");
611 return;
612 }
613 of_node_put(np);
614
615 /*
616 * Setup PSL Timebase Control and Status register
617 * with the recommended Timebase Sync Count value
618 */
619 if (adapter->native->sl_ops->write_timebase_ctrl)
620 adapter->native->sl_ops->write_timebase_ctrl(adapter);
621
622 /* Enable PSL Timebase */
623 cxl_p1_write(adapter, CXL_PSL_Control, 0x0000000000000000);
624 cxl_p1_write(adapter, CXL_PSL_Control, CXL_PSL_Control_tb);
625
626 return;
627 }
628
init_implementation_afu_regs_psl9(struct cxl_afu * afu)629 static int init_implementation_afu_regs_psl9(struct cxl_afu *afu)
630 {
631 return 0;
632 }
633
init_implementation_afu_regs_psl8(struct cxl_afu * afu)634 static int init_implementation_afu_regs_psl8(struct cxl_afu *afu)
635 {
636 /* read/write masks for this slice */
637 cxl_p1n_write(afu, CXL_PSL_APCALLOC_A, 0xFFFFFFFEFEFEFEFEULL);
638 /* APC read/write masks for this slice */
639 cxl_p1n_write(afu, CXL_PSL_COALLOC_A, 0xFF000000FEFEFEFEULL);
640 /* for debugging with trace arrays */
641 cxl_p1n_write(afu, CXL_PSL_SLICE_TRACE, 0x0000FFFF00000000ULL);
642 cxl_p1n_write(afu, CXL_PSL_RXCTL_A, CXL_PSL_RXCTL_AFUHP_4S);
643
644 return 0;
645 }
646
cxl_pci_setup_irq(struct cxl * adapter,unsigned int hwirq,unsigned int virq)647 int cxl_pci_setup_irq(struct cxl *adapter, unsigned int hwirq,
648 unsigned int virq)
649 {
650 struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
651
652 return pnv_cxl_ioda_msi_setup(dev, hwirq, virq);
653 }
654
cxl_update_image_control(struct cxl * adapter)655 int cxl_update_image_control(struct cxl *adapter)
656 {
657 struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
658 int rc;
659 int vsec;
660 u8 image_state;
661
662 if (!(vsec = find_cxl_vsec(dev))) {
663 dev_err(&dev->dev, "ABORTING: CXL VSEC not found!\n");
664 return -ENODEV;
665 }
666
667 if ((rc = CXL_READ_VSEC_IMAGE_STATE(dev, vsec, &image_state))) {
668 dev_err(&dev->dev, "failed to read image state: %i\n", rc);
669 return rc;
670 }
671
672 if (adapter->perst_loads_image)
673 image_state |= CXL_VSEC_PERST_LOADS_IMAGE;
674 else
675 image_state &= ~CXL_VSEC_PERST_LOADS_IMAGE;
676
677 if (adapter->perst_select_user)
678 image_state |= CXL_VSEC_PERST_SELECT_USER;
679 else
680 image_state &= ~CXL_VSEC_PERST_SELECT_USER;
681
682 if ((rc = CXL_WRITE_VSEC_IMAGE_STATE(dev, vsec, image_state))) {
683 dev_err(&dev->dev, "failed to update image control: %i\n", rc);
684 return rc;
685 }
686
687 return 0;
688 }
689
cxl_pci_alloc_one_irq(struct cxl * adapter)690 int cxl_pci_alloc_one_irq(struct cxl *adapter)
691 {
692 struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
693
694 return pnv_cxl_alloc_hwirqs(dev, 1);
695 }
696
cxl_pci_release_one_irq(struct cxl * adapter,int hwirq)697 void cxl_pci_release_one_irq(struct cxl *adapter, int hwirq)
698 {
699 struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
700
701 return pnv_cxl_release_hwirqs(dev, hwirq, 1);
702 }
703
cxl_pci_alloc_irq_ranges(struct cxl_irq_ranges * irqs,struct cxl * adapter,unsigned int num)704 int cxl_pci_alloc_irq_ranges(struct cxl_irq_ranges *irqs,
705 struct cxl *adapter, unsigned int num)
706 {
707 struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
708
709 return pnv_cxl_alloc_hwirq_ranges(irqs, dev, num);
710 }
711
cxl_pci_release_irq_ranges(struct cxl_irq_ranges * irqs,struct cxl * adapter)712 void cxl_pci_release_irq_ranges(struct cxl_irq_ranges *irqs,
713 struct cxl *adapter)
714 {
715 struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
716
717 pnv_cxl_release_hwirq_ranges(irqs, dev);
718 }
719
setup_cxl_bars(struct pci_dev * dev)720 static int setup_cxl_bars(struct pci_dev *dev)
721 {
722 /* Safety check in case we get backported to < 3.17 without M64 */
723 if ((p1_base(dev) < 0x100000000ULL) ||
724 (p2_base(dev) < 0x100000000ULL)) {
725 dev_err(&dev->dev, "ABORTING: M32 BAR assignment incompatible with CXL\n");
726 return -ENODEV;
727 }
728
729 /*
730 * BAR 4/5 has a special meaning for CXL and must be programmed with a
731 * special value corresponding to the CXL protocol address range.
732 * For POWER 8/9 that means bits 48:49 must be set to 10
733 */
734 pci_write_config_dword(dev, PCI_BASE_ADDRESS_4, 0x00000000);
735 pci_write_config_dword(dev, PCI_BASE_ADDRESS_5, 0x00020000);
736
737 return 0;
738 }
739
740 /* pciex node: ibm,opal-m64-window = <0x3d058 0x0 0x3d058 0x0 0x8 0x0>; */
switch_card_to_cxl(struct pci_dev * dev)741 static int switch_card_to_cxl(struct pci_dev *dev)
742 {
743 int vsec;
744 u8 val;
745 int rc;
746
747 dev_info(&dev->dev, "switch card to CXL\n");
748
749 if (!(vsec = find_cxl_vsec(dev))) {
750 dev_err(&dev->dev, "ABORTING: CXL VSEC not found!\n");
751 return -ENODEV;
752 }
753
754 if ((rc = CXL_READ_VSEC_MODE_CONTROL(dev, vsec, &val))) {
755 dev_err(&dev->dev, "failed to read current mode control: %i", rc);
756 return rc;
757 }
758 val &= ~CXL_VSEC_PROTOCOL_MASK;
759 val |= CXL_VSEC_PROTOCOL_256TB | CXL_VSEC_PROTOCOL_ENABLE;
760 if ((rc = CXL_WRITE_VSEC_MODE_CONTROL(dev, vsec, val))) {
761 dev_err(&dev->dev, "failed to enable CXL protocol: %i", rc);
762 return rc;
763 }
764 /*
765 * The CAIA spec (v0.12 11.6 Bi-modal Device Support) states
766 * we must wait 100ms after this mode switch before touching
767 * PCIe config space.
768 */
769 msleep(100);
770
771 return 0;
772 }
773
pci_map_slice_regs(struct cxl_afu * afu,struct cxl * adapter,struct pci_dev * dev)774 static int pci_map_slice_regs(struct cxl_afu *afu, struct cxl *adapter, struct pci_dev *dev)
775 {
776 u64 p1n_base, p2n_base, afu_desc;
777 const u64 p1n_size = 0x100;
778 const u64 p2n_size = 0x1000;
779
780 p1n_base = p1_base(dev) + 0x10000 + (afu->slice * p1n_size);
781 p2n_base = p2_base(dev) + (afu->slice * p2n_size);
782 afu->psn_phys = p2_base(dev) + (adapter->native->ps_off + (afu->slice * adapter->ps_size));
783 afu_desc = p2_base(dev) + adapter->native->afu_desc_off + (afu->slice * adapter->native->afu_desc_size);
784
785 if (!(afu->native->p1n_mmio = ioremap(p1n_base, p1n_size)))
786 goto err;
787 if (!(afu->p2n_mmio = ioremap(p2n_base, p2n_size)))
788 goto err1;
789 if (afu_desc) {
790 if (!(afu->native->afu_desc_mmio = ioremap(afu_desc, adapter->native->afu_desc_size)))
791 goto err2;
792 }
793
794 return 0;
795 err2:
796 iounmap(afu->p2n_mmio);
797 err1:
798 iounmap(afu->native->p1n_mmio);
799 err:
800 dev_err(&afu->dev, "Error mapping AFU MMIO regions\n");
801 return -ENOMEM;
802 }
803
pci_unmap_slice_regs(struct cxl_afu * afu)804 static void pci_unmap_slice_regs(struct cxl_afu *afu)
805 {
806 if (afu->p2n_mmio) {
807 iounmap(afu->p2n_mmio);
808 afu->p2n_mmio = NULL;
809 }
810 if (afu->native->p1n_mmio) {
811 iounmap(afu->native->p1n_mmio);
812 afu->native->p1n_mmio = NULL;
813 }
814 if (afu->native->afu_desc_mmio) {
815 iounmap(afu->native->afu_desc_mmio);
816 afu->native->afu_desc_mmio = NULL;
817 }
818 }
819
cxl_pci_release_afu(struct device * dev)820 void cxl_pci_release_afu(struct device *dev)
821 {
822 struct cxl_afu *afu = to_cxl_afu(dev);
823
824 pr_devel("%s\n", __func__);
825
826 idr_destroy(&afu->contexts_idr);
827 cxl_release_spa(afu);
828
829 kfree(afu->native);
830 kfree(afu);
831 }
832
833 /* Expects AFU struct to have recently been zeroed out */
cxl_read_afu_descriptor(struct cxl_afu * afu)834 static int cxl_read_afu_descriptor(struct cxl_afu *afu)
835 {
836 u64 val;
837
838 val = AFUD_READ_INFO(afu);
839 afu->pp_irqs = AFUD_NUM_INTS_PER_PROC(val);
840 afu->max_procs_virtualised = AFUD_NUM_PROCS(val);
841 afu->crs_num = AFUD_NUM_CRS(val);
842
843 if (AFUD_AFU_DIRECTED(val))
844 afu->modes_supported |= CXL_MODE_DIRECTED;
845 if (AFUD_DEDICATED_PROCESS(val))
846 afu->modes_supported |= CXL_MODE_DEDICATED;
847 if (AFUD_TIME_SLICED(val))
848 afu->modes_supported |= CXL_MODE_TIME_SLICED;
849
850 val = AFUD_READ_PPPSA(afu);
851 afu->pp_size = AFUD_PPPSA_LEN(val) * 4096;
852 afu->psa = AFUD_PPPSA_PSA(val);
853 if ((afu->pp_psa = AFUD_PPPSA_PP(val)))
854 afu->native->pp_offset = AFUD_READ_PPPSA_OFF(afu);
855
856 val = AFUD_READ_CR(afu);
857 afu->crs_len = AFUD_CR_LEN(val) * 256;
858 afu->crs_offset = AFUD_READ_CR_OFF(afu);
859
860
861 /* eb_len is in multiple of 4K */
862 afu->eb_len = AFUD_EB_LEN(AFUD_READ_EB(afu)) * 4096;
863 afu->eb_offset = AFUD_READ_EB_OFF(afu);
864
865 /* eb_off is 4K aligned so lower 12 bits are always zero */
866 if (EXTRACT_PPC_BITS(afu->eb_offset, 0, 11) != 0) {
867 dev_warn(&afu->dev,
868 "Invalid AFU error buffer offset %Lx\n",
869 afu->eb_offset);
870 dev_info(&afu->dev,
871 "Ignoring AFU error buffer in the descriptor\n");
872 /* indicate that no afu buffer exists */
873 afu->eb_len = 0;
874 }
875
876 return 0;
877 }
878
cxl_afu_descriptor_looks_ok(struct cxl_afu * afu)879 static int cxl_afu_descriptor_looks_ok(struct cxl_afu *afu)
880 {
881 int i, rc;
882 u32 val;
883
884 if (afu->psa && afu->adapter->ps_size <
885 (afu->native->pp_offset + afu->pp_size*afu->max_procs_virtualised)) {
886 dev_err(&afu->dev, "per-process PSA can't fit inside the PSA!\n");
887 return -ENODEV;
888 }
889
890 if (afu->pp_psa && (afu->pp_size < PAGE_SIZE))
891 dev_warn(&afu->dev, "AFU uses pp_size(%#016llx) < PAGE_SIZE per-process PSA!\n", afu->pp_size);
892
893 for (i = 0; i < afu->crs_num; i++) {
894 rc = cxl_ops->afu_cr_read32(afu, i, 0, &val);
895 if (rc || val == 0) {
896 dev_err(&afu->dev, "ABORTING: AFU configuration record %i is invalid\n", i);
897 return -EINVAL;
898 }
899 }
900
901 if ((afu->modes_supported & ~CXL_MODE_DEDICATED) && afu->max_procs_virtualised == 0) {
902 /*
903 * We could also check this for the dedicated process model
904 * since the architecture indicates it should be set to 1, but
905 * in that case we ignore the value and I'd rather not risk
906 * breaking any existing dedicated process AFUs that left it as
907 * 0 (not that I'm aware of any). It is clearly an error for an
908 * AFU directed AFU to set this to 0, and would have previously
909 * triggered a bug resulting in the maximum not being enforced
910 * at all since idr_alloc treats 0 as no maximum.
911 */
912 dev_err(&afu->dev, "AFU does not support any processes\n");
913 return -EINVAL;
914 }
915
916 return 0;
917 }
918
sanitise_afu_regs_psl9(struct cxl_afu * afu)919 static int sanitise_afu_regs_psl9(struct cxl_afu *afu)
920 {
921 u64 reg;
922
923 /*
924 * Clear out any regs that contain either an IVTE or address or may be
925 * waiting on an acknowledgment to try to be a bit safer as we bring
926 * it online
927 */
928 reg = cxl_p2n_read(afu, CXL_AFU_Cntl_An);
929 if ((reg & CXL_AFU_Cntl_An_ES_MASK) != CXL_AFU_Cntl_An_ES_Disabled) {
930 dev_warn(&afu->dev, "WARNING: AFU was not disabled: %#016llx\n", reg);
931 if (cxl_ops->afu_reset(afu))
932 return -EIO;
933 if (cxl_afu_disable(afu))
934 return -EIO;
935 if (cxl_psl_purge(afu))
936 return -EIO;
937 }
938 cxl_p1n_write(afu, CXL_PSL_SPAP_An, 0x0000000000000000);
939 cxl_p1n_write(afu, CXL_PSL_AMBAR_An, 0x0000000000000000);
940 reg = cxl_p2n_read(afu, CXL_PSL_DSISR_An);
941 if (reg) {
942 dev_warn(&afu->dev, "AFU had pending DSISR: %#016llx\n", reg);
943 if (reg & CXL_PSL9_DSISR_An_TF)
944 cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_AE);
945 else
946 cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_A);
947 }
948 if (afu->adapter->native->sl_ops->register_serr_irq) {
949 reg = cxl_p1n_read(afu, CXL_PSL_SERR_An);
950 if (reg) {
951 if (reg & ~0x000000007fffffff)
952 dev_warn(&afu->dev, "AFU had pending SERR: %#016llx\n", reg);
953 cxl_p1n_write(afu, CXL_PSL_SERR_An, reg & ~0xffff);
954 }
955 }
956 reg = cxl_p2n_read(afu, CXL_PSL_ErrStat_An);
957 if (reg) {
958 dev_warn(&afu->dev, "AFU had pending error status: %#016llx\n", reg);
959 cxl_p2n_write(afu, CXL_PSL_ErrStat_An, reg);
960 }
961
962 return 0;
963 }
964
sanitise_afu_regs_psl8(struct cxl_afu * afu)965 static int sanitise_afu_regs_psl8(struct cxl_afu *afu)
966 {
967 u64 reg;
968
969 /*
970 * Clear out any regs that contain either an IVTE or address or may be
971 * waiting on an acknowledgement to try to be a bit safer as we bring
972 * it online
973 */
974 reg = cxl_p2n_read(afu, CXL_AFU_Cntl_An);
975 if ((reg & CXL_AFU_Cntl_An_ES_MASK) != CXL_AFU_Cntl_An_ES_Disabled) {
976 dev_warn(&afu->dev, "WARNING: AFU was not disabled: %#016llx\n", reg);
977 if (cxl_ops->afu_reset(afu))
978 return -EIO;
979 if (cxl_afu_disable(afu))
980 return -EIO;
981 if (cxl_psl_purge(afu))
982 return -EIO;
983 }
984 cxl_p1n_write(afu, CXL_PSL_SPAP_An, 0x0000000000000000);
985 cxl_p1n_write(afu, CXL_PSL_IVTE_Limit_An, 0x0000000000000000);
986 cxl_p1n_write(afu, CXL_PSL_IVTE_Offset_An, 0x0000000000000000);
987 cxl_p1n_write(afu, CXL_PSL_AMBAR_An, 0x0000000000000000);
988 cxl_p1n_write(afu, CXL_PSL_SPOffset_An, 0x0000000000000000);
989 cxl_p1n_write(afu, CXL_HAURP_An, 0x0000000000000000);
990 cxl_p2n_write(afu, CXL_CSRP_An, 0x0000000000000000);
991 cxl_p2n_write(afu, CXL_AURP1_An, 0x0000000000000000);
992 cxl_p2n_write(afu, CXL_AURP0_An, 0x0000000000000000);
993 cxl_p2n_write(afu, CXL_SSTP1_An, 0x0000000000000000);
994 cxl_p2n_write(afu, CXL_SSTP0_An, 0x0000000000000000);
995 reg = cxl_p2n_read(afu, CXL_PSL_DSISR_An);
996 if (reg) {
997 dev_warn(&afu->dev, "AFU had pending DSISR: %#016llx\n", reg);
998 if (reg & CXL_PSL_DSISR_TRANS)
999 cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_AE);
1000 else
1001 cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_A);
1002 }
1003 if (afu->adapter->native->sl_ops->register_serr_irq) {
1004 reg = cxl_p1n_read(afu, CXL_PSL_SERR_An);
1005 if (reg) {
1006 if (reg & ~0xffff)
1007 dev_warn(&afu->dev, "AFU had pending SERR: %#016llx\n", reg);
1008 cxl_p1n_write(afu, CXL_PSL_SERR_An, reg & ~0xffff);
1009 }
1010 }
1011 reg = cxl_p2n_read(afu, CXL_PSL_ErrStat_An);
1012 if (reg) {
1013 dev_warn(&afu->dev, "AFU had pending error status: %#016llx\n", reg);
1014 cxl_p2n_write(afu, CXL_PSL_ErrStat_An, reg);
1015 }
1016
1017 return 0;
1018 }
1019
1020 #define ERR_BUFF_MAX_COPY_SIZE PAGE_SIZE
1021 /*
1022 * afu_eb_read:
1023 * Called from sysfs and reads the afu error info buffer. The h/w only supports
1024 * 4/8 bytes aligned access. So in case the requested offset/count arent 8 byte
1025 * aligned the function uses a bounce buffer which can be max PAGE_SIZE.
1026 */
cxl_pci_afu_read_err_buffer(struct cxl_afu * afu,char * buf,loff_t off,size_t count)1027 ssize_t cxl_pci_afu_read_err_buffer(struct cxl_afu *afu, char *buf,
1028 loff_t off, size_t count)
1029 {
1030 loff_t aligned_start, aligned_end;
1031 size_t aligned_length;
1032 void *tbuf;
1033 const void __iomem *ebuf = afu->native->afu_desc_mmio + afu->eb_offset;
1034
1035 if (count == 0 || off < 0 || (size_t)off >= afu->eb_len)
1036 return 0;
1037
1038 /* calculate aligned read window */
1039 count = min((size_t)(afu->eb_len - off), count);
1040 aligned_start = round_down(off, 8);
1041 aligned_end = round_up(off + count, 8);
1042 aligned_length = aligned_end - aligned_start;
1043
1044 /* max we can copy in one read is PAGE_SIZE */
1045 if (aligned_length > ERR_BUFF_MAX_COPY_SIZE) {
1046 aligned_length = ERR_BUFF_MAX_COPY_SIZE;
1047 count = ERR_BUFF_MAX_COPY_SIZE - (off & 0x7);
1048 }
1049
1050 /* use bounce buffer for copy */
1051 tbuf = (void *)__get_free_page(GFP_KERNEL);
1052 if (!tbuf)
1053 return -ENOMEM;
1054
1055 /* perform aligned read from the mmio region */
1056 memcpy_fromio(tbuf, ebuf + aligned_start, aligned_length);
1057 memcpy(buf, tbuf + (off & 0x7), count);
1058
1059 free_page((unsigned long)tbuf);
1060
1061 return count;
1062 }
1063
pci_configure_afu(struct cxl_afu * afu,struct cxl * adapter,struct pci_dev * dev)1064 static int pci_configure_afu(struct cxl_afu *afu, struct cxl *adapter, struct pci_dev *dev)
1065 {
1066 int rc;
1067
1068 if ((rc = pci_map_slice_regs(afu, adapter, dev)))
1069 return rc;
1070
1071 if (adapter->native->sl_ops->sanitise_afu_regs) {
1072 rc = adapter->native->sl_ops->sanitise_afu_regs(afu);
1073 if (rc)
1074 goto err1;
1075 }
1076
1077 /* We need to reset the AFU before we can read the AFU descriptor */
1078 if ((rc = cxl_ops->afu_reset(afu)))
1079 goto err1;
1080
1081 if (cxl_verbose)
1082 dump_afu_descriptor(afu);
1083
1084 if ((rc = cxl_read_afu_descriptor(afu)))
1085 goto err1;
1086
1087 if ((rc = cxl_afu_descriptor_looks_ok(afu)))
1088 goto err1;
1089
1090 if (adapter->native->sl_ops->afu_regs_init)
1091 if ((rc = adapter->native->sl_ops->afu_regs_init(afu)))
1092 goto err1;
1093
1094 if (adapter->native->sl_ops->register_serr_irq)
1095 if ((rc = adapter->native->sl_ops->register_serr_irq(afu)))
1096 goto err1;
1097
1098 if ((rc = cxl_native_register_psl_irq(afu)))
1099 goto err2;
1100
1101 atomic_set(&afu->configured_state, 0);
1102 return 0;
1103
1104 err2:
1105 if (adapter->native->sl_ops->release_serr_irq)
1106 adapter->native->sl_ops->release_serr_irq(afu);
1107 err1:
1108 pci_unmap_slice_regs(afu);
1109 return rc;
1110 }
1111
pci_deconfigure_afu(struct cxl_afu * afu)1112 static void pci_deconfigure_afu(struct cxl_afu *afu)
1113 {
1114 /*
1115 * It's okay to deconfigure when AFU is already locked, otherwise wait
1116 * until there are no readers
1117 */
1118 if (atomic_read(&afu->configured_state) != -1) {
1119 while (atomic_cmpxchg(&afu->configured_state, 0, -1) != -1)
1120 schedule();
1121 }
1122 cxl_native_release_psl_irq(afu);
1123 if (afu->adapter->native->sl_ops->release_serr_irq)
1124 afu->adapter->native->sl_ops->release_serr_irq(afu);
1125 pci_unmap_slice_regs(afu);
1126 }
1127
pci_init_afu(struct cxl * adapter,int slice,struct pci_dev * dev)1128 static int pci_init_afu(struct cxl *adapter, int slice, struct pci_dev *dev)
1129 {
1130 struct cxl_afu *afu;
1131 int rc = -ENOMEM;
1132
1133 afu = cxl_alloc_afu(adapter, slice);
1134 if (!afu)
1135 return -ENOMEM;
1136
1137 afu->native = kzalloc(sizeof(struct cxl_afu_native), GFP_KERNEL);
1138 if (!afu->native)
1139 goto err_free_afu;
1140
1141 mutex_init(&afu->native->spa_mutex);
1142
1143 rc = dev_set_name(&afu->dev, "afu%i.%i", adapter->adapter_num, slice);
1144 if (rc)
1145 goto err_free_native;
1146
1147 rc = pci_configure_afu(afu, adapter, dev);
1148 if (rc)
1149 goto err_free_native;
1150
1151 /* Don't care if this fails */
1152 cxl_debugfs_afu_add(afu);
1153
1154 /*
1155 * After we call this function we must not free the afu directly, even
1156 * if it returns an error!
1157 */
1158 if ((rc = cxl_register_afu(afu)))
1159 goto err_put_dev;
1160
1161 if ((rc = cxl_sysfs_afu_add(afu)))
1162 goto err_del_dev;
1163
1164 adapter->afu[afu->slice] = afu;
1165
1166 if ((rc = cxl_pci_vphb_add(afu)))
1167 dev_info(&afu->dev, "Can't register vPHB\n");
1168
1169 return 0;
1170
1171 err_del_dev:
1172 device_del(&afu->dev);
1173 err_put_dev:
1174 pci_deconfigure_afu(afu);
1175 cxl_debugfs_afu_remove(afu);
1176 put_device(&afu->dev);
1177 return rc;
1178
1179 err_free_native:
1180 kfree(afu->native);
1181 err_free_afu:
1182 kfree(afu);
1183 return rc;
1184
1185 }
1186
cxl_pci_remove_afu(struct cxl_afu * afu)1187 static void cxl_pci_remove_afu(struct cxl_afu *afu)
1188 {
1189 pr_devel("%s\n", __func__);
1190
1191 if (!afu)
1192 return;
1193
1194 cxl_pci_vphb_remove(afu);
1195 cxl_sysfs_afu_remove(afu);
1196 cxl_debugfs_afu_remove(afu);
1197
1198 spin_lock(&afu->adapter->afu_list_lock);
1199 afu->adapter->afu[afu->slice] = NULL;
1200 spin_unlock(&afu->adapter->afu_list_lock);
1201
1202 cxl_context_detach_all(afu);
1203 cxl_ops->afu_deactivate_mode(afu, afu->current_mode);
1204
1205 pci_deconfigure_afu(afu);
1206 device_unregister(&afu->dev);
1207 }
1208
cxl_pci_reset(struct cxl * adapter)1209 int cxl_pci_reset(struct cxl *adapter)
1210 {
1211 struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
1212 int rc;
1213
1214 if (adapter->perst_same_image) {
1215 dev_warn(&dev->dev,
1216 "cxl: refusing to reset/reflash when perst_reloads_same_image is set.\n");
1217 return -EINVAL;
1218 }
1219
1220 dev_info(&dev->dev, "CXL reset\n");
1221
1222 /*
1223 * The adapter is about to be reset, so ignore errors.
1224 */
1225 cxl_data_cache_flush(adapter);
1226
1227 /* pcie_warm_reset requests a fundamental pci reset which includes a
1228 * PERST assert/deassert. PERST triggers a loading of the image
1229 * if "user" or "factory" is selected in sysfs */
1230 if ((rc = pci_set_pcie_reset_state(dev, pcie_warm_reset))) {
1231 dev_err(&dev->dev, "cxl: pcie_warm_reset failed\n");
1232 return rc;
1233 }
1234
1235 return rc;
1236 }
1237
cxl_map_adapter_regs(struct cxl * adapter,struct pci_dev * dev)1238 static int cxl_map_adapter_regs(struct cxl *adapter, struct pci_dev *dev)
1239 {
1240 if (pci_request_region(dev, 2, "priv 2 regs"))
1241 goto err1;
1242 if (pci_request_region(dev, 0, "priv 1 regs"))
1243 goto err2;
1244
1245 pr_devel("cxl_map_adapter_regs: p1: %#016llx %#llx, p2: %#016llx %#llx",
1246 p1_base(dev), p1_size(dev), p2_base(dev), p2_size(dev));
1247
1248 if (!(adapter->native->p1_mmio = ioremap(p1_base(dev), p1_size(dev))))
1249 goto err3;
1250
1251 if (!(adapter->native->p2_mmio = ioremap(p2_base(dev), p2_size(dev))))
1252 goto err4;
1253
1254 return 0;
1255
1256 err4:
1257 iounmap(adapter->native->p1_mmio);
1258 adapter->native->p1_mmio = NULL;
1259 err3:
1260 pci_release_region(dev, 0);
1261 err2:
1262 pci_release_region(dev, 2);
1263 err1:
1264 return -ENOMEM;
1265 }
1266
cxl_unmap_adapter_regs(struct cxl * adapter)1267 static void cxl_unmap_adapter_regs(struct cxl *adapter)
1268 {
1269 if (adapter->native->p1_mmio) {
1270 iounmap(adapter->native->p1_mmio);
1271 adapter->native->p1_mmio = NULL;
1272 pci_release_region(to_pci_dev(adapter->dev.parent), 2);
1273 }
1274 if (adapter->native->p2_mmio) {
1275 iounmap(adapter->native->p2_mmio);
1276 adapter->native->p2_mmio = NULL;
1277 pci_release_region(to_pci_dev(adapter->dev.parent), 0);
1278 }
1279 }
1280
cxl_read_vsec(struct cxl * adapter,struct pci_dev * dev)1281 static int cxl_read_vsec(struct cxl *adapter, struct pci_dev *dev)
1282 {
1283 int vsec;
1284 u32 afu_desc_off, afu_desc_size;
1285 u32 ps_off, ps_size;
1286 u16 vseclen;
1287 u8 image_state;
1288
1289 if (!(vsec = find_cxl_vsec(dev))) {
1290 dev_err(&dev->dev, "ABORTING: CXL VSEC not found!\n");
1291 return -ENODEV;
1292 }
1293
1294 CXL_READ_VSEC_LENGTH(dev, vsec, &vseclen);
1295 if (vseclen < CXL_VSEC_MIN_SIZE) {
1296 dev_err(&dev->dev, "ABORTING: CXL VSEC too short\n");
1297 return -EINVAL;
1298 }
1299
1300 CXL_READ_VSEC_STATUS(dev, vsec, &adapter->vsec_status);
1301 CXL_READ_VSEC_PSL_REVISION(dev, vsec, &adapter->psl_rev);
1302 CXL_READ_VSEC_CAIA_MAJOR(dev, vsec, &adapter->caia_major);
1303 CXL_READ_VSEC_CAIA_MINOR(dev, vsec, &adapter->caia_minor);
1304 CXL_READ_VSEC_BASE_IMAGE(dev, vsec, &adapter->base_image);
1305 CXL_READ_VSEC_IMAGE_STATE(dev, vsec, &image_state);
1306 adapter->user_image_loaded = !!(image_state & CXL_VSEC_USER_IMAGE_LOADED);
1307 adapter->perst_select_user = !!(image_state & CXL_VSEC_USER_IMAGE_LOADED);
1308 adapter->perst_loads_image = !!(image_state & CXL_VSEC_PERST_LOADS_IMAGE);
1309
1310 CXL_READ_VSEC_NAFUS(dev, vsec, &adapter->slices);
1311 CXL_READ_VSEC_AFU_DESC_OFF(dev, vsec, &afu_desc_off);
1312 CXL_READ_VSEC_AFU_DESC_SIZE(dev, vsec, &afu_desc_size);
1313 CXL_READ_VSEC_PS_OFF(dev, vsec, &ps_off);
1314 CXL_READ_VSEC_PS_SIZE(dev, vsec, &ps_size);
1315
1316 /* Convert everything to bytes, because there is NO WAY I'd look at the
1317 * code a month later and forget what units these are in ;-) */
1318 adapter->native->ps_off = ps_off * 64 * 1024;
1319 adapter->ps_size = ps_size * 64 * 1024;
1320 adapter->native->afu_desc_off = afu_desc_off * 64 * 1024;
1321 adapter->native->afu_desc_size = afu_desc_size * 64 * 1024;
1322
1323 /* Total IRQs - 1 PSL ERROR - #AFU*(1 slice error + 1 DSI) */
1324 adapter->user_irqs = pnv_cxl_get_irq_count(dev) - 1 - 2*adapter->slices;
1325
1326 return 0;
1327 }
1328
1329 /*
1330 * Workaround a PCIe Host Bridge defect on some cards, that can cause
1331 * malformed Transaction Layer Packet (TLP) errors to be erroneously
1332 * reported. Mask this error in the Uncorrectable Error Mask Register.
1333 *
1334 * The upper nibble of the PSL revision is used to distinguish between
1335 * different cards. The affected ones have it set to 0.
1336 */
cxl_fixup_malformed_tlp(struct cxl * adapter,struct pci_dev * dev)1337 static void cxl_fixup_malformed_tlp(struct cxl *adapter, struct pci_dev *dev)
1338 {
1339 int aer;
1340 u32 data;
1341
1342 if (adapter->psl_rev & 0xf000)
1343 return;
1344 if (!(aer = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR)))
1345 return;
1346 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, &data);
1347 if (data & PCI_ERR_UNC_MALF_TLP)
1348 if (data & PCI_ERR_UNC_INTN)
1349 return;
1350 data |= PCI_ERR_UNC_MALF_TLP;
1351 data |= PCI_ERR_UNC_INTN;
1352 pci_write_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, data);
1353 }
1354
cxl_compatible_caia_version(struct cxl * adapter)1355 static bool cxl_compatible_caia_version(struct cxl *adapter)
1356 {
1357 if (cxl_is_power8() && (adapter->caia_major == 1))
1358 return true;
1359
1360 if (cxl_is_power9() && (adapter->caia_major == 2))
1361 return true;
1362
1363 return false;
1364 }
1365
cxl_vsec_looks_ok(struct cxl * adapter,struct pci_dev * dev)1366 static int cxl_vsec_looks_ok(struct cxl *adapter, struct pci_dev *dev)
1367 {
1368 if (adapter->vsec_status & CXL_STATUS_SECOND_PORT)
1369 return -EBUSY;
1370
1371 if (adapter->vsec_status & CXL_UNSUPPORTED_FEATURES) {
1372 dev_err(&dev->dev, "ABORTING: CXL requires unsupported features\n");
1373 return -EINVAL;
1374 }
1375
1376 if (!cxl_compatible_caia_version(adapter)) {
1377 dev_info(&dev->dev, "Ignoring card. PSL type is not supported (caia version: %d)\n",
1378 adapter->caia_major);
1379 return -ENODEV;
1380 }
1381
1382 if (!adapter->slices) {
1383 /* Once we support dynamic reprogramming we can use the card if
1384 * it supports loadable AFUs */
1385 dev_err(&dev->dev, "ABORTING: Device has no AFUs\n");
1386 return -EINVAL;
1387 }
1388
1389 if (!adapter->native->afu_desc_off || !adapter->native->afu_desc_size) {
1390 dev_err(&dev->dev, "ABORTING: VSEC shows no AFU descriptors\n");
1391 return -EINVAL;
1392 }
1393
1394 if (adapter->ps_size > p2_size(dev) - adapter->native->ps_off) {
1395 dev_err(&dev->dev, "ABORTING: Problem state size larger than "
1396 "available in BAR2: 0x%llx > 0x%llx\n",
1397 adapter->ps_size, p2_size(dev) - adapter->native->ps_off);
1398 return -EINVAL;
1399 }
1400
1401 return 0;
1402 }
1403
cxl_pci_read_adapter_vpd(struct cxl * adapter,void * buf,size_t len)1404 ssize_t cxl_pci_read_adapter_vpd(struct cxl *adapter, void *buf, size_t len)
1405 {
1406 return pci_read_vpd(to_pci_dev(adapter->dev.parent), 0, len, buf);
1407 }
1408
cxl_release_adapter(struct device * dev)1409 static void cxl_release_adapter(struct device *dev)
1410 {
1411 struct cxl *adapter = to_cxl_adapter(dev);
1412
1413 pr_devel("cxl_release_adapter\n");
1414
1415 cxl_remove_adapter_nr(adapter);
1416
1417 kfree(adapter->native);
1418 kfree(adapter);
1419 }
1420
1421 #define CXL_PSL_ErrIVTE_tberror (0x1ull << (63-31))
1422
sanitise_adapter_regs(struct cxl * adapter)1423 static int sanitise_adapter_regs(struct cxl *adapter)
1424 {
1425 int rc = 0;
1426
1427 /* Clear PSL tberror bit by writing 1 to it */
1428 cxl_p1_write(adapter, CXL_PSL_ErrIVTE, CXL_PSL_ErrIVTE_tberror);
1429
1430 if (adapter->native->sl_ops->invalidate_all) {
1431 /* do not invalidate ERAT entries when not reloading on PERST */
1432 if (cxl_is_power9() && (adapter->perst_loads_image))
1433 return 0;
1434 rc = adapter->native->sl_ops->invalidate_all(adapter);
1435 }
1436
1437 return rc;
1438 }
1439
1440 /* This should contain *only* operations that can safely be done in
1441 * both creation and recovery.
1442 */
cxl_configure_adapter(struct cxl * adapter,struct pci_dev * dev)1443 static int cxl_configure_adapter(struct cxl *adapter, struct pci_dev *dev)
1444 {
1445 int rc;
1446
1447 adapter->dev.parent = &dev->dev;
1448 adapter->dev.release = cxl_release_adapter;
1449 pci_set_drvdata(dev, adapter);
1450
1451 rc = pci_enable_device(dev);
1452 if (rc) {
1453 dev_err(&dev->dev, "pci_enable_device failed: %i\n", rc);
1454 return rc;
1455 }
1456
1457 if ((rc = cxl_read_vsec(adapter, dev)))
1458 return rc;
1459
1460 if ((rc = cxl_vsec_looks_ok(adapter, dev)))
1461 return rc;
1462
1463 cxl_fixup_malformed_tlp(adapter, dev);
1464
1465 if ((rc = setup_cxl_bars(dev)))
1466 return rc;
1467
1468 if ((rc = switch_card_to_cxl(dev)))
1469 return rc;
1470
1471 if ((rc = cxl_update_image_control(adapter)))
1472 return rc;
1473
1474 if ((rc = cxl_map_adapter_regs(adapter, dev)))
1475 return rc;
1476
1477 if ((rc = sanitise_adapter_regs(adapter)))
1478 goto err;
1479
1480 if ((rc = adapter->native->sl_ops->adapter_regs_init(adapter, dev)))
1481 goto err;
1482
1483 /* Required for devices using CAPP DMA mode, harmless for others */
1484 pci_set_master(dev);
1485
1486 adapter->tunneled_ops_supported = false;
1487
1488 if (cxl_is_power9()) {
1489 if (pnv_pci_set_tunnel_bar(dev, 0x00020000E0000000ull, 1))
1490 dev_info(&dev->dev, "Tunneled operations unsupported\n");
1491 else
1492 adapter->tunneled_ops_supported = true;
1493 }
1494
1495 if ((rc = pnv_phb_to_cxl_mode(dev, adapter->native->sl_ops->capi_mode)))
1496 goto err;
1497
1498 /* If recovery happened, the last step is to turn on snooping.
1499 * In the non-recovery case this has no effect */
1500 if ((rc = pnv_phb_to_cxl_mode(dev, OPAL_PHB_CAPI_MODE_SNOOP_ON)))
1501 goto err;
1502
1503 /* Ignore error, adapter init is not dependant on timebase sync */
1504 cxl_setup_psl_timebase(adapter, dev);
1505
1506 if ((rc = cxl_native_register_psl_err_irq(adapter)))
1507 goto err;
1508
1509 return 0;
1510
1511 err:
1512 cxl_unmap_adapter_regs(adapter);
1513 return rc;
1514
1515 }
1516
cxl_deconfigure_adapter(struct cxl * adapter)1517 static void cxl_deconfigure_adapter(struct cxl *adapter)
1518 {
1519 struct pci_dev *pdev = to_pci_dev(adapter->dev.parent);
1520
1521 if (cxl_is_power9())
1522 pnv_pci_set_tunnel_bar(pdev, 0x00020000E0000000ull, 0);
1523
1524 cxl_native_release_psl_err_irq(adapter);
1525 cxl_unmap_adapter_regs(adapter);
1526
1527 pci_disable_device(pdev);
1528 }
1529
cxl_stop_trace_psl9(struct cxl * adapter)1530 static void cxl_stop_trace_psl9(struct cxl *adapter)
1531 {
1532 int traceid;
1533 u64 trace_state, trace_mask;
1534 struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
1535
1536 /* read each tracearray state and issue mmio to stop them is needed */
1537 for (traceid = 0; traceid <= CXL_PSL9_TRACEID_MAX; ++traceid) {
1538 trace_state = cxl_p1_read(adapter, CXL_PSL9_CTCCFG);
1539 trace_mask = (0x3ULL << (62 - traceid * 2));
1540 trace_state = (trace_state & trace_mask) >> (62 - traceid * 2);
1541 dev_dbg(&dev->dev, "cxl: Traceid-%d trace_state=0x%0llX\n",
1542 traceid, trace_state);
1543
1544 /* issue mmio if the trace array isn't in FIN state */
1545 if (trace_state != CXL_PSL9_TRACESTATE_FIN)
1546 cxl_p1_write(adapter, CXL_PSL9_TRACECFG,
1547 0x8400000000000000ULL | traceid);
1548 }
1549 }
1550
cxl_stop_trace_psl8(struct cxl * adapter)1551 static void cxl_stop_trace_psl8(struct cxl *adapter)
1552 {
1553 int slice;
1554
1555 /* Stop the trace */
1556 cxl_p1_write(adapter, CXL_PSL_TRACE, 0x8000000000000017LL);
1557
1558 /* Stop the slice traces */
1559 spin_lock(&adapter->afu_list_lock);
1560 for (slice = 0; slice < adapter->slices; slice++) {
1561 if (adapter->afu[slice])
1562 cxl_p1n_write(adapter->afu[slice], CXL_PSL_SLICE_TRACE,
1563 0x8000000000000000LL);
1564 }
1565 spin_unlock(&adapter->afu_list_lock);
1566 }
1567
1568 static const struct cxl_service_layer_ops psl9_ops = {
1569 .adapter_regs_init = init_implementation_adapter_regs_psl9,
1570 .invalidate_all = cxl_invalidate_all_psl9,
1571 .afu_regs_init = init_implementation_afu_regs_psl9,
1572 .sanitise_afu_regs = sanitise_afu_regs_psl9,
1573 .register_serr_irq = cxl_native_register_serr_irq,
1574 .release_serr_irq = cxl_native_release_serr_irq,
1575 .handle_interrupt = cxl_irq_psl9,
1576 .fail_irq = cxl_fail_irq_psl,
1577 .activate_dedicated_process = cxl_activate_dedicated_process_psl9,
1578 .attach_afu_directed = cxl_attach_afu_directed_psl9,
1579 .attach_dedicated_process = cxl_attach_dedicated_process_psl9,
1580 .update_dedicated_ivtes = cxl_update_dedicated_ivtes_psl9,
1581 .debugfs_add_adapter_regs = cxl_debugfs_add_adapter_regs_psl9,
1582 .debugfs_add_afu_regs = cxl_debugfs_add_afu_regs_psl9,
1583 .psl_irq_dump_registers = cxl_native_irq_dump_regs_psl9,
1584 .err_irq_dump_registers = cxl_native_err_irq_dump_regs_psl9,
1585 .debugfs_stop_trace = cxl_stop_trace_psl9,
1586 .timebase_read = timebase_read_psl9,
1587 .capi_mode = OPAL_PHB_CAPI_MODE_CAPI,
1588 .needs_reset_before_disable = true,
1589 };
1590
1591 static const struct cxl_service_layer_ops psl8_ops = {
1592 .adapter_regs_init = init_implementation_adapter_regs_psl8,
1593 .invalidate_all = cxl_invalidate_all_psl8,
1594 .afu_regs_init = init_implementation_afu_regs_psl8,
1595 .sanitise_afu_regs = sanitise_afu_regs_psl8,
1596 .register_serr_irq = cxl_native_register_serr_irq,
1597 .release_serr_irq = cxl_native_release_serr_irq,
1598 .handle_interrupt = cxl_irq_psl8,
1599 .fail_irq = cxl_fail_irq_psl,
1600 .activate_dedicated_process = cxl_activate_dedicated_process_psl8,
1601 .attach_afu_directed = cxl_attach_afu_directed_psl8,
1602 .attach_dedicated_process = cxl_attach_dedicated_process_psl8,
1603 .update_dedicated_ivtes = cxl_update_dedicated_ivtes_psl8,
1604 .debugfs_add_adapter_regs = cxl_debugfs_add_adapter_regs_psl8,
1605 .debugfs_add_afu_regs = cxl_debugfs_add_afu_regs_psl8,
1606 .psl_irq_dump_registers = cxl_native_irq_dump_regs_psl8,
1607 .err_irq_dump_registers = cxl_native_err_irq_dump_regs_psl8,
1608 .debugfs_stop_trace = cxl_stop_trace_psl8,
1609 .write_timebase_ctrl = write_timebase_ctrl_psl8,
1610 .timebase_read = timebase_read_psl8,
1611 .capi_mode = OPAL_PHB_CAPI_MODE_CAPI,
1612 .needs_reset_before_disable = true,
1613 };
1614
set_sl_ops(struct cxl * adapter,struct pci_dev * dev)1615 static void set_sl_ops(struct cxl *adapter, struct pci_dev *dev)
1616 {
1617 if (cxl_is_power8()) {
1618 dev_info(&dev->dev, "Device uses a PSL8\n");
1619 adapter->native->sl_ops = &psl8_ops;
1620 } else {
1621 dev_info(&dev->dev, "Device uses a PSL9\n");
1622 adapter->native->sl_ops = &psl9_ops;
1623 }
1624 }
1625
1626
cxl_pci_init_adapter(struct pci_dev * dev)1627 static struct cxl *cxl_pci_init_adapter(struct pci_dev *dev)
1628 {
1629 struct cxl *adapter;
1630 int rc;
1631
1632 adapter = cxl_alloc_adapter();
1633 if (!adapter)
1634 return ERR_PTR(-ENOMEM);
1635
1636 adapter->native = kzalloc(sizeof(struct cxl_native), GFP_KERNEL);
1637 if (!adapter->native) {
1638 rc = -ENOMEM;
1639 goto err_release;
1640 }
1641
1642 set_sl_ops(adapter, dev);
1643
1644 /* Set defaults for parameters which need to persist over
1645 * configure/reconfigure
1646 */
1647 adapter->perst_loads_image = true;
1648 adapter->perst_same_image = false;
1649
1650 rc = cxl_configure_adapter(adapter, dev);
1651 if (rc) {
1652 pci_disable_device(dev);
1653 goto err_release;
1654 }
1655
1656 /* Don't care if this one fails: */
1657 cxl_debugfs_adapter_add(adapter);
1658
1659 /*
1660 * After we call this function we must not free the adapter directly,
1661 * even if it returns an error!
1662 */
1663 if ((rc = cxl_register_adapter(adapter)))
1664 goto err_put_dev;
1665
1666 if ((rc = cxl_sysfs_adapter_add(adapter)))
1667 goto err_del_dev;
1668
1669 /* Release the context lock as adapter is configured */
1670 cxl_adapter_context_unlock(adapter);
1671
1672 return adapter;
1673
1674 err_del_dev:
1675 device_del(&adapter->dev);
1676 err_put_dev:
1677 /* This should mirror cxl_remove_adapter, except without the
1678 * sysfs parts
1679 */
1680 cxl_debugfs_adapter_remove(adapter);
1681 cxl_deconfigure_adapter(adapter);
1682 put_device(&adapter->dev);
1683 return ERR_PTR(rc);
1684
1685 err_release:
1686 cxl_release_adapter(&adapter->dev);
1687 return ERR_PTR(rc);
1688 }
1689
cxl_pci_remove_adapter(struct cxl * adapter)1690 static void cxl_pci_remove_adapter(struct cxl *adapter)
1691 {
1692 pr_devel("cxl_remove_adapter\n");
1693
1694 cxl_sysfs_adapter_remove(adapter);
1695 cxl_debugfs_adapter_remove(adapter);
1696
1697 /*
1698 * Flush adapter datacache as its about to be removed.
1699 */
1700 cxl_data_cache_flush(adapter);
1701
1702 cxl_deconfigure_adapter(adapter);
1703
1704 device_unregister(&adapter->dev);
1705 }
1706
1707 #define CXL_MAX_PCIEX_PARENT 2
1708
cxl_slot_is_switched(struct pci_dev * dev)1709 int cxl_slot_is_switched(struct pci_dev *dev)
1710 {
1711 struct device_node *np;
1712 int depth = 0;
1713
1714 if (!(np = pci_device_to_OF_node(dev))) {
1715 pr_err("cxl: np = NULL\n");
1716 return -ENODEV;
1717 }
1718 of_node_get(np);
1719 while (np) {
1720 np = of_get_next_parent(np);
1721 if (!of_node_is_type(np, "pciex"))
1722 break;
1723 depth++;
1724 }
1725 of_node_put(np);
1726 return (depth > CXL_MAX_PCIEX_PARENT);
1727 }
1728
cxl_probe(struct pci_dev * dev,const struct pci_device_id * id)1729 static int cxl_probe(struct pci_dev *dev, const struct pci_device_id *id)
1730 {
1731 struct cxl *adapter;
1732 int slice;
1733 int rc;
1734
1735 if (cxl_pci_is_vphb_device(dev)) {
1736 dev_dbg(&dev->dev, "cxl_init_adapter: Ignoring cxl vphb device\n");
1737 return -ENODEV;
1738 }
1739
1740 if (cxl_slot_is_switched(dev)) {
1741 dev_info(&dev->dev, "Ignoring card on incompatible PCI slot\n");
1742 return -ENODEV;
1743 }
1744
1745 if (cxl_is_power9() && !radix_enabled()) {
1746 dev_info(&dev->dev, "Only Radix mode supported\n");
1747 return -ENODEV;
1748 }
1749
1750 if (cxl_verbose)
1751 dump_cxl_config_space(dev);
1752
1753 adapter = cxl_pci_init_adapter(dev);
1754 if (IS_ERR(adapter)) {
1755 dev_err(&dev->dev, "cxl_init_adapter failed: %li\n", PTR_ERR(adapter));
1756 return PTR_ERR(adapter);
1757 }
1758
1759 for (slice = 0; slice < adapter->slices; slice++) {
1760 if ((rc = pci_init_afu(adapter, slice, dev))) {
1761 dev_err(&dev->dev, "AFU %i failed to initialise: %i\n", slice, rc);
1762 continue;
1763 }
1764
1765 rc = cxl_afu_select_best_mode(adapter->afu[slice]);
1766 if (rc)
1767 dev_err(&dev->dev, "AFU %i failed to start: %i\n", slice, rc);
1768 }
1769
1770 return 0;
1771 }
1772
cxl_remove(struct pci_dev * dev)1773 static void cxl_remove(struct pci_dev *dev)
1774 {
1775 struct cxl *adapter = pci_get_drvdata(dev);
1776 struct cxl_afu *afu;
1777 int i;
1778
1779 /*
1780 * Lock to prevent someone grabbing a ref through the adapter list as
1781 * we are removing it
1782 */
1783 for (i = 0; i < adapter->slices; i++) {
1784 afu = adapter->afu[i];
1785 cxl_pci_remove_afu(afu);
1786 }
1787 cxl_pci_remove_adapter(adapter);
1788 }
1789
cxl_vphb_error_detected(struct cxl_afu * afu,pci_channel_state_t state)1790 static pci_ers_result_t cxl_vphb_error_detected(struct cxl_afu *afu,
1791 pci_channel_state_t state)
1792 {
1793 struct pci_dev *afu_dev;
1794 struct pci_driver *afu_drv;
1795 const struct pci_error_handlers *err_handler;
1796 pci_ers_result_t result = PCI_ERS_RESULT_NEED_RESET;
1797 pci_ers_result_t afu_result = PCI_ERS_RESULT_NEED_RESET;
1798
1799 /* There should only be one entry, but go through the list
1800 * anyway
1801 */
1802 if (afu == NULL || afu->phb == NULL)
1803 return result;
1804
1805 list_for_each_entry(afu_dev, &afu->phb->bus->devices, bus_list) {
1806 afu_drv = to_pci_driver(afu_dev->dev.driver);
1807 if (!afu_drv)
1808 continue;
1809
1810 afu_dev->error_state = state;
1811
1812 err_handler = afu_drv->err_handler;
1813 if (err_handler)
1814 afu_result = err_handler->error_detected(afu_dev,
1815 state);
1816 /* Disconnect trumps all, NONE trumps NEED_RESET */
1817 if (afu_result == PCI_ERS_RESULT_DISCONNECT)
1818 result = PCI_ERS_RESULT_DISCONNECT;
1819 else if ((afu_result == PCI_ERS_RESULT_NONE) &&
1820 (result == PCI_ERS_RESULT_NEED_RESET))
1821 result = PCI_ERS_RESULT_NONE;
1822 }
1823 return result;
1824 }
1825
cxl_pci_error_detected(struct pci_dev * pdev,pci_channel_state_t state)1826 static pci_ers_result_t cxl_pci_error_detected(struct pci_dev *pdev,
1827 pci_channel_state_t state)
1828 {
1829 struct cxl *adapter = pci_get_drvdata(pdev);
1830 struct cxl_afu *afu;
1831 pci_ers_result_t result = PCI_ERS_RESULT_NEED_RESET;
1832 pci_ers_result_t afu_result = PCI_ERS_RESULT_NEED_RESET;
1833 int i;
1834
1835 /* At this point, we could still have an interrupt pending.
1836 * Let's try to get them out of the way before they do
1837 * anything we don't like.
1838 */
1839 schedule();
1840
1841 /* If we're permanently dead, give up. */
1842 if (state == pci_channel_io_perm_failure) {
1843 spin_lock(&adapter->afu_list_lock);
1844 for (i = 0; i < adapter->slices; i++) {
1845 afu = adapter->afu[i];
1846 /*
1847 * Tell the AFU drivers; but we don't care what they
1848 * say, we're going away.
1849 */
1850 cxl_vphb_error_detected(afu, state);
1851 }
1852 spin_unlock(&adapter->afu_list_lock);
1853 return PCI_ERS_RESULT_DISCONNECT;
1854 }
1855
1856 /* Are we reflashing?
1857 *
1858 * If we reflash, we could come back as something entirely
1859 * different, including a non-CAPI card. As such, by default
1860 * we don't participate in the process. We'll be unbound and
1861 * the slot re-probed. (TODO: check EEH doesn't blindly rebind
1862 * us!)
1863 *
1864 * However, this isn't the entire story: for reliablity
1865 * reasons, we usually want to reflash the FPGA on PERST in
1866 * order to get back to a more reliable known-good state.
1867 *
1868 * This causes us a bit of a problem: if we reflash we can't
1869 * trust that we'll come back the same - we could have a new
1870 * image and been PERSTed in order to load that
1871 * image. However, most of the time we actually *will* come
1872 * back the same - for example a regular EEH event.
1873 *
1874 * Therefore, we allow the user to assert that the image is
1875 * indeed the same and that we should continue on into EEH
1876 * anyway.
1877 */
1878 if (adapter->perst_loads_image && !adapter->perst_same_image) {
1879 /* TODO take the PHB out of CXL mode */
1880 dev_info(&pdev->dev, "reflashing, so opting out of EEH!\n");
1881 return PCI_ERS_RESULT_NONE;
1882 }
1883
1884 /*
1885 * At this point, we want to try to recover. We'll always
1886 * need a complete slot reset: we don't trust any other reset.
1887 *
1888 * Now, we go through each AFU:
1889 * - We send the driver, if bound, an error_detected callback.
1890 * We expect it to clean up, but it can also tell us to give
1891 * up and permanently detach the card. To simplify things, if
1892 * any bound AFU driver doesn't support EEH, we give up on EEH.
1893 *
1894 * - We detach all contexts associated with the AFU. This
1895 * does not free them, but puts them into a CLOSED state
1896 * which causes any the associated files to return useful
1897 * errors to userland. It also unmaps, but does not free,
1898 * any IRQs.
1899 *
1900 * - We clean up our side: releasing and unmapping resources we hold
1901 * so we can wire them up again when the hardware comes back up.
1902 *
1903 * Driver authors should note:
1904 *
1905 * - Any contexts you create in your kernel driver (except
1906 * those associated with anonymous file descriptors) are
1907 * your responsibility to free and recreate. Likewise with
1908 * any attached resources.
1909 *
1910 * - We will take responsibility for re-initialising the
1911 * device context (the one set up for you in
1912 * cxl_pci_enable_device_hook and accessed through
1913 * cxl_get_context). If you've attached IRQs or other
1914 * resources to it, they remains yours to free.
1915 *
1916 * You can call the same functions to release resources as you
1917 * normally would: we make sure that these functions continue
1918 * to work when the hardware is down.
1919 *
1920 * Two examples:
1921 *
1922 * 1) If you normally free all your resources at the end of
1923 * each request, or if you use anonymous FDs, your
1924 * error_detected callback can simply set a flag to tell
1925 * your driver not to start any new calls. You can then
1926 * clear the flag in the resume callback.
1927 *
1928 * 2) If you normally allocate your resources on startup:
1929 * * Set a flag in error_detected as above.
1930 * * Let CXL detach your contexts.
1931 * * In slot_reset, free the old resources and allocate new ones.
1932 * * In resume, clear the flag to allow things to start.
1933 */
1934
1935 /* Make sure no one else changes the afu list */
1936 spin_lock(&adapter->afu_list_lock);
1937
1938 for (i = 0; i < adapter->slices; i++) {
1939 afu = adapter->afu[i];
1940
1941 if (afu == NULL)
1942 continue;
1943
1944 afu_result = cxl_vphb_error_detected(afu, state);
1945 cxl_context_detach_all(afu);
1946 cxl_ops->afu_deactivate_mode(afu, afu->current_mode);
1947 pci_deconfigure_afu(afu);
1948
1949 /* Disconnect trumps all, NONE trumps NEED_RESET */
1950 if (afu_result == PCI_ERS_RESULT_DISCONNECT)
1951 result = PCI_ERS_RESULT_DISCONNECT;
1952 else if ((afu_result == PCI_ERS_RESULT_NONE) &&
1953 (result == PCI_ERS_RESULT_NEED_RESET))
1954 result = PCI_ERS_RESULT_NONE;
1955 }
1956 spin_unlock(&adapter->afu_list_lock);
1957
1958 /* should take the context lock here */
1959 if (cxl_adapter_context_lock(adapter) != 0)
1960 dev_warn(&adapter->dev,
1961 "Couldn't take context lock with %d active-contexts\n",
1962 atomic_read(&adapter->contexts_num));
1963
1964 cxl_deconfigure_adapter(adapter);
1965
1966 return result;
1967 }
1968
cxl_pci_slot_reset(struct pci_dev * pdev)1969 static pci_ers_result_t cxl_pci_slot_reset(struct pci_dev *pdev)
1970 {
1971 struct cxl *adapter = pci_get_drvdata(pdev);
1972 struct cxl_afu *afu;
1973 struct cxl_context *ctx;
1974 struct pci_dev *afu_dev;
1975 struct pci_driver *afu_drv;
1976 const struct pci_error_handlers *err_handler;
1977 pci_ers_result_t afu_result = PCI_ERS_RESULT_RECOVERED;
1978 pci_ers_result_t result = PCI_ERS_RESULT_RECOVERED;
1979 int i;
1980
1981 if (cxl_configure_adapter(adapter, pdev))
1982 goto err;
1983
1984 /*
1985 * Unlock context activation for the adapter. Ideally this should be
1986 * done in cxl_pci_resume but cxlflash module tries to activate the
1987 * master context as part of slot_reset callback.
1988 */
1989 cxl_adapter_context_unlock(adapter);
1990
1991 spin_lock(&adapter->afu_list_lock);
1992 for (i = 0; i < adapter->slices; i++) {
1993 afu = adapter->afu[i];
1994
1995 if (afu == NULL)
1996 continue;
1997
1998 if (pci_configure_afu(afu, adapter, pdev))
1999 goto err_unlock;
2000
2001 if (cxl_afu_select_best_mode(afu))
2002 goto err_unlock;
2003
2004 if (afu->phb == NULL)
2005 continue;
2006
2007 list_for_each_entry(afu_dev, &afu->phb->bus->devices, bus_list) {
2008 /* Reset the device context.
2009 * TODO: make this less disruptive
2010 */
2011 ctx = cxl_get_context(afu_dev);
2012
2013 if (ctx && cxl_release_context(ctx))
2014 goto err_unlock;
2015
2016 ctx = cxl_dev_context_init(afu_dev);
2017 if (IS_ERR(ctx))
2018 goto err_unlock;
2019
2020 afu_dev->dev.archdata.cxl_ctx = ctx;
2021
2022 if (cxl_ops->afu_check_and_enable(afu))
2023 goto err_unlock;
2024
2025 afu_dev->error_state = pci_channel_io_normal;
2026
2027 /* If there's a driver attached, allow it to
2028 * chime in on recovery. Drivers should check
2029 * if everything has come back OK, but
2030 * shouldn't start new work until we call
2031 * their resume function.
2032 */
2033 afu_drv = to_pci_driver(afu_dev->dev.driver);
2034 if (!afu_drv)
2035 continue;
2036
2037 err_handler = afu_drv->err_handler;
2038 if (err_handler && err_handler->slot_reset)
2039 afu_result = err_handler->slot_reset(afu_dev);
2040
2041 if (afu_result == PCI_ERS_RESULT_DISCONNECT)
2042 result = PCI_ERS_RESULT_DISCONNECT;
2043 }
2044 }
2045
2046 spin_unlock(&adapter->afu_list_lock);
2047 return result;
2048
2049 err_unlock:
2050 spin_unlock(&adapter->afu_list_lock);
2051
2052 err:
2053 /* All the bits that happen in both error_detected and cxl_remove
2054 * should be idempotent, so we don't need to worry about leaving a mix
2055 * of unconfigured and reconfigured resources.
2056 */
2057 dev_err(&pdev->dev, "EEH recovery failed. Asking to be disconnected.\n");
2058 return PCI_ERS_RESULT_DISCONNECT;
2059 }
2060
cxl_pci_resume(struct pci_dev * pdev)2061 static void cxl_pci_resume(struct pci_dev *pdev)
2062 {
2063 struct cxl *adapter = pci_get_drvdata(pdev);
2064 struct cxl_afu *afu;
2065 struct pci_dev *afu_dev;
2066 struct pci_driver *afu_drv;
2067 const struct pci_error_handlers *err_handler;
2068 int i;
2069
2070 /* Everything is back now. Drivers should restart work now.
2071 * This is not the place to be checking if everything came back up
2072 * properly, because there's no return value: do that in slot_reset.
2073 */
2074 spin_lock(&adapter->afu_list_lock);
2075 for (i = 0; i < adapter->slices; i++) {
2076 afu = adapter->afu[i];
2077
2078 if (afu == NULL || afu->phb == NULL)
2079 continue;
2080
2081 list_for_each_entry(afu_dev, &afu->phb->bus->devices, bus_list) {
2082 afu_drv = to_pci_driver(afu_dev->dev.driver);
2083 if (!afu_drv)
2084 continue;
2085
2086 err_handler = afu_drv->err_handler;
2087 if (err_handler && err_handler->resume)
2088 err_handler->resume(afu_dev);
2089 }
2090 }
2091 spin_unlock(&adapter->afu_list_lock);
2092 }
2093
2094 static const struct pci_error_handlers cxl_err_handler = {
2095 .error_detected = cxl_pci_error_detected,
2096 .slot_reset = cxl_pci_slot_reset,
2097 .resume = cxl_pci_resume,
2098 };
2099
2100 struct pci_driver cxl_pci_driver = {
2101 .name = "cxl-pci",
2102 .id_table = cxl_pci_tbl,
2103 .probe = cxl_probe,
2104 .remove = cxl_remove,
2105 .shutdown = cxl_remove,
2106 .err_handler = &cxl_err_handler,
2107 };
2108
