1 /***********************license start***************
2  * Author: Cavium Networks
3  *
4  * Contact: support@caviumnetworks.com
5  * This file is part of the OCTEON SDK
6  *
7  * Copyright (C) 2003-2018 Cavium, Inc.
8  *
9  * This file is free software; you can redistribute it and/or modify
10  * it under the terms of the GNU General Public License, Version 2, as
11  * published by the Free Software Foundation.
12  *
13  * This file is distributed in the hope that it will be useful, but
14  * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16  * NONINFRINGEMENT.  See the GNU General Public License for more
17  * details.
18  *
19  * You should have received a copy of the GNU General Public License
20  * along with this file; if not, write to the Free Software
21  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22  * or visit http://www.gnu.org/licenses/.
23  *
24  * This file may also be available under a different license from Cavium.
25  * Contact Cavium Networks for more information
26  ***********************license end**************************************/
27 
28 #ifndef __CVMX_PCSX_DEFS_H__
29 #define __CVMX_PCSX_DEFS_H__
30 
CVMX_PCSX_ANX_ADV_REG(unsigned long offset,unsigned long block_id)31 static inline uint64_t CVMX_PCSX_ANX_ADV_REG(unsigned long offset, unsigned long block_id)
32 {
33 	switch (cvmx_get_octeon_family()) {
34 	case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
35 		return CVMX_ADD_IO_SEG(0x00011800B0001010ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
36 	case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
37 	case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
38 		return CVMX_ADD_IO_SEG(0x00011800B0001010ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
39 	case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
40 	case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
41 	case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
42 		return CVMX_ADD_IO_SEG(0x00011800B0001010ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
43 	case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
44 		return CVMX_ADD_IO_SEG(0x00011800B0001010ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
45 	}
46 	return CVMX_ADD_IO_SEG(0x00011800B0001010ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
47 }
48 
CVMX_PCSX_ANX_EXT_ST_REG(unsigned long offset,unsigned long block_id)49 static inline uint64_t CVMX_PCSX_ANX_EXT_ST_REG(unsigned long offset, unsigned long block_id)
50 {
51 	switch (cvmx_get_octeon_family()) {
52 	case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
53 		return CVMX_ADD_IO_SEG(0x00011800B0001028ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
54 	case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
55 	case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
56 		return CVMX_ADD_IO_SEG(0x00011800B0001028ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
57 	case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
58 	case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
59 	case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
60 		return CVMX_ADD_IO_SEG(0x00011800B0001028ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
61 	case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
62 		return CVMX_ADD_IO_SEG(0x00011800B0001028ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
63 	}
64 	return CVMX_ADD_IO_SEG(0x00011800B0001028ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
65 }
66 
CVMX_PCSX_ANX_LP_ABIL_REG(unsigned long offset,unsigned long block_id)67 static inline uint64_t CVMX_PCSX_ANX_LP_ABIL_REG(unsigned long offset, unsigned long block_id)
68 {
69 	switch (cvmx_get_octeon_family()) {
70 	case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
71 		return CVMX_ADD_IO_SEG(0x00011800B0001018ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
72 	case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
73 	case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
74 		return CVMX_ADD_IO_SEG(0x00011800B0001018ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
75 	case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
76 	case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
77 	case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
78 		return CVMX_ADD_IO_SEG(0x00011800B0001018ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
79 	case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
80 		return CVMX_ADD_IO_SEG(0x00011800B0001018ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
81 	}
82 	return CVMX_ADD_IO_SEG(0x00011800B0001018ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
83 }
84 
CVMX_PCSX_ANX_RESULTS_REG(unsigned long offset,unsigned long block_id)85 static inline uint64_t CVMX_PCSX_ANX_RESULTS_REG(unsigned long offset, unsigned long block_id)
86 {
87 	switch (cvmx_get_octeon_family()) {
88 	case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
89 		return CVMX_ADD_IO_SEG(0x00011800B0001020ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
90 	case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
91 	case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
92 		return CVMX_ADD_IO_SEG(0x00011800B0001020ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
93 	case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
94 	case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
95 	case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
96 		return CVMX_ADD_IO_SEG(0x00011800B0001020ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
97 	case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
98 		return CVMX_ADD_IO_SEG(0x00011800B0001020ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
99 	}
100 	return CVMX_ADD_IO_SEG(0x00011800B0001020ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
101 }
102 
CVMX_PCSX_INTX_EN_REG(unsigned long offset,unsigned long block_id)103 static inline uint64_t CVMX_PCSX_INTX_EN_REG(unsigned long offset, unsigned long block_id)
104 {
105 	switch (cvmx_get_octeon_family()) {
106 	case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
107 		return CVMX_ADD_IO_SEG(0x00011800B0001088ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
108 	case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
109 	case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
110 		return CVMX_ADD_IO_SEG(0x00011800B0001088ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
111 	case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
112 	case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
113 	case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
114 		return CVMX_ADD_IO_SEG(0x00011800B0001088ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
115 	case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
116 		return CVMX_ADD_IO_SEG(0x00011800B0001088ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
117 	}
118 	return CVMX_ADD_IO_SEG(0x00011800B0001088ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
119 }
120 
CVMX_PCSX_INTX_REG(unsigned long offset,unsigned long block_id)121 static inline uint64_t CVMX_PCSX_INTX_REG(unsigned long offset, unsigned long block_id)
122 {
123 	switch (cvmx_get_octeon_family()) {
124 	case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
125 		return CVMX_ADD_IO_SEG(0x00011800B0001080ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
126 	case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
127 	case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
128 		return CVMX_ADD_IO_SEG(0x00011800B0001080ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
129 	case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
130 	case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
131 	case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
132 		return CVMX_ADD_IO_SEG(0x00011800B0001080ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
133 	case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
134 		return CVMX_ADD_IO_SEG(0x00011800B0001080ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
135 	}
136 	return CVMX_ADD_IO_SEG(0x00011800B0001080ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
137 }
138 
CVMX_PCSX_LINKX_TIMER_COUNT_REG(unsigned long offset,unsigned long block_id)139 static inline uint64_t CVMX_PCSX_LINKX_TIMER_COUNT_REG(unsigned long offset, unsigned long block_id)
140 {
141 	switch (cvmx_get_octeon_family()) {
142 	case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
143 		return CVMX_ADD_IO_SEG(0x00011800B0001040ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
144 	case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
145 	case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
146 		return CVMX_ADD_IO_SEG(0x00011800B0001040ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
147 	case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
148 	case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
149 	case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
150 		return CVMX_ADD_IO_SEG(0x00011800B0001040ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
151 	case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
152 		return CVMX_ADD_IO_SEG(0x00011800B0001040ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
153 	}
154 	return CVMX_ADD_IO_SEG(0x00011800B0001040ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
155 }
156 
CVMX_PCSX_LOG_ANLX_REG(unsigned long offset,unsigned long block_id)157 static inline uint64_t CVMX_PCSX_LOG_ANLX_REG(unsigned long offset, unsigned long block_id)
158 {
159 	switch (cvmx_get_octeon_family()) {
160 	case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
161 		return CVMX_ADD_IO_SEG(0x00011800B0001090ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
162 	case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
163 	case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
164 		return CVMX_ADD_IO_SEG(0x00011800B0001090ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
165 	case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
166 	case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
167 	case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
168 		return CVMX_ADD_IO_SEG(0x00011800B0001090ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
169 	case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
170 		return CVMX_ADD_IO_SEG(0x00011800B0001090ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
171 	}
172 	return CVMX_ADD_IO_SEG(0x00011800B0001090ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
173 }
174 
CVMX_PCSX_MISCX_CTL_REG(unsigned long offset,unsigned long block_id)175 static inline uint64_t CVMX_PCSX_MISCX_CTL_REG(unsigned long offset, unsigned long block_id)
176 {
177 	switch (cvmx_get_octeon_family()) {
178 	case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
179 		return CVMX_ADD_IO_SEG(0x00011800B0001078ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
180 	case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
181 	case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
182 		return CVMX_ADD_IO_SEG(0x00011800B0001078ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
183 	case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
184 	case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
185 	case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
186 		return CVMX_ADD_IO_SEG(0x00011800B0001078ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
187 	case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
188 		return CVMX_ADD_IO_SEG(0x00011800B0001078ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
189 	}
190 	return CVMX_ADD_IO_SEG(0x00011800B0001078ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
191 }
192 
CVMX_PCSX_MRX_CONTROL_REG(unsigned long offset,unsigned long block_id)193 static inline uint64_t CVMX_PCSX_MRX_CONTROL_REG(unsigned long offset, unsigned long block_id)
194 {
195 	switch (cvmx_get_octeon_family()) {
196 	case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
197 		return CVMX_ADD_IO_SEG(0x00011800B0001000ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
198 	case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
199 	case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
200 		return CVMX_ADD_IO_SEG(0x00011800B0001000ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
201 	case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
202 	case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
203 	case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
204 		return CVMX_ADD_IO_SEG(0x00011800B0001000ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
205 	case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
206 		return CVMX_ADD_IO_SEG(0x00011800B0001000ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
207 	}
208 	return CVMX_ADD_IO_SEG(0x00011800B0001000ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
209 }
210 
CVMX_PCSX_MRX_STATUS_REG(unsigned long offset,unsigned long block_id)211 static inline uint64_t CVMX_PCSX_MRX_STATUS_REG(unsigned long offset, unsigned long block_id)
212 {
213 	switch (cvmx_get_octeon_family()) {
214 	case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
215 		return CVMX_ADD_IO_SEG(0x00011800B0001008ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
216 	case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
217 	case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
218 		return CVMX_ADD_IO_SEG(0x00011800B0001008ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
219 	case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
220 	case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
221 	case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
222 		return CVMX_ADD_IO_SEG(0x00011800B0001008ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
223 	case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
224 		return CVMX_ADD_IO_SEG(0x00011800B0001008ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
225 	}
226 	return CVMX_ADD_IO_SEG(0x00011800B0001008ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
227 }
228 
CVMX_PCSX_RXX_STATES_REG(unsigned long offset,unsigned long block_id)229 static inline uint64_t CVMX_PCSX_RXX_STATES_REG(unsigned long offset, unsigned long block_id)
230 {
231 	switch (cvmx_get_octeon_family()) {
232 	case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
233 		return CVMX_ADD_IO_SEG(0x00011800B0001058ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
234 	case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
235 	case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
236 		return CVMX_ADD_IO_SEG(0x00011800B0001058ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
237 	case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
238 	case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
239 	case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
240 		return CVMX_ADD_IO_SEG(0x00011800B0001058ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
241 	case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
242 		return CVMX_ADD_IO_SEG(0x00011800B0001058ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
243 	}
244 	return CVMX_ADD_IO_SEG(0x00011800B0001058ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
245 }
246 
CVMX_PCSX_RXX_SYNC_REG(unsigned long offset,unsigned long block_id)247 static inline uint64_t CVMX_PCSX_RXX_SYNC_REG(unsigned long offset, unsigned long block_id)
248 {
249 	switch (cvmx_get_octeon_family()) {
250 	case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
251 		return CVMX_ADD_IO_SEG(0x00011800B0001050ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
252 	case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
253 	case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
254 		return CVMX_ADD_IO_SEG(0x00011800B0001050ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
255 	case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
256 	case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
257 	case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
258 		return CVMX_ADD_IO_SEG(0x00011800B0001050ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
259 	case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
260 		return CVMX_ADD_IO_SEG(0x00011800B0001050ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
261 	}
262 	return CVMX_ADD_IO_SEG(0x00011800B0001050ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
263 }
264 
CVMX_PCSX_SGMX_AN_ADV_REG(unsigned long offset,unsigned long block_id)265 static inline uint64_t CVMX_PCSX_SGMX_AN_ADV_REG(unsigned long offset, unsigned long block_id)
266 {
267 	switch (cvmx_get_octeon_family()) {
268 	case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
269 		return CVMX_ADD_IO_SEG(0x00011800B0001068ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
270 	case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
271 	case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
272 		return CVMX_ADD_IO_SEG(0x00011800B0001068ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
273 	case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
274 	case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
275 	case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
276 		return CVMX_ADD_IO_SEG(0x00011800B0001068ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
277 	case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
278 		return CVMX_ADD_IO_SEG(0x00011800B0001068ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
279 	}
280 	return CVMX_ADD_IO_SEG(0x00011800B0001068ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
281 }
282 
CVMX_PCSX_SGMX_LP_ADV_REG(unsigned long offset,unsigned long block_id)283 static inline uint64_t CVMX_PCSX_SGMX_LP_ADV_REG(unsigned long offset, unsigned long block_id)
284 {
285 	switch (cvmx_get_octeon_family()) {
286 	case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
287 		return CVMX_ADD_IO_SEG(0x00011800B0001070ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
288 	case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
289 	case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
290 		return CVMX_ADD_IO_SEG(0x00011800B0001070ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
291 	case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
292 	case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
293 	case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
294 		return CVMX_ADD_IO_SEG(0x00011800B0001070ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
295 	case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
296 		return CVMX_ADD_IO_SEG(0x00011800B0001070ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
297 	}
298 	return CVMX_ADD_IO_SEG(0x00011800B0001070ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
299 }
300 
CVMX_PCSX_TXX_STATES_REG(unsigned long offset,unsigned long block_id)301 static inline uint64_t CVMX_PCSX_TXX_STATES_REG(unsigned long offset, unsigned long block_id)
302 {
303 	switch (cvmx_get_octeon_family()) {
304 	case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
305 		return CVMX_ADD_IO_SEG(0x00011800B0001060ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
306 	case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
307 	case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
308 		return CVMX_ADD_IO_SEG(0x00011800B0001060ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
309 	case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
310 	case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
311 	case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
312 		return CVMX_ADD_IO_SEG(0x00011800B0001060ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
313 	case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
314 		return CVMX_ADD_IO_SEG(0x00011800B0001060ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
315 	}
316 	return CVMX_ADD_IO_SEG(0x00011800B0001060ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
317 }
318 
CVMX_PCSX_TX_RXX_POLARITY_REG(unsigned long offset,unsigned long block_id)319 static inline uint64_t CVMX_PCSX_TX_RXX_POLARITY_REG(unsigned long offset, unsigned long block_id)
320 {
321 	switch (cvmx_get_octeon_family()) {
322 	case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
323 		return CVMX_ADD_IO_SEG(0x00011800B0001048ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
324 	case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
325 	case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
326 		return CVMX_ADD_IO_SEG(0x00011800B0001048ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
327 	case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
328 	case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
329 	case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
330 		return CVMX_ADD_IO_SEG(0x00011800B0001048ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
331 	case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
332 		return CVMX_ADD_IO_SEG(0x00011800B0001048ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
333 	}
334 	return CVMX_ADD_IO_SEG(0x00011800B0001048ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
335 }
336 
337 void __cvmx_interrupt_pcsx_intx_en_reg_enable(int index, int block);
338 
339 union cvmx_pcsx_anx_adv_reg {
340 	uint64_t u64;
341 	struct cvmx_pcsx_anx_adv_reg_s {
342 #ifdef __BIG_ENDIAN_BITFIELD
343 		uint64_t reserved_16_63:48;
344 		uint64_t np:1;
345 		uint64_t reserved_14_14:1;
346 		uint64_t rem_flt:2;
347 		uint64_t reserved_9_11:3;
348 		uint64_t pause:2;
349 		uint64_t hfd:1;
350 		uint64_t fd:1;
351 		uint64_t reserved_0_4:5;
352 #else
353 		uint64_t reserved_0_4:5;
354 		uint64_t fd:1;
355 		uint64_t hfd:1;
356 		uint64_t pause:2;
357 		uint64_t reserved_9_11:3;
358 		uint64_t rem_flt:2;
359 		uint64_t reserved_14_14:1;
360 		uint64_t np:1;
361 		uint64_t reserved_16_63:48;
362 #endif
363 	} s;
364 	struct cvmx_pcsx_anx_adv_reg_s cn52xx;
365 	struct cvmx_pcsx_anx_adv_reg_s cn52xxp1;
366 	struct cvmx_pcsx_anx_adv_reg_s cn56xx;
367 	struct cvmx_pcsx_anx_adv_reg_s cn56xxp1;
368 	struct cvmx_pcsx_anx_adv_reg_s cn61xx;
369 	struct cvmx_pcsx_anx_adv_reg_s cn63xx;
370 	struct cvmx_pcsx_anx_adv_reg_s cn63xxp1;
371 	struct cvmx_pcsx_anx_adv_reg_s cn66xx;
372 	struct cvmx_pcsx_anx_adv_reg_s cn68xx;
373 	struct cvmx_pcsx_anx_adv_reg_s cn68xxp1;
374 	struct cvmx_pcsx_anx_adv_reg_s cnf71xx;
375 };
376 
377 union cvmx_pcsx_anx_ext_st_reg {
378 	uint64_t u64;
379 	struct cvmx_pcsx_anx_ext_st_reg_s {
380 #ifdef __BIG_ENDIAN_BITFIELD
381 		uint64_t reserved_16_63:48;
382 		uint64_t thou_xfd:1;
383 		uint64_t thou_xhd:1;
384 		uint64_t thou_tfd:1;
385 		uint64_t thou_thd:1;
386 		uint64_t reserved_0_11:12;
387 #else
388 		uint64_t reserved_0_11:12;
389 		uint64_t thou_thd:1;
390 		uint64_t thou_tfd:1;
391 		uint64_t thou_xhd:1;
392 		uint64_t thou_xfd:1;
393 		uint64_t reserved_16_63:48;
394 #endif
395 	} s;
396 	struct cvmx_pcsx_anx_ext_st_reg_s cn52xx;
397 	struct cvmx_pcsx_anx_ext_st_reg_s cn52xxp1;
398 	struct cvmx_pcsx_anx_ext_st_reg_s cn56xx;
399 	struct cvmx_pcsx_anx_ext_st_reg_s cn56xxp1;
400 	struct cvmx_pcsx_anx_ext_st_reg_s cn61xx;
401 	struct cvmx_pcsx_anx_ext_st_reg_s cn63xx;
402 	struct cvmx_pcsx_anx_ext_st_reg_s cn63xxp1;
403 	struct cvmx_pcsx_anx_ext_st_reg_s cn66xx;
404 	struct cvmx_pcsx_anx_ext_st_reg_s cn68xx;
405 	struct cvmx_pcsx_anx_ext_st_reg_s cn68xxp1;
406 	struct cvmx_pcsx_anx_ext_st_reg_s cnf71xx;
407 };
408 
409 union cvmx_pcsx_anx_lp_abil_reg {
410 	uint64_t u64;
411 	struct cvmx_pcsx_anx_lp_abil_reg_s {
412 #ifdef __BIG_ENDIAN_BITFIELD
413 		uint64_t reserved_16_63:48;
414 		uint64_t np:1;
415 		uint64_t ack:1;
416 		uint64_t rem_flt:2;
417 		uint64_t reserved_9_11:3;
418 		uint64_t pause:2;
419 		uint64_t hfd:1;
420 		uint64_t fd:1;
421 		uint64_t reserved_0_4:5;
422 #else
423 		uint64_t reserved_0_4:5;
424 		uint64_t fd:1;
425 		uint64_t hfd:1;
426 		uint64_t pause:2;
427 		uint64_t reserved_9_11:3;
428 		uint64_t rem_flt:2;
429 		uint64_t ack:1;
430 		uint64_t np:1;
431 		uint64_t reserved_16_63:48;
432 #endif
433 	} s;
434 	struct cvmx_pcsx_anx_lp_abil_reg_s cn52xx;
435 	struct cvmx_pcsx_anx_lp_abil_reg_s cn52xxp1;
436 	struct cvmx_pcsx_anx_lp_abil_reg_s cn56xx;
437 	struct cvmx_pcsx_anx_lp_abil_reg_s cn56xxp1;
438 	struct cvmx_pcsx_anx_lp_abil_reg_s cn61xx;
439 	struct cvmx_pcsx_anx_lp_abil_reg_s cn63xx;
440 	struct cvmx_pcsx_anx_lp_abil_reg_s cn63xxp1;
441 	struct cvmx_pcsx_anx_lp_abil_reg_s cn66xx;
442 	struct cvmx_pcsx_anx_lp_abil_reg_s cn68xx;
443 	struct cvmx_pcsx_anx_lp_abil_reg_s cn68xxp1;
444 	struct cvmx_pcsx_anx_lp_abil_reg_s cnf71xx;
445 };
446 
447 union cvmx_pcsx_anx_results_reg {
448 	uint64_t u64;
449 	struct cvmx_pcsx_anx_results_reg_s {
450 #ifdef __BIG_ENDIAN_BITFIELD
451 		uint64_t reserved_7_63:57;
452 		uint64_t pause:2;
453 		uint64_t spd:2;
454 		uint64_t an_cpt:1;
455 		uint64_t dup:1;
456 		uint64_t link_ok:1;
457 #else
458 		uint64_t link_ok:1;
459 		uint64_t dup:1;
460 		uint64_t an_cpt:1;
461 		uint64_t spd:2;
462 		uint64_t pause:2;
463 		uint64_t reserved_7_63:57;
464 #endif
465 	} s;
466 	struct cvmx_pcsx_anx_results_reg_s cn52xx;
467 	struct cvmx_pcsx_anx_results_reg_s cn52xxp1;
468 	struct cvmx_pcsx_anx_results_reg_s cn56xx;
469 	struct cvmx_pcsx_anx_results_reg_s cn56xxp1;
470 	struct cvmx_pcsx_anx_results_reg_s cn61xx;
471 	struct cvmx_pcsx_anx_results_reg_s cn63xx;
472 	struct cvmx_pcsx_anx_results_reg_s cn63xxp1;
473 	struct cvmx_pcsx_anx_results_reg_s cn66xx;
474 	struct cvmx_pcsx_anx_results_reg_s cn68xx;
475 	struct cvmx_pcsx_anx_results_reg_s cn68xxp1;
476 	struct cvmx_pcsx_anx_results_reg_s cnf71xx;
477 };
478 
479 union cvmx_pcsx_intx_en_reg {
480 	uint64_t u64;
481 	struct cvmx_pcsx_intx_en_reg_s {
482 #ifdef __BIG_ENDIAN_BITFIELD
483 		uint64_t reserved_13_63:51;
484 		uint64_t dbg_sync_en:1;
485 		uint64_t dup:1;
486 		uint64_t sync_bad_en:1;
487 		uint64_t an_bad_en:1;
488 		uint64_t rxlock_en:1;
489 		uint64_t rxbad_en:1;
490 		uint64_t rxerr_en:1;
491 		uint64_t txbad_en:1;
492 		uint64_t txfifo_en:1;
493 		uint64_t txfifu_en:1;
494 		uint64_t an_err_en:1;
495 		uint64_t xmit_en:1;
496 		uint64_t lnkspd_en:1;
497 #else
498 		uint64_t lnkspd_en:1;
499 		uint64_t xmit_en:1;
500 		uint64_t an_err_en:1;
501 		uint64_t txfifu_en:1;
502 		uint64_t txfifo_en:1;
503 		uint64_t txbad_en:1;
504 		uint64_t rxerr_en:1;
505 		uint64_t rxbad_en:1;
506 		uint64_t rxlock_en:1;
507 		uint64_t an_bad_en:1;
508 		uint64_t sync_bad_en:1;
509 		uint64_t dup:1;
510 		uint64_t dbg_sync_en:1;
511 		uint64_t reserved_13_63:51;
512 #endif
513 	} s;
514 	struct cvmx_pcsx_intx_en_reg_cn52xx {
515 #ifdef __BIG_ENDIAN_BITFIELD
516 		uint64_t reserved_12_63:52;
517 		uint64_t dup:1;
518 		uint64_t sync_bad_en:1;
519 		uint64_t an_bad_en:1;
520 		uint64_t rxlock_en:1;
521 		uint64_t rxbad_en:1;
522 		uint64_t rxerr_en:1;
523 		uint64_t txbad_en:1;
524 		uint64_t txfifo_en:1;
525 		uint64_t txfifu_en:1;
526 		uint64_t an_err_en:1;
527 		uint64_t xmit_en:1;
528 		uint64_t lnkspd_en:1;
529 #else
530 		uint64_t lnkspd_en:1;
531 		uint64_t xmit_en:1;
532 		uint64_t an_err_en:1;
533 		uint64_t txfifu_en:1;
534 		uint64_t txfifo_en:1;
535 		uint64_t txbad_en:1;
536 		uint64_t rxerr_en:1;
537 		uint64_t rxbad_en:1;
538 		uint64_t rxlock_en:1;
539 		uint64_t an_bad_en:1;
540 		uint64_t sync_bad_en:1;
541 		uint64_t dup:1;
542 		uint64_t reserved_12_63:52;
543 #endif
544 	} cn52xx;
545 	struct cvmx_pcsx_intx_en_reg_cn52xx cn52xxp1;
546 	struct cvmx_pcsx_intx_en_reg_cn52xx cn56xx;
547 	struct cvmx_pcsx_intx_en_reg_cn52xx cn56xxp1;
548 	struct cvmx_pcsx_intx_en_reg_s cn61xx;
549 	struct cvmx_pcsx_intx_en_reg_s cn63xx;
550 	struct cvmx_pcsx_intx_en_reg_s cn63xxp1;
551 	struct cvmx_pcsx_intx_en_reg_s cn66xx;
552 	struct cvmx_pcsx_intx_en_reg_s cn68xx;
553 	struct cvmx_pcsx_intx_en_reg_s cn68xxp1;
554 	struct cvmx_pcsx_intx_en_reg_s cnf71xx;
555 };
556 
557 union cvmx_pcsx_intx_reg {
558 	uint64_t u64;
559 	struct cvmx_pcsx_intx_reg_s {
560 #ifdef __BIG_ENDIAN_BITFIELD
561 		uint64_t reserved_13_63:51;
562 		uint64_t dbg_sync:1;
563 		uint64_t dup:1;
564 		uint64_t sync_bad:1;
565 		uint64_t an_bad:1;
566 		uint64_t rxlock:1;
567 		uint64_t rxbad:1;
568 		uint64_t rxerr:1;
569 		uint64_t txbad:1;
570 		uint64_t txfifo:1;
571 		uint64_t txfifu:1;
572 		uint64_t an_err:1;
573 		uint64_t xmit:1;
574 		uint64_t lnkspd:1;
575 #else
576 		uint64_t lnkspd:1;
577 		uint64_t xmit:1;
578 		uint64_t an_err:1;
579 		uint64_t txfifu:1;
580 		uint64_t txfifo:1;
581 		uint64_t txbad:1;
582 		uint64_t rxerr:1;
583 		uint64_t rxbad:1;
584 		uint64_t rxlock:1;
585 		uint64_t an_bad:1;
586 		uint64_t sync_bad:1;
587 		uint64_t dup:1;
588 		uint64_t dbg_sync:1;
589 		uint64_t reserved_13_63:51;
590 #endif
591 	} s;
592 	struct cvmx_pcsx_intx_reg_cn52xx {
593 #ifdef __BIG_ENDIAN_BITFIELD
594 		uint64_t reserved_12_63:52;
595 		uint64_t dup:1;
596 		uint64_t sync_bad:1;
597 		uint64_t an_bad:1;
598 		uint64_t rxlock:1;
599 		uint64_t rxbad:1;
600 		uint64_t rxerr:1;
601 		uint64_t txbad:1;
602 		uint64_t txfifo:1;
603 		uint64_t txfifu:1;
604 		uint64_t an_err:1;
605 		uint64_t xmit:1;
606 		uint64_t lnkspd:1;
607 #else
608 		uint64_t lnkspd:1;
609 		uint64_t xmit:1;
610 		uint64_t an_err:1;
611 		uint64_t txfifu:1;
612 		uint64_t txfifo:1;
613 		uint64_t txbad:1;
614 		uint64_t rxerr:1;
615 		uint64_t rxbad:1;
616 		uint64_t rxlock:1;
617 		uint64_t an_bad:1;
618 		uint64_t sync_bad:1;
619 		uint64_t dup:1;
620 		uint64_t reserved_12_63:52;
621 #endif
622 	} cn52xx;
623 	struct cvmx_pcsx_intx_reg_cn52xx cn52xxp1;
624 	struct cvmx_pcsx_intx_reg_cn52xx cn56xx;
625 	struct cvmx_pcsx_intx_reg_cn52xx cn56xxp1;
626 	struct cvmx_pcsx_intx_reg_s cn61xx;
627 	struct cvmx_pcsx_intx_reg_s cn63xx;
628 	struct cvmx_pcsx_intx_reg_s cn63xxp1;
629 	struct cvmx_pcsx_intx_reg_s cn66xx;
630 	struct cvmx_pcsx_intx_reg_s cn68xx;
631 	struct cvmx_pcsx_intx_reg_s cn68xxp1;
632 	struct cvmx_pcsx_intx_reg_s cnf71xx;
633 };
634 
635 union cvmx_pcsx_linkx_timer_count_reg {
636 	uint64_t u64;
637 	struct cvmx_pcsx_linkx_timer_count_reg_s {
638 #ifdef __BIG_ENDIAN_BITFIELD
639 		uint64_t reserved_16_63:48;
640 		uint64_t count:16;
641 #else
642 		uint64_t count:16;
643 		uint64_t reserved_16_63:48;
644 #endif
645 	} s;
646 	struct cvmx_pcsx_linkx_timer_count_reg_s cn52xx;
647 	struct cvmx_pcsx_linkx_timer_count_reg_s cn52xxp1;
648 	struct cvmx_pcsx_linkx_timer_count_reg_s cn56xx;
649 	struct cvmx_pcsx_linkx_timer_count_reg_s cn56xxp1;
650 	struct cvmx_pcsx_linkx_timer_count_reg_s cn61xx;
651 	struct cvmx_pcsx_linkx_timer_count_reg_s cn63xx;
652 	struct cvmx_pcsx_linkx_timer_count_reg_s cn63xxp1;
653 	struct cvmx_pcsx_linkx_timer_count_reg_s cn66xx;
654 	struct cvmx_pcsx_linkx_timer_count_reg_s cn68xx;
655 	struct cvmx_pcsx_linkx_timer_count_reg_s cn68xxp1;
656 	struct cvmx_pcsx_linkx_timer_count_reg_s cnf71xx;
657 };
658 
659 union cvmx_pcsx_log_anlx_reg {
660 	uint64_t u64;
661 	struct cvmx_pcsx_log_anlx_reg_s {
662 #ifdef __BIG_ENDIAN_BITFIELD
663 		uint64_t reserved_4_63:60;
664 		uint64_t lafifovfl:1;
665 		uint64_t la_en:1;
666 		uint64_t pkt_sz:2;
667 #else
668 		uint64_t pkt_sz:2;
669 		uint64_t la_en:1;
670 		uint64_t lafifovfl:1;
671 		uint64_t reserved_4_63:60;
672 #endif
673 	} s;
674 	struct cvmx_pcsx_log_anlx_reg_s cn52xx;
675 	struct cvmx_pcsx_log_anlx_reg_s cn52xxp1;
676 	struct cvmx_pcsx_log_anlx_reg_s cn56xx;
677 	struct cvmx_pcsx_log_anlx_reg_s cn56xxp1;
678 	struct cvmx_pcsx_log_anlx_reg_s cn61xx;
679 	struct cvmx_pcsx_log_anlx_reg_s cn63xx;
680 	struct cvmx_pcsx_log_anlx_reg_s cn63xxp1;
681 	struct cvmx_pcsx_log_anlx_reg_s cn66xx;
682 	struct cvmx_pcsx_log_anlx_reg_s cn68xx;
683 	struct cvmx_pcsx_log_anlx_reg_s cn68xxp1;
684 	struct cvmx_pcsx_log_anlx_reg_s cnf71xx;
685 };
686 
687 union cvmx_pcsx_miscx_ctl_reg {
688 	uint64_t u64;
689 	struct cvmx_pcsx_miscx_ctl_reg_s {
690 #ifdef __BIG_ENDIAN_BITFIELD
691 		uint64_t reserved_13_63:51;
692 		uint64_t sgmii:1;
693 		uint64_t gmxeno:1;
694 		uint64_t loopbck2:1;
695 		uint64_t mac_phy:1;
696 		uint64_t mode:1;
697 		uint64_t an_ovrd:1;
698 		uint64_t samp_pt:7;
699 #else
700 		uint64_t samp_pt:7;
701 		uint64_t an_ovrd:1;
702 		uint64_t mode:1;
703 		uint64_t mac_phy:1;
704 		uint64_t loopbck2:1;
705 		uint64_t gmxeno:1;
706 		uint64_t sgmii:1;
707 		uint64_t reserved_13_63:51;
708 #endif
709 	} s;
710 	struct cvmx_pcsx_miscx_ctl_reg_s cn52xx;
711 	struct cvmx_pcsx_miscx_ctl_reg_s cn52xxp1;
712 	struct cvmx_pcsx_miscx_ctl_reg_s cn56xx;
713 	struct cvmx_pcsx_miscx_ctl_reg_s cn56xxp1;
714 	struct cvmx_pcsx_miscx_ctl_reg_s cn61xx;
715 	struct cvmx_pcsx_miscx_ctl_reg_s cn63xx;
716 	struct cvmx_pcsx_miscx_ctl_reg_s cn63xxp1;
717 	struct cvmx_pcsx_miscx_ctl_reg_s cn66xx;
718 	struct cvmx_pcsx_miscx_ctl_reg_s cn68xx;
719 	struct cvmx_pcsx_miscx_ctl_reg_s cn68xxp1;
720 	struct cvmx_pcsx_miscx_ctl_reg_s cnf71xx;
721 };
722 
723 union cvmx_pcsx_mrx_control_reg {
724 	uint64_t u64;
725 	struct cvmx_pcsx_mrx_control_reg_s {
726 #ifdef __BIG_ENDIAN_BITFIELD
727 		uint64_t reserved_16_63:48;
728 		uint64_t reset:1;
729 		uint64_t loopbck1:1;
730 		uint64_t spdlsb:1;
731 		uint64_t an_en:1;
732 		uint64_t pwr_dn:1;
733 		uint64_t reserved_10_10:1;
734 		uint64_t rst_an:1;
735 		uint64_t dup:1;
736 		uint64_t coltst:1;
737 		uint64_t spdmsb:1;
738 		uint64_t uni:1;
739 		uint64_t reserved_0_4:5;
740 #else
741 		uint64_t reserved_0_4:5;
742 		uint64_t uni:1;
743 		uint64_t spdmsb:1;
744 		uint64_t coltst:1;
745 		uint64_t dup:1;
746 		uint64_t rst_an:1;
747 		uint64_t reserved_10_10:1;
748 		uint64_t pwr_dn:1;
749 		uint64_t an_en:1;
750 		uint64_t spdlsb:1;
751 		uint64_t loopbck1:1;
752 		uint64_t reset:1;
753 		uint64_t reserved_16_63:48;
754 #endif
755 	} s;
756 	struct cvmx_pcsx_mrx_control_reg_s cn52xx;
757 	struct cvmx_pcsx_mrx_control_reg_s cn52xxp1;
758 	struct cvmx_pcsx_mrx_control_reg_s cn56xx;
759 	struct cvmx_pcsx_mrx_control_reg_s cn56xxp1;
760 	struct cvmx_pcsx_mrx_control_reg_s cn61xx;
761 	struct cvmx_pcsx_mrx_control_reg_s cn63xx;
762 	struct cvmx_pcsx_mrx_control_reg_s cn63xxp1;
763 	struct cvmx_pcsx_mrx_control_reg_s cn66xx;
764 	struct cvmx_pcsx_mrx_control_reg_s cn68xx;
765 	struct cvmx_pcsx_mrx_control_reg_s cn68xxp1;
766 	struct cvmx_pcsx_mrx_control_reg_s cnf71xx;
767 };
768 
769 union cvmx_pcsx_mrx_status_reg {
770 	uint64_t u64;
771 	struct cvmx_pcsx_mrx_status_reg_s {
772 #ifdef __BIG_ENDIAN_BITFIELD
773 		uint64_t reserved_16_63:48;
774 		uint64_t hun_t4:1;
775 		uint64_t hun_xfd:1;
776 		uint64_t hun_xhd:1;
777 		uint64_t ten_fd:1;
778 		uint64_t ten_hd:1;
779 		uint64_t hun_t2fd:1;
780 		uint64_t hun_t2hd:1;
781 		uint64_t ext_st:1;
782 		uint64_t reserved_7_7:1;
783 		uint64_t prb_sup:1;
784 		uint64_t an_cpt:1;
785 		uint64_t rm_flt:1;
786 		uint64_t an_abil:1;
787 		uint64_t lnk_st:1;
788 		uint64_t reserved_1_1:1;
789 		uint64_t extnd:1;
790 #else
791 		uint64_t extnd:1;
792 		uint64_t reserved_1_1:1;
793 		uint64_t lnk_st:1;
794 		uint64_t an_abil:1;
795 		uint64_t rm_flt:1;
796 		uint64_t an_cpt:1;
797 		uint64_t prb_sup:1;
798 		uint64_t reserved_7_7:1;
799 		uint64_t ext_st:1;
800 		uint64_t hun_t2hd:1;
801 		uint64_t hun_t2fd:1;
802 		uint64_t ten_hd:1;
803 		uint64_t ten_fd:1;
804 		uint64_t hun_xhd:1;
805 		uint64_t hun_xfd:1;
806 		uint64_t hun_t4:1;
807 		uint64_t reserved_16_63:48;
808 #endif
809 	} s;
810 	struct cvmx_pcsx_mrx_status_reg_s cn52xx;
811 	struct cvmx_pcsx_mrx_status_reg_s cn52xxp1;
812 	struct cvmx_pcsx_mrx_status_reg_s cn56xx;
813 	struct cvmx_pcsx_mrx_status_reg_s cn56xxp1;
814 	struct cvmx_pcsx_mrx_status_reg_s cn61xx;
815 	struct cvmx_pcsx_mrx_status_reg_s cn63xx;
816 	struct cvmx_pcsx_mrx_status_reg_s cn63xxp1;
817 	struct cvmx_pcsx_mrx_status_reg_s cn66xx;
818 	struct cvmx_pcsx_mrx_status_reg_s cn68xx;
819 	struct cvmx_pcsx_mrx_status_reg_s cn68xxp1;
820 	struct cvmx_pcsx_mrx_status_reg_s cnf71xx;
821 };
822 
823 union cvmx_pcsx_rxx_states_reg {
824 	uint64_t u64;
825 	struct cvmx_pcsx_rxx_states_reg_s {
826 #ifdef __BIG_ENDIAN_BITFIELD
827 		uint64_t reserved_16_63:48;
828 		uint64_t rx_bad:1;
829 		uint64_t rx_st:5;
830 		uint64_t sync_bad:1;
831 		uint64_t sync:4;
832 		uint64_t an_bad:1;
833 		uint64_t an_st:4;
834 #else
835 		uint64_t an_st:4;
836 		uint64_t an_bad:1;
837 		uint64_t sync:4;
838 		uint64_t sync_bad:1;
839 		uint64_t rx_st:5;
840 		uint64_t rx_bad:1;
841 		uint64_t reserved_16_63:48;
842 #endif
843 	} s;
844 	struct cvmx_pcsx_rxx_states_reg_s cn52xx;
845 	struct cvmx_pcsx_rxx_states_reg_s cn52xxp1;
846 	struct cvmx_pcsx_rxx_states_reg_s cn56xx;
847 	struct cvmx_pcsx_rxx_states_reg_s cn56xxp1;
848 	struct cvmx_pcsx_rxx_states_reg_s cn61xx;
849 	struct cvmx_pcsx_rxx_states_reg_s cn63xx;
850 	struct cvmx_pcsx_rxx_states_reg_s cn63xxp1;
851 	struct cvmx_pcsx_rxx_states_reg_s cn66xx;
852 	struct cvmx_pcsx_rxx_states_reg_s cn68xx;
853 	struct cvmx_pcsx_rxx_states_reg_s cn68xxp1;
854 	struct cvmx_pcsx_rxx_states_reg_s cnf71xx;
855 };
856 
857 union cvmx_pcsx_rxx_sync_reg {
858 	uint64_t u64;
859 	struct cvmx_pcsx_rxx_sync_reg_s {
860 #ifdef __BIG_ENDIAN_BITFIELD
861 		uint64_t reserved_2_63:62;
862 		uint64_t sync:1;
863 		uint64_t bit_lock:1;
864 #else
865 		uint64_t bit_lock:1;
866 		uint64_t sync:1;
867 		uint64_t reserved_2_63:62;
868 #endif
869 	} s;
870 	struct cvmx_pcsx_rxx_sync_reg_s cn52xx;
871 	struct cvmx_pcsx_rxx_sync_reg_s cn52xxp1;
872 	struct cvmx_pcsx_rxx_sync_reg_s cn56xx;
873 	struct cvmx_pcsx_rxx_sync_reg_s cn56xxp1;
874 	struct cvmx_pcsx_rxx_sync_reg_s cn61xx;
875 	struct cvmx_pcsx_rxx_sync_reg_s cn63xx;
876 	struct cvmx_pcsx_rxx_sync_reg_s cn63xxp1;
877 	struct cvmx_pcsx_rxx_sync_reg_s cn66xx;
878 	struct cvmx_pcsx_rxx_sync_reg_s cn68xx;
879 	struct cvmx_pcsx_rxx_sync_reg_s cn68xxp1;
880 	struct cvmx_pcsx_rxx_sync_reg_s cnf71xx;
881 };
882 
883 union cvmx_pcsx_sgmx_an_adv_reg {
884 	uint64_t u64;
885 	struct cvmx_pcsx_sgmx_an_adv_reg_s {
886 #ifdef __BIG_ENDIAN_BITFIELD
887 		uint64_t reserved_16_63:48;
888 		uint64_t link:1;
889 		uint64_t ack:1;
890 		uint64_t reserved_13_13:1;
891 		uint64_t dup:1;
892 		uint64_t speed:2;
893 		uint64_t reserved_1_9:9;
894 		uint64_t one:1;
895 #else
896 		uint64_t one:1;
897 		uint64_t reserved_1_9:9;
898 		uint64_t speed:2;
899 		uint64_t dup:1;
900 		uint64_t reserved_13_13:1;
901 		uint64_t ack:1;
902 		uint64_t link:1;
903 		uint64_t reserved_16_63:48;
904 #endif
905 	} s;
906 	struct cvmx_pcsx_sgmx_an_adv_reg_s cn52xx;
907 	struct cvmx_pcsx_sgmx_an_adv_reg_s cn52xxp1;
908 	struct cvmx_pcsx_sgmx_an_adv_reg_s cn56xx;
909 	struct cvmx_pcsx_sgmx_an_adv_reg_s cn56xxp1;
910 	struct cvmx_pcsx_sgmx_an_adv_reg_s cn61xx;
911 	struct cvmx_pcsx_sgmx_an_adv_reg_s cn63xx;
912 	struct cvmx_pcsx_sgmx_an_adv_reg_s cn63xxp1;
913 	struct cvmx_pcsx_sgmx_an_adv_reg_s cn66xx;
914 	struct cvmx_pcsx_sgmx_an_adv_reg_s cn68xx;
915 	struct cvmx_pcsx_sgmx_an_adv_reg_s cn68xxp1;
916 	struct cvmx_pcsx_sgmx_an_adv_reg_s cnf71xx;
917 };
918 
919 union cvmx_pcsx_sgmx_lp_adv_reg {
920 	uint64_t u64;
921 	struct cvmx_pcsx_sgmx_lp_adv_reg_s {
922 #ifdef __BIG_ENDIAN_BITFIELD
923 		uint64_t reserved_16_63:48;
924 		uint64_t link:1;
925 		uint64_t reserved_13_14:2;
926 		uint64_t dup:1;
927 		uint64_t speed:2;
928 		uint64_t reserved_1_9:9;
929 		uint64_t one:1;
930 #else
931 		uint64_t one:1;
932 		uint64_t reserved_1_9:9;
933 		uint64_t speed:2;
934 		uint64_t dup:1;
935 		uint64_t reserved_13_14:2;
936 		uint64_t link:1;
937 		uint64_t reserved_16_63:48;
938 #endif
939 	} s;
940 	struct cvmx_pcsx_sgmx_lp_adv_reg_s cn52xx;
941 	struct cvmx_pcsx_sgmx_lp_adv_reg_s cn52xxp1;
942 	struct cvmx_pcsx_sgmx_lp_adv_reg_s cn56xx;
943 	struct cvmx_pcsx_sgmx_lp_adv_reg_s cn56xxp1;
944 	struct cvmx_pcsx_sgmx_lp_adv_reg_s cn61xx;
945 	struct cvmx_pcsx_sgmx_lp_adv_reg_s cn63xx;
946 	struct cvmx_pcsx_sgmx_lp_adv_reg_s cn63xxp1;
947 	struct cvmx_pcsx_sgmx_lp_adv_reg_s cn66xx;
948 	struct cvmx_pcsx_sgmx_lp_adv_reg_s cn68xx;
949 	struct cvmx_pcsx_sgmx_lp_adv_reg_s cn68xxp1;
950 	struct cvmx_pcsx_sgmx_lp_adv_reg_s cnf71xx;
951 };
952 
953 union cvmx_pcsx_txx_states_reg {
954 	uint64_t u64;
955 	struct cvmx_pcsx_txx_states_reg_s {
956 #ifdef __BIG_ENDIAN_BITFIELD
957 		uint64_t reserved_7_63:57;
958 		uint64_t xmit:2;
959 		uint64_t tx_bad:1;
960 		uint64_t ord_st:4;
961 #else
962 		uint64_t ord_st:4;
963 		uint64_t tx_bad:1;
964 		uint64_t xmit:2;
965 		uint64_t reserved_7_63:57;
966 #endif
967 	} s;
968 	struct cvmx_pcsx_txx_states_reg_s cn52xx;
969 	struct cvmx_pcsx_txx_states_reg_s cn52xxp1;
970 	struct cvmx_pcsx_txx_states_reg_s cn56xx;
971 	struct cvmx_pcsx_txx_states_reg_s cn56xxp1;
972 	struct cvmx_pcsx_txx_states_reg_s cn61xx;
973 	struct cvmx_pcsx_txx_states_reg_s cn63xx;
974 	struct cvmx_pcsx_txx_states_reg_s cn63xxp1;
975 	struct cvmx_pcsx_txx_states_reg_s cn66xx;
976 	struct cvmx_pcsx_txx_states_reg_s cn68xx;
977 	struct cvmx_pcsx_txx_states_reg_s cn68xxp1;
978 	struct cvmx_pcsx_txx_states_reg_s cnf71xx;
979 };
980 
981 union cvmx_pcsx_tx_rxx_polarity_reg {
982 	uint64_t u64;
983 	struct cvmx_pcsx_tx_rxx_polarity_reg_s {
984 #ifdef __BIG_ENDIAN_BITFIELD
985 		uint64_t reserved_4_63:60;
986 		uint64_t rxovrd:1;
987 		uint64_t autorxpl:1;
988 		uint64_t rxplrt:1;
989 		uint64_t txplrt:1;
990 #else
991 		uint64_t txplrt:1;
992 		uint64_t rxplrt:1;
993 		uint64_t autorxpl:1;
994 		uint64_t rxovrd:1;
995 		uint64_t reserved_4_63:60;
996 #endif
997 	} s;
998 	struct cvmx_pcsx_tx_rxx_polarity_reg_s cn52xx;
999 	struct cvmx_pcsx_tx_rxx_polarity_reg_s cn52xxp1;
1000 	struct cvmx_pcsx_tx_rxx_polarity_reg_s cn56xx;
1001 	struct cvmx_pcsx_tx_rxx_polarity_reg_s cn56xxp1;
1002 	struct cvmx_pcsx_tx_rxx_polarity_reg_s cn61xx;
1003 	struct cvmx_pcsx_tx_rxx_polarity_reg_s cn63xx;
1004 	struct cvmx_pcsx_tx_rxx_polarity_reg_s cn63xxp1;
1005 	struct cvmx_pcsx_tx_rxx_polarity_reg_s cn66xx;
1006 	struct cvmx_pcsx_tx_rxx_polarity_reg_s cn68xx;
1007 	struct cvmx_pcsx_tx_rxx_polarity_reg_s cn68xxp1;
1008 	struct cvmx_pcsx_tx_rxx_polarity_reg_s cnf71xx;
1009 };
1010 
1011 #endif
1012