1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /* Copyright(c) 2018-2019 Realtek Corporation
3 */
4
5 #ifndef __RTK_MAIN_H_
6 #define __RTK_MAIN_H_
7
8 #include <net/mac80211.h>
9 #include <linux/vmalloc.h>
10 #include <linux/firmware.h>
11 #include <linux/average.h>
12 #include <linux/bitops.h>
13 #include <linux/bitfield.h>
14 #include <linux/iopoll.h>
15 #include <linux/interrupt.h>
16 #include <linux/workqueue.h>
17
18 #include "util.h"
19
20 #define RTW_MAX_MAC_ID_NUM 32
21 #define RTW_MAX_SEC_CAM_NUM 32
22 #define MAX_PG_CAM_BACKUP_NUM 8
23
24 #define RTW_SCAN_MAX_SSIDS 4
25
26 #define RTW_MAX_PATTERN_NUM 12
27 #define RTW_MAX_PATTERN_MASK_SIZE 16
28 #define RTW_MAX_PATTERN_SIZE 128
29
30 #define RTW_WATCH_DOG_DELAY_TIME round_jiffies_relative(HZ * 2)
31
32 #define RFREG_MASK 0xfffff
33 #define INV_RF_DATA 0xffffffff
34 #define TX_PAGE_SIZE_SHIFT 7
35 #define TX_PAGE_SIZE (1 << TX_PAGE_SIZE_SHIFT)
36
37 #define RTW_CHANNEL_WIDTH_MAX 3
38 #define RTW_RF_PATH_MAX 4
39 #define HW_FEATURE_LEN 13
40
41 #define RTW_TP_SHIFT 18 /* bytes/2s --> Mbps */
42
43 extern bool rtw_bf_support;
44 extern bool rtw_disable_lps_deep_mode;
45 extern unsigned int rtw_debug_mask;
46 extern bool rtw_edcca_enabled;
47 extern const struct ieee80211_ops rtw_ops;
48
49 #define RTW_MAX_CHANNEL_NUM_2G 14
50 #define RTW_MAX_CHANNEL_NUM_5G 49
51
52 struct rtw_dev;
53
54 enum rtw_hci_type {
55 RTW_HCI_TYPE_PCIE,
56 RTW_HCI_TYPE_USB,
57 RTW_HCI_TYPE_SDIO,
58
59 RTW_HCI_TYPE_UNDEFINE,
60 };
61
62 struct rtw_hci {
63 struct rtw_hci_ops *ops;
64 enum rtw_hci_type type;
65
66 u32 rpwm_addr;
67 u32 cpwm_addr;
68
69 u8 bulkout_num;
70 };
71
72 #define IS_CH_5G_BAND_1(channel) ((channel) >= 36 && (channel <= 48))
73 #define IS_CH_5G_BAND_2(channel) ((channel) >= 52 && (channel <= 64))
74 #define IS_CH_5G_BAND_3(channel) ((channel) >= 100 && (channel <= 144))
75 #define IS_CH_5G_BAND_4(channel) ((channel) >= 149 && (channel <= 177))
76
77 #define IS_CH_5G_BAND_MID(channel) \
78 (IS_CH_5G_BAND_2(channel) || IS_CH_5G_BAND_3(channel))
79
80 #define IS_CH_2G_BAND(channel) ((channel) <= 14)
81 #define IS_CH_5G_BAND(channel) \
82 (IS_CH_5G_BAND_1(channel) || IS_CH_5G_BAND_2(channel) || \
83 IS_CH_5G_BAND_3(channel) || IS_CH_5G_BAND_4(channel))
84
85 enum rtw_supported_band {
86 RTW_BAND_2G = BIT(NL80211_BAND_2GHZ),
87 RTW_BAND_5G = BIT(NL80211_BAND_5GHZ),
88 RTW_BAND_60G = BIT(NL80211_BAND_60GHZ),
89 };
90
91 /* now, support upto 80M bw */
92 #define RTW_MAX_CHANNEL_WIDTH RTW_CHANNEL_WIDTH_80
93
94 enum rtw_bandwidth {
95 RTW_CHANNEL_WIDTH_20 = 0,
96 RTW_CHANNEL_WIDTH_40 = 1,
97 RTW_CHANNEL_WIDTH_80 = 2,
98 RTW_CHANNEL_WIDTH_160 = 3,
99 RTW_CHANNEL_WIDTH_80_80 = 4,
100 RTW_CHANNEL_WIDTH_5 = 5,
101 RTW_CHANNEL_WIDTH_10 = 6,
102 };
103
104 enum rtw_sc_offset {
105 RTW_SC_DONT_CARE = 0,
106 RTW_SC_20_UPPER = 1,
107 RTW_SC_20_LOWER = 2,
108 RTW_SC_20_UPMOST = 3,
109 RTW_SC_20_LOWEST = 4,
110 RTW_SC_40_UPPER = 9,
111 RTW_SC_40_LOWER = 10,
112 };
113
114 enum rtw_net_type {
115 RTW_NET_NO_LINK = 0,
116 RTW_NET_AD_HOC = 1,
117 RTW_NET_MGD_LINKED = 2,
118 RTW_NET_AP_MODE = 3,
119 };
120
121 enum rtw_rf_type {
122 RF_1T1R = 0,
123 RF_1T2R = 1,
124 RF_2T2R = 2,
125 RF_2T3R = 3,
126 RF_2T4R = 4,
127 RF_3T3R = 5,
128 RF_3T4R = 6,
129 RF_4T4R = 7,
130 RF_TYPE_MAX,
131 };
132
133 enum rtw_rf_path {
134 RF_PATH_A = 0,
135 RF_PATH_B = 1,
136 RF_PATH_C = 2,
137 RF_PATH_D = 3,
138 };
139
140 enum rtw_bb_path {
141 BB_PATH_A = BIT(0),
142 BB_PATH_B = BIT(1),
143 BB_PATH_C = BIT(2),
144 BB_PATH_D = BIT(3),
145
146 BB_PATH_AB = (BB_PATH_A | BB_PATH_B),
147 BB_PATH_AC = (BB_PATH_A | BB_PATH_C),
148 BB_PATH_AD = (BB_PATH_A | BB_PATH_D),
149 BB_PATH_BC = (BB_PATH_B | BB_PATH_C),
150 BB_PATH_BD = (BB_PATH_B | BB_PATH_D),
151 BB_PATH_CD = (BB_PATH_C | BB_PATH_D),
152
153 BB_PATH_ABC = (BB_PATH_A | BB_PATH_B | BB_PATH_C),
154 BB_PATH_ABD = (BB_PATH_A | BB_PATH_B | BB_PATH_D),
155 BB_PATH_ACD = (BB_PATH_A | BB_PATH_C | BB_PATH_D),
156 BB_PATH_BCD = (BB_PATH_B | BB_PATH_C | BB_PATH_D),
157
158 BB_PATH_ABCD = (BB_PATH_A | BB_PATH_B | BB_PATH_C | BB_PATH_D),
159 };
160
161 enum rtw_rate_section {
162 RTW_RATE_SECTION_CCK = 0,
163 RTW_RATE_SECTION_OFDM,
164 RTW_RATE_SECTION_HT_1S,
165 RTW_RATE_SECTION_HT_2S,
166 RTW_RATE_SECTION_VHT_1S,
167 RTW_RATE_SECTION_VHT_2S,
168
169 /* keep last */
170 RTW_RATE_SECTION_MAX,
171 };
172
173 enum rtw_wireless_set {
174 WIRELESS_CCK = 0x00000001,
175 WIRELESS_OFDM = 0x00000002,
176 WIRELESS_HT = 0x00000004,
177 WIRELESS_VHT = 0x00000008,
178 };
179
180 #define HT_STBC_EN BIT(0)
181 #define VHT_STBC_EN BIT(1)
182 #define HT_LDPC_EN BIT(0)
183 #define VHT_LDPC_EN BIT(1)
184
185 enum rtw_chip_type {
186 RTW_CHIP_TYPE_8822B,
187 RTW_CHIP_TYPE_8822C,
188 RTW_CHIP_TYPE_8723D,
189 RTW_CHIP_TYPE_8821C,
190 };
191
192 enum rtw_tx_queue_type {
193 /* the order of AC queues matters */
194 RTW_TX_QUEUE_BK = 0x0,
195 RTW_TX_QUEUE_BE = 0x1,
196 RTW_TX_QUEUE_VI = 0x2,
197 RTW_TX_QUEUE_VO = 0x3,
198
199 RTW_TX_QUEUE_BCN = 0x4,
200 RTW_TX_QUEUE_MGMT = 0x5,
201 RTW_TX_QUEUE_HI0 = 0x6,
202 RTW_TX_QUEUE_H2C = 0x7,
203 /* keep it last */
204 RTK_MAX_TX_QUEUE_NUM
205 };
206
207 enum rtw_rx_queue_type {
208 RTW_RX_QUEUE_MPDU = 0x0,
209 RTW_RX_QUEUE_C2H = 0x1,
210 /* keep it last */
211 RTK_MAX_RX_QUEUE_NUM
212 };
213
214 enum rtw_fw_type {
215 RTW_NORMAL_FW = 0x0,
216 RTW_WOWLAN_FW = 0x1,
217 };
218
219 enum rtw_rate_index {
220 RTW_RATEID_BGN_40M_2SS = 0,
221 RTW_RATEID_BGN_40M_1SS = 1,
222 RTW_RATEID_BGN_20M_2SS = 2,
223 RTW_RATEID_BGN_20M_1SS = 3,
224 RTW_RATEID_GN_N2SS = 4,
225 RTW_RATEID_GN_N1SS = 5,
226 RTW_RATEID_BG = 6,
227 RTW_RATEID_G = 7,
228 RTW_RATEID_B_20M = 8,
229 RTW_RATEID_ARFR0_AC_2SS = 9,
230 RTW_RATEID_ARFR1_AC_1SS = 10,
231 RTW_RATEID_ARFR2_AC_2G_1SS = 11,
232 RTW_RATEID_ARFR3_AC_2G_2SS = 12,
233 RTW_RATEID_ARFR4_AC_3SS = 13,
234 RTW_RATEID_ARFR5_N_3SS = 14,
235 RTW_RATEID_ARFR7_N_4SS = 15,
236 RTW_RATEID_ARFR6_AC_4SS = 16
237 };
238
239 enum rtw_trx_desc_rate {
240 DESC_RATE1M = 0x00,
241 DESC_RATE2M = 0x01,
242 DESC_RATE5_5M = 0x02,
243 DESC_RATE11M = 0x03,
244
245 DESC_RATE6M = 0x04,
246 DESC_RATE9M = 0x05,
247 DESC_RATE12M = 0x06,
248 DESC_RATE18M = 0x07,
249 DESC_RATE24M = 0x08,
250 DESC_RATE36M = 0x09,
251 DESC_RATE48M = 0x0a,
252 DESC_RATE54M = 0x0b,
253
254 DESC_RATEMCS0 = 0x0c,
255 DESC_RATEMCS1 = 0x0d,
256 DESC_RATEMCS2 = 0x0e,
257 DESC_RATEMCS3 = 0x0f,
258 DESC_RATEMCS4 = 0x10,
259 DESC_RATEMCS5 = 0x11,
260 DESC_RATEMCS6 = 0x12,
261 DESC_RATEMCS7 = 0x13,
262 DESC_RATEMCS8 = 0x14,
263 DESC_RATEMCS9 = 0x15,
264 DESC_RATEMCS10 = 0x16,
265 DESC_RATEMCS11 = 0x17,
266 DESC_RATEMCS12 = 0x18,
267 DESC_RATEMCS13 = 0x19,
268 DESC_RATEMCS14 = 0x1a,
269 DESC_RATEMCS15 = 0x1b,
270 DESC_RATEMCS16 = 0x1c,
271 DESC_RATEMCS17 = 0x1d,
272 DESC_RATEMCS18 = 0x1e,
273 DESC_RATEMCS19 = 0x1f,
274 DESC_RATEMCS20 = 0x20,
275 DESC_RATEMCS21 = 0x21,
276 DESC_RATEMCS22 = 0x22,
277 DESC_RATEMCS23 = 0x23,
278 DESC_RATEMCS24 = 0x24,
279 DESC_RATEMCS25 = 0x25,
280 DESC_RATEMCS26 = 0x26,
281 DESC_RATEMCS27 = 0x27,
282 DESC_RATEMCS28 = 0x28,
283 DESC_RATEMCS29 = 0x29,
284 DESC_RATEMCS30 = 0x2a,
285 DESC_RATEMCS31 = 0x2b,
286
287 DESC_RATEVHT1SS_MCS0 = 0x2c,
288 DESC_RATEVHT1SS_MCS1 = 0x2d,
289 DESC_RATEVHT1SS_MCS2 = 0x2e,
290 DESC_RATEVHT1SS_MCS3 = 0x2f,
291 DESC_RATEVHT1SS_MCS4 = 0x30,
292 DESC_RATEVHT1SS_MCS5 = 0x31,
293 DESC_RATEVHT1SS_MCS6 = 0x32,
294 DESC_RATEVHT1SS_MCS7 = 0x33,
295 DESC_RATEVHT1SS_MCS8 = 0x34,
296 DESC_RATEVHT1SS_MCS9 = 0x35,
297
298 DESC_RATEVHT2SS_MCS0 = 0x36,
299 DESC_RATEVHT2SS_MCS1 = 0x37,
300 DESC_RATEVHT2SS_MCS2 = 0x38,
301 DESC_RATEVHT2SS_MCS3 = 0x39,
302 DESC_RATEVHT2SS_MCS4 = 0x3a,
303 DESC_RATEVHT2SS_MCS5 = 0x3b,
304 DESC_RATEVHT2SS_MCS6 = 0x3c,
305 DESC_RATEVHT2SS_MCS7 = 0x3d,
306 DESC_RATEVHT2SS_MCS8 = 0x3e,
307 DESC_RATEVHT2SS_MCS9 = 0x3f,
308
309 DESC_RATEVHT3SS_MCS0 = 0x40,
310 DESC_RATEVHT3SS_MCS1 = 0x41,
311 DESC_RATEVHT3SS_MCS2 = 0x42,
312 DESC_RATEVHT3SS_MCS3 = 0x43,
313 DESC_RATEVHT3SS_MCS4 = 0x44,
314 DESC_RATEVHT3SS_MCS5 = 0x45,
315 DESC_RATEVHT3SS_MCS6 = 0x46,
316 DESC_RATEVHT3SS_MCS7 = 0x47,
317 DESC_RATEVHT3SS_MCS8 = 0x48,
318 DESC_RATEVHT3SS_MCS9 = 0x49,
319
320 DESC_RATEVHT4SS_MCS0 = 0x4a,
321 DESC_RATEVHT4SS_MCS1 = 0x4b,
322 DESC_RATEVHT4SS_MCS2 = 0x4c,
323 DESC_RATEVHT4SS_MCS3 = 0x4d,
324 DESC_RATEVHT4SS_MCS4 = 0x4e,
325 DESC_RATEVHT4SS_MCS5 = 0x4f,
326 DESC_RATEVHT4SS_MCS6 = 0x50,
327 DESC_RATEVHT4SS_MCS7 = 0x51,
328 DESC_RATEVHT4SS_MCS8 = 0x52,
329 DESC_RATEVHT4SS_MCS9 = 0x53,
330
331 DESC_RATE_MAX,
332 };
333
334 enum rtw_regulatory_domains {
335 RTW_REGD_FCC = 0,
336 RTW_REGD_MKK = 1,
337 RTW_REGD_ETSI = 2,
338 RTW_REGD_IC = 3,
339 RTW_REGD_KCC = 4,
340 RTW_REGD_ACMA = 5,
341 RTW_REGD_CHILE = 6,
342 RTW_REGD_UKRAINE = 7,
343 RTW_REGD_MEXICO = 8,
344 RTW_REGD_CN = 9,
345 RTW_REGD_WW,
346
347 RTW_REGD_MAX
348 };
349
350 enum rtw_txq_flags {
351 RTW_TXQ_AMPDU,
352 RTW_TXQ_BLOCK_BA,
353 };
354
355 enum rtw_flags {
356 RTW_FLAG_RUNNING,
357 RTW_FLAG_FW_RUNNING,
358 RTW_FLAG_SCANNING,
359 RTW_FLAG_INACTIVE_PS,
360 RTW_FLAG_LEISURE_PS,
361 RTW_FLAG_LEISURE_PS_DEEP,
362 RTW_FLAG_DIG_DISABLE,
363 RTW_FLAG_BUSY_TRAFFIC,
364 RTW_FLAG_WOWLAN,
365 RTW_FLAG_RESTARTING,
366 RTW_FLAG_RESTART_TRIGGERING,
367 RTW_FLAG_FORCE_LOWEST_RATE,
368
369 NUM_OF_RTW_FLAGS,
370 };
371
372 enum rtw_evm {
373 RTW_EVM_OFDM = 0,
374 RTW_EVM_1SS,
375 RTW_EVM_2SS_A,
376 RTW_EVM_2SS_B,
377 /* keep it last */
378 RTW_EVM_NUM
379 };
380
381 enum rtw_snr {
382 RTW_SNR_OFDM_A = 0,
383 RTW_SNR_OFDM_B,
384 RTW_SNR_OFDM_C,
385 RTW_SNR_OFDM_D,
386 RTW_SNR_1SS_A,
387 RTW_SNR_1SS_B,
388 RTW_SNR_1SS_C,
389 RTW_SNR_1SS_D,
390 RTW_SNR_2SS_A,
391 RTW_SNR_2SS_B,
392 RTW_SNR_2SS_C,
393 RTW_SNR_2SS_D,
394 /* keep it last */
395 RTW_SNR_NUM
396 };
397
398 enum rtw_wow_flags {
399 RTW_WOW_FLAG_EN_MAGIC_PKT,
400 RTW_WOW_FLAG_EN_REKEY_PKT,
401 RTW_WOW_FLAG_EN_DISCONNECT,
402
403 /* keep it last */
404 RTW_WOW_FLAG_MAX,
405 };
406
407 /* the power index is represented by differences, which cck-1s & ht40-1s are
408 * the base values, so for 1s's differences, there are only ht20 & ofdm
409 */
410 struct rtw_2g_1s_pwr_idx_diff {
411 #ifdef __LITTLE_ENDIAN
412 s8 ofdm:4;
413 s8 bw20:4;
414 #else
415 s8 bw20:4;
416 s8 ofdm:4;
417 #endif
418 } __packed;
419
420 struct rtw_2g_ns_pwr_idx_diff {
421 #ifdef __LITTLE_ENDIAN
422 s8 bw20:4;
423 s8 bw40:4;
424 s8 cck:4;
425 s8 ofdm:4;
426 #else
427 s8 ofdm:4;
428 s8 cck:4;
429 s8 bw40:4;
430 s8 bw20:4;
431 #endif
432 } __packed;
433
434 struct rtw_2g_txpwr_idx {
435 u8 cck_base[6];
436 u8 bw40_base[5];
437 struct rtw_2g_1s_pwr_idx_diff ht_1s_diff;
438 struct rtw_2g_ns_pwr_idx_diff ht_2s_diff;
439 struct rtw_2g_ns_pwr_idx_diff ht_3s_diff;
440 struct rtw_2g_ns_pwr_idx_diff ht_4s_diff;
441 };
442
443 struct rtw_5g_ht_1s_pwr_idx_diff {
444 #ifdef __LITTLE_ENDIAN
445 s8 ofdm:4;
446 s8 bw20:4;
447 #else
448 s8 bw20:4;
449 s8 ofdm:4;
450 #endif
451 } __packed;
452
453 struct rtw_5g_ht_ns_pwr_idx_diff {
454 #ifdef __LITTLE_ENDIAN
455 s8 bw20:4;
456 s8 bw40:4;
457 #else
458 s8 bw40:4;
459 s8 bw20:4;
460 #endif
461 } __packed;
462
463 struct rtw_5g_ofdm_ns_pwr_idx_diff {
464 #ifdef __LITTLE_ENDIAN
465 s8 ofdm_3s:4;
466 s8 ofdm_2s:4;
467 s8 ofdm_4s:4;
468 s8 res:4;
469 #else
470 s8 res:4;
471 s8 ofdm_4s:4;
472 s8 ofdm_2s:4;
473 s8 ofdm_3s:4;
474 #endif
475 } __packed;
476
477 struct rtw_5g_vht_ns_pwr_idx_diff {
478 #ifdef __LITTLE_ENDIAN
479 s8 bw160:4;
480 s8 bw80:4;
481 #else
482 s8 bw80:4;
483 s8 bw160:4;
484 #endif
485 } __packed;
486
487 struct rtw_5g_txpwr_idx {
488 u8 bw40_base[14];
489 struct rtw_5g_ht_1s_pwr_idx_diff ht_1s_diff;
490 struct rtw_5g_ht_ns_pwr_idx_diff ht_2s_diff;
491 struct rtw_5g_ht_ns_pwr_idx_diff ht_3s_diff;
492 struct rtw_5g_ht_ns_pwr_idx_diff ht_4s_diff;
493 struct rtw_5g_ofdm_ns_pwr_idx_diff ofdm_diff;
494 struct rtw_5g_vht_ns_pwr_idx_diff vht_1s_diff;
495 struct rtw_5g_vht_ns_pwr_idx_diff vht_2s_diff;
496 struct rtw_5g_vht_ns_pwr_idx_diff vht_3s_diff;
497 struct rtw_5g_vht_ns_pwr_idx_diff vht_4s_diff;
498 };
499
500 struct rtw_txpwr_idx {
501 struct rtw_2g_txpwr_idx pwr_idx_2g;
502 struct rtw_5g_txpwr_idx pwr_idx_5g;
503 };
504
505 struct rtw_timer_list {
506 struct timer_list timer;
507 void (*function)(void *data);
508 void *args;
509 };
510
511 struct rtw_channel_params {
512 u8 center_chan;
513 u8 primary_chan;
514 u8 bandwidth;
515 };
516
517 struct rtw_hw_reg {
518 u32 addr;
519 u32 mask;
520 };
521
522 struct rtw_ltecoex_addr {
523 u32 ctrl;
524 u32 wdata;
525 u32 rdata;
526 };
527
528 struct rtw_reg_domain {
529 u32 addr;
530 u32 mask;
531 #define RTW_REG_DOMAIN_MAC32 0
532 #define RTW_REG_DOMAIN_MAC16 1
533 #define RTW_REG_DOMAIN_MAC8 2
534 #define RTW_REG_DOMAIN_RF_A 3
535 #define RTW_REG_DOMAIN_RF_B 4
536 #define RTW_REG_DOMAIN_NL 0xFF
537 u8 domain;
538 };
539
540 struct rtw_rf_sipi_addr {
541 u32 hssi_1;
542 u32 hssi_2;
543 u32 lssi_read;
544 u32 lssi_read_pi;
545 };
546
547 struct rtw_hw_reg_offset {
548 struct rtw_hw_reg hw_reg;
549 u8 offset;
550 };
551
552 struct rtw_backup_info {
553 u8 len;
554 u32 reg;
555 u32 val;
556 };
557
558 enum rtw_vif_port_set {
559 PORT_SET_MAC_ADDR = BIT(0),
560 PORT_SET_BSSID = BIT(1),
561 PORT_SET_NET_TYPE = BIT(2),
562 PORT_SET_AID = BIT(3),
563 PORT_SET_BCN_CTRL = BIT(4),
564 };
565
566 struct rtw_vif_port {
567 struct rtw_hw_reg mac_addr;
568 struct rtw_hw_reg bssid;
569 struct rtw_hw_reg net_type;
570 struct rtw_hw_reg aid;
571 struct rtw_hw_reg bcn_ctrl;
572 };
573
574 struct rtw_tx_pkt_info {
575 u32 tx_pkt_size;
576 u8 offset;
577 u8 pkt_offset;
578 u8 tim_offset;
579 u8 mac_id;
580 u8 rate_id;
581 u8 rate;
582 u8 qsel;
583 u8 bw;
584 u8 sec_type;
585 u8 sn;
586 bool ampdu_en;
587 u8 ampdu_factor;
588 u8 ampdu_density;
589 u16 seq;
590 bool stbc;
591 bool ldpc;
592 bool dis_rate_fallback;
593 bool bmc;
594 bool use_rate;
595 bool ls;
596 bool fs;
597 bool short_gi;
598 bool report;
599 bool rts;
600 bool dis_qselseq;
601 bool en_hwseq;
602 u8 hw_ssn_sel;
603 bool nav_use_hdr;
604 bool bt_null;
605 };
606
607 struct rtw_rx_pkt_stat {
608 bool phy_status;
609 bool icv_err;
610 bool crc_err;
611 bool decrypted;
612 bool is_c2h;
613
614 s32 signal_power;
615 u16 pkt_len;
616 u8 bw;
617 u8 drv_info_sz;
618 u8 shift;
619 u8 rate;
620 u8 mac_id;
621 u8 cam_id;
622 u8 ppdu_cnt;
623 u32 tsf_low;
624 s8 rx_power[RTW_RF_PATH_MAX];
625 u8 rssi;
626 u8 rxsc;
627 s8 rx_snr[RTW_RF_PATH_MAX];
628 u8 rx_evm[RTW_RF_PATH_MAX];
629 s8 cfo_tail[RTW_RF_PATH_MAX];
630 u16 freq;
631 u8 band;
632
633 struct rtw_sta_info *si;
634 struct ieee80211_vif *vif;
635 struct ieee80211_hdr *hdr;
636 };
637
638 DECLARE_EWMA(tp, 10, 2);
639
640 struct rtw_traffic_stats {
641 /* units in bytes */
642 u64 tx_unicast;
643 u64 rx_unicast;
644
645 /* count for packets */
646 u64 tx_cnt;
647 u64 rx_cnt;
648
649 /* units in Mbps */
650 u32 tx_throughput;
651 u32 rx_throughput;
652 struct ewma_tp tx_ewma_tp;
653 struct ewma_tp rx_ewma_tp;
654 };
655
656 enum rtw_lps_mode {
657 RTW_MODE_ACTIVE = 0,
658 RTW_MODE_LPS = 1,
659 RTW_MODE_WMM_PS = 2,
660 };
661
662 enum rtw_lps_deep_mode {
663 LPS_DEEP_MODE_NONE = 0,
664 LPS_DEEP_MODE_LCLK = 1,
665 LPS_DEEP_MODE_PG = 2,
666 };
667
668 enum rtw_pwr_state {
669 RTW_RF_OFF = 0x0,
670 RTW_RF_ON = 0x4,
671 RTW_ALL_ON = 0xc,
672 };
673
674 struct rtw_lps_conf {
675 enum rtw_lps_mode mode;
676 enum rtw_lps_deep_mode deep_mode;
677 enum rtw_lps_deep_mode wow_deep_mode;
678 enum rtw_pwr_state state;
679 u8 awake_interval;
680 u8 rlbm;
681 u8 smart_ps;
682 u8 port_id;
683 bool sec_cam_backup;
684 bool pattern_cam_backup;
685 };
686
687 enum rtw_hw_key_type {
688 RTW_CAM_NONE = 0,
689 RTW_CAM_WEP40 = 1,
690 RTW_CAM_TKIP = 2,
691 RTW_CAM_AES = 4,
692 RTW_CAM_WEP104 = 5,
693 };
694
695 struct rtw_cam_entry {
696 bool valid;
697 bool group;
698 u8 addr[ETH_ALEN];
699 u8 hw_key_type;
700 struct ieee80211_key_conf *key;
701 };
702
703 struct rtw_sec_desc {
704 /* search strategy */
705 bool default_key_search;
706
707 u32 total_cam_num;
708 struct rtw_cam_entry cam_table[RTW_MAX_SEC_CAM_NUM];
709 DECLARE_BITMAP(cam_map, RTW_MAX_SEC_CAM_NUM);
710 };
711
712 struct rtw_tx_report {
713 /* protect the tx report queue */
714 spinlock_t q_lock;
715 struct sk_buff_head queue;
716 atomic_t sn;
717 struct timer_list purge_timer;
718 };
719
720 struct rtw_ra_report {
721 struct rate_info txrate;
722 u32 bit_rate;
723 u8 desc_rate;
724 };
725
726 struct rtw_txq {
727 struct list_head list;
728
729 unsigned long flags;
730 unsigned long last_push;
731 };
732
733 #define RTW_BC_MC_MACID 1
734 DECLARE_EWMA(rssi, 10, 16);
735
736 struct rtw_sta_info {
737 struct ieee80211_sta *sta;
738 struct ieee80211_vif *vif;
739
740 struct ewma_rssi avg_rssi;
741 u8 rssi_level;
742
743 u8 mac_id;
744 u8 rate_id;
745 enum rtw_bandwidth bw_mode;
746 enum rtw_rf_type rf_type;
747 enum rtw_wireless_set wireless_set;
748 u8 stbc_en:2;
749 u8 ldpc_en:2;
750 bool sgi_enable;
751 bool vht_enable;
752 u8 init_ra_lv;
753 u64 ra_mask;
754
755 DECLARE_BITMAP(tid_ba, IEEE80211_NUM_TIDS);
756
757 struct rtw_ra_report ra_report;
758
759 bool use_cfg_mask;
760 struct cfg80211_bitrate_mask *mask;
761 };
762
763 enum rtw_bfee_role {
764 RTW_BFEE_NONE,
765 RTW_BFEE_SU,
766 RTW_BFEE_MU
767 };
768
769 struct rtw_bfee {
770 enum rtw_bfee_role role;
771
772 u16 p_aid;
773 u8 g_id;
774 u8 mac_addr[ETH_ALEN];
775 u8 sound_dim;
776
777 /* SU-MIMO */
778 u8 su_reg_index;
779
780 /* MU-MIMO */
781 u16 aid;
782 };
783
784 struct rtw_bf_info {
785 u8 bfer_mu_cnt;
786 u8 bfer_su_cnt;
787 DECLARE_BITMAP(bfer_su_reg_maping, 2);
788 u8 cur_csi_rpt_rate;
789 };
790
791 struct rtw_vif {
792 enum rtw_net_type net_type;
793 u16 aid;
794 u8 mac_addr[ETH_ALEN];
795 u8 bssid[ETH_ALEN];
796 u8 port;
797 u8 bcn_ctrl;
798 struct list_head rsvd_page_list;
799 struct ieee80211_tx_queue_params tx_params[IEEE80211_NUM_ACS];
800 const struct rtw_vif_port *conf;
801 struct cfg80211_scan_request *scan_req;
802 struct ieee80211_scan_ies *scan_ies;
803
804 struct rtw_traffic_stats stats;
805
806 struct rtw_bfee bfee;
807 };
808
809 struct rtw_regulatory {
810 char alpha2[2];
811 u8 txpwr_regd_2g;
812 u8 txpwr_regd_5g;
813 };
814
815 enum rtw_regd_state {
816 RTW_REGD_STATE_WORLDWIDE,
817 RTW_REGD_STATE_PROGRAMMED,
818 RTW_REGD_STATE_SETTING,
819
820 RTW_REGD_STATE_NR,
821 };
822
823 struct rtw_regd {
824 enum rtw_regd_state state;
825 const struct rtw_regulatory *regulatory;
826 enum nl80211_dfs_regions dfs_region;
827 };
828
829 struct rtw_chip_ops {
830 int (*mac_init)(struct rtw_dev *rtwdev);
831 int (*dump_fw_crash)(struct rtw_dev *rtwdev);
832 void (*shutdown)(struct rtw_dev *rtwdev);
833 int (*read_efuse)(struct rtw_dev *rtwdev, u8 *map);
834 void (*phy_set_param)(struct rtw_dev *rtwdev);
835 void (*set_channel)(struct rtw_dev *rtwdev, u8 channel,
836 u8 bandwidth, u8 primary_chan_idx);
837 void (*query_rx_desc)(struct rtw_dev *rtwdev, u8 *rx_desc,
838 struct rtw_rx_pkt_stat *pkt_stat,
839 struct ieee80211_rx_status *rx_status);
840 u32 (*read_rf)(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path,
841 u32 addr, u32 mask);
842 bool (*write_rf)(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path,
843 u32 addr, u32 mask, u32 data);
844 void (*set_tx_power_index)(struct rtw_dev *rtwdev);
845 int (*rsvd_page_dump)(struct rtw_dev *rtwdev, u8 *buf, u32 offset,
846 u32 size);
847 int (*set_antenna)(struct rtw_dev *rtwdev,
848 u32 antenna_tx,
849 u32 antenna_rx);
850 void (*cfg_ldo25)(struct rtw_dev *rtwdev, bool enable);
851 void (*efuse_grant)(struct rtw_dev *rtwdev, bool enable);
852 void (*false_alarm_statistics)(struct rtw_dev *rtwdev);
853 void (*phy_calibration)(struct rtw_dev *rtwdev);
854 void (*dpk_track)(struct rtw_dev *rtwdev);
855 void (*cck_pd_set)(struct rtw_dev *rtwdev, u8 level);
856 void (*pwr_track)(struct rtw_dev *rtwdev);
857 void (*config_bfee)(struct rtw_dev *rtwdev, struct rtw_vif *vif,
858 struct rtw_bfee *bfee, bool enable);
859 void (*set_gid_table)(struct rtw_dev *rtwdev,
860 struct ieee80211_vif *vif,
861 struct ieee80211_bss_conf *conf);
862 void (*cfg_csi_rate)(struct rtw_dev *rtwdev, u8 rssi, u8 cur_rate,
863 u8 fixrate_en, u8 *new_rate);
864 void (*adaptivity_init)(struct rtw_dev *rtwdev);
865 void (*adaptivity)(struct rtw_dev *rtwdev);
866 void (*cfo_init)(struct rtw_dev *rtwdev);
867 void (*cfo_track)(struct rtw_dev *rtwdev);
868 void (*config_tx_path)(struct rtw_dev *rtwdev, u8 tx_path,
869 enum rtw_bb_path tx_path_1ss,
870 enum rtw_bb_path tx_path_cck,
871 bool is_tx2_path);
872 void (*config_txrx_mode)(struct rtw_dev *rtwdev, u8 tx_path,
873 u8 rx_path, bool is_tx2_path);
874
875 /* for coex */
876 void (*coex_set_init)(struct rtw_dev *rtwdev);
877 void (*coex_set_ant_switch)(struct rtw_dev *rtwdev,
878 u8 ctrl_type, u8 pos_type);
879 void (*coex_set_gnt_fix)(struct rtw_dev *rtwdev);
880 void (*coex_set_gnt_debug)(struct rtw_dev *rtwdev);
881 void (*coex_set_rfe_type)(struct rtw_dev *rtwdev);
882 void (*coex_set_wl_tx_power)(struct rtw_dev *rtwdev, u8 wl_pwr);
883 void (*coex_set_wl_rx_gain)(struct rtw_dev *rtwdev, bool low_gain);
884 };
885
886 #define RTW_PWR_POLLING_CNT 20000
887
888 #define RTW_PWR_CMD_READ 0x00
889 #define RTW_PWR_CMD_WRITE 0x01
890 #define RTW_PWR_CMD_POLLING 0x02
891 #define RTW_PWR_CMD_DELAY 0x03
892 #define RTW_PWR_CMD_END 0x04
893
894 /* define the base address of each block */
895 #define RTW_PWR_ADDR_MAC 0x00
896 #define RTW_PWR_ADDR_USB 0x01
897 #define RTW_PWR_ADDR_PCIE 0x02
898 #define RTW_PWR_ADDR_SDIO 0x03
899
900 #define RTW_PWR_INTF_SDIO_MSK BIT(0)
901 #define RTW_PWR_INTF_USB_MSK BIT(1)
902 #define RTW_PWR_INTF_PCI_MSK BIT(2)
903 #define RTW_PWR_INTF_ALL_MSK (BIT(0) | BIT(1) | BIT(2) | BIT(3))
904
905 #define RTW_PWR_CUT_TEST_MSK BIT(0)
906 #define RTW_PWR_CUT_A_MSK BIT(1)
907 #define RTW_PWR_CUT_B_MSK BIT(2)
908 #define RTW_PWR_CUT_C_MSK BIT(3)
909 #define RTW_PWR_CUT_D_MSK BIT(4)
910 #define RTW_PWR_CUT_E_MSK BIT(5)
911 #define RTW_PWR_CUT_F_MSK BIT(6)
912 #define RTW_PWR_CUT_G_MSK BIT(7)
913 #define RTW_PWR_CUT_ALL_MSK 0xFF
914
915 enum rtw_pwr_seq_cmd_delay_unit {
916 RTW_PWR_DELAY_US,
917 RTW_PWR_DELAY_MS,
918 };
919
920 struct rtw_pwr_seq_cmd {
921 u16 offset;
922 u8 cut_mask;
923 u8 intf_mask;
924 u8 base:4;
925 u8 cmd:4;
926 u8 mask;
927 u8 value;
928 };
929
930 enum rtw_chip_ver {
931 RTW_CHIP_VER_CUT_A = 0x00,
932 RTW_CHIP_VER_CUT_B = 0x01,
933 RTW_CHIP_VER_CUT_C = 0x02,
934 RTW_CHIP_VER_CUT_D = 0x03,
935 RTW_CHIP_VER_CUT_E = 0x04,
936 RTW_CHIP_VER_CUT_F = 0x05,
937 RTW_CHIP_VER_CUT_G = 0x06,
938 };
939
940 #define RTW_INTF_PHY_PLATFORM_ALL 0
941
942 enum rtw_intf_phy_cut {
943 RTW_INTF_PHY_CUT_A = BIT(0),
944 RTW_INTF_PHY_CUT_B = BIT(1),
945 RTW_INTF_PHY_CUT_C = BIT(2),
946 RTW_INTF_PHY_CUT_D = BIT(3),
947 RTW_INTF_PHY_CUT_E = BIT(4),
948 RTW_INTF_PHY_CUT_F = BIT(5),
949 RTW_INTF_PHY_CUT_G = BIT(6),
950 RTW_INTF_PHY_CUT_ALL = 0xFFFF,
951 };
952
953 enum rtw_ip_sel {
954 RTW_IP_SEL_PHY = 0,
955 RTW_IP_SEL_MAC = 1,
956 RTW_IP_SEL_DBI = 2,
957
958 RTW_IP_SEL_UNDEF = 0xFFFF
959 };
960
961 enum rtw_pq_map_id {
962 RTW_PQ_MAP_VO = 0x0,
963 RTW_PQ_MAP_VI = 0x1,
964 RTW_PQ_MAP_BE = 0x2,
965 RTW_PQ_MAP_BK = 0x3,
966 RTW_PQ_MAP_MG = 0x4,
967 RTW_PQ_MAP_HI = 0x5,
968 RTW_PQ_MAP_NUM = 0x6,
969
970 RTW_PQ_MAP_UNDEF,
971 };
972
973 enum rtw_dma_mapping {
974 RTW_DMA_MAPPING_EXTRA = 0,
975 RTW_DMA_MAPPING_LOW = 1,
976 RTW_DMA_MAPPING_NORMAL = 2,
977 RTW_DMA_MAPPING_HIGH = 3,
978
979 RTW_DMA_MAPPING_MAX,
980 RTW_DMA_MAPPING_UNDEF,
981 };
982
983 struct rtw_rqpn {
984 enum rtw_dma_mapping dma_map_vo;
985 enum rtw_dma_mapping dma_map_vi;
986 enum rtw_dma_mapping dma_map_be;
987 enum rtw_dma_mapping dma_map_bk;
988 enum rtw_dma_mapping dma_map_mg;
989 enum rtw_dma_mapping dma_map_hi;
990 };
991
992 struct rtw_prioq_addr {
993 u32 rsvd;
994 u32 avail;
995 };
996
997 struct rtw_prioq_addrs {
998 struct rtw_prioq_addr prio[RTW_DMA_MAPPING_MAX];
999 bool wsize;
1000 };
1001
1002 struct rtw_page_table {
1003 u16 hq_num;
1004 u16 nq_num;
1005 u16 lq_num;
1006 u16 exq_num;
1007 u16 gapq_num;
1008 };
1009
1010 struct rtw_intf_phy_para {
1011 u16 offset;
1012 u16 value;
1013 u16 ip_sel;
1014 u16 cut_mask;
1015 u16 platform;
1016 };
1017
1018 struct rtw_wow_pattern {
1019 u16 crc;
1020 u8 type;
1021 u8 valid;
1022 u8 mask[RTW_MAX_PATTERN_MASK_SIZE];
1023 };
1024
1025 struct rtw_pno_request {
1026 bool inited;
1027 u32 match_set_cnt;
1028 struct cfg80211_match_set *match_sets;
1029 u8 channel_cnt;
1030 struct ieee80211_channel *channels;
1031 struct cfg80211_sched_scan_plan scan_plan;
1032 };
1033
1034 struct rtw_wow_param {
1035 struct ieee80211_vif *wow_vif;
1036 DECLARE_BITMAP(flags, RTW_WOW_FLAG_MAX);
1037 u8 txpause;
1038 u8 pattern_cnt;
1039 struct rtw_wow_pattern patterns[RTW_MAX_PATTERN_NUM];
1040
1041 bool ips_enabled;
1042 struct rtw_pno_request pno_req;
1043 };
1044
1045 struct rtw_intf_phy_para_table {
1046 const struct rtw_intf_phy_para *usb2_para;
1047 const struct rtw_intf_phy_para *usb3_para;
1048 const struct rtw_intf_phy_para *gen1_para;
1049 const struct rtw_intf_phy_para *gen2_para;
1050 u8 n_usb2_para;
1051 u8 n_usb3_para;
1052 u8 n_gen1_para;
1053 u8 n_gen2_para;
1054 };
1055
1056 struct rtw_table {
1057 const void *data;
1058 const u32 size;
1059 void (*parse)(struct rtw_dev *rtwdev, const struct rtw_table *tbl);
1060 void (*do_cfg)(struct rtw_dev *rtwdev, const struct rtw_table *tbl,
1061 u32 addr, u32 data);
1062 enum rtw_rf_path rf_path;
1063 };
1064
rtw_load_table(struct rtw_dev * rtwdev,const struct rtw_table * tbl)1065 static inline void rtw_load_table(struct rtw_dev *rtwdev,
1066 const struct rtw_table *tbl)
1067 {
1068 (*tbl->parse)(rtwdev, tbl);
1069 }
1070
1071 enum rtw_rfe_fem {
1072 RTW_RFE_IFEM,
1073 RTW_RFE_EFEM,
1074 RTW_RFE_IFEM2G_EFEM5G,
1075 RTW_RFE_NUM,
1076 };
1077
1078 struct rtw_rfe_def {
1079 const struct rtw_table *phy_pg_tbl;
1080 const struct rtw_table *txpwr_lmt_tbl;
1081 const struct rtw_table *agc_btg_tbl;
1082 };
1083
1084 #define RTW_DEF_RFE(chip, bb_pg, pwrlmt) { \
1085 .phy_pg_tbl = &rtw ## chip ## _bb_pg_type ## bb_pg ## _tbl, \
1086 .txpwr_lmt_tbl = &rtw ## chip ## _txpwr_lmt_type ## pwrlmt ## _tbl, \
1087 }
1088
1089 #define RTW_DEF_RFE_EXT(chip, bb_pg, pwrlmt, btg) { \
1090 .phy_pg_tbl = &rtw ## chip ## _bb_pg_type ## bb_pg ## _tbl, \
1091 .txpwr_lmt_tbl = &rtw ## chip ## _txpwr_lmt_type ## pwrlmt ## _tbl, \
1092 .agc_btg_tbl = &rtw ## chip ## _agc_btg_type ## btg ## _tbl, \
1093 }
1094
1095 #define RTW_PWR_TRK_5G_1 0
1096 #define RTW_PWR_TRK_5G_2 1
1097 #define RTW_PWR_TRK_5G_3 2
1098 #define RTW_PWR_TRK_5G_NUM 3
1099
1100 #define RTW_PWR_TRK_TBL_SZ 30
1101
1102 /* This table stores the values of TX power that will be adjusted by power
1103 * tracking.
1104 *
1105 * For 5G bands, there are 3 different settings.
1106 * For 2G there are cck rate and ofdm rate with different settings.
1107 */
1108 struct rtw_pwr_track_tbl {
1109 const u8 *pwrtrk_5gb_n[RTW_PWR_TRK_5G_NUM];
1110 const u8 *pwrtrk_5gb_p[RTW_PWR_TRK_5G_NUM];
1111 const u8 *pwrtrk_5ga_n[RTW_PWR_TRK_5G_NUM];
1112 const u8 *pwrtrk_5ga_p[RTW_PWR_TRK_5G_NUM];
1113 const u8 *pwrtrk_2gb_n;
1114 const u8 *pwrtrk_2gb_p;
1115 const u8 *pwrtrk_2ga_n;
1116 const u8 *pwrtrk_2ga_p;
1117 const u8 *pwrtrk_2g_cckb_n;
1118 const u8 *pwrtrk_2g_cckb_p;
1119 const u8 *pwrtrk_2g_ccka_n;
1120 const u8 *pwrtrk_2g_ccka_p;
1121 const s8 *pwrtrk_xtal_n;
1122 const s8 *pwrtrk_xtal_p;
1123 };
1124
1125 enum rtw_wlan_cpu {
1126 RTW_WCPU_11AC,
1127 RTW_WCPU_11N,
1128 };
1129
1130 enum rtw_fw_fifo_sel {
1131 RTW_FW_FIFO_SEL_TX,
1132 RTW_FW_FIFO_SEL_RX,
1133 RTW_FW_FIFO_SEL_RSVD_PAGE,
1134 RTW_FW_FIFO_SEL_REPORT,
1135 RTW_FW_FIFO_SEL_LLT,
1136 RTW_FW_FIFO_SEL_RXBUF_FW,
1137
1138 RTW_FW_FIFO_MAX,
1139 };
1140
1141 enum rtw_fwcd_item {
1142 RTW_FWCD_TLV,
1143 RTW_FWCD_REG,
1144 RTW_FWCD_ROM,
1145 RTW_FWCD_IMEM,
1146 RTW_FWCD_DMEM,
1147 RTW_FWCD_EMEM,
1148 };
1149
1150 /* hardware configuration for each IC */
1151 struct rtw_chip_info {
1152 struct rtw_chip_ops *ops;
1153 u8 id;
1154
1155 const char *fw_name;
1156 enum rtw_wlan_cpu wlan_cpu;
1157 u8 tx_pkt_desc_sz;
1158 u8 tx_buf_desc_sz;
1159 u8 rx_pkt_desc_sz;
1160 u8 rx_buf_desc_sz;
1161 u32 phy_efuse_size;
1162 u32 log_efuse_size;
1163 u32 ptct_efuse_size;
1164 u32 txff_size;
1165 u32 rxff_size;
1166 u32 fw_rxff_size;
1167 u8 band;
1168 u8 page_size;
1169 u8 csi_buf_pg_num;
1170 u8 dig_max;
1171 u8 dig_min;
1172 u8 txgi_factor;
1173 bool is_pwr_by_rate_dec;
1174 bool rx_ldpc;
1175 bool tx_stbc;
1176 u8 max_power_index;
1177 u8 ampdu_density;
1178
1179 u16 fw_fifo_addr[RTW_FW_FIFO_MAX];
1180 const struct rtw_fwcd_segs *fwcd_segs;
1181
1182 u8 default_1ss_tx_path;
1183
1184 bool path_div_supported;
1185 bool ht_supported;
1186 bool vht_supported;
1187 u8 lps_deep_mode_supported;
1188
1189 /* init values */
1190 u8 sys_func_en;
1191 const struct rtw_pwr_seq_cmd **pwr_on_seq;
1192 const struct rtw_pwr_seq_cmd **pwr_off_seq;
1193 const struct rtw_rqpn *rqpn_table;
1194 const struct rtw_prioq_addrs *prioq_addrs;
1195 const struct rtw_page_table *page_table;
1196 const struct rtw_intf_phy_para_table *intf_table;
1197
1198 const struct rtw_hw_reg *dig;
1199 const struct rtw_hw_reg *dig_cck;
1200 u32 rf_base_addr[2];
1201 u32 rf_sipi_addr[2];
1202 const struct rtw_rf_sipi_addr *rf_sipi_read_addr;
1203 u8 fix_rf_phy_num;
1204 const struct rtw_ltecoex_addr *ltecoex_addr;
1205
1206 const struct rtw_table *mac_tbl;
1207 const struct rtw_table *agc_tbl;
1208 const struct rtw_table *bb_tbl;
1209 const struct rtw_table *rf_tbl[RTW_RF_PATH_MAX];
1210 const struct rtw_table *rfk_init_tbl;
1211
1212 const struct rtw_rfe_def *rfe_defs;
1213 u32 rfe_defs_size;
1214
1215 bool en_dis_dpd;
1216 u16 dpd_ratemask;
1217 u8 iqk_threshold;
1218 u8 lck_threshold;
1219 const struct rtw_pwr_track_tbl *pwr_track_tbl;
1220
1221 u8 bfer_su_max_num;
1222 u8 bfer_mu_max_num;
1223
1224 struct rtw_hw_reg_offset *edcca_th;
1225 s8 l2h_th_ini_cs;
1226 s8 l2h_th_ini_ad;
1227
1228 const char *wow_fw_name;
1229 const struct wiphy_wowlan_support *wowlan_stub;
1230 const u8 max_sched_scan_ssids;
1231 const u16 max_scan_ie_len;
1232
1233 /* coex paras */
1234 u32 coex_para_ver;
1235 u8 bt_desired_ver;
1236 bool scbd_support;
1237 bool new_scbd10_def; /* true: fix 2M(8822c) */
1238 bool ble_hid_profile_support;
1239 bool wl_mimo_ps_support;
1240 u8 pstdma_type; /* 0: LPSoff, 1:LPSon */
1241 u8 bt_rssi_type;
1242 u8 ant_isolation;
1243 u8 rssi_tolerance;
1244 u8 table_sant_num;
1245 u8 table_nsant_num;
1246 u8 tdma_sant_num;
1247 u8 tdma_nsant_num;
1248 u8 bt_afh_span_bw20;
1249 u8 bt_afh_span_bw40;
1250 u8 afh_5g_num;
1251 u8 wl_rf_para_num;
1252 u8 coex_info_hw_regs_num;
1253 const u8 *bt_rssi_step;
1254 const u8 *wl_rssi_step;
1255 const struct coex_table_para *table_nsant;
1256 const struct coex_table_para *table_sant;
1257 const struct coex_tdma_para *tdma_sant;
1258 const struct coex_tdma_para *tdma_nsant;
1259 const struct coex_rf_para *wl_rf_para_tx;
1260 const struct coex_rf_para *wl_rf_para_rx;
1261 const struct coex_5g_afh_map *afh_5g;
1262 const struct rtw_hw_reg *btg_reg;
1263 const struct rtw_reg_domain *coex_info_hw_regs;
1264 u32 wl_fw_desired_ver;
1265 };
1266
1267 enum rtw_coex_bt_state_cnt {
1268 COEX_CNT_BT_RETRY,
1269 COEX_CNT_BT_REINIT,
1270 COEX_CNT_BT_REENABLE,
1271 COEX_CNT_BT_POPEVENT,
1272 COEX_CNT_BT_SETUPLINK,
1273 COEX_CNT_BT_IGNWLANACT,
1274 COEX_CNT_BT_INQ,
1275 COEX_CNT_BT_PAGE,
1276 COEX_CNT_BT_ROLESWITCH,
1277 COEX_CNT_BT_AFHUPDATE,
1278 COEX_CNT_BT_INFOUPDATE,
1279 COEX_CNT_BT_IQK,
1280 COEX_CNT_BT_IQKFAIL,
1281
1282 COEX_CNT_BT_MAX
1283 };
1284
1285 enum rtw_coex_wl_state_cnt {
1286 COEX_CNT_WL_SCANAP,
1287 COEX_CNT_WL_CONNPKT,
1288 COEX_CNT_WL_COEXRUN,
1289 COEX_CNT_WL_NOISY0,
1290 COEX_CNT_WL_NOISY1,
1291 COEX_CNT_WL_NOISY2,
1292 COEX_CNT_WL_5MS_NOEXTEND,
1293 COEX_CNT_WL_FW_NOTIFY,
1294
1295 COEX_CNT_WL_MAX
1296 };
1297
1298 struct rtw_coex_rfe {
1299 bool ant_switch_exist;
1300 bool ant_switch_diversity;
1301 bool ant_switch_with_bt;
1302 u8 rfe_module_type;
1303 u8 ant_switch_polarity;
1304
1305 /* true if WLG at BTG, else at WLAG */
1306 bool wlg_at_btg;
1307 };
1308
1309 #define COEX_WL_TDMA_PARA_LENGTH 5
1310
1311 struct rtw_coex_dm {
1312 bool cur_ps_tdma_on;
1313 bool cur_wl_rx_low_gain_en;
1314 bool ignore_wl_act;
1315
1316 u8 reason;
1317 u8 bt_rssi_state[4];
1318 u8 wl_rssi_state[4];
1319 u8 wl_ch_info[3];
1320 u8 cur_ps_tdma;
1321 u8 cur_table;
1322 u8 ps_tdma_para[5];
1323 u8 cur_bt_pwr_lvl;
1324 u8 cur_bt_lna_lvl;
1325 u8 cur_wl_pwr_lvl;
1326 u8 bt_status;
1327 u32 cur_ant_pos_type;
1328 u32 cur_switch_status;
1329 u32 setting_tdma;
1330 u8 fw_tdma_para[COEX_WL_TDMA_PARA_LENGTH];
1331 };
1332
1333 #define COEX_BTINFO_SRC_WL_FW 0x0
1334 #define COEX_BTINFO_SRC_BT_RSP 0x1
1335 #define COEX_BTINFO_SRC_BT_ACT 0x2
1336 #define COEX_BTINFO_SRC_BT_IQK 0x3
1337 #define COEX_BTINFO_SRC_BT_SCBD 0x4
1338 #define COEX_BTINFO_SRC_H2C60 0x5
1339 #define COEX_BTINFO_SRC_MAX 0x6
1340
1341 #define COEX_INFO_FTP BIT(7)
1342 #define COEX_INFO_A2DP BIT(6)
1343 #define COEX_INFO_HID BIT(5)
1344 #define COEX_INFO_SCO_BUSY BIT(4)
1345 #define COEX_INFO_ACL_BUSY BIT(3)
1346 #define COEX_INFO_INQ_PAGE BIT(2)
1347 #define COEX_INFO_SCO_ESCO BIT(1)
1348 #define COEX_INFO_CONNECTION BIT(0)
1349 #define COEX_BTINFO_LENGTH_MAX 10
1350 #define COEX_BTINFO_LENGTH 7
1351
1352 #define COEX_BT_HIDINFO_LIST 0x0
1353 #define COEX_BT_HIDINFO_A 0x1
1354 #define COEX_BT_HIDINFO_NAME 3
1355
1356 #define COEX_BT_HIDINFO_LENGTH 6
1357 #define COEX_BT_HIDINFO_HANDLE_NUM 4
1358 #define COEX_BT_HIDINFO_C2H_HANDLE 0
1359 #define COEX_BT_HIDINFO_C2H_VENDOR 1
1360 #define COEX_BT_BLE_HANDLE_THRS 0x10
1361 #define COEX_BT_HIDINFO_NOTCON 0xff
1362
1363 struct rtw_coex_hid {
1364 u8 hid_handle;
1365 u8 hid_vendor;
1366 u8 hid_name[COEX_BT_HIDINFO_NAME];
1367 bool hid_info_completed;
1368 bool is_game_hid;
1369 };
1370
1371 struct rtw_coex_hid_handle_list {
1372 u8 cmd_id;
1373 u8 len;
1374 u8 subid;
1375 u8 handle_cnt;
1376 u8 handle[COEX_BT_HIDINFO_HANDLE_NUM];
1377 } __packed;
1378
1379 struct rtw_coex_hid_info_a {
1380 u8 cmd_id;
1381 u8 len;
1382 u8 subid;
1383 u8 handle;
1384 u8 vendor;
1385 u8 name[COEX_BT_HIDINFO_NAME];
1386 } __packed;
1387
1388 struct rtw_coex_stat {
1389 bool bt_disabled;
1390 bool bt_disabled_pre;
1391 bool bt_link_exist;
1392 bool bt_whck_test;
1393 bool bt_inq_page;
1394 bool bt_inq_remain;
1395 bool bt_inq;
1396 bool bt_page;
1397 bool bt_ble_voice;
1398 bool bt_ble_exist;
1399 bool bt_hfp_exist;
1400 bool bt_a2dp_exist;
1401 bool bt_hid_exist;
1402 bool bt_pan_exist; /* PAN or OPP */
1403 bool bt_opp_exist; /* OPP only */
1404 bool bt_acl_busy;
1405 bool bt_fix_2M;
1406 bool bt_setup_link;
1407 bool bt_multi_link;
1408 bool bt_multi_link_pre;
1409 bool bt_multi_link_remain;
1410 bool bt_a2dp_sink;
1411 bool bt_a2dp_active;
1412 bool bt_reenable;
1413 bool bt_ble_scan_en;
1414 bool bt_init_scan;
1415 bool bt_slave;
1416 bool bt_418_hid_exist;
1417 bool bt_ble_hid_exist;
1418 bool bt_game_hid_exist;
1419 bool bt_hid_handle_cnt;
1420 bool bt_mailbox_reply;
1421
1422 bool wl_under_lps;
1423 bool wl_under_ips;
1424 bool wl_hi_pri_task1;
1425 bool wl_hi_pri_task2;
1426 bool wl_force_lps_ctrl;
1427 bool wl_gl_busy;
1428 bool wl_linkscan_proc;
1429 bool wl_ps_state_fail;
1430 bool wl_tx_limit_en;
1431 bool wl_ampdu_limit_en;
1432 bool wl_connected;
1433 bool wl_slot_extend;
1434 bool wl_cck_lock;
1435 bool wl_cck_lock_pre;
1436 bool wl_cck_lock_ever;
1437 bool wl_connecting;
1438 bool wl_slot_toggle;
1439 bool wl_slot_toggle_change; /* if toggle to no-toggle */
1440 bool wl_mimo_ps;
1441
1442 u32 bt_supported_version;
1443 u32 bt_supported_feature;
1444 u32 hi_pri_tx;
1445 u32 hi_pri_rx;
1446 u32 lo_pri_tx;
1447 u32 lo_pri_rx;
1448 u32 patch_ver;
1449 u16 bt_reg_vendor_ae;
1450 u16 bt_reg_vendor_ac;
1451 s8 bt_rssi;
1452 u8 kt_ver;
1453 u8 gnt_workaround_state;
1454 u8 tdma_timer_base;
1455 u8 bt_profile_num;
1456 u8 bt_info_c2h[COEX_BTINFO_SRC_MAX][COEX_BTINFO_LENGTH_MAX];
1457 u8 bt_info_lb2;
1458 u8 bt_info_lb3;
1459 u8 bt_info_hb0;
1460 u8 bt_info_hb1;
1461 u8 bt_info_hb2;
1462 u8 bt_info_hb3;
1463 u8 bt_ble_scan_type;
1464 u8 bt_hid_pair_num;
1465 u8 bt_hid_slot;
1466 u8 bt_a2dp_bitpool;
1467 u8 bt_iqk_state;
1468
1469 u16 wl_beacon_interval;
1470 u8 wl_noisy_level;
1471 u8 wl_fw_dbg_info[10];
1472 u8 wl_fw_dbg_info_pre[10];
1473 u8 wl_rx_rate;
1474 u8 wl_tx_rate;
1475 u8 wl_rts_rx_rate;
1476 u8 wl_coex_mode;
1477 u8 wl_iot_peer;
1478 u8 ampdu_max_time;
1479 u8 wl_tput_dir;
1480
1481 u8 wl_toggle_para[6];
1482 u8 wl_toggle_interval;
1483
1484 u16 score_board;
1485 u16 retry_limit;
1486
1487 /* counters to record bt states */
1488 u32 cnt_bt[COEX_CNT_BT_MAX];
1489
1490 /* counters to record wifi states */
1491 u32 cnt_wl[COEX_CNT_WL_MAX];
1492
1493 /* counters to record bt c2h data */
1494 u32 cnt_bt_info_c2h[COEX_BTINFO_SRC_MAX];
1495
1496 u32 darfrc;
1497 u32 darfrch;
1498
1499 struct rtw_coex_hid hid_info[COEX_BT_HIDINFO_HANDLE_NUM];
1500 struct rtw_coex_hid_handle_list hid_handle_list;
1501 };
1502
1503 struct rtw_coex {
1504 /* protects coex info request section */
1505 struct mutex mutex;
1506 struct sk_buff_head queue;
1507 wait_queue_head_t wait;
1508
1509 bool under_5g;
1510 bool stop_dm;
1511 bool freeze;
1512 bool freerun;
1513 bool wl_rf_off;
1514 bool manual_control;
1515
1516 struct rtw_coex_stat stat;
1517 struct rtw_coex_dm dm;
1518 struct rtw_coex_rfe rfe;
1519
1520 struct delayed_work bt_relink_work;
1521 struct delayed_work bt_reenable_work;
1522 struct delayed_work defreeze_work;
1523 struct delayed_work wl_remain_work;
1524 struct delayed_work bt_remain_work;
1525 struct delayed_work wl_connecting_work;
1526 struct delayed_work bt_multi_link_remain_work;
1527 struct delayed_work wl_ccklock_work;
1528
1529 };
1530
1531 #define DPK_RF_REG_NUM 7
1532 #define DPK_RF_PATH_NUM 2
1533 #define DPK_BB_REG_NUM 18
1534 #define DPK_CHANNEL_WIDTH_80 1
1535
1536 DECLARE_EWMA(thermal, 10, 4);
1537
1538 struct rtw_dpk_info {
1539 bool is_dpk_pwr_on;
1540 bool is_reload;
1541
1542 DECLARE_BITMAP(dpk_path_ok, DPK_RF_PATH_NUM);
1543
1544 u8 thermal_dpk[DPK_RF_PATH_NUM];
1545 struct ewma_thermal avg_thermal[DPK_RF_PATH_NUM];
1546
1547 u32 gnt_control;
1548 u32 gnt_value;
1549
1550 u8 result[RTW_RF_PATH_MAX];
1551 u8 dpk_txagc[RTW_RF_PATH_MAX];
1552 u32 coef[RTW_RF_PATH_MAX][20];
1553 u16 dpk_gs[RTW_RF_PATH_MAX];
1554 u8 thermal_dpk_delta[RTW_RF_PATH_MAX];
1555 u8 pre_pwsf[RTW_RF_PATH_MAX];
1556
1557 u8 dpk_band;
1558 u8 dpk_ch;
1559 u8 dpk_bw;
1560 };
1561
1562 struct rtw_phy_cck_pd_reg {
1563 u32 reg_pd;
1564 u32 mask_pd;
1565 u32 reg_cs;
1566 u32 mask_cs;
1567 };
1568
1569 #define DACK_MSBK_BACKUP_NUM 0xf
1570 #define DACK_DCK_BACKUP_NUM 0x2
1571
1572 struct rtw_swing_table {
1573 const u8 *p[RTW_RF_PATH_MAX];
1574 const u8 *n[RTW_RF_PATH_MAX];
1575 };
1576
1577 struct rtw_pkt_count {
1578 u16 num_bcn_pkt;
1579 u16 num_qry_pkt[DESC_RATE_MAX];
1580 };
1581
1582 DECLARE_EWMA(evm, 10, 4);
1583 DECLARE_EWMA(snr, 10, 4);
1584
1585 struct rtw_iqk_info {
1586 bool done;
1587 struct {
1588 u32 s1_x;
1589 u32 s1_y;
1590 u32 s0_x;
1591 u32 s0_y;
1592 } result;
1593 };
1594
1595 enum rtw_rf_band {
1596 RF_BAND_2G_CCK,
1597 RF_BAND_2G_OFDM,
1598 RF_BAND_5G_L,
1599 RF_BAND_5G_M,
1600 RF_BAND_5G_H,
1601 RF_BAND_MAX
1602 };
1603
1604 #define RF_GAIN_NUM 11
1605 #define RF_HW_OFFSET_NUM 10
1606
1607 struct rtw_gapk_info {
1608 u32 rf3f_bp[RF_BAND_MAX][RF_GAIN_NUM][RTW_RF_PATH_MAX];
1609 u32 rf3f_fs[RTW_RF_PATH_MAX][RF_GAIN_NUM];
1610 bool txgapk_bp_done;
1611 s8 offset[RF_GAIN_NUM][RTW_RF_PATH_MAX];
1612 s8 fianl_offset[RF_GAIN_NUM][RTW_RF_PATH_MAX];
1613 u8 read_txgain;
1614 u8 channel;
1615 };
1616
1617 #define EDCCA_TH_L2H_IDX 0
1618 #define EDCCA_TH_H2L_IDX 1
1619 #define EDCCA_TH_L2H_LB 48
1620 #define EDCCA_ADC_BACKOFF 12
1621 #define EDCCA_IGI_BASE 50
1622 #define EDCCA_IGI_L2H_DIFF 8
1623 #define EDCCA_L2H_H2L_DIFF 7
1624 #define EDCCA_L2H_H2L_DIFF_NORMAL 8
1625
1626 enum rtw_edcca_mode {
1627 RTW_EDCCA_NORMAL = 0,
1628 RTW_EDCCA_ADAPTIVITY = 1,
1629 };
1630
1631 struct rtw_cfo_track {
1632 bool is_adjust;
1633 u8 crystal_cap;
1634 s32 cfo_tail[RTW_RF_PATH_MAX];
1635 s32 cfo_cnt[RTW_RF_PATH_MAX];
1636 u32 packet_count;
1637 u32 packet_count_pre;
1638 };
1639
1640 #define RRSR_INIT_2G 0x15f
1641 #define RRSR_INIT_5G 0x150
1642
1643 enum rtw_dm_cap {
1644 RTW_DM_CAP_NA,
1645 RTW_DM_CAP_TXGAPK,
1646 RTW_DM_CAP_NUM
1647 };
1648
1649 struct rtw_dm_info {
1650 u32 cck_fa_cnt;
1651 u32 ofdm_fa_cnt;
1652 u32 total_fa_cnt;
1653 u32 cck_cca_cnt;
1654 u32 ofdm_cca_cnt;
1655 u32 total_cca_cnt;
1656
1657 u32 cck_ok_cnt;
1658 u32 cck_err_cnt;
1659 u32 ofdm_ok_cnt;
1660 u32 ofdm_err_cnt;
1661 u32 ht_ok_cnt;
1662 u32 ht_err_cnt;
1663 u32 vht_ok_cnt;
1664 u32 vht_err_cnt;
1665
1666 u8 min_rssi;
1667 u8 pre_min_rssi;
1668 u16 fa_history[4];
1669 u8 igi_history[4];
1670 u8 igi_bitmap;
1671 bool damping;
1672 u8 damping_cnt;
1673 u8 damping_rssi;
1674
1675 u8 cck_gi_u_bnd;
1676 u8 cck_gi_l_bnd;
1677
1678 u8 fix_rate;
1679 u8 tx_rate;
1680 u32 rrsr_val_init;
1681 u32 rrsr_mask_min;
1682 u8 thermal_avg[RTW_RF_PATH_MAX];
1683 u8 thermal_meter_k;
1684 u8 thermal_meter_lck;
1685 s8 delta_power_index[RTW_RF_PATH_MAX];
1686 s8 delta_power_index_last[RTW_RF_PATH_MAX];
1687 u8 default_ofdm_index;
1688 bool pwr_trk_triggered;
1689 bool pwr_trk_init_trigger;
1690 struct ewma_thermal avg_thermal[RTW_RF_PATH_MAX];
1691 s8 txagc_remnant_cck;
1692 s8 txagc_remnant_ofdm;
1693
1694 /* backup dack results for each path and I/Q */
1695 u32 dack_adck[RTW_RF_PATH_MAX];
1696 u16 dack_msbk[RTW_RF_PATH_MAX][2][DACK_MSBK_BACKUP_NUM];
1697 u8 dack_dck[RTW_RF_PATH_MAX][2][DACK_DCK_BACKUP_NUM];
1698
1699 struct rtw_dpk_info dpk_info;
1700 struct rtw_cfo_track cfo_track;
1701
1702 /* [bandwidth 0:20M/1:40M][number of path] */
1703 u8 cck_pd_lv[2][RTW_RF_PATH_MAX];
1704 u32 cck_fa_avg;
1705 u8 cck_pd_default;
1706
1707 /* save the last rx phy status for debug */
1708 s8 rx_snr[RTW_RF_PATH_MAX];
1709 u8 rx_evm_dbm[RTW_RF_PATH_MAX];
1710 s16 cfo_tail[RTW_RF_PATH_MAX];
1711 u8 rssi[RTW_RF_PATH_MAX];
1712 u8 curr_rx_rate;
1713 struct rtw_pkt_count cur_pkt_count;
1714 struct rtw_pkt_count last_pkt_count;
1715 struct ewma_evm ewma_evm[RTW_EVM_NUM];
1716 struct ewma_snr ewma_snr[RTW_SNR_NUM];
1717
1718 u32 dm_flags; /* enum rtw_dm_cap */
1719 struct rtw_iqk_info iqk;
1720 struct rtw_gapk_info gapk;
1721 bool is_bt_iqk_timeout;
1722
1723 s8 l2h_th_ini;
1724 enum rtw_edcca_mode edcca_mode;
1725 u8 scan_density;
1726 };
1727
1728 struct rtw_efuse {
1729 u32 size;
1730 u32 physical_size;
1731 u32 logical_size;
1732 u32 protect_size;
1733
1734 u8 addr[ETH_ALEN];
1735 u8 channel_plan;
1736 u8 country_code[2];
1737 u8 rf_board_option;
1738 u8 rfe_option;
1739 u8 power_track_type;
1740 u8 thermal_meter[RTW_RF_PATH_MAX];
1741 u8 thermal_meter_k;
1742 u8 crystal_cap;
1743 u8 ant_div_cfg;
1744 u8 ant_div_type;
1745 u8 regd;
1746 u8 afe;
1747
1748 u8 lna_type_2g;
1749 u8 lna_type_5g;
1750 u8 glna_type;
1751 u8 alna_type;
1752 bool ext_lna_2g;
1753 bool ext_lna_5g;
1754 u8 pa_type_2g;
1755 u8 pa_type_5g;
1756 u8 gpa_type;
1757 u8 apa_type;
1758 bool ext_pa_2g;
1759 bool ext_pa_5g;
1760 u8 tx_bb_swing_setting_2g;
1761 u8 tx_bb_swing_setting_5g;
1762
1763 bool btcoex;
1764 /* bt share antenna with wifi */
1765 bool share_ant;
1766 u8 bt_setting;
1767
1768 struct {
1769 u8 hci;
1770 u8 bw;
1771 u8 ptcl;
1772 u8 nss;
1773 u8 ant_num;
1774 } hw_cap;
1775
1776 struct rtw_txpwr_idx txpwr_idx_table[4];
1777 };
1778
1779 struct rtw_phy_cond {
1780 #ifdef __LITTLE_ENDIAN
1781 u32 rfe:8;
1782 u32 intf:4;
1783 u32 pkg:4;
1784 u32 plat:4;
1785 u32 intf_rsvd:4;
1786 u32 cut:4;
1787 u32 branch:2;
1788 u32 neg:1;
1789 u32 pos:1;
1790 #else
1791 u32 pos:1;
1792 u32 neg:1;
1793 u32 branch:2;
1794 u32 cut:4;
1795 u32 intf_rsvd:4;
1796 u32 plat:4;
1797 u32 pkg:4;
1798 u32 intf:4;
1799 u32 rfe:8;
1800 #endif
1801 /* for intf:4 */
1802 #define INTF_PCIE BIT(0)
1803 #define INTF_USB BIT(1)
1804 #define INTF_SDIO BIT(2)
1805 /* for branch:2 */
1806 #define BRANCH_IF 0
1807 #define BRANCH_ELIF 1
1808 #define BRANCH_ELSE 2
1809 #define BRANCH_ENDIF 3
1810 };
1811
1812 struct rtw_fifo_conf {
1813 /* tx fifo information */
1814 u16 rsvd_boundary;
1815 u16 rsvd_pg_num;
1816 u16 rsvd_drv_pg_num;
1817 u16 txff_pg_num;
1818 u16 acq_pg_num;
1819 u16 rsvd_drv_addr;
1820 u16 rsvd_h2c_info_addr;
1821 u16 rsvd_h2c_sta_info_addr;
1822 u16 rsvd_h2cq_addr;
1823 u16 rsvd_cpu_instr_addr;
1824 u16 rsvd_fw_txbuf_addr;
1825 u16 rsvd_csibuf_addr;
1826 const struct rtw_rqpn *rqpn;
1827 };
1828
1829 struct rtw_fwcd_desc {
1830 u32 size;
1831 u8 *next;
1832 u8 *data;
1833 };
1834
1835 struct rtw_fwcd_segs {
1836 const u32 *segs;
1837 u8 num;
1838 };
1839
1840 #define FW_CD_TYPE 0xffff
1841 #define FW_CD_LEN 4
1842 #define FW_CD_VAL 0xaabbccdd
1843 struct rtw_fw_state {
1844 const struct firmware *firmware;
1845 struct rtw_dev *rtwdev;
1846 struct completion completion;
1847 struct rtw_fwcd_desc fwcd_desc;
1848 u16 version;
1849 u8 sub_version;
1850 u8 sub_index;
1851 u16 h2c_version;
1852 u32 feature;
1853 u32 feature_ext;
1854 };
1855
1856 enum rtw_sar_sources {
1857 RTW_SAR_SOURCE_NONE,
1858 RTW_SAR_SOURCE_COMMON,
1859 };
1860
1861 enum rtw_sar_bands {
1862 RTW_SAR_BAND_0,
1863 RTW_SAR_BAND_1,
1864 /* RTW_SAR_BAND_2, not used now */
1865 RTW_SAR_BAND_3,
1866 RTW_SAR_BAND_4,
1867
1868 RTW_SAR_BAND_NR,
1869 };
1870
1871 /* the union is reserved for other knids of SAR sources
1872 * which might not re-use same format with array common.
1873 */
1874 union rtw_sar_cfg {
1875 s8 common[RTW_SAR_BAND_NR];
1876 };
1877
1878 struct rtw_sar {
1879 enum rtw_sar_sources src;
1880 union rtw_sar_cfg cfg[RTW_RF_PATH_MAX][RTW_RATE_SECTION_MAX];
1881 };
1882
1883 struct rtw_hal {
1884 u32 rcr;
1885
1886 u32 chip_version;
1887 u8 cut_version;
1888 u8 mp_chip;
1889 u8 oem_id;
1890 struct rtw_phy_cond phy_cond;
1891
1892 u8 ps_mode;
1893 u8 current_channel;
1894 u8 current_primary_channel_index;
1895 u8 current_band_width;
1896 u8 current_band_type;
1897 u8 primary_channel;
1898
1899 /* center channel for different available bandwidth,
1900 * val of (bw > current_band_width) is invalid
1901 */
1902 u8 cch_by_bw[RTW_MAX_CHANNEL_WIDTH + 1];
1903
1904 u8 sec_ch_offset;
1905 u8 rf_type;
1906 u8 rf_path_num;
1907 u8 rf_phy_num;
1908 u32 antenna_tx;
1909 u32 antenna_rx;
1910 u8 bfee_sts_cap;
1911 bool txrx_1ss;
1912
1913 /* protect tx power section */
1914 struct mutex tx_power_mutex;
1915 s8 tx_pwr_by_rate_offset_2g[RTW_RF_PATH_MAX]
1916 [DESC_RATE_MAX];
1917 s8 tx_pwr_by_rate_offset_5g[RTW_RF_PATH_MAX]
1918 [DESC_RATE_MAX];
1919 s8 tx_pwr_by_rate_base_2g[RTW_RF_PATH_MAX]
1920 [RTW_RATE_SECTION_MAX];
1921 s8 tx_pwr_by_rate_base_5g[RTW_RF_PATH_MAX]
1922 [RTW_RATE_SECTION_MAX];
1923 s8 tx_pwr_limit_2g[RTW_REGD_MAX]
1924 [RTW_CHANNEL_WIDTH_MAX]
1925 [RTW_RATE_SECTION_MAX]
1926 [RTW_MAX_CHANNEL_NUM_2G];
1927 s8 tx_pwr_limit_5g[RTW_REGD_MAX]
1928 [RTW_CHANNEL_WIDTH_MAX]
1929 [RTW_RATE_SECTION_MAX]
1930 [RTW_MAX_CHANNEL_NUM_5G];
1931 s8 tx_pwr_tbl[RTW_RF_PATH_MAX]
1932 [DESC_RATE_MAX];
1933
1934 enum rtw_sar_bands sar_band;
1935 struct rtw_sar sar;
1936
1937 /* for 8821c set channel */
1938 u32 ch_param[3];
1939 };
1940
1941 struct rtw_path_div {
1942 enum rtw_bb_path current_tx_path;
1943 u32 path_a_sum;
1944 u32 path_b_sum;
1945 u16 path_a_cnt;
1946 u16 path_b_cnt;
1947 };
1948
1949 struct rtw_chan_info {
1950 int pri_ch_idx;
1951 int action_id;
1952 int bw;
1953 u8 extra_info;
1954 u8 channel;
1955 u16 timeout;
1956 };
1957
1958 struct rtw_chan_list {
1959 u32 buf_size;
1960 u32 ch_num;
1961 u32 size;
1962 u16 addr;
1963 };
1964
1965 struct rtw_hw_scan_info {
1966 struct ieee80211_vif *scanning_vif;
1967 u8 probe_pg_size;
1968 u8 op_pri_ch_idx;
1969 u8 op_pri_ch;
1970 u8 op_chan;
1971 u8 op_bw;
1972 };
1973
1974 struct rtw_dev {
1975 struct ieee80211_hw *hw;
1976 struct device *dev;
1977
1978 struct rtw_hci hci;
1979
1980 struct rtw_hw_scan_info scan_info;
1981 const struct rtw_chip_info *chip;
1982 struct rtw_hal hal;
1983 struct rtw_fifo_conf fifo;
1984 struct rtw_fw_state fw;
1985 struct rtw_efuse efuse;
1986 struct rtw_sec_desc sec;
1987 struct rtw_traffic_stats stats;
1988 struct rtw_regd regd;
1989 struct rtw_bf_info bf_info;
1990
1991 struct rtw_dm_info dm_info;
1992 struct rtw_coex coex;
1993
1994 /* ensures exclusive access from mac80211 callbacks */
1995 struct mutex mutex;
1996
1997 /* read/write rf register */
1998 spinlock_t rf_lock;
1999
2000 /* watch dog every 2 sec */
2001 struct delayed_work watch_dog_work;
2002 u32 watch_dog_cnt;
2003
2004 struct list_head rsvd_page_list;
2005
2006 /* c2h cmd queue & handler work */
2007 struct sk_buff_head c2h_queue;
2008 struct work_struct c2h_work;
2009 struct work_struct ips_work;
2010 struct work_struct fw_recovery_work;
2011 struct work_struct update_beacon_work;
2012
2013 /* used to protect txqs list */
2014 spinlock_t txq_lock;
2015 struct list_head txqs;
2016 struct workqueue_struct *tx_wq;
2017 struct work_struct tx_work;
2018 struct work_struct ba_work;
2019
2020 struct rtw_tx_report tx_report;
2021
2022 struct {
2023 /* incicate the mail box to use with fw */
2024 u8 last_box_num;
2025 /* protect to send h2c to fw */
2026 spinlock_t lock;
2027 u32 seq;
2028 } h2c;
2029
2030 /* lps power state & handler work */
2031 struct rtw_lps_conf lps_conf;
2032 bool ps_enabled;
2033 bool beacon_loss;
2034 struct completion lps_leave_check;
2035
2036 struct dentry *debugfs;
2037
2038 u8 sta_cnt;
2039 u32 rts_threshold;
2040
2041 DECLARE_BITMAP(mac_id_map, RTW_MAX_MAC_ID_NUM);
2042 DECLARE_BITMAP(flags, NUM_OF_RTW_FLAGS);
2043
2044 u8 mp_mode;
2045 struct rtw_path_div dm_path_div;
2046
2047 struct rtw_fw_state wow_fw;
2048 struct rtw_wow_param wow;
2049
2050 bool need_rfk;
2051 struct completion fw_scan_density;
2052
2053 /* hci related data, must be last */
2054 u8 priv[] __aligned(sizeof(void *));
2055 };
2056
2057 #include "hci.h"
2058
rtw_is_assoc(struct rtw_dev * rtwdev)2059 static inline bool rtw_is_assoc(struct rtw_dev *rtwdev)
2060 {
2061 return !!rtwdev->sta_cnt;
2062 }
2063
rtwtxq_to_txq(struct rtw_txq * rtwtxq)2064 static inline struct ieee80211_txq *rtwtxq_to_txq(struct rtw_txq *rtwtxq)
2065 {
2066 void *p = rtwtxq;
2067
2068 return container_of(p, struct ieee80211_txq, drv_priv);
2069 }
2070
rtwvif_to_vif(struct rtw_vif * rtwvif)2071 static inline struct ieee80211_vif *rtwvif_to_vif(struct rtw_vif *rtwvif)
2072 {
2073 void *p = rtwvif;
2074
2075 return container_of(p, struct ieee80211_vif, drv_priv);
2076 }
2077
rtw_ssid_equal(struct cfg80211_ssid * a,struct cfg80211_ssid * b)2078 static inline bool rtw_ssid_equal(struct cfg80211_ssid *a,
2079 struct cfg80211_ssid *b)
2080 {
2081 if (!a || !b || a->ssid_len != b->ssid_len)
2082 return false;
2083
2084 if (memcmp(a->ssid, b->ssid, a->ssid_len))
2085 return false;
2086
2087 return true;
2088 }
2089
rtw_chip_efuse_grant_on(struct rtw_dev * rtwdev)2090 static inline void rtw_chip_efuse_grant_on(struct rtw_dev *rtwdev)
2091 {
2092 if (rtwdev->chip->ops->efuse_grant)
2093 rtwdev->chip->ops->efuse_grant(rtwdev, true);
2094 }
2095
rtw_chip_efuse_grant_off(struct rtw_dev * rtwdev)2096 static inline void rtw_chip_efuse_grant_off(struct rtw_dev *rtwdev)
2097 {
2098 if (rtwdev->chip->ops->efuse_grant)
2099 rtwdev->chip->ops->efuse_grant(rtwdev, false);
2100 }
2101
rtw_chip_wcpu_11n(struct rtw_dev * rtwdev)2102 static inline bool rtw_chip_wcpu_11n(struct rtw_dev *rtwdev)
2103 {
2104 return rtwdev->chip->wlan_cpu == RTW_WCPU_11N;
2105 }
2106
rtw_chip_wcpu_11ac(struct rtw_dev * rtwdev)2107 static inline bool rtw_chip_wcpu_11ac(struct rtw_dev *rtwdev)
2108 {
2109 return rtwdev->chip->wlan_cpu == RTW_WCPU_11AC;
2110 }
2111
rtw_chip_has_rx_ldpc(struct rtw_dev * rtwdev)2112 static inline bool rtw_chip_has_rx_ldpc(struct rtw_dev *rtwdev)
2113 {
2114 return rtwdev->chip->rx_ldpc;
2115 }
2116
rtw_chip_has_tx_stbc(struct rtw_dev * rtwdev)2117 static inline bool rtw_chip_has_tx_stbc(struct rtw_dev *rtwdev)
2118 {
2119 return rtwdev->chip->tx_stbc;
2120 }
2121
rtw_release_macid(struct rtw_dev * rtwdev,u8 mac_id)2122 static inline void rtw_release_macid(struct rtw_dev *rtwdev, u8 mac_id)
2123 {
2124 clear_bit(mac_id, rtwdev->mac_id_map);
2125 }
2126
rtw_chip_dump_fw_crash(struct rtw_dev * rtwdev)2127 static inline int rtw_chip_dump_fw_crash(struct rtw_dev *rtwdev)
2128 {
2129 if (rtwdev->chip->ops->dump_fw_crash)
2130 return rtwdev->chip->ops->dump_fw_crash(rtwdev);
2131
2132 return 0;
2133 }
2134
2135 static inline
rtw_hw_to_nl80211_band(enum rtw_supported_band hw_band)2136 enum nl80211_band rtw_hw_to_nl80211_band(enum rtw_supported_band hw_band)
2137 {
2138 switch (hw_band) {
2139 default:
2140 case RTW_BAND_2G:
2141 return NL80211_BAND_2GHZ;
2142 case RTW_BAND_5G:
2143 return NL80211_BAND_5GHZ;
2144 case RTW_BAND_60G:
2145 return NL80211_BAND_60GHZ;
2146 }
2147 }
2148
2149 void rtw_set_rx_freq_band(struct rtw_rx_pkt_stat *pkt_stat, u8 channel);
2150 void rtw_set_dtim_period(struct rtw_dev *rtwdev, int dtim_period);
2151 void rtw_get_channel_params(struct cfg80211_chan_def *chandef,
2152 struct rtw_channel_params *ch_param);
2153 bool check_hw_ready(struct rtw_dev *rtwdev, u32 addr, u32 mask, u32 target);
2154 bool ltecoex_read_reg(struct rtw_dev *rtwdev, u16 offset, u32 *val);
2155 bool ltecoex_reg_write(struct rtw_dev *rtwdev, u16 offset, u32 value);
2156 void rtw_restore_reg(struct rtw_dev *rtwdev,
2157 struct rtw_backup_info *bckp, u32 num);
2158 void rtw_desc_to_mcsrate(u16 rate, u8 *mcs, u8 *nss);
2159 void rtw_set_channel(struct rtw_dev *rtwdev);
2160 void rtw_chip_prepare_tx(struct rtw_dev *rtwdev);
2161 void rtw_vif_port_config(struct rtw_dev *rtwdev, struct rtw_vif *rtwvif,
2162 u32 config);
2163 void rtw_tx_report_purge_timer(struct timer_list *t);
2164 void rtw_update_sta_info(struct rtw_dev *rtwdev, struct rtw_sta_info *si,
2165 bool reset_ra_mask);
2166 void rtw_core_scan_start(struct rtw_dev *rtwdev, struct rtw_vif *rtwvif,
2167 const u8 *mac_addr, bool hw_scan);
2168 void rtw_core_scan_complete(struct rtw_dev *rtwdev, struct ieee80211_vif *vif,
2169 bool hw_scan);
2170 int rtw_core_start(struct rtw_dev *rtwdev);
2171 void rtw_core_stop(struct rtw_dev *rtwdev);
2172 int rtw_chip_info_setup(struct rtw_dev *rtwdev);
2173 int rtw_core_init(struct rtw_dev *rtwdev);
2174 void rtw_core_deinit(struct rtw_dev *rtwdev);
2175 int rtw_register_hw(struct rtw_dev *rtwdev, struct ieee80211_hw *hw);
2176 void rtw_unregister_hw(struct rtw_dev *rtwdev, struct ieee80211_hw *hw);
2177 u16 rtw_desc_to_bitrate(u8 desc_rate);
2178 void rtw_vif_assoc_changed(struct rtw_vif *rtwvif,
2179 struct ieee80211_bss_conf *conf);
2180 int rtw_sta_add(struct rtw_dev *rtwdev, struct ieee80211_sta *sta,
2181 struct ieee80211_vif *vif);
2182 void rtw_sta_remove(struct rtw_dev *rtwdev, struct ieee80211_sta *sta,
2183 bool fw_exist);
2184 void rtw_fw_recovery(struct rtw_dev *rtwdev);
2185 void rtw_core_fw_scan_notify(struct rtw_dev *rtwdev, bool start);
2186 int rtw_dump_fw(struct rtw_dev *rtwdev, const u32 ocp_src, u32 size,
2187 u32 fwcd_item);
2188 int rtw_dump_reg(struct rtw_dev *rtwdev, const u32 addr, const u32 size);
2189 void rtw_set_txrx_1ss(struct rtw_dev *rtwdev, bool config_1ss);
2190 void rtw_update_channel(struct rtw_dev *rtwdev, u8 center_channel,
2191 u8 primary_channel, enum rtw_supported_band band,
2192 enum rtw_bandwidth bandwidth);
2193 #endif
2194
