1 /******************************************************************************
2 *
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * GPL LICENSE SUMMARY
7 *
8 * Copyright(c) 2017 Intel Deutschland GmbH
9 * Copyright(c) 2018 Intel Corporation
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of version 2 of the GNU General Public License as
13 * published by the Free Software Foundation.
14 *
15 * This program is distributed in the hope that it will be useful, but
16 * WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 * General Public License for more details.
19 *
20 * BSD LICENSE
21 *
22 * Copyright(c) 2017 Intel Deutschland GmbH
23 * Copyright(c) 2018 Intel Corporation
24 * All rights reserved.
25 *
26 * Redistribution and use in source and binary forms, with or without
27 * modification, are permitted provided that the following conditions
28 * are met:
29 *
30 * * Redistributions of source code must retain the above copyright
31 * notice, this list of conditions and the following disclaimer.
32 * * Redistributions in binary form must reproduce the above copyright
33 * notice, this list of conditions and the following disclaimer in
34 * the documentation and/or other materials provided with the
35 * distribution.
36 * * Neither the name Intel Corporation nor the names of its
37 * contributors may be used to endorse or promote products derived
38 * from this software without specific prior written permission.
39 *
40 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
41 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
42 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
43 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
44 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
45 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
46 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
47 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
48 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
49 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
50 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
51 *
52 *****************************************************************************/
53
54 #include "iwl-trans.h"
55 #include "iwl-fh.h"
56 #include "iwl-context-info.h"
57 #include "internal.h"
58 #include "iwl-prph.h"
59
iwl_pcie_ctxt_info_free_paging(struct iwl_trans * trans)60 void iwl_pcie_ctxt_info_free_paging(struct iwl_trans *trans)
61 {
62 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
63 struct iwl_self_init_dram *dram = &trans_pcie->init_dram;
64 int i;
65
66 if (!dram->paging) {
67 WARN_ON(dram->paging_cnt);
68 return;
69 }
70
71 /* free paging*/
72 for (i = 0; i < dram->paging_cnt; i++)
73 dma_free_coherent(trans->dev, dram->paging[i].size,
74 dram->paging[i].block,
75 dram->paging[i].physical);
76
77 kfree(dram->paging);
78 dram->paging_cnt = 0;
79 dram->paging = NULL;
80 }
81
iwl_pcie_init_fw_sec(struct iwl_trans * trans,const struct fw_img * fw,struct iwl_context_info_dram * ctxt_dram)82 int iwl_pcie_init_fw_sec(struct iwl_trans *trans,
83 const struct fw_img *fw,
84 struct iwl_context_info_dram *ctxt_dram)
85 {
86 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
87 struct iwl_self_init_dram *dram = &trans_pcie->init_dram;
88 int i, ret, lmac_cnt, umac_cnt, paging_cnt;
89
90 if (WARN(dram->paging,
91 "paging shouldn't already be initialized (%d pages)\n",
92 dram->paging_cnt))
93 iwl_pcie_ctxt_info_free_paging(trans);
94
95 lmac_cnt = iwl_pcie_get_num_sections(fw, 0);
96 /* add 1 due to separator */
97 umac_cnt = iwl_pcie_get_num_sections(fw, lmac_cnt + 1);
98 /* add 2 due to separators */
99 paging_cnt = iwl_pcie_get_num_sections(fw, lmac_cnt + umac_cnt + 2);
100
101 dram->fw = kcalloc(umac_cnt + lmac_cnt, sizeof(*dram->fw), GFP_KERNEL);
102 if (!dram->fw)
103 return -ENOMEM;
104 dram->paging = kcalloc(paging_cnt, sizeof(*dram->paging), GFP_KERNEL);
105 if (!dram->paging)
106 return -ENOMEM;
107
108 /* initialize lmac sections */
109 for (i = 0; i < lmac_cnt; i++) {
110 ret = iwl_pcie_ctxt_info_alloc_dma(trans, &fw->sec[i],
111 &dram->fw[dram->fw_cnt]);
112 if (ret)
113 return ret;
114 ctxt_dram->lmac_img[i] =
115 cpu_to_le64(dram->fw[dram->fw_cnt].physical);
116 dram->fw_cnt++;
117 }
118
119 /* initialize umac sections */
120 for (i = 0; i < umac_cnt; i++) {
121 /* access FW with +1 to make up for lmac separator */
122 ret = iwl_pcie_ctxt_info_alloc_dma(trans,
123 &fw->sec[dram->fw_cnt + 1],
124 &dram->fw[dram->fw_cnt]);
125 if (ret)
126 return ret;
127 ctxt_dram->umac_img[i] =
128 cpu_to_le64(dram->fw[dram->fw_cnt].physical);
129 dram->fw_cnt++;
130 }
131
132 /*
133 * Initialize paging.
134 * Paging memory isn't stored in dram->fw as the umac and lmac - it is
135 * stored separately.
136 * This is since the timing of its release is different -
137 * while fw memory can be released on alive, the paging memory can be
138 * freed only when the device goes down.
139 * Given that, the logic here in accessing the fw image is a bit
140 * different - fw_cnt isn't changing so loop counter is added to it.
141 */
142 for (i = 0; i < paging_cnt; i++) {
143 /* access FW with +2 to make up for lmac & umac separators */
144 int fw_idx = dram->fw_cnt + i + 2;
145
146 ret = iwl_pcie_ctxt_info_alloc_dma(trans, &fw->sec[fw_idx],
147 &dram->paging[i]);
148 if (ret)
149 return ret;
150
151 ctxt_dram->virtual_img[i] =
152 cpu_to_le64(dram->paging[i].physical);
153 dram->paging_cnt++;
154 }
155
156 return 0;
157 }
158
iwl_pcie_ctxt_info_init(struct iwl_trans * trans,const struct fw_img * fw)159 int iwl_pcie_ctxt_info_init(struct iwl_trans *trans,
160 const struct fw_img *fw)
161 {
162 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
163 struct iwl_context_info *ctxt_info;
164 struct iwl_context_info_rbd_cfg *rx_cfg;
165 u32 control_flags = 0;
166 int ret;
167
168 ctxt_info = dma_alloc_coherent(trans->dev, sizeof(*ctxt_info),
169 &trans_pcie->ctxt_info_dma_addr,
170 GFP_KERNEL);
171 if (!ctxt_info)
172 return -ENOMEM;
173
174 ctxt_info->version.version = 0;
175 ctxt_info->version.mac_id =
176 cpu_to_le16((u16)iwl_read32(trans, CSR_HW_REV));
177 /* size is in DWs */
178 ctxt_info->version.size = cpu_to_le16(sizeof(*ctxt_info) / 4);
179
180 BUILD_BUG_ON(RX_QUEUE_CB_SIZE(MQ_RX_TABLE_SIZE) > 0xF);
181 control_flags = IWL_CTXT_INFO_RB_SIZE_4K |
182 IWL_CTXT_INFO_TFD_FORMAT_LONG |
183 RX_QUEUE_CB_SIZE(MQ_RX_TABLE_SIZE) <<
184 IWL_CTXT_INFO_RB_CB_SIZE_POS;
185 ctxt_info->control.control_flags = cpu_to_le32(control_flags);
186
187 /* initialize RX default queue */
188 rx_cfg = &ctxt_info->rbd_cfg;
189 rx_cfg->free_rbd_addr = cpu_to_le64(trans_pcie->rxq->bd_dma);
190 rx_cfg->used_rbd_addr = cpu_to_le64(trans_pcie->rxq->used_bd_dma);
191 rx_cfg->status_wr_ptr = cpu_to_le64(trans_pcie->rxq->rb_stts_dma);
192
193 /* initialize TX command queue */
194 ctxt_info->hcmd_cfg.cmd_queue_addr =
195 cpu_to_le64(trans_pcie->txq[trans_pcie->cmd_queue]->dma_addr);
196 ctxt_info->hcmd_cfg.cmd_queue_size =
197 TFD_QUEUE_CB_SIZE(TFD_CMD_SLOTS);
198
199 /* allocate ucode sections in dram and set addresses */
200 ret = iwl_pcie_init_fw_sec(trans, fw, &ctxt_info->dram);
201 if (ret) {
202 dma_free_coherent(trans->dev, sizeof(*trans_pcie->ctxt_info),
203 ctxt_info, trans_pcie->ctxt_info_dma_addr);
204 return ret;
205 }
206
207 trans_pcie->ctxt_info = ctxt_info;
208
209 iwl_enable_interrupts(trans);
210
211 /* Configure debug, if exists */
212 if (trans->dbg_dest_tlv)
213 iwl_pcie_apply_destination(trans);
214
215 /* kick FW self load */
216 iwl_write64(trans, CSR_CTXT_INFO_BA, trans_pcie->ctxt_info_dma_addr);
217 iwl_write_prph(trans, UREG_CPU_INIT_RUN, 1);
218
219 /* Context info will be released upon alive or failure to get one */
220
221 return 0;
222 }
223
iwl_pcie_ctxt_info_free(struct iwl_trans * trans)224 void iwl_pcie_ctxt_info_free(struct iwl_trans *trans)
225 {
226 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
227
228 if (!trans_pcie->ctxt_info)
229 return;
230
231 dma_free_coherent(trans->dev, sizeof(*trans_pcie->ctxt_info),
232 trans_pcie->ctxt_info,
233 trans_pcie->ctxt_info_dma_addr);
234 trans_pcie->ctxt_info_dma_addr = 0;
235 trans_pcie->ctxt_info = NULL;
236
237 iwl_pcie_ctxt_info_free_fw_img(trans);
238 }
239
