1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Driver for CPM (SCC/SMC) serial ports; core driver
4 *
5 * Based on arch/ppc/cpm2_io/uart.c by Dan Malek
6 * Based on ppc8xx.c by Thomas Gleixner
7 * Based on drivers/serial/amba.c by Russell King
8 *
9 * Maintainer: Kumar Gala (galak@kernel.crashing.org) (CPM2)
10 * Pantelis Antoniou (panto@intracom.gr) (CPM1)
11 *
12 * Copyright (C) 2004, 2007 Freescale Semiconductor, Inc.
13 * (C) 2004 Intracom, S.A.
14 * (C) 2005-2006 MontaVista Software, Inc.
15 * Vitaly Bordug <vbordug@ru.mvista.com>
16 */
17
18 #include <linux/module.h>
19 #include <linux/tty.h>
20 #include <linux/tty_flip.h>
21 #include <linux/ioport.h>
22 #include <linux/init.h>
23 #include <linux/serial.h>
24 #include <linux/console.h>
25 #include <linux/sysrq.h>
26 #include <linux/device.h>
27 #include <linux/memblock.h>
28 #include <linux/dma-mapping.h>
29 #include <linux/fs_uart_pd.h>
30 #include <linux/of_address.h>
31 #include <linux/of_irq.h>
32 #include <linux/of_platform.h>
33 #include <linux/gpio/consumer.h>
34 #include <linux/clk.h>
35
36 #include <asm/io.h>
37 #include <asm/irq.h>
38 #include <asm/delay.h>
39 #include <asm/fs_pd.h>
40 #include <asm/udbg.h>
41
42 #include <linux/serial_core.h>
43 #include <linux/kernel.h>
44
45 #include "cpm_uart.h"
46
47
48 /**************************************************************/
49
50 static int cpm_uart_tx_pump(struct uart_port *port);
51 static void cpm_uart_init_smc(struct uart_cpm_port *pinfo);
52 static void cpm_uart_init_scc(struct uart_cpm_port *pinfo);
53 static void cpm_uart_initbd(struct uart_cpm_port *pinfo);
54
55 /**************************************************************/
56
57 #define HW_BUF_SPD_THRESHOLD 2400
58
59 /*
60 * Check, if transmit buffers are processed
61 */
cpm_uart_tx_empty(struct uart_port * port)62 static unsigned int cpm_uart_tx_empty(struct uart_port *port)
63 {
64 struct uart_cpm_port *pinfo =
65 container_of(port, struct uart_cpm_port, port);
66 cbd_t __iomem *bdp = pinfo->tx_bd_base;
67 int ret = 0;
68
69 while (1) {
70 if (in_be16(&bdp->cbd_sc) & BD_SC_READY)
71 break;
72
73 if (in_be16(&bdp->cbd_sc) & BD_SC_WRAP) {
74 ret = TIOCSER_TEMT;
75 break;
76 }
77 bdp++;
78 }
79
80 pr_debug("CPM uart[%d]:tx_empty: %d\n", port->line, ret);
81
82 return ret;
83 }
84
cpm_uart_set_mctrl(struct uart_port * port,unsigned int mctrl)85 static void cpm_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
86 {
87 struct uart_cpm_port *pinfo =
88 container_of(port, struct uart_cpm_port, port);
89
90 if (pinfo->gpios[GPIO_RTS])
91 gpiod_set_value(pinfo->gpios[GPIO_RTS], !(mctrl & TIOCM_RTS));
92
93 if (pinfo->gpios[GPIO_DTR])
94 gpiod_set_value(pinfo->gpios[GPIO_DTR], !(mctrl & TIOCM_DTR));
95 }
96
cpm_uart_get_mctrl(struct uart_port * port)97 static unsigned int cpm_uart_get_mctrl(struct uart_port *port)
98 {
99 struct uart_cpm_port *pinfo =
100 container_of(port, struct uart_cpm_port, port);
101 unsigned int mctrl = TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
102
103 if (pinfo->gpios[GPIO_CTS]) {
104 if (gpiod_get_value(pinfo->gpios[GPIO_CTS]))
105 mctrl &= ~TIOCM_CTS;
106 }
107
108 if (pinfo->gpios[GPIO_DSR]) {
109 if (gpiod_get_value(pinfo->gpios[GPIO_DSR]))
110 mctrl &= ~TIOCM_DSR;
111 }
112
113 if (pinfo->gpios[GPIO_DCD]) {
114 if (gpiod_get_value(pinfo->gpios[GPIO_DCD]))
115 mctrl &= ~TIOCM_CAR;
116 }
117
118 if (pinfo->gpios[GPIO_RI]) {
119 if (!gpiod_get_value(pinfo->gpios[GPIO_RI]))
120 mctrl |= TIOCM_RNG;
121 }
122
123 return mctrl;
124 }
125
126 /*
127 * Stop transmitter
128 */
cpm_uart_stop_tx(struct uart_port * port)129 static void cpm_uart_stop_tx(struct uart_port *port)
130 {
131 struct uart_cpm_port *pinfo =
132 container_of(port, struct uart_cpm_port, port);
133 smc_t __iomem *smcp = pinfo->smcp;
134 scc_t __iomem *sccp = pinfo->sccp;
135
136 pr_debug("CPM uart[%d]:stop tx\n", port->line);
137
138 if (IS_SMC(pinfo))
139 clrbits8(&smcp->smc_smcm, SMCM_TX);
140 else
141 clrbits16(&sccp->scc_sccm, UART_SCCM_TX);
142 }
143
144 /*
145 * Start transmitter
146 */
cpm_uart_start_tx(struct uart_port * port)147 static void cpm_uart_start_tx(struct uart_port *port)
148 {
149 struct uart_cpm_port *pinfo =
150 container_of(port, struct uart_cpm_port, port);
151 smc_t __iomem *smcp = pinfo->smcp;
152 scc_t __iomem *sccp = pinfo->sccp;
153
154 pr_debug("CPM uart[%d]:start tx\n", port->line);
155
156 if (IS_SMC(pinfo)) {
157 if (in_8(&smcp->smc_smcm) & SMCM_TX)
158 return;
159 } else {
160 if (in_be16(&sccp->scc_sccm) & UART_SCCM_TX)
161 return;
162 }
163
164 if (cpm_uart_tx_pump(port) != 0) {
165 if (IS_SMC(pinfo)) {
166 setbits8(&smcp->smc_smcm, SMCM_TX);
167 } else {
168 setbits16(&sccp->scc_sccm, UART_SCCM_TX);
169 }
170 }
171 }
172
173 /*
174 * Stop receiver
175 */
cpm_uart_stop_rx(struct uart_port * port)176 static void cpm_uart_stop_rx(struct uart_port *port)
177 {
178 struct uart_cpm_port *pinfo =
179 container_of(port, struct uart_cpm_port, port);
180 smc_t __iomem *smcp = pinfo->smcp;
181 scc_t __iomem *sccp = pinfo->sccp;
182
183 pr_debug("CPM uart[%d]:stop rx\n", port->line);
184
185 if (IS_SMC(pinfo))
186 clrbits8(&smcp->smc_smcm, SMCM_RX);
187 else
188 clrbits16(&sccp->scc_sccm, UART_SCCM_RX);
189 }
190
191 /*
192 * Generate a break.
193 */
cpm_uart_break_ctl(struct uart_port * port,int break_state)194 static void cpm_uart_break_ctl(struct uart_port *port, int break_state)
195 {
196 struct uart_cpm_port *pinfo =
197 container_of(port, struct uart_cpm_port, port);
198
199 pr_debug("CPM uart[%d]:break ctrl, break_state: %d\n", port->line,
200 break_state);
201
202 if (break_state)
203 cpm_line_cr_cmd(pinfo, CPM_CR_STOP_TX);
204 else
205 cpm_line_cr_cmd(pinfo, CPM_CR_RESTART_TX);
206 }
207
208 /*
209 * Transmit characters, refill buffer descriptor, if possible
210 */
cpm_uart_int_tx(struct uart_port * port)211 static void cpm_uart_int_tx(struct uart_port *port)
212 {
213 pr_debug("CPM uart[%d]:TX INT\n", port->line);
214
215 cpm_uart_tx_pump(port);
216 }
217
218 #ifdef CONFIG_CONSOLE_POLL
219 static int serial_polled;
220 #endif
221
222 /*
223 * Receive characters
224 */
cpm_uart_int_rx(struct uart_port * port)225 static void cpm_uart_int_rx(struct uart_port *port)
226 {
227 int i;
228 unsigned char ch;
229 u8 *cp;
230 struct tty_port *tport = &port->state->port;
231 struct uart_cpm_port *pinfo =
232 container_of(port, struct uart_cpm_port, port);
233 cbd_t __iomem *bdp;
234 u16 status;
235 unsigned int flg;
236
237 pr_debug("CPM uart[%d]:RX INT\n", port->line);
238
239 /* Just loop through the closed BDs and copy the characters into
240 * the buffer.
241 */
242 bdp = pinfo->rx_cur;
243 for (;;) {
244 #ifdef CONFIG_CONSOLE_POLL
245 if (unlikely(serial_polled)) {
246 serial_polled = 0;
247 return;
248 }
249 #endif
250 /* get status */
251 status = in_be16(&bdp->cbd_sc);
252 /* If this one is empty, return happy */
253 if (status & BD_SC_EMPTY)
254 break;
255
256 /* get number of characters, and check spce in flip-buffer */
257 i = in_be16(&bdp->cbd_datlen);
258
259 /* If we have not enough room in tty flip buffer, then we try
260 * later, which will be the next rx-interrupt or a timeout
261 */
262 if (tty_buffer_request_room(tport, i) < i) {
263 printk(KERN_WARNING "No room in flip buffer\n");
264 return;
265 }
266
267 /* get pointer */
268 cp = cpm2cpu_addr(in_be32(&bdp->cbd_bufaddr), pinfo);
269
270 /* loop through the buffer */
271 while (i-- > 0) {
272 ch = *cp++;
273 port->icount.rx++;
274 flg = TTY_NORMAL;
275
276 if (status &
277 (BD_SC_BR | BD_SC_FR | BD_SC_PR | BD_SC_OV))
278 goto handle_error;
279 if (uart_handle_sysrq_char(port, ch))
280 continue;
281 #ifdef CONFIG_CONSOLE_POLL
282 if (unlikely(serial_polled)) {
283 serial_polled = 0;
284 return;
285 }
286 #endif
287 error_return:
288 tty_insert_flip_char(tport, ch, flg);
289
290 } /* End while (i--) */
291
292 /* This BD is ready to be used again. Clear status. get next */
293 clrbits16(&bdp->cbd_sc, BD_SC_BR | BD_SC_FR | BD_SC_PR |
294 BD_SC_OV | BD_SC_ID);
295 setbits16(&bdp->cbd_sc, BD_SC_EMPTY);
296
297 if (in_be16(&bdp->cbd_sc) & BD_SC_WRAP)
298 bdp = pinfo->rx_bd_base;
299 else
300 bdp++;
301
302 } /* End for (;;) */
303
304 /* Write back buffer pointer */
305 pinfo->rx_cur = bdp;
306
307 /* activate BH processing */
308 tty_flip_buffer_push(tport);
309
310 return;
311
312 /* Error processing */
313
314 handle_error:
315 /* Statistics */
316 if (status & BD_SC_BR)
317 port->icount.brk++;
318 if (status & BD_SC_PR)
319 port->icount.parity++;
320 if (status & BD_SC_FR)
321 port->icount.frame++;
322 if (status & BD_SC_OV)
323 port->icount.overrun++;
324
325 /* Mask out ignored conditions */
326 status &= port->read_status_mask;
327
328 /* Handle the remaining ones */
329 if (status & BD_SC_BR)
330 flg = TTY_BREAK;
331 else if (status & BD_SC_PR)
332 flg = TTY_PARITY;
333 else if (status & BD_SC_FR)
334 flg = TTY_FRAME;
335
336 /* overrun does not affect the current character ! */
337 if (status & BD_SC_OV) {
338 ch = 0;
339 flg = TTY_OVERRUN;
340 /* We skip this buffer */
341 /* CHECK: Is really nothing senseful there */
342 /* ASSUMPTION: it contains nothing valid */
343 i = 0;
344 }
345 port->sysrq = 0;
346 goto error_return;
347 }
348
349 /*
350 * Asynchron mode interrupt handler
351 */
cpm_uart_int(int irq,void * data)352 static irqreturn_t cpm_uart_int(int irq, void *data)
353 {
354 u8 events;
355 struct uart_port *port = data;
356 struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port;
357 smc_t __iomem *smcp = pinfo->smcp;
358 scc_t __iomem *sccp = pinfo->sccp;
359
360 pr_debug("CPM uart[%d]:IRQ\n", port->line);
361
362 if (IS_SMC(pinfo)) {
363 events = in_8(&smcp->smc_smce);
364 out_8(&smcp->smc_smce, events);
365 if (events & SMCM_BRKE)
366 uart_handle_break(port);
367 if (events & SMCM_RX)
368 cpm_uart_int_rx(port);
369 if (events & SMCM_TX)
370 cpm_uart_int_tx(port);
371 } else {
372 events = in_be16(&sccp->scc_scce);
373 out_be16(&sccp->scc_scce, events);
374 if (events & UART_SCCM_BRKE)
375 uart_handle_break(port);
376 if (events & UART_SCCM_RX)
377 cpm_uart_int_rx(port);
378 if (events & UART_SCCM_TX)
379 cpm_uart_int_tx(port);
380 }
381 return (events) ? IRQ_HANDLED : IRQ_NONE;
382 }
383
cpm_uart_startup(struct uart_port * port)384 static int cpm_uart_startup(struct uart_port *port)
385 {
386 int retval;
387 struct uart_cpm_port *pinfo =
388 container_of(port, struct uart_cpm_port, port);
389
390 pr_debug("CPM uart[%d]:startup\n", port->line);
391
392 /* If the port is not the console, make sure rx is disabled. */
393 if (!(pinfo->flags & FLAG_CONSOLE)) {
394 /* Disable UART rx */
395 if (IS_SMC(pinfo)) {
396 clrbits16(&pinfo->smcp->smc_smcmr, SMCMR_REN);
397 clrbits8(&pinfo->smcp->smc_smcm, SMCM_RX);
398 } else {
399 clrbits32(&pinfo->sccp->scc_gsmrl, SCC_GSMRL_ENR);
400 clrbits16(&pinfo->sccp->scc_sccm, UART_SCCM_RX);
401 }
402 cpm_uart_initbd(pinfo);
403 if (IS_SMC(pinfo)) {
404 out_be32(&pinfo->smcup->smc_rstate, 0);
405 out_be32(&pinfo->smcup->smc_tstate, 0);
406 out_be16(&pinfo->smcup->smc_rbptr,
407 in_be16(&pinfo->smcup->smc_rbase));
408 out_be16(&pinfo->smcup->smc_tbptr,
409 in_be16(&pinfo->smcup->smc_tbase));
410 } else {
411 cpm_line_cr_cmd(pinfo, CPM_CR_INIT_TRX);
412 }
413 }
414 /* Install interrupt handler. */
415 retval = request_irq(port->irq, cpm_uart_int, 0, "cpm_uart", port);
416 if (retval)
417 return retval;
418
419 /* Startup rx-int */
420 if (IS_SMC(pinfo)) {
421 setbits8(&pinfo->smcp->smc_smcm, SMCM_RX);
422 setbits16(&pinfo->smcp->smc_smcmr, (SMCMR_REN | SMCMR_TEN));
423 } else {
424 setbits16(&pinfo->sccp->scc_sccm, UART_SCCM_RX);
425 setbits32(&pinfo->sccp->scc_gsmrl, (SCC_GSMRL_ENR | SCC_GSMRL_ENT));
426 }
427
428 return 0;
429 }
430
cpm_uart_wait_until_send(struct uart_cpm_port * pinfo)431 inline void cpm_uart_wait_until_send(struct uart_cpm_port *pinfo)
432 {
433 set_current_state(TASK_UNINTERRUPTIBLE);
434 schedule_timeout(pinfo->wait_closing);
435 }
436
437 /*
438 * Shutdown the uart
439 */
cpm_uart_shutdown(struct uart_port * port)440 static void cpm_uart_shutdown(struct uart_port *port)
441 {
442 struct uart_cpm_port *pinfo =
443 container_of(port, struct uart_cpm_port, port);
444
445 pr_debug("CPM uart[%d]:shutdown\n", port->line);
446
447 /* free interrupt handler */
448 free_irq(port->irq, port);
449
450 /* If the port is not the console, disable Rx and Tx. */
451 if (!(pinfo->flags & FLAG_CONSOLE)) {
452 /* Wait for all the BDs marked sent */
453 while(!cpm_uart_tx_empty(port)) {
454 set_current_state(TASK_UNINTERRUPTIBLE);
455 schedule_timeout(2);
456 }
457
458 if (pinfo->wait_closing)
459 cpm_uart_wait_until_send(pinfo);
460
461 /* Stop uarts */
462 if (IS_SMC(pinfo)) {
463 smc_t __iomem *smcp = pinfo->smcp;
464 clrbits16(&smcp->smc_smcmr, SMCMR_REN | SMCMR_TEN);
465 clrbits8(&smcp->smc_smcm, SMCM_RX | SMCM_TX);
466 } else {
467 scc_t __iomem *sccp = pinfo->sccp;
468 clrbits32(&sccp->scc_gsmrl, SCC_GSMRL_ENR | SCC_GSMRL_ENT);
469 clrbits16(&sccp->scc_sccm, UART_SCCM_TX | UART_SCCM_RX);
470 }
471
472 /* Shut them really down and reinit buffer descriptors */
473 if (IS_SMC(pinfo)) {
474 out_be16(&pinfo->smcup->smc_brkcr, 0);
475 cpm_line_cr_cmd(pinfo, CPM_CR_STOP_TX);
476 } else {
477 out_be16(&pinfo->sccup->scc_brkcr, 0);
478 cpm_line_cr_cmd(pinfo, CPM_CR_GRA_STOP_TX);
479 }
480
481 cpm_uart_initbd(pinfo);
482 }
483 }
484
cpm_uart_set_termios(struct uart_port * port,struct ktermios * termios,struct ktermios * old)485 static void cpm_uart_set_termios(struct uart_port *port,
486 struct ktermios *termios,
487 struct ktermios *old)
488 {
489 int baud;
490 unsigned long flags;
491 u16 cval, scval, prev_mode;
492 int bits, sbits;
493 struct uart_cpm_port *pinfo =
494 container_of(port, struct uart_cpm_port, port);
495 smc_t __iomem *smcp = pinfo->smcp;
496 scc_t __iomem *sccp = pinfo->sccp;
497 int maxidl;
498
499 pr_debug("CPM uart[%d]:set_termios\n", port->line);
500
501 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
502 if (baud < HW_BUF_SPD_THRESHOLD || port->flags & UPF_LOW_LATENCY)
503 pinfo->rx_fifosize = 1;
504 else
505 pinfo->rx_fifosize = RX_BUF_SIZE;
506
507 /* MAXIDL is the timeout after which a receive buffer is closed
508 * when not full if no more characters are received.
509 * We calculate it from the baudrate so that the duration is
510 * always the same at standard rates: about 4ms.
511 */
512 maxidl = baud / 2400;
513 if (maxidl < 1)
514 maxidl = 1;
515 if (maxidl > 0x10)
516 maxidl = 0x10;
517
518 /* Character length programmed into the mode register is the
519 * sum of: 1 start bit, number of data bits, 0 or 1 parity bit,
520 * 1 or 2 stop bits, minus 1.
521 * The value 'bits' counts this for us.
522 */
523 cval = 0;
524 scval = 0;
525
526 /* byte size */
527 bits = tty_get_char_size(termios->c_cflag);
528 sbits = bits - 5;
529
530 if (termios->c_cflag & CSTOPB) {
531 cval |= SMCMR_SL; /* Two stops */
532 scval |= SCU_PSMR_SL;
533 bits++;
534 }
535
536 if (termios->c_cflag & PARENB) {
537 cval |= SMCMR_PEN;
538 scval |= SCU_PSMR_PEN;
539 bits++;
540 if (!(termios->c_cflag & PARODD)) {
541 cval |= SMCMR_PM_EVEN;
542 scval |= (SCU_PSMR_REVP | SCU_PSMR_TEVP);
543 }
544 }
545
546 /*
547 * Update the timeout
548 */
549 uart_update_timeout(port, termios->c_cflag, baud);
550
551 /*
552 * Set up parity check flag
553 */
554 port->read_status_mask = (BD_SC_EMPTY | BD_SC_OV);
555 if (termios->c_iflag & INPCK)
556 port->read_status_mask |= BD_SC_FR | BD_SC_PR;
557 if ((termios->c_iflag & BRKINT) || (termios->c_iflag & PARMRK))
558 port->read_status_mask |= BD_SC_BR;
559
560 /*
561 * Characters to ignore
562 */
563 port->ignore_status_mask = 0;
564 if (termios->c_iflag & IGNPAR)
565 port->ignore_status_mask |= BD_SC_PR | BD_SC_FR;
566 if (termios->c_iflag & IGNBRK) {
567 port->ignore_status_mask |= BD_SC_BR;
568 /*
569 * If we're ignore parity and break indicators, ignore
570 * overruns too. (For real raw support).
571 */
572 if (termios->c_iflag & IGNPAR)
573 port->ignore_status_mask |= BD_SC_OV;
574 }
575 /*
576 * !!! ignore all characters if CREAD is not set
577 */
578 if ((termios->c_cflag & CREAD) == 0)
579 port->read_status_mask &= ~BD_SC_EMPTY;
580
581 spin_lock_irqsave(&port->lock, flags);
582
583 /* Start bit has not been added (so don't, because we would just
584 * subtract it later), and we need to add one for the number of
585 * stops bits (there is always at least one).
586 */
587 bits++;
588 if (IS_SMC(pinfo)) {
589 /*
590 * MRBLR can be changed while an SMC/SCC is operating only
591 * if it is done in a single bus cycle with one 16-bit move
592 * (not two 8-bit bus cycles back-to-back). This occurs when
593 * the cp shifts control to the next RxBD, so the change does
594 * not take effect immediately. To guarantee the exact RxBD
595 * on which the change occurs, change MRBLR only while the
596 * SMC/SCC receiver is disabled.
597 */
598 out_be16(&pinfo->smcup->smc_mrblr, pinfo->rx_fifosize);
599 out_be16(&pinfo->smcup->smc_maxidl, maxidl);
600
601 /* Set the mode register. We want to keep a copy of the
602 * enables, because we want to put them back if they were
603 * present.
604 */
605 prev_mode = in_be16(&smcp->smc_smcmr) & (SMCMR_REN | SMCMR_TEN);
606 /* Output in *one* operation, so we don't interrupt RX/TX if they
607 * were already enabled. */
608 out_be16(&smcp->smc_smcmr, smcr_mk_clen(bits) | cval |
609 SMCMR_SM_UART | prev_mode);
610 } else {
611 out_be16(&pinfo->sccup->scc_genscc.scc_mrblr, pinfo->rx_fifosize);
612 out_be16(&pinfo->sccup->scc_maxidl, maxidl);
613 out_be16(&sccp->scc_psmr, (sbits << 12) | scval);
614 }
615
616 if (pinfo->clk)
617 clk_set_rate(pinfo->clk, baud);
618 else
619 cpm_set_brg(pinfo->brg - 1, baud);
620 spin_unlock_irqrestore(&port->lock, flags);
621 }
622
cpm_uart_type(struct uart_port * port)623 static const char *cpm_uart_type(struct uart_port *port)
624 {
625 pr_debug("CPM uart[%d]:uart_type\n", port->line);
626
627 return port->type == PORT_CPM ? "CPM UART" : NULL;
628 }
629
630 /*
631 * verify the new serial_struct (for TIOCSSERIAL).
632 */
cpm_uart_verify_port(struct uart_port * port,struct serial_struct * ser)633 static int cpm_uart_verify_port(struct uart_port *port,
634 struct serial_struct *ser)
635 {
636 int ret = 0;
637
638 pr_debug("CPM uart[%d]:verify_port\n", port->line);
639
640 if (ser->type != PORT_UNKNOWN && ser->type != PORT_CPM)
641 ret = -EINVAL;
642 if (ser->irq < 0 || ser->irq >= nr_irqs)
643 ret = -EINVAL;
644 if (ser->baud_base < 9600)
645 ret = -EINVAL;
646 return ret;
647 }
648
649 /*
650 * Transmit characters, refill buffer descriptor, if possible
651 */
cpm_uart_tx_pump(struct uart_port * port)652 static int cpm_uart_tx_pump(struct uart_port *port)
653 {
654 cbd_t __iomem *bdp;
655 u8 *p;
656 int count;
657 struct uart_cpm_port *pinfo =
658 container_of(port, struct uart_cpm_port, port);
659 struct circ_buf *xmit = &port->state->xmit;
660
661 /* Handle xon/xoff */
662 if (port->x_char) {
663 /* Pick next descriptor and fill from buffer */
664 bdp = pinfo->tx_cur;
665
666 p = cpm2cpu_addr(in_be32(&bdp->cbd_bufaddr), pinfo);
667
668 *p++ = port->x_char;
669
670 out_be16(&bdp->cbd_datlen, 1);
671 setbits16(&bdp->cbd_sc, BD_SC_READY);
672 /* Get next BD. */
673 if (in_be16(&bdp->cbd_sc) & BD_SC_WRAP)
674 bdp = pinfo->tx_bd_base;
675 else
676 bdp++;
677 pinfo->tx_cur = bdp;
678
679 port->icount.tx++;
680 port->x_char = 0;
681 return 1;
682 }
683
684 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
685 cpm_uart_stop_tx(port);
686 return 0;
687 }
688
689 /* Pick next descriptor and fill from buffer */
690 bdp = pinfo->tx_cur;
691
692 while (!(in_be16(&bdp->cbd_sc) & BD_SC_READY) &&
693 xmit->tail != xmit->head) {
694 count = 0;
695 p = cpm2cpu_addr(in_be32(&bdp->cbd_bufaddr), pinfo);
696 while (count < pinfo->tx_fifosize) {
697 *p++ = xmit->buf[xmit->tail];
698 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
699 port->icount.tx++;
700 count++;
701 if (xmit->head == xmit->tail)
702 break;
703 }
704 out_be16(&bdp->cbd_datlen, count);
705 setbits16(&bdp->cbd_sc, BD_SC_READY);
706 /* Get next BD. */
707 if (in_be16(&bdp->cbd_sc) & BD_SC_WRAP)
708 bdp = pinfo->tx_bd_base;
709 else
710 bdp++;
711 }
712 pinfo->tx_cur = bdp;
713
714 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
715 uart_write_wakeup(port);
716
717 if (uart_circ_empty(xmit)) {
718 cpm_uart_stop_tx(port);
719 return 0;
720 }
721
722 return 1;
723 }
724
725 /*
726 * init buffer descriptors
727 */
cpm_uart_initbd(struct uart_cpm_port * pinfo)728 static void cpm_uart_initbd(struct uart_cpm_port *pinfo)
729 {
730 int i;
731 u8 *mem_addr;
732 cbd_t __iomem *bdp;
733
734 pr_debug("CPM uart[%d]:initbd\n", pinfo->port.line);
735
736 /* Set the physical address of the host memory
737 * buffers in the buffer descriptors, and the
738 * virtual address for us to work with.
739 */
740 mem_addr = pinfo->mem_addr;
741 bdp = pinfo->rx_cur = pinfo->rx_bd_base;
742 for (i = 0; i < (pinfo->rx_nrfifos - 1); i++, bdp++) {
743 out_be32(&bdp->cbd_bufaddr, cpu2cpm_addr(mem_addr, pinfo));
744 out_be16(&bdp->cbd_sc, BD_SC_EMPTY | BD_SC_INTRPT);
745 mem_addr += pinfo->rx_fifosize;
746 }
747
748 out_be32(&bdp->cbd_bufaddr, cpu2cpm_addr(mem_addr, pinfo));
749 out_be16(&bdp->cbd_sc, BD_SC_WRAP | BD_SC_EMPTY | BD_SC_INTRPT);
750
751 /* Set the physical address of the host memory
752 * buffers in the buffer descriptors, and the
753 * virtual address for us to work with.
754 */
755 mem_addr = pinfo->mem_addr + L1_CACHE_ALIGN(pinfo->rx_nrfifos * pinfo->rx_fifosize);
756 bdp = pinfo->tx_cur = pinfo->tx_bd_base;
757 for (i = 0; i < (pinfo->tx_nrfifos - 1); i++, bdp++) {
758 out_be32(&bdp->cbd_bufaddr, cpu2cpm_addr(mem_addr, pinfo));
759 out_be16(&bdp->cbd_sc, BD_SC_INTRPT);
760 mem_addr += pinfo->tx_fifosize;
761 }
762
763 out_be32(&bdp->cbd_bufaddr, cpu2cpm_addr(mem_addr, pinfo));
764 out_be16(&bdp->cbd_sc, BD_SC_WRAP | BD_SC_INTRPT);
765 }
766
cpm_uart_init_scc(struct uart_cpm_port * pinfo)767 static void cpm_uart_init_scc(struct uart_cpm_port *pinfo)
768 {
769 scc_t __iomem *scp;
770 scc_uart_t __iomem *sup;
771
772 pr_debug("CPM uart[%d]:init_scc\n", pinfo->port.line);
773
774 scp = pinfo->sccp;
775 sup = pinfo->sccup;
776
777 /* Store address */
778 out_be16(&pinfo->sccup->scc_genscc.scc_rbase,
779 (u8 __iomem *)pinfo->rx_bd_base - DPRAM_BASE);
780 out_be16(&pinfo->sccup->scc_genscc.scc_tbase,
781 (u8 __iomem *)pinfo->tx_bd_base - DPRAM_BASE);
782
783 /* Set up the uart parameters in the
784 * parameter ram.
785 */
786
787 cpm_set_scc_fcr(sup);
788
789 out_be16(&sup->scc_genscc.scc_mrblr, pinfo->rx_fifosize);
790 out_be16(&sup->scc_maxidl, 0x10);
791 out_be16(&sup->scc_brkcr, 1);
792 out_be16(&sup->scc_parec, 0);
793 out_be16(&sup->scc_frmec, 0);
794 out_be16(&sup->scc_nosec, 0);
795 out_be16(&sup->scc_brkec, 0);
796 out_be16(&sup->scc_uaddr1, 0);
797 out_be16(&sup->scc_uaddr2, 0);
798 out_be16(&sup->scc_toseq, 0);
799 out_be16(&sup->scc_char1, 0x8000);
800 out_be16(&sup->scc_char2, 0x8000);
801 out_be16(&sup->scc_char3, 0x8000);
802 out_be16(&sup->scc_char4, 0x8000);
803 out_be16(&sup->scc_char5, 0x8000);
804 out_be16(&sup->scc_char6, 0x8000);
805 out_be16(&sup->scc_char7, 0x8000);
806 out_be16(&sup->scc_char8, 0x8000);
807 out_be16(&sup->scc_rccm, 0xc0ff);
808
809 /* Send the CPM an initialize command.
810 */
811 cpm_line_cr_cmd(pinfo, CPM_CR_INIT_TRX);
812
813 /* Set UART mode, 8 bit, no parity, one stop.
814 * Enable receive and transmit.
815 */
816 out_be32(&scp->scc_gsmrh, 0);
817 out_be32(&scp->scc_gsmrl,
818 SCC_GSMRL_MODE_UART | SCC_GSMRL_TDCR_16 | SCC_GSMRL_RDCR_16);
819
820 /* Enable rx interrupts and clear all pending events. */
821 out_be16(&scp->scc_sccm, 0);
822 out_be16(&scp->scc_scce, 0xffff);
823 out_be16(&scp->scc_dsr, 0x7e7e);
824 out_be16(&scp->scc_psmr, 0x3000);
825
826 setbits32(&scp->scc_gsmrl, SCC_GSMRL_ENR | SCC_GSMRL_ENT);
827 }
828
cpm_uart_init_smc(struct uart_cpm_port * pinfo)829 static void cpm_uart_init_smc(struct uart_cpm_port *pinfo)
830 {
831 smc_t __iomem *sp;
832 smc_uart_t __iomem *up;
833
834 pr_debug("CPM uart[%d]:init_smc\n", pinfo->port.line);
835
836 sp = pinfo->smcp;
837 up = pinfo->smcup;
838
839 /* Store address */
840 out_be16(&pinfo->smcup->smc_rbase,
841 (u8 __iomem *)pinfo->rx_bd_base - DPRAM_BASE);
842 out_be16(&pinfo->smcup->smc_tbase,
843 (u8 __iomem *)pinfo->tx_bd_base - DPRAM_BASE);
844
845 /*
846 * In case SMC is being relocated...
847 */
848 out_be16(&up->smc_rbptr, in_be16(&pinfo->smcup->smc_rbase));
849 out_be16(&up->smc_tbptr, in_be16(&pinfo->smcup->smc_tbase));
850 out_be32(&up->smc_rstate, 0);
851 out_be32(&up->smc_tstate, 0);
852 out_be16(&up->smc_brkcr, 1); /* number of break chars */
853 out_be16(&up->smc_brkec, 0);
854
855 /* Set up the uart parameters in the
856 * parameter ram.
857 */
858 cpm_set_smc_fcr(up);
859
860 /* Using idle character time requires some additional tuning. */
861 out_be16(&up->smc_mrblr, pinfo->rx_fifosize);
862 out_be16(&up->smc_maxidl, 0x10);
863 out_be16(&up->smc_brklen, 0);
864 out_be16(&up->smc_brkec, 0);
865 out_be16(&up->smc_brkcr, 1);
866
867 /* Set UART mode, 8 bit, no parity, one stop.
868 * Enable receive and transmit.
869 */
870 out_be16(&sp->smc_smcmr, smcr_mk_clen(9) | SMCMR_SM_UART);
871
872 /* Enable only rx interrupts clear all pending events. */
873 out_8(&sp->smc_smcm, 0);
874 out_8(&sp->smc_smce, 0xff);
875
876 setbits16(&sp->smc_smcmr, SMCMR_REN | SMCMR_TEN);
877 }
878
879 /*
880 * Initialize port. This is called from early_console stuff
881 * so we have to be careful here !
882 */
cpm_uart_request_port(struct uart_port * port)883 static int cpm_uart_request_port(struct uart_port *port)
884 {
885 struct uart_cpm_port *pinfo =
886 container_of(port, struct uart_cpm_port, port);
887 int ret;
888
889 pr_debug("CPM uart[%d]:request port\n", port->line);
890
891 if (pinfo->flags & FLAG_CONSOLE)
892 return 0;
893
894 if (IS_SMC(pinfo)) {
895 clrbits8(&pinfo->smcp->smc_smcm, SMCM_RX | SMCM_TX);
896 clrbits16(&pinfo->smcp->smc_smcmr, SMCMR_REN | SMCMR_TEN);
897 } else {
898 clrbits16(&pinfo->sccp->scc_sccm, UART_SCCM_TX | UART_SCCM_RX);
899 clrbits32(&pinfo->sccp->scc_gsmrl, SCC_GSMRL_ENR | SCC_GSMRL_ENT);
900 }
901
902 ret = cpm_uart_allocbuf(pinfo, 0);
903
904 if (ret)
905 return ret;
906
907 cpm_uart_initbd(pinfo);
908 if (IS_SMC(pinfo))
909 cpm_uart_init_smc(pinfo);
910 else
911 cpm_uart_init_scc(pinfo);
912
913 return 0;
914 }
915
cpm_uart_release_port(struct uart_port * port)916 static void cpm_uart_release_port(struct uart_port *port)
917 {
918 struct uart_cpm_port *pinfo =
919 container_of(port, struct uart_cpm_port, port);
920
921 if (!(pinfo->flags & FLAG_CONSOLE))
922 cpm_uart_freebuf(pinfo);
923 }
924
925 /*
926 * Configure/autoconfigure the port.
927 */
cpm_uart_config_port(struct uart_port * port,int flags)928 static void cpm_uart_config_port(struct uart_port *port, int flags)
929 {
930 pr_debug("CPM uart[%d]:config_port\n", port->line);
931
932 if (flags & UART_CONFIG_TYPE) {
933 port->type = PORT_CPM;
934 cpm_uart_request_port(port);
935 }
936 }
937
938 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_CPM_CONSOLE)
939 /*
940 * Write a string to the serial port
941 * Note that this is called with interrupts already disabled
942 */
cpm_uart_early_write(struct uart_cpm_port * pinfo,const char * string,u_int count,bool handle_linefeed)943 static void cpm_uart_early_write(struct uart_cpm_port *pinfo,
944 const char *string, u_int count, bool handle_linefeed)
945 {
946 unsigned int i;
947 cbd_t __iomem *bdp, *bdbase;
948 unsigned char *cpm_outp_addr;
949
950 /* Get the address of the host memory buffer.
951 */
952 bdp = pinfo->tx_cur;
953 bdbase = pinfo->tx_bd_base;
954
955 /*
956 * Now, do each character. This is not as bad as it looks
957 * since this is a holding FIFO and not a transmitting FIFO.
958 * We could add the complexity of filling the entire transmit
959 * buffer, but we would just wait longer between accesses......
960 */
961 for (i = 0; i < count; i++, string++) {
962 /* Wait for transmitter fifo to empty.
963 * Ready indicates output is ready, and xmt is doing
964 * that, not that it is ready for us to send.
965 */
966 while ((in_be16(&bdp->cbd_sc) & BD_SC_READY) != 0)
967 ;
968
969 /* Send the character out.
970 * If the buffer address is in the CPM DPRAM, don't
971 * convert it.
972 */
973 cpm_outp_addr = cpm2cpu_addr(in_be32(&bdp->cbd_bufaddr),
974 pinfo);
975 *cpm_outp_addr = *string;
976
977 out_be16(&bdp->cbd_datlen, 1);
978 setbits16(&bdp->cbd_sc, BD_SC_READY);
979
980 if (in_be16(&bdp->cbd_sc) & BD_SC_WRAP)
981 bdp = bdbase;
982 else
983 bdp++;
984
985 /* if a LF, also do CR... */
986 if (handle_linefeed && *string == 10) {
987 while ((in_be16(&bdp->cbd_sc) & BD_SC_READY) != 0)
988 ;
989
990 cpm_outp_addr = cpm2cpu_addr(in_be32(&bdp->cbd_bufaddr),
991 pinfo);
992 *cpm_outp_addr = 13;
993
994 out_be16(&bdp->cbd_datlen, 1);
995 setbits16(&bdp->cbd_sc, BD_SC_READY);
996
997 if (in_be16(&bdp->cbd_sc) & BD_SC_WRAP)
998 bdp = bdbase;
999 else
1000 bdp++;
1001 }
1002 }
1003
1004 /*
1005 * Finally, Wait for transmitter & holding register to empty
1006 * and restore the IER
1007 */
1008 while ((in_be16(&bdp->cbd_sc) & BD_SC_READY) != 0)
1009 ;
1010
1011 pinfo->tx_cur = bdp;
1012 }
1013 #endif
1014
1015 #ifdef CONFIG_CONSOLE_POLL
1016 /* Serial polling routines for writing and reading from the uart while
1017 * in an interrupt or debug context.
1018 */
1019
1020 #define GDB_BUF_SIZE 512 /* power of 2, please */
1021
1022 static char poll_buf[GDB_BUF_SIZE];
1023 static char *pollp;
1024 static int poll_chars;
1025
poll_wait_key(char * obuf,struct uart_cpm_port * pinfo)1026 static int poll_wait_key(char *obuf, struct uart_cpm_port *pinfo)
1027 {
1028 u_char c, *cp;
1029 volatile cbd_t *bdp;
1030 int i;
1031
1032 /* Get the address of the host memory buffer.
1033 */
1034 bdp = pinfo->rx_cur;
1035 if (bdp->cbd_sc & BD_SC_EMPTY)
1036 return NO_POLL_CHAR;
1037
1038 /* If the buffer address is in the CPM DPRAM, don't
1039 * convert it.
1040 */
1041 cp = cpm2cpu_addr(bdp->cbd_bufaddr, pinfo);
1042
1043 if (obuf) {
1044 i = c = bdp->cbd_datlen;
1045 while (i-- > 0)
1046 *obuf++ = *cp++;
1047 } else
1048 c = *cp;
1049 bdp->cbd_sc &= ~(BD_SC_BR | BD_SC_FR | BD_SC_PR | BD_SC_OV | BD_SC_ID);
1050 bdp->cbd_sc |= BD_SC_EMPTY;
1051
1052 if (bdp->cbd_sc & BD_SC_WRAP)
1053 bdp = pinfo->rx_bd_base;
1054 else
1055 bdp++;
1056 pinfo->rx_cur = (cbd_t *)bdp;
1057
1058 return (int)c;
1059 }
1060
cpm_get_poll_char(struct uart_port * port)1061 static int cpm_get_poll_char(struct uart_port *port)
1062 {
1063 struct uart_cpm_port *pinfo =
1064 container_of(port, struct uart_cpm_port, port);
1065
1066 if (!serial_polled) {
1067 serial_polled = 1;
1068 poll_chars = 0;
1069 }
1070 if (poll_chars <= 0) {
1071 int ret = poll_wait_key(poll_buf, pinfo);
1072
1073 if (ret == NO_POLL_CHAR)
1074 return ret;
1075 poll_chars = ret;
1076 pollp = poll_buf;
1077 }
1078 poll_chars--;
1079 return *pollp++;
1080 }
1081
cpm_put_poll_char(struct uart_port * port,unsigned char c)1082 static void cpm_put_poll_char(struct uart_port *port,
1083 unsigned char c)
1084 {
1085 struct uart_cpm_port *pinfo =
1086 container_of(port, struct uart_cpm_port, port);
1087 static char ch[2];
1088
1089 ch[0] = (char)c;
1090 cpm_uart_early_write(pinfo, ch, 1, false);
1091 }
1092
1093 static struct uart_port *udbg_port;
1094
udbg_cpm_putc(char c)1095 static void udbg_cpm_putc(char c)
1096 {
1097 if (c == '\n')
1098 cpm_put_poll_char(udbg_port, '\r');
1099 cpm_put_poll_char(udbg_port, c);
1100 }
1101
udbg_cpm_getc_poll(void)1102 static int udbg_cpm_getc_poll(void)
1103 {
1104 int c = cpm_get_poll_char(udbg_port);
1105
1106 return c == NO_POLL_CHAR ? -1 : c;
1107 }
1108
udbg_cpm_getc(void)1109 static int udbg_cpm_getc(void)
1110 {
1111 int c;
1112
1113 while ((c = udbg_cpm_getc_poll()) == -1)
1114 cpu_relax();
1115 return c;
1116 }
1117
1118 #endif /* CONFIG_CONSOLE_POLL */
1119
1120 static const struct uart_ops cpm_uart_pops = {
1121 .tx_empty = cpm_uart_tx_empty,
1122 .set_mctrl = cpm_uart_set_mctrl,
1123 .get_mctrl = cpm_uart_get_mctrl,
1124 .stop_tx = cpm_uart_stop_tx,
1125 .start_tx = cpm_uart_start_tx,
1126 .stop_rx = cpm_uart_stop_rx,
1127 .break_ctl = cpm_uart_break_ctl,
1128 .startup = cpm_uart_startup,
1129 .shutdown = cpm_uart_shutdown,
1130 .set_termios = cpm_uart_set_termios,
1131 .type = cpm_uart_type,
1132 .release_port = cpm_uart_release_port,
1133 .request_port = cpm_uart_request_port,
1134 .config_port = cpm_uart_config_port,
1135 .verify_port = cpm_uart_verify_port,
1136 #ifdef CONFIG_CONSOLE_POLL
1137 .poll_get_char = cpm_get_poll_char,
1138 .poll_put_char = cpm_put_poll_char,
1139 #endif
1140 };
1141
1142 struct uart_cpm_port cpm_uart_ports[UART_NR];
1143
cpm_uart_init_port(struct device_node * np,struct uart_cpm_port * pinfo)1144 static int cpm_uart_init_port(struct device_node *np,
1145 struct uart_cpm_port *pinfo)
1146 {
1147 const u32 *data;
1148 void __iomem *mem, *pram;
1149 struct device *dev = pinfo->port.dev;
1150 int len;
1151 int ret;
1152 int i;
1153
1154 data = of_get_property(np, "clock", NULL);
1155 if (data) {
1156 struct clk *clk = clk_get(NULL, (const char*)data);
1157 if (!IS_ERR(clk))
1158 pinfo->clk = clk;
1159 }
1160 if (!pinfo->clk) {
1161 data = of_get_property(np, "fsl,cpm-brg", &len);
1162 if (!data || len != 4) {
1163 printk(KERN_ERR "CPM UART %pOFn has no/invalid "
1164 "fsl,cpm-brg property.\n", np);
1165 return -EINVAL;
1166 }
1167 pinfo->brg = *data;
1168 }
1169
1170 data = of_get_property(np, "fsl,cpm-command", &len);
1171 if (!data || len != 4) {
1172 printk(KERN_ERR "CPM UART %pOFn has no/invalid "
1173 "fsl,cpm-command property.\n", np);
1174 return -EINVAL;
1175 }
1176 pinfo->command = *data;
1177
1178 mem = of_iomap(np, 0);
1179 if (!mem)
1180 return -ENOMEM;
1181
1182 if (of_device_is_compatible(np, "fsl,cpm1-scc-uart") ||
1183 of_device_is_compatible(np, "fsl,cpm2-scc-uart")) {
1184 pinfo->sccp = mem;
1185 pinfo->sccup = pram = cpm_uart_map_pram(pinfo, np);
1186 } else if (of_device_is_compatible(np, "fsl,cpm1-smc-uart") ||
1187 of_device_is_compatible(np, "fsl,cpm2-smc-uart")) {
1188 pinfo->flags |= FLAG_SMC;
1189 pinfo->smcp = mem;
1190 pinfo->smcup = pram = cpm_uart_map_pram(pinfo, np);
1191 } else {
1192 ret = -ENODEV;
1193 goto out_mem;
1194 }
1195
1196 if (!pram) {
1197 ret = -ENOMEM;
1198 goto out_mem;
1199 }
1200
1201 pinfo->tx_nrfifos = TX_NUM_FIFO;
1202 pinfo->tx_fifosize = TX_BUF_SIZE;
1203 pinfo->rx_nrfifos = RX_NUM_FIFO;
1204 pinfo->rx_fifosize = RX_BUF_SIZE;
1205
1206 pinfo->port.uartclk = ppc_proc_freq;
1207 pinfo->port.mapbase = (unsigned long)mem;
1208 pinfo->port.type = PORT_CPM;
1209 pinfo->port.ops = &cpm_uart_pops;
1210 pinfo->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_CPM_CONSOLE);
1211 pinfo->port.iotype = UPIO_MEM;
1212 pinfo->port.fifosize = pinfo->tx_nrfifos * pinfo->tx_fifosize;
1213 spin_lock_init(&pinfo->port.lock);
1214
1215 pinfo->port.irq = irq_of_parse_and_map(np, 0);
1216 if (pinfo->port.irq == NO_IRQ) {
1217 ret = -EINVAL;
1218 goto out_pram;
1219 }
1220
1221 for (i = 0; i < NUM_GPIOS; i++) {
1222 struct gpio_desc *gpiod;
1223
1224 pinfo->gpios[i] = NULL;
1225
1226 gpiod = devm_gpiod_get_index_optional(dev, NULL, i, GPIOD_ASIS);
1227
1228 if (IS_ERR(gpiod)) {
1229 ret = PTR_ERR(gpiod);
1230 goto out_irq;
1231 }
1232
1233 if (gpiod) {
1234 if (i == GPIO_RTS || i == GPIO_DTR)
1235 ret = gpiod_direction_output(gpiod, 0);
1236 else
1237 ret = gpiod_direction_input(gpiod);
1238 if (ret) {
1239 pr_err("can't set direction for gpio #%d: %d\n",
1240 i, ret);
1241 continue;
1242 }
1243 pinfo->gpios[i] = gpiod;
1244 }
1245 }
1246
1247 #ifdef CONFIG_PPC_EARLY_DEBUG_CPM
1248 #ifdef CONFIG_CONSOLE_POLL
1249 if (!udbg_port)
1250 #endif
1251 udbg_putc = NULL;
1252 #endif
1253
1254 return cpm_uart_request_port(&pinfo->port);
1255
1256 out_irq:
1257 irq_dispose_mapping(pinfo->port.irq);
1258 out_pram:
1259 cpm_uart_unmap_pram(pinfo, pram);
1260 out_mem:
1261 iounmap(mem);
1262 return ret;
1263 }
1264
1265 #ifdef CONFIG_SERIAL_CPM_CONSOLE
1266 /*
1267 * Print a string to the serial port trying not to disturb
1268 * any possible real use of the port...
1269 *
1270 * Note that this is called with interrupts already disabled
1271 */
cpm_uart_console_write(struct console * co,const char * s,u_int count)1272 static void cpm_uart_console_write(struct console *co, const char *s,
1273 u_int count)
1274 {
1275 struct uart_cpm_port *pinfo = &cpm_uart_ports[co->index];
1276 unsigned long flags;
1277 int nolock = oops_in_progress;
1278
1279 if (unlikely(nolock)) {
1280 local_irq_save(flags);
1281 } else {
1282 spin_lock_irqsave(&pinfo->port.lock, flags);
1283 }
1284
1285 cpm_uart_early_write(pinfo, s, count, true);
1286
1287 if (unlikely(nolock)) {
1288 local_irq_restore(flags);
1289 } else {
1290 spin_unlock_irqrestore(&pinfo->port.lock, flags);
1291 }
1292 }
1293
1294
cpm_uart_console_setup(struct console * co,char * options)1295 static int __init cpm_uart_console_setup(struct console *co, char *options)
1296 {
1297 int baud = 38400;
1298 int bits = 8;
1299 int parity = 'n';
1300 int flow = 'n';
1301 int ret;
1302 struct uart_cpm_port *pinfo;
1303 struct uart_port *port;
1304
1305 struct device_node *np;
1306 int i = 0;
1307
1308 if (co->index >= UART_NR) {
1309 printk(KERN_ERR "cpm_uart: console index %d too high\n",
1310 co->index);
1311 return -ENODEV;
1312 }
1313
1314 for_each_node_by_type(np, "serial") {
1315 if (!of_device_is_compatible(np, "fsl,cpm1-smc-uart") &&
1316 !of_device_is_compatible(np, "fsl,cpm1-scc-uart") &&
1317 !of_device_is_compatible(np, "fsl,cpm2-smc-uart") &&
1318 !of_device_is_compatible(np, "fsl,cpm2-scc-uart"))
1319 continue;
1320
1321 if (i++ == co->index)
1322 break;
1323 }
1324
1325 if (!np)
1326 return -ENODEV;
1327
1328 pinfo = &cpm_uart_ports[co->index];
1329
1330 pinfo->flags |= FLAG_CONSOLE;
1331 port = &pinfo->port;
1332
1333 ret = cpm_uart_init_port(np, pinfo);
1334 of_node_put(np);
1335 if (ret)
1336 return ret;
1337
1338 if (options) {
1339 uart_parse_options(options, &baud, &parity, &bits, &flow);
1340 } else {
1341 if ((baud = uart_baudrate()) == -1)
1342 baud = 9600;
1343 }
1344
1345 if (IS_SMC(pinfo)) {
1346 out_be16(&pinfo->smcup->smc_brkcr, 0);
1347 cpm_line_cr_cmd(pinfo, CPM_CR_STOP_TX);
1348 clrbits8(&pinfo->smcp->smc_smcm, SMCM_RX | SMCM_TX);
1349 clrbits16(&pinfo->smcp->smc_smcmr, SMCMR_REN | SMCMR_TEN);
1350 } else {
1351 out_be16(&pinfo->sccup->scc_brkcr, 0);
1352 cpm_line_cr_cmd(pinfo, CPM_CR_GRA_STOP_TX);
1353 clrbits16(&pinfo->sccp->scc_sccm, UART_SCCM_TX | UART_SCCM_RX);
1354 clrbits32(&pinfo->sccp->scc_gsmrl, SCC_GSMRL_ENR | SCC_GSMRL_ENT);
1355 }
1356
1357 ret = cpm_uart_allocbuf(pinfo, 1);
1358
1359 if (ret)
1360 return ret;
1361
1362 cpm_uart_initbd(pinfo);
1363
1364 if (IS_SMC(pinfo))
1365 cpm_uart_init_smc(pinfo);
1366 else
1367 cpm_uart_init_scc(pinfo);
1368
1369 uart_set_options(port, co, baud, parity, bits, flow);
1370 cpm_line_cr_cmd(pinfo, CPM_CR_RESTART_TX);
1371
1372 #ifdef CONFIG_CONSOLE_POLL
1373 if (!udbg_port) {
1374 udbg_port = &pinfo->port;
1375 udbg_putc = udbg_cpm_putc;
1376 udbg_getc = udbg_cpm_getc;
1377 udbg_getc_poll = udbg_cpm_getc_poll;
1378 }
1379 #endif
1380
1381 return 0;
1382 }
1383
1384 static struct uart_driver cpm_reg;
1385 static struct console cpm_scc_uart_console = {
1386 .name = "ttyCPM",
1387 .write = cpm_uart_console_write,
1388 .device = uart_console_device,
1389 .setup = cpm_uart_console_setup,
1390 .flags = CON_PRINTBUFFER,
1391 .index = -1,
1392 .data = &cpm_reg,
1393 };
1394
cpm_uart_console_init(void)1395 static int __init cpm_uart_console_init(void)
1396 {
1397 cpm_muram_init();
1398 register_console(&cpm_scc_uart_console);
1399 return 0;
1400 }
1401
1402 console_initcall(cpm_uart_console_init);
1403
1404 #define CPM_UART_CONSOLE &cpm_scc_uart_console
1405 #else
1406 #define CPM_UART_CONSOLE NULL
1407 #endif
1408
1409 static struct uart_driver cpm_reg = {
1410 .owner = THIS_MODULE,
1411 .driver_name = "ttyCPM",
1412 .dev_name = "ttyCPM",
1413 .major = SERIAL_CPM_MAJOR,
1414 .minor = SERIAL_CPM_MINOR,
1415 .cons = CPM_UART_CONSOLE,
1416 .nr = UART_NR,
1417 };
1418
1419 static int probe_index;
1420
cpm_uart_probe(struct platform_device * ofdev)1421 static int cpm_uart_probe(struct platform_device *ofdev)
1422 {
1423 int index = probe_index++;
1424 struct uart_cpm_port *pinfo = &cpm_uart_ports[index];
1425 int ret;
1426
1427 pinfo->port.line = index;
1428
1429 if (index >= UART_NR)
1430 return -ENODEV;
1431
1432 platform_set_drvdata(ofdev, pinfo);
1433
1434 /* initialize the device pointer for the port */
1435 pinfo->port.dev = &ofdev->dev;
1436
1437 ret = cpm_uart_init_port(ofdev->dev.of_node, pinfo);
1438 if (ret)
1439 return ret;
1440
1441 return uart_add_one_port(&cpm_reg, &pinfo->port);
1442 }
1443
cpm_uart_remove(struct platform_device * ofdev)1444 static int cpm_uart_remove(struct platform_device *ofdev)
1445 {
1446 struct uart_cpm_port *pinfo = platform_get_drvdata(ofdev);
1447 return uart_remove_one_port(&cpm_reg, &pinfo->port);
1448 }
1449
1450 static const struct of_device_id cpm_uart_match[] = {
1451 {
1452 .compatible = "fsl,cpm1-smc-uart",
1453 },
1454 {
1455 .compatible = "fsl,cpm1-scc-uart",
1456 },
1457 {
1458 .compatible = "fsl,cpm2-smc-uart",
1459 },
1460 {
1461 .compatible = "fsl,cpm2-scc-uart",
1462 },
1463 {}
1464 };
1465 MODULE_DEVICE_TABLE(of, cpm_uart_match);
1466
1467 static struct platform_driver cpm_uart_driver = {
1468 .driver = {
1469 .name = "cpm_uart",
1470 .of_match_table = cpm_uart_match,
1471 },
1472 .probe = cpm_uart_probe,
1473 .remove = cpm_uart_remove,
1474 };
1475
cpm_uart_init(void)1476 static int __init cpm_uart_init(void)
1477 {
1478 int ret = uart_register_driver(&cpm_reg);
1479 if (ret)
1480 return ret;
1481
1482 ret = platform_driver_register(&cpm_uart_driver);
1483 if (ret)
1484 uart_unregister_driver(&cpm_reg);
1485
1486 return ret;
1487 }
1488
cpm_uart_exit(void)1489 static void __exit cpm_uart_exit(void)
1490 {
1491 platform_driver_unregister(&cpm_uart_driver);
1492 uart_unregister_driver(&cpm_reg);
1493 }
1494
1495 module_init(cpm_uart_init);
1496 module_exit(cpm_uart_exit);
1497
1498 MODULE_AUTHOR("Kumar Gala/Antoniou Pantelis");
1499 MODULE_DESCRIPTION("CPM SCC/SMC port driver $Revision: 0.01 $");
1500 MODULE_LICENSE("GPL");
1501 MODULE_ALIAS_CHARDEV(SERIAL_CPM_MAJOR, SERIAL_CPM_MINOR);
1502
