1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Renesas Clock Pulse Generator / Module Standby and Software Reset
4 *
5 * Copyright (C) 2015 Glider bvba
6 *
7 * Based on clk-mstp.c, clk-rcar-gen2.c, and clk-rcar-gen3.c
8 *
9 * Copyright (C) 2013 Ideas On Board SPRL
10 * Copyright (C) 2015 Renesas Electronics Corp.
11 */
12
13 #include <linux/clk.h>
14 #include <linux/clk-provider.h>
15 #include <linux/clk/renesas.h>
16 #include <linux/delay.h>
17 #include <linux/device.h>
18 #include <linux/init.h>
19 #include <linux/io.h>
20 #include <linux/mod_devicetable.h>
21 #include <linux/module.h>
22 #include <linux/of_address.h>
23 #include <linux/of_device.h>
24 #include <linux/platform_device.h>
25 #include <linux/pm_clock.h>
26 #include <linux/pm_domain.h>
27 #include <linux/psci.h>
28 #include <linux/reset-controller.h>
29 #include <linux/slab.h>
30
31 #include <dt-bindings/clock/renesas-cpg-mssr.h>
32
33 #include "renesas-cpg-mssr.h"
34 #include "clk-div6.h"
35
36 #ifdef DEBUG
37 #define WARN_DEBUG(x) WARN_ON(x)
38 #else
39 #define WARN_DEBUG(x) do { } while (0)
40 #endif
41
42
43 /*
44 * Module Standby and Software Reset register offets.
45 *
46 * If the registers exist, these are valid for SH-Mobile, R-Mobile,
47 * R-Car Gen2, R-Car Gen3, and RZ/G1.
48 * These are NOT valid for R-Car Gen1 and RZ/A1!
49 */
50
51 /*
52 * Module Stop Status Register offsets
53 */
54
55 static const u16 mstpsr[] = {
56 0x030, 0x038, 0x040, 0x048, 0x04C, 0x03C, 0x1C0, 0x1C4,
57 0x9A0, 0x9A4, 0x9A8, 0x9AC,
58 };
59
60 static const u16 mstpsr_for_v3u[] = {
61 0x2E00, 0x2E04, 0x2E08, 0x2E0C, 0x2E10, 0x2E14, 0x2E18, 0x2E1C,
62 0x2E20, 0x2E24, 0x2E28, 0x2E2C, 0x2E30, 0x2E34, 0x2E38,
63 };
64
65 /*
66 * System Module Stop Control Register offsets
67 */
68
69 static const u16 smstpcr[] = {
70 0x130, 0x134, 0x138, 0x13C, 0x140, 0x144, 0x148, 0x14C,
71 0x990, 0x994, 0x998, 0x99C,
72 };
73
74 static const u16 mstpcr_for_v3u[] = {
75 0x2D00, 0x2D04, 0x2D08, 0x2D0C, 0x2D10, 0x2D14, 0x2D18, 0x2D1C,
76 0x2D20, 0x2D24, 0x2D28, 0x2D2C, 0x2D30, 0x2D34, 0x2D38,
77 };
78
79 /*
80 * Standby Control Register offsets (RZ/A)
81 * Base address is FRQCR register
82 */
83
84 static const u16 stbcr[] = {
85 0xFFFF/*dummy*/, 0x010, 0x014, 0x410, 0x414, 0x418, 0x41C, 0x420,
86 0x424, 0x428, 0x42C,
87 };
88
89 /*
90 * Software Reset Register offsets
91 */
92
93 static const u16 srcr[] = {
94 0x0A0, 0x0A8, 0x0B0, 0x0B8, 0x0BC, 0x0C4, 0x1C8, 0x1CC,
95 0x920, 0x924, 0x928, 0x92C,
96 };
97
98 static const u16 srcr_for_v3u[] = {
99 0x2C00, 0x2C04, 0x2C08, 0x2C0C, 0x2C10, 0x2C14, 0x2C18, 0x2C1C,
100 0x2C20, 0x2C24, 0x2C28, 0x2C2C, 0x2C30, 0x2C34, 0x2C38,
101 };
102
103 /*
104 * Software Reset Clearing Register offsets
105 */
106
107 static const u16 srstclr[] = {
108 0x940, 0x944, 0x948, 0x94C, 0x950, 0x954, 0x958, 0x95C,
109 0x960, 0x964, 0x968, 0x96C,
110 };
111
112 static const u16 srstclr_for_v3u[] = {
113 0x2C80, 0x2C84, 0x2C88, 0x2C8C, 0x2C90, 0x2C94, 0x2C98, 0x2C9C,
114 0x2CA0, 0x2CA4, 0x2CA8, 0x2CAC, 0x2CB0, 0x2CB4, 0x2CB8,
115 };
116
117 /**
118 * struct cpg_mssr_priv - Clock Pulse Generator / Module Standby
119 * and Software Reset Private Data
120 *
121 * @rcdev: Optional reset controller entity
122 * @dev: CPG/MSSR device
123 * @base: CPG/MSSR register block base address
124 * @reg_layout: CPG/MSSR register layout
125 * @rmw_lock: protects RMW register accesses
126 * @np: Device node in DT for this CPG/MSSR module
127 * @num_core_clks: Number of Core Clocks in clks[]
128 * @num_mod_clks: Number of Module Clocks in clks[]
129 * @last_dt_core_clk: ID of the last Core Clock exported to DT
130 * @notifiers: Notifier chain to save/restore clock state for system resume
131 * @status_regs: Pointer to status registers array
132 * @control_regs: Pointer to control registers array
133 * @reset_regs: Pointer to reset registers array
134 * @reset_clear_regs: Pointer to reset clearing registers array
135 * @smstpcr_saved: [].mask: Mask of SMSTPCR[] bits under our control
136 * [].val: Saved values of SMSTPCR[]
137 * @clks: Array containing all Core and Module Clocks
138 */
139 struct cpg_mssr_priv {
140 #ifdef CONFIG_RESET_CONTROLLER
141 struct reset_controller_dev rcdev;
142 #endif
143 struct device *dev;
144 void __iomem *base;
145 enum clk_reg_layout reg_layout;
146 spinlock_t rmw_lock;
147 struct device_node *np;
148
149 unsigned int num_core_clks;
150 unsigned int num_mod_clks;
151 unsigned int last_dt_core_clk;
152
153 struct raw_notifier_head notifiers;
154 const u16 *status_regs;
155 const u16 *control_regs;
156 const u16 *reset_regs;
157 const u16 *reset_clear_regs;
158 struct {
159 u32 mask;
160 u32 val;
161 } smstpcr_saved[ARRAY_SIZE(mstpsr_for_v3u)];
162
163 struct clk *clks[];
164 };
165
166 static struct cpg_mssr_priv *cpg_mssr_priv;
167
168 /**
169 * struct mstp_clock - MSTP gating clock
170 * @hw: handle between common and hardware-specific interfaces
171 * @index: MSTP clock number
172 * @priv: CPG/MSSR private data
173 */
174 struct mstp_clock {
175 struct clk_hw hw;
176 u32 index;
177 struct cpg_mssr_priv *priv;
178 };
179
180 #define to_mstp_clock(_hw) container_of(_hw, struct mstp_clock, hw)
181
cpg_mstp_clock_endisable(struct clk_hw * hw,bool enable)182 static int cpg_mstp_clock_endisable(struct clk_hw *hw, bool enable)
183 {
184 struct mstp_clock *clock = to_mstp_clock(hw);
185 struct cpg_mssr_priv *priv = clock->priv;
186 unsigned int reg = clock->index / 32;
187 unsigned int bit = clock->index % 32;
188 struct device *dev = priv->dev;
189 u32 bitmask = BIT(bit);
190 unsigned long flags;
191 unsigned int i;
192 u32 value;
193
194 dev_dbg(dev, "MSTP %u%02u/%pC %s\n", reg, bit, hw->clk,
195 enable ? "ON" : "OFF");
196 spin_lock_irqsave(&priv->rmw_lock, flags);
197
198 if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) {
199 value = readb(priv->base + priv->control_regs[reg]);
200 if (enable)
201 value &= ~bitmask;
202 else
203 value |= bitmask;
204 writeb(value, priv->base + priv->control_regs[reg]);
205
206 /* dummy read to ensure write has completed */
207 readb(priv->base + priv->control_regs[reg]);
208 barrier_data(priv->base + priv->control_regs[reg]);
209 } else {
210 value = readl(priv->base + priv->control_regs[reg]);
211 if (enable)
212 value &= ~bitmask;
213 else
214 value |= bitmask;
215 writel(value, priv->base + priv->control_regs[reg]);
216 }
217
218 spin_unlock_irqrestore(&priv->rmw_lock, flags);
219
220 if (!enable || priv->reg_layout == CLK_REG_LAYOUT_RZ_A)
221 return 0;
222
223 for (i = 1000; i > 0; --i) {
224 if (!(readl(priv->base + priv->status_regs[reg]) & bitmask))
225 break;
226 cpu_relax();
227 }
228
229 if (!i) {
230 dev_err(dev, "Failed to enable SMSTP %p[%d]\n",
231 priv->base + priv->control_regs[reg], bit);
232 return -ETIMEDOUT;
233 }
234
235 return 0;
236 }
237
cpg_mstp_clock_enable(struct clk_hw * hw)238 static int cpg_mstp_clock_enable(struct clk_hw *hw)
239 {
240 return cpg_mstp_clock_endisable(hw, true);
241 }
242
cpg_mstp_clock_disable(struct clk_hw * hw)243 static void cpg_mstp_clock_disable(struct clk_hw *hw)
244 {
245 cpg_mstp_clock_endisable(hw, false);
246 }
247
cpg_mstp_clock_is_enabled(struct clk_hw * hw)248 static int cpg_mstp_clock_is_enabled(struct clk_hw *hw)
249 {
250 struct mstp_clock *clock = to_mstp_clock(hw);
251 struct cpg_mssr_priv *priv = clock->priv;
252 u32 value;
253
254 if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A)
255 value = readb(priv->base + priv->control_regs[clock->index / 32]);
256 else
257 value = readl(priv->base + priv->status_regs[clock->index / 32]);
258
259 return !(value & BIT(clock->index % 32));
260 }
261
262 static const struct clk_ops cpg_mstp_clock_ops = {
263 .enable = cpg_mstp_clock_enable,
264 .disable = cpg_mstp_clock_disable,
265 .is_enabled = cpg_mstp_clock_is_enabled,
266 };
267
268 static
cpg_mssr_clk_src_twocell_get(struct of_phandle_args * clkspec,void * data)269 struct clk *cpg_mssr_clk_src_twocell_get(struct of_phandle_args *clkspec,
270 void *data)
271 {
272 unsigned int clkidx = clkspec->args[1];
273 struct cpg_mssr_priv *priv = data;
274 struct device *dev = priv->dev;
275 unsigned int idx;
276 const char *type;
277 struct clk *clk;
278 int range_check;
279
280 switch (clkspec->args[0]) {
281 case CPG_CORE:
282 type = "core";
283 if (clkidx > priv->last_dt_core_clk) {
284 dev_err(dev, "Invalid %s clock index %u\n", type,
285 clkidx);
286 return ERR_PTR(-EINVAL);
287 }
288 clk = priv->clks[clkidx];
289 break;
290
291 case CPG_MOD:
292 type = "module";
293 if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) {
294 idx = MOD_CLK_PACK_10(clkidx);
295 range_check = 7 - (clkidx % 10);
296 } else {
297 idx = MOD_CLK_PACK(clkidx);
298 range_check = 31 - (clkidx % 100);
299 }
300 if (range_check < 0 || idx >= priv->num_mod_clks) {
301 dev_err(dev, "Invalid %s clock index %u\n", type,
302 clkidx);
303 return ERR_PTR(-EINVAL);
304 }
305 clk = priv->clks[priv->num_core_clks + idx];
306 break;
307
308 default:
309 dev_err(dev, "Invalid CPG clock type %u\n", clkspec->args[0]);
310 return ERR_PTR(-EINVAL);
311 }
312
313 if (IS_ERR(clk))
314 dev_err(dev, "Cannot get %s clock %u: %ld", type, clkidx,
315 PTR_ERR(clk));
316 else
317 dev_dbg(dev, "clock (%u, %u) is %pC at %lu Hz\n",
318 clkspec->args[0], clkspec->args[1], clk,
319 clk_get_rate(clk));
320 return clk;
321 }
322
cpg_mssr_register_core_clk(const struct cpg_core_clk * core,const struct cpg_mssr_info * info,struct cpg_mssr_priv * priv)323 static void __init cpg_mssr_register_core_clk(const struct cpg_core_clk *core,
324 const struct cpg_mssr_info *info,
325 struct cpg_mssr_priv *priv)
326 {
327 struct clk *clk = ERR_PTR(-ENOTSUPP), *parent;
328 struct device *dev = priv->dev;
329 unsigned int id = core->id, div = core->div;
330 const char *parent_name;
331
332 WARN_DEBUG(id >= priv->num_core_clks);
333 WARN_DEBUG(PTR_ERR(priv->clks[id]) != -ENOENT);
334
335 if (!core->name) {
336 /* Skip NULLified clock */
337 return;
338 }
339
340 switch (core->type) {
341 case CLK_TYPE_IN:
342 clk = of_clk_get_by_name(priv->np, core->name);
343 break;
344
345 case CLK_TYPE_FF:
346 case CLK_TYPE_DIV6P1:
347 case CLK_TYPE_DIV6_RO:
348 WARN_DEBUG(core->parent >= priv->num_core_clks);
349 parent = priv->clks[core->parent];
350 if (IS_ERR(parent)) {
351 clk = parent;
352 goto fail;
353 }
354
355 parent_name = __clk_get_name(parent);
356
357 if (core->type == CLK_TYPE_DIV6_RO)
358 /* Multiply with the DIV6 register value */
359 div *= (readl(priv->base + core->offset) & 0x3f) + 1;
360
361 if (core->type == CLK_TYPE_DIV6P1) {
362 clk = cpg_div6_register(core->name, 1, &parent_name,
363 priv->base + core->offset,
364 &priv->notifiers);
365 } else {
366 clk = clk_register_fixed_factor(NULL, core->name,
367 parent_name, 0,
368 core->mult, div);
369 }
370 break;
371
372 case CLK_TYPE_FR:
373 clk = clk_register_fixed_rate(NULL, core->name, NULL, 0,
374 core->mult);
375 break;
376
377 default:
378 if (info->cpg_clk_register)
379 clk = info->cpg_clk_register(dev, core, info,
380 priv->clks, priv->base,
381 &priv->notifiers);
382 else
383 dev_err(dev, "%s has unsupported core clock type %u\n",
384 core->name, core->type);
385 break;
386 }
387
388 if (IS_ERR_OR_NULL(clk))
389 goto fail;
390
391 dev_dbg(dev, "Core clock %pC at %lu Hz\n", clk, clk_get_rate(clk));
392 priv->clks[id] = clk;
393 return;
394
395 fail:
396 dev_err(dev, "Failed to register %s clock %s: %ld\n", "core",
397 core->name, PTR_ERR(clk));
398 }
399
cpg_mssr_register_mod_clk(const struct mssr_mod_clk * mod,const struct cpg_mssr_info * info,struct cpg_mssr_priv * priv)400 static void __init cpg_mssr_register_mod_clk(const struct mssr_mod_clk *mod,
401 const struct cpg_mssr_info *info,
402 struct cpg_mssr_priv *priv)
403 {
404 struct mstp_clock *clock = NULL;
405 struct device *dev = priv->dev;
406 unsigned int id = mod->id;
407 struct clk_init_data init = {};
408 struct clk *parent, *clk;
409 const char *parent_name;
410 unsigned int i;
411
412 WARN_DEBUG(id < priv->num_core_clks);
413 WARN_DEBUG(id >= priv->num_core_clks + priv->num_mod_clks);
414 WARN_DEBUG(mod->parent >= priv->num_core_clks + priv->num_mod_clks);
415 WARN_DEBUG(PTR_ERR(priv->clks[id]) != -ENOENT);
416
417 if (!mod->name) {
418 /* Skip NULLified clock */
419 return;
420 }
421
422 parent = priv->clks[mod->parent];
423 if (IS_ERR(parent)) {
424 clk = parent;
425 goto fail;
426 }
427
428 clock = kzalloc(sizeof(*clock), GFP_KERNEL);
429 if (!clock) {
430 clk = ERR_PTR(-ENOMEM);
431 goto fail;
432 }
433
434 init.name = mod->name;
435 init.ops = &cpg_mstp_clock_ops;
436 init.flags = CLK_SET_RATE_PARENT;
437 parent_name = __clk_get_name(parent);
438 init.parent_names = &parent_name;
439 init.num_parents = 1;
440
441 clock->index = id - priv->num_core_clks;
442 clock->priv = priv;
443 clock->hw.init = &init;
444
445 for (i = 0; i < info->num_crit_mod_clks; i++)
446 if (id == info->crit_mod_clks[i] &&
447 cpg_mstp_clock_is_enabled(&clock->hw)) {
448 dev_dbg(dev, "MSTP %s setting CLK_IS_CRITICAL\n",
449 mod->name);
450 init.flags |= CLK_IS_CRITICAL;
451 break;
452 }
453
454 clk = clk_register(NULL, &clock->hw);
455 if (IS_ERR(clk))
456 goto fail;
457
458 dev_dbg(dev, "Module clock %pC at %lu Hz\n", clk, clk_get_rate(clk));
459 priv->clks[id] = clk;
460 priv->smstpcr_saved[clock->index / 32].mask |= BIT(clock->index % 32);
461 return;
462
463 fail:
464 dev_err(dev, "Failed to register %s clock %s: %ld\n", "module",
465 mod->name, PTR_ERR(clk));
466 kfree(clock);
467 }
468
469 struct cpg_mssr_clk_domain {
470 struct generic_pm_domain genpd;
471 unsigned int num_core_pm_clks;
472 unsigned int core_pm_clks[];
473 };
474
475 static struct cpg_mssr_clk_domain *cpg_mssr_clk_domain;
476
cpg_mssr_is_pm_clk(const struct of_phandle_args * clkspec,struct cpg_mssr_clk_domain * pd)477 static bool cpg_mssr_is_pm_clk(const struct of_phandle_args *clkspec,
478 struct cpg_mssr_clk_domain *pd)
479 {
480 unsigned int i;
481
482 if (clkspec->np != pd->genpd.dev.of_node || clkspec->args_count != 2)
483 return false;
484
485 switch (clkspec->args[0]) {
486 case CPG_CORE:
487 for (i = 0; i < pd->num_core_pm_clks; i++)
488 if (clkspec->args[1] == pd->core_pm_clks[i])
489 return true;
490 return false;
491
492 case CPG_MOD:
493 return true;
494
495 default:
496 return false;
497 }
498 }
499
cpg_mssr_attach_dev(struct generic_pm_domain * unused,struct device * dev)500 int cpg_mssr_attach_dev(struct generic_pm_domain *unused, struct device *dev)
501 {
502 struct cpg_mssr_clk_domain *pd = cpg_mssr_clk_domain;
503 struct device_node *np = dev->of_node;
504 struct of_phandle_args clkspec;
505 struct clk *clk;
506 int i = 0;
507 int error;
508
509 if (!pd) {
510 dev_dbg(dev, "CPG/MSSR clock domain not yet available\n");
511 return -EPROBE_DEFER;
512 }
513
514 while (!of_parse_phandle_with_args(np, "clocks", "#clock-cells", i,
515 &clkspec)) {
516 if (cpg_mssr_is_pm_clk(&clkspec, pd))
517 goto found;
518
519 of_node_put(clkspec.np);
520 i++;
521 }
522
523 return 0;
524
525 found:
526 clk = of_clk_get_from_provider(&clkspec);
527 of_node_put(clkspec.np);
528
529 if (IS_ERR(clk))
530 return PTR_ERR(clk);
531
532 error = pm_clk_create(dev);
533 if (error)
534 goto fail_put;
535
536 error = pm_clk_add_clk(dev, clk);
537 if (error)
538 goto fail_destroy;
539
540 return 0;
541
542 fail_destroy:
543 pm_clk_destroy(dev);
544 fail_put:
545 clk_put(clk);
546 return error;
547 }
548
cpg_mssr_detach_dev(struct generic_pm_domain * unused,struct device * dev)549 void cpg_mssr_detach_dev(struct generic_pm_domain *unused, struct device *dev)
550 {
551 if (!pm_clk_no_clocks(dev))
552 pm_clk_destroy(dev);
553 }
554
cpg_mssr_add_clk_domain(struct device * dev,const unsigned int * core_pm_clks,unsigned int num_core_pm_clks)555 static int __init cpg_mssr_add_clk_domain(struct device *dev,
556 const unsigned int *core_pm_clks,
557 unsigned int num_core_pm_clks)
558 {
559 struct device_node *np = dev->of_node;
560 struct generic_pm_domain *genpd;
561 struct cpg_mssr_clk_domain *pd;
562 size_t pm_size = num_core_pm_clks * sizeof(core_pm_clks[0]);
563
564 pd = devm_kzalloc(dev, sizeof(*pd) + pm_size, GFP_KERNEL);
565 if (!pd)
566 return -ENOMEM;
567
568 pd->num_core_pm_clks = num_core_pm_clks;
569 memcpy(pd->core_pm_clks, core_pm_clks, pm_size);
570
571 genpd = &pd->genpd;
572 genpd->name = np->name;
573 genpd->flags = GENPD_FLAG_PM_CLK | GENPD_FLAG_ALWAYS_ON |
574 GENPD_FLAG_ACTIVE_WAKEUP;
575 genpd->attach_dev = cpg_mssr_attach_dev;
576 genpd->detach_dev = cpg_mssr_detach_dev;
577 pm_genpd_init(genpd, &pm_domain_always_on_gov, false);
578 cpg_mssr_clk_domain = pd;
579
580 of_genpd_add_provider_simple(np, genpd);
581 return 0;
582 }
583
584 #ifdef CONFIG_RESET_CONTROLLER
585
586 #define rcdev_to_priv(x) container_of(x, struct cpg_mssr_priv, rcdev)
587
cpg_mssr_reset(struct reset_controller_dev * rcdev,unsigned long id)588 static int cpg_mssr_reset(struct reset_controller_dev *rcdev,
589 unsigned long id)
590 {
591 struct cpg_mssr_priv *priv = rcdev_to_priv(rcdev);
592 unsigned int reg = id / 32;
593 unsigned int bit = id % 32;
594 u32 bitmask = BIT(bit);
595
596 dev_dbg(priv->dev, "reset %u%02u\n", reg, bit);
597
598 /* Reset module */
599 writel(bitmask, priv->base + priv->reset_regs[reg]);
600
601 /* Wait for at least one cycle of the RCLK clock (@ ca. 32 kHz) */
602 udelay(35);
603
604 /* Release module from reset state */
605 writel(bitmask, priv->base + priv->reset_clear_regs[reg]);
606
607 return 0;
608 }
609
cpg_mssr_assert(struct reset_controller_dev * rcdev,unsigned long id)610 static int cpg_mssr_assert(struct reset_controller_dev *rcdev, unsigned long id)
611 {
612 struct cpg_mssr_priv *priv = rcdev_to_priv(rcdev);
613 unsigned int reg = id / 32;
614 unsigned int bit = id % 32;
615 u32 bitmask = BIT(bit);
616
617 dev_dbg(priv->dev, "assert %u%02u\n", reg, bit);
618
619 writel(bitmask, priv->base + priv->reset_regs[reg]);
620 return 0;
621 }
622
cpg_mssr_deassert(struct reset_controller_dev * rcdev,unsigned long id)623 static int cpg_mssr_deassert(struct reset_controller_dev *rcdev,
624 unsigned long id)
625 {
626 struct cpg_mssr_priv *priv = rcdev_to_priv(rcdev);
627 unsigned int reg = id / 32;
628 unsigned int bit = id % 32;
629 u32 bitmask = BIT(bit);
630
631 dev_dbg(priv->dev, "deassert %u%02u\n", reg, bit);
632
633 writel(bitmask, priv->base + priv->reset_clear_regs[reg]);
634 return 0;
635 }
636
cpg_mssr_status(struct reset_controller_dev * rcdev,unsigned long id)637 static int cpg_mssr_status(struct reset_controller_dev *rcdev,
638 unsigned long id)
639 {
640 struct cpg_mssr_priv *priv = rcdev_to_priv(rcdev);
641 unsigned int reg = id / 32;
642 unsigned int bit = id % 32;
643 u32 bitmask = BIT(bit);
644
645 return !!(readl(priv->base + priv->reset_regs[reg]) & bitmask);
646 }
647
648 static const struct reset_control_ops cpg_mssr_reset_ops = {
649 .reset = cpg_mssr_reset,
650 .assert = cpg_mssr_assert,
651 .deassert = cpg_mssr_deassert,
652 .status = cpg_mssr_status,
653 };
654
cpg_mssr_reset_xlate(struct reset_controller_dev * rcdev,const struct of_phandle_args * reset_spec)655 static int cpg_mssr_reset_xlate(struct reset_controller_dev *rcdev,
656 const struct of_phandle_args *reset_spec)
657 {
658 struct cpg_mssr_priv *priv = rcdev_to_priv(rcdev);
659 unsigned int unpacked = reset_spec->args[0];
660 unsigned int idx = MOD_CLK_PACK(unpacked);
661
662 if (unpacked % 100 > 31 || idx >= rcdev->nr_resets) {
663 dev_err(priv->dev, "Invalid reset index %u\n", unpacked);
664 return -EINVAL;
665 }
666
667 return idx;
668 }
669
cpg_mssr_reset_controller_register(struct cpg_mssr_priv * priv)670 static int cpg_mssr_reset_controller_register(struct cpg_mssr_priv *priv)
671 {
672 priv->rcdev.ops = &cpg_mssr_reset_ops;
673 priv->rcdev.of_node = priv->dev->of_node;
674 priv->rcdev.of_reset_n_cells = 1;
675 priv->rcdev.of_xlate = cpg_mssr_reset_xlate;
676 priv->rcdev.nr_resets = priv->num_mod_clks;
677 return devm_reset_controller_register(priv->dev, &priv->rcdev);
678 }
679
680 #else /* !CONFIG_RESET_CONTROLLER */
cpg_mssr_reset_controller_register(struct cpg_mssr_priv * priv)681 static inline int cpg_mssr_reset_controller_register(struct cpg_mssr_priv *priv)
682 {
683 return 0;
684 }
685 #endif /* !CONFIG_RESET_CONTROLLER */
686
687
688 static const struct of_device_id cpg_mssr_match[] = {
689 #ifdef CONFIG_CLK_R7S9210
690 {
691 .compatible = "renesas,r7s9210-cpg-mssr",
692 .data = &r7s9210_cpg_mssr_info,
693 },
694 #endif
695 #ifdef CONFIG_CLK_R8A7742
696 {
697 .compatible = "renesas,r8a7742-cpg-mssr",
698 .data = &r8a7742_cpg_mssr_info,
699 },
700 #endif
701 #ifdef CONFIG_CLK_R8A7743
702 {
703 .compatible = "renesas,r8a7743-cpg-mssr",
704 .data = &r8a7743_cpg_mssr_info,
705 },
706 /* RZ/G1N is (almost) identical to RZ/G1M w.r.t. clocks. */
707 {
708 .compatible = "renesas,r8a7744-cpg-mssr",
709 .data = &r8a7743_cpg_mssr_info,
710 },
711 #endif
712 #ifdef CONFIG_CLK_R8A7745
713 {
714 .compatible = "renesas,r8a7745-cpg-mssr",
715 .data = &r8a7745_cpg_mssr_info,
716 },
717 #endif
718 #ifdef CONFIG_CLK_R8A77470
719 {
720 .compatible = "renesas,r8a77470-cpg-mssr",
721 .data = &r8a77470_cpg_mssr_info,
722 },
723 #endif
724 #ifdef CONFIG_CLK_R8A774A1
725 {
726 .compatible = "renesas,r8a774a1-cpg-mssr",
727 .data = &r8a774a1_cpg_mssr_info,
728 },
729 #endif
730 #ifdef CONFIG_CLK_R8A774B1
731 {
732 .compatible = "renesas,r8a774b1-cpg-mssr",
733 .data = &r8a774b1_cpg_mssr_info,
734 },
735 #endif
736 #ifdef CONFIG_CLK_R8A774C0
737 {
738 .compatible = "renesas,r8a774c0-cpg-mssr",
739 .data = &r8a774c0_cpg_mssr_info,
740 },
741 #endif
742 #ifdef CONFIG_CLK_R8A774E1
743 {
744 .compatible = "renesas,r8a774e1-cpg-mssr",
745 .data = &r8a774e1_cpg_mssr_info,
746 },
747 #endif
748 #ifdef CONFIG_CLK_R8A7790
749 {
750 .compatible = "renesas,r8a7790-cpg-mssr",
751 .data = &r8a7790_cpg_mssr_info,
752 },
753 #endif
754 #ifdef CONFIG_CLK_R8A7791
755 {
756 .compatible = "renesas,r8a7791-cpg-mssr",
757 .data = &r8a7791_cpg_mssr_info,
758 },
759 /* R-Car M2-N is (almost) identical to R-Car M2-W w.r.t. clocks. */
760 {
761 .compatible = "renesas,r8a7793-cpg-mssr",
762 .data = &r8a7791_cpg_mssr_info,
763 },
764 #endif
765 #ifdef CONFIG_CLK_R8A7792
766 {
767 .compatible = "renesas,r8a7792-cpg-mssr",
768 .data = &r8a7792_cpg_mssr_info,
769 },
770 #endif
771 #ifdef CONFIG_CLK_R8A7794
772 {
773 .compatible = "renesas,r8a7794-cpg-mssr",
774 .data = &r8a7794_cpg_mssr_info,
775 },
776 #endif
777 #ifdef CONFIG_CLK_R8A7795
778 {
779 .compatible = "renesas,r8a7795-cpg-mssr",
780 .data = &r8a7795_cpg_mssr_info,
781 },
782 #endif
783 #ifdef CONFIG_CLK_R8A77960
784 {
785 .compatible = "renesas,r8a7796-cpg-mssr",
786 .data = &r8a7796_cpg_mssr_info,
787 },
788 #endif
789 #ifdef CONFIG_CLK_R8A77961
790 {
791 .compatible = "renesas,r8a77961-cpg-mssr",
792 .data = &r8a7796_cpg_mssr_info,
793 },
794 #endif
795 #ifdef CONFIG_CLK_R8A77965
796 {
797 .compatible = "renesas,r8a77965-cpg-mssr",
798 .data = &r8a77965_cpg_mssr_info,
799 },
800 #endif
801 #ifdef CONFIG_CLK_R8A77970
802 {
803 .compatible = "renesas,r8a77970-cpg-mssr",
804 .data = &r8a77970_cpg_mssr_info,
805 },
806 #endif
807 #ifdef CONFIG_CLK_R8A77980
808 {
809 .compatible = "renesas,r8a77980-cpg-mssr",
810 .data = &r8a77980_cpg_mssr_info,
811 },
812 #endif
813 #ifdef CONFIG_CLK_R8A77990
814 {
815 .compatible = "renesas,r8a77990-cpg-mssr",
816 .data = &r8a77990_cpg_mssr_info,
817 },
818 #endif
819 #ifdef CONFIG_CLK_R8A77995
820 {
821 .compatible = "renesas,r8a77995-cpg-mssr",
822 .data = &r8a77995_cpg_mssr_info,
823 },
824 #endif
825 #ifdef CONFIG_CLK_R8A779A0
826 {
827 .compatible = "renesas,r8a779a0-cpg-mssr",
828 .data = &r8a779a0_cpg_mssr_info,
829 },
830 #endif
831 { /* sentinel */ }
832 };
833
cpg_mssr_del_clk_provider(void * data)834 static void cpg_mssr_del_clk_provider(void *data)
835 {
836 of_clk_del_provider(data);
837 }
838
839 #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM_PSCI_FW)
cpg_mssr_suspend_noirq(struct device * dev)840 static int cpg_mssr_suspend_noirq(struct device *dev)
841 {
842 struct cpg_mssr_priv *priv = dev_get_drvdata(dev);
843 unsigned int reg;
844
845 /* This is the best we can do to check for the presence of PSCI */
846 if (!psci_ops.cpu_suspend)
847 return 0;
848
849 /* Save module registers with bits under our control */
850 for (reg = 0; reg < ARRAY_SIZE(priv->smstpcr_saved); reg++) {
851 if (priv->smstpcr_saved[reg].mask)
852 priv->smstpcr_saved[reg].val =
853 priv->reg_layout == CLK_REG_LAYOUT_RZ_A ?
854 readb(priv->base + priv->control_regs[reg]) :
855 readl(priv->base + priv->control_regs[reg]);
856 }
857
858 /* Save core clocks */
859 raw_notifier_call_chain(&priv->notifiers, PM_EVENT_SUSPEND, NULL);
860
861 return 0;
862 }
863
cpg_mssr_resume_noirq(struct device * dev)864 static int cpg_mssr_resume_noirq(struct device *dev)
865 {
866 struct cpg_mssr_priv *priv = dev_get_drvdata(dev);
867 unsigned int reg, i;
868 u32 mask, oldval, newval;
869
870 /* This is the best we can do to check for the presence of PSCI */
871 if (!psci_ops.cpu_suspend)
872 return 0;
873
874 /* Restore core clocks */
875 raw_notifier_call_chain(&priv->notifiers, PM_EVENT_RESUME, NULL);
876
877 /* Restore module clocks */
878 for (reg = 0; reg < ARRAY_SIZE(priv->smstpcr_saved); reg++) {
879 mask = priv->smstpcr_saved[reg].mask;
880 if (!mask)
881 continue;
882
883 if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A)
884 oldval = readb(priv->base + priv->control_regs[reg]);
885 else
886 oldval = readl(priv->base + priv->control_regs[reg]);
887 newval = oldval & ~mask;
888 newval |= priv->smstpcr_saved[reg].val & mask;
889 if (newval == oldval)
890 continue;
891
892 if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) {
893 writeb(newval, priv->base + priv->control_regs[reg]);
894 /* dummy read to ensure write has completed */
895 readb(priv->base + priv->control_regs[reg]);
896 barrier_data(priv->base + priv->control_regs[reg]);
897 continue;
898 } else
899 writel(newval, priv->base + priv->control_regs[reg]);
900
901 /* Wait until enabled clocks are really enabled */
902 mask &= ~priv->smstpcr_saved[reg].val;
903 if (!mask)
904 continue;
905
906 for (i = 1000; i > 0; --i) {
907 oldval = readl(priv->base + priv->status_regs[reg]);
908 if (!(oldval & mask))
909 break;
910 cpu_relax();
911 }
912
913 if (!i)
914 dev_warn(dev, "Failed to enable %s%u[0x%x]\n",
915 priv->reg_layout == CLK_REG_LAYOUT_RZ_A ?
916 "STB" : "SMSTP", reg, oldval & mask);
917 }
918
919 return 0;
920 }
921
922 static const struct dev_pm_ops cpg_mssr_pm = {
923 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(cpg_mssr_suspend_noirq,
924 cpg_mssr_resume_noirq)
925 };
926 #define DEV_PM_OPS &cpg_mssr_pm
927 #else
928 #define DEV_PM_OPS NULL
929 #endif /* CONFIG_PM_SLEEP && CONFIG_ARM_PSCI_FW */
930
cpg_mssr_common_init(struct device * dev,struct device_node * np,const struct cpg_mssr_info * info)931 static int __init cpg_mssr_common_init(struct device *dev,
932 struct device_node *np,
933 const struct cpg_mssr_info *info)
934 {
935 struct cpg_mssr_priv *priv;
936 unsigned int nclks, i;
937 int error;
938
939 if (info->init) {
940 error = info->init(dev);
941 if (error)
942 return error;
943 }
944
945 nclks = info->num_total_core_clks + info->num_hw_mod_clks;
946 priv = kzalloc(struct_size(priv, clks, nclks), GFP_KERNEL);
947 if (!priv)
948 return -ENOMEM;
949
950 priv->np = np;
951 priv->dev = dev;
952 spin_lock_init(&priv->rmw_lock);
953
954 priv->base = of_iomap(np, 0);
955 if (!priv->base) {
956 error = -ENOMEM;
957 goto out_err;
958 }
959
960 cpg_mssr_priv = priv;
961 priv->num_core_clks = info->num_total_core_clks;
962 priv->num_mod_clks = info->num_hw_mod_clks;
963 priv->last_dt_core_clk = info->last_dt_core_clk;
964 RAW_INIT_NOTIFIER_HEAD(&priv->notifiers);
965 priv->reg_layout = info->reg_layout;
966 if (priv->reg_layout == CLK_REG_LAYOUT_RCAR_GEN2_AND_GEN3) {
967 priv->status_regs = mstpsr;
968 priv->control_regs = smstpcr;
969 priv->reset_regs = srcr;
970 priv->reset_clear_regs = srstclr;
971 } else if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) {
972 priv->control_regs = stbcr;
973 } else if (priv->reg_layout == CLK_REG_LAYOUT_RCAR_V3U) {
974 priv->status_regs = mstpsr_for_v3u;
975 priv->control_regs = mstpcr_for_v3u;
976 priv->reset_regs = srcr_for_v3u;
977 priv->reset_clear_regs = srstclr_for_v3u;
978 } else {
979 error = -EINVAL;
980 goto out_err;
981 }
982
983 for (i = 0; i < nclks; i++)
984 priv->clks[i] = ERR_PTR(-ENOENT);
985
986 error = of_clk_add_provider(np, cpg_mssr_clk_src_twocell_get, priv);
987 if (error)
988 goto out_err;
989
990 return 0;
991
992 out_err:
993 if (priv->base)
994 iounmap(priv->base);
995 kfree(priv);
996
997 return error;
998 }
999
cpg_mssr_early_init(struct device_node * np,const struct cpg_mssr_info * info)1000 void __init cpg_mssr_early_init(struct device_node *np,
1001 const struct cpg_mssr_info *info)
1002 {
1003 int error;
1004 int i;
1005
1006 error = cpg_mssr_common_init(NULL, np, info);
1007 if (error)
1008 return;
1009
1010 for (i = 0; i < info->num_early_core_clks; i++)
1011 cpg_mssr_register_core_clk(&info->early_core_clks[i], info,
1012 cpg_mssr_priv);
1013
1014 for (i = 0; i < info->num_early_mod_clks; i++)
1015 cpg_mssr_register_mod_clk(&info->early_mod_clks[i], info,
1016 cpg_mssr_priv);
1017
1018 }
1019
cpg_mssr_probe(struct platform_device * pdev)1020 static int __init cpg_mssr_probe(struct platform_device *pdev)
1021 {
1022 struct device *dev = &pdev->dev;
1023 struct device_node *np = dev->of_node;
1024 const struct cpg_mssr_info *info;
1025 struct cpg_mssr_priv *priv;
1026 unsigned int i;
1027 int error;
1028
1029 info = of_device_get_match_data(dev);
1030
1031 if (!cpg_mssr_priv) {
1032 error = cpg_mssr_common_init(dev, dev->of_node, info);
1033 if (error)
1034 return error;
1035 }
1036
1037 priv = cpg_mssr_priv;
1038 priv->dev = dev;
1039 dev_set_drvdata(dev, priv);
1040
1041 for (i = 0; i < info->num_core_clks; i++)
1042 cpg_mssr_register_core_clk(&info->core_clks[i], info, priv);
1043
1044 for (i = 0; i < info->num_mod_clks; i++)
1045 cpg_mssr_register_mod_clk(&info->mod_clks[i], info, priv);
1046
1047 error = devm_add_action_or_reset(dev,
1048 cpg_mssr_del_clk_provider,
1049 np);
1050 if (error)
1051 return error;
1052
1053 error = cpg_mssr_add_clk_domain(dev, info->core_pm_clks,
1054 info->num_core_pm_clks);
1055 if (error)
1056 return error;
1057
1058 /* Reset Controller not supported for Standby Control SoCs */
1059 if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A)
1060 return 0;
1061
1062 error = cpg_mssr_reset_controller_register(priv);
1063 if (error)
1064 return error;
1065
1066 return 0;
1067 }
1068
1069 static struct platform_driver cpg_mssr_driver = {
1070 .driver = {
1071 .name = "renesas-cpg-mssr",
1072 .of_match_table = cpg_mssr_match,
1073 .pm = DEV_PM_OPS,
1074 },
1075 };
1076
cpg_mssr_init(void)1077 static int __init cpg_mssr_init(void)
1078 {
1079 return platform_driver_probe(&cpg_mssr_driver, cpg_mssr_probe);
1080 }
1081
1082 subsys_initcall(cpg_mssr_init);
1083
cpg_core_nullify_range(struct cpg_core_clk * core_clks,unsigned int num_core_clks,unsigned int first_clk,unsigned int last_clk)1084 void __init cpg_core_nullify_range(struct cpg_core_clk *core_clks,
1085 unsigned int num_core_clks,
1086 unsigned int first_clk,
1087 unsigned int last_clk)
1088 {
1089 unsigned int i;
1090
1091 for (i = 0; i < num_core_clks; i++)
1092 if (core_clks[i].id >= first_clk &&
1093 core_clks[i].id <= last_clk)
1094 core_clks[i].name = NULL;
1095 }
1096
mssr_mod_nullify(struct mssr_mod_clk * mod_clks,unsigned int num_mod_clks,const unsigned int * clks,unsigned int n)1097 void __init mssr_mod_nullify(struct mssr_mod_clk *mod_clks,
1098 unsigned int num_mod_clks,
1099 const unsigned int *clks, unsigned int n)
1100 {
1101 unsigned int i, j;
1102
1103 for (i = 0, j = 0; i < num_mod_clks && j < n; i++)
1104 if (mod_clks[i].id == clks[j]) {
1105 mod_clks[i].name = NULL;
1106 j++;
1107 }
1108 }
1109
mssr_mod_reparent(struct mssr_mod_clk * mod_clks,unsigned int num_mod_clks,const struct mssr_mod_reparent * clks,unsigned int n)1110 void __init mssr_mod_reparent(struct mssr_mod_clk *mod_clks,
1111 unsigned int num_mod_clks,
1112 const struct mssr_mod_reparent *clks,
1113 unsigned int n)
1114 {
1115 unsigned int i, j;
1116
1117 for (i = 0, j = 0; i < num_mod_clks && j < n; i++)
1118 if (mod_clks[i].id == clks[j].clk) {
1119 mod_clks[i].parent = clks[j].parent;
1120 j++;
1121 }
1122 }
1123
1124 MODULE_DESCRIPTION("Renesas CPG/MSSR Driver");
1125 MODULE_LICENSE("GPL v2");
1126
