1 /* 2 * Copyright (C) 2015 - ARM Ltd 3 * Author: Marc Zyngier <marc.zyngier@arm.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program. If not, see <http://www.gnu.org/licenses/>. 16 */ 17 18 #ifndef __ARM64_KVM_HYP_H__ 19 #define __ARM64_KVM_HYP_H__ 20 21 #include <linux/compiler.h> 22 #include <linux/kvm_host.h> 23 #include <asm/sysreg.h> 24 25 #define __hyp_text __section(.hyp.text) notrace 26 27 #define read_sysreg_elx(r,nvh,vh) \ 28 ({ \ 29 u64 reg; \ 30 asm volatile(ALTERNATIVE("mrs %0, " __stringify(r##nvh),\ 31 "mrs_s %0, " __stringify(r##vh),\ 32 ARM64_HAS_VIRT_HOST_EXTN) \ 33 : "=r" (reg)); \ 34 reg; \ 35 }) 36 37 #define write_sysreg_elx(v,r,nvh,vh) \ 38 do { \ 39 u64 __val = (u64)(v); \ 40 asm volatile(ALTERNATIVE("msr " __stringify(r##nvh) ", %x0",\ 41 "msr_s " __stringify(r##vh) ", %x0",\ 42 ARM64_HAS_VIRT_HOST_EXTN) \ 43 : : "rZ" (__val)); \ 44 } while (0) 45 46 /* 47 * Unified accessors for registers that have a different encoding 48 * between VHE and non-VHE. They must be specified without their "ELx" 49 * encoding. 50 */ 51 #define read_sysreg_el2(r) \ 52 ({ \ 53 u64 reg; \ 54 asm volatile(ALTERNATIVE("mrs %0, " __stringify(r##_EL2),\ 55 "mrs %0, " __stringify(r##_EL1),\ 56 ARM64_HAS_VIRT_HOST_EXTN) \ 57 : "=r" (reg)); \ 58 reg; \ 59 }) 60 61 #define write_sysreg_el2(v,r) \ 62 do { \ 63 u64 __val = (u64)(v); \ 64 asm volatile(ALTERNATIVE("msr " __stringify(r##_EL2) ", %x0",\ 65 "msr " __stringify(r##_EL1) ", %x0",\ 66 ARM64_HAS_VIRT_HOST_EXTN) \ 67 : : "rZ" (__val)); \ 68 } while (0) 69 70 #define read_sysreg_el0(r) read_sysreg_elx(r, _EL0, _EL02) 71 #define write_sysreg_el0(v,r) write_sysreg_elx(v, r, _EL0, _EL02) 72 #define read_sysreg_el1(r) read_sysreg_elx(r, _EL1, _EL12) 73 #define write_sysreg_el1(v,r) write_sysreg_elx(v, r, _EL1, _EL12) 74 75 /* The VHE specific system registers and their encoding */ 76 #define sctlr_EL12 sys_reg(3, 5, 1, 0, 0) 77 #define cpacr_EL12 sys_reg(3, 5, 1, 0, 2) 78 #define ttbr0_EL12 sys_reg(3, 5, 2, 0, 0) 79 #define ttbr1_EL12 sys_reg(3, 5, 2, 0, 1) 80 #define tcr_EL12 sys_reg(3, 5, 2, 0, 2) 81 #define afsr0_EL12 sys_reg(3, 5, 5, 1, 0) 82 #define afsr1_EL12 sys_reg(3, 5, 5, 1, 1) 83 #define esr_EL12 sys_reg(3, 5, 5, 2, 0) 84 #define far_EL12 sys_reg(3, 5, 6, 0, 0) 85 #define mair_EL12 sys_reg(3, 5, 10, 2, 0) 86 #define amair_EL12 sys_reg(3, 5, 10, 3, 0) 87 #define vbar_EL12 sys_reg(3, 5, 12, 0, 0) 88 #define contextidr_EL12 sys_reg(3, 5, 13, 0, 1) 89 #define cntkctl_EL12 sys_reg(3, 5, 14, 1, 0) 90 #define cntp_tval_EL02 sys_reg(3, 5, 14, 2, 0) 91 #define cntp_ctl_EL02 sys_reg(3, 5, 14, 2, 1) 92 #define cntp_cval_EL02 sys_reg(3, 5, 14, 2, 2) 93 #define cntv_tval_EL02 sys_reg(3, 5, 14, 3, 0) 94 #define cntv_ctl_EL02 sys_reg(3, 5, 14, 3, 1) 95 #define cntv_cval_EL02 sys_reg(3, 5, 14, 3, 2) 96 #define spsr_EL12 sys_reg(3, 5, 4, 0, 0) 97 #define elr_EL12 sys_reg(3, 5, 4, 0, 1) 98 99 /** 100 * hyp_alternate_select - Generates patchable code sequences that are 101 * used to switch between two implementations of a function, depending 102 * on the availability of a feature. 103 * 104 * @fname: a symbol name that will be defined as a function returning a 105 * function pointer whose type will match @orig and @alt 106 * @orig: A pointer to the default function, as returned by @fname when 107 * @cond doesn't hold 108 * @alt: A pointer to the alternate function, as returned by @fname 109 * when @cond holds 110 * @cond: a CPU feature (as described in asm/cpufeature.h) 111 */ 112 #define hyp_alternate_select(fname, orig, alt, cond) \ 113 typeof(orig) * __hyp_text fname(void) \ 114 { \ 115 typeof(alt) *val = orig; \ 116 asm volatile(ALTERNATIVE("nop \n", \ 117 "mov %0, %1 \n", \ 118 cond) \ 119 : "+r" (val) : "r" (alt)); \ 120 return val; \ 121 } 122 123 int __vgic_v2_perform_cpuif_access(struct kvm_vcpu *vcpu); 124 125 void __vgic_v3_save_state(struct kvm_vcpu *vcpu); 126 void __vgic_v3_restore_state(struct kvm_vcpu *vcpu); 127 void __vgic_v3_activate_traps(struct kvm_vcpu *vcpu); 128 void __vgic_v3_deactivate_traps(struct kvm_vcpu *vcpu); 129 void __vgic_v3_save_aprs(struct kvm_vcpu *vcpu); 130 void __vgic_v3_restore_aprs(struct kvm_vcpu *vcpu); 131 int __vgic_v3_perform_cpuif_access(struct kvm_vcpu *vcpu); 132 133 void __timer_enable_traps(struct kvm_vcpu *vcpu); 134 void __timer_disable_traps(struct kvm_vcpu *vcpu); 135 136 void __sysreg_save_state_nvhe(struct kvm_cpu_context *ctxt); 137 void __sysreg_restore_state_nvhe(struct kvm_cpu_context *ctxt); 138 void sysreg_save_host_state_vhe(struct kvm_cpu_context *ctxt); 139 void sysreg_restore_host_state_vhe(struct kvm_cpu_context *ctxt); 140 void sysreg_save_guest_state_vhe(struct kvm_cpu_context *ctxt); 141 void sysreg_restore_guest_state_vhe(struct kvm_cpu_context *ctxt); 142 void __sysreg32_save_state(struct kvm_vcpu *vcpu); 143 void __sysreg32_restore_state(struct kvm_vcpu *vcpu); 144 145 void __debug_switch_to_guest(struct kvm_vcpu *vcpu); 146 void __debug_switch_to_host(struct kvm_vcpu *vcpu); 147 148 void __fpsimd_save_state(struct user_fpsimd_state *fp_regs); 149 void __fpsimd_restore_state(struct user_fpsimd_state *fp_regs); 150 bool __fpsimd_enabled(void); 151 152 void activate_traps_vhe_load(struct kvm_vcpu *vcpu); 153 void deactivate_traps_vhe_put(void); 154 155 u64 __guest_enter(struct kvm_vcpu *vcpu, struct kvm_cpu_context *host_ctxt); 156 void __noreturn __hyp_do_panic(unsigned long, ...); 157 158 #endif /* __ARM64_KVM_HYP_H__ */ 159 160
