1 // SPDX-License-Identifier: GPL-2.0
2 /******************************************************************************
3  *
4  * Copyright(c) 2007 - 2016  Realtek Corporation.
5  *
6  * Contact Information:
7  * wlanfae <wlanfae@realtek.com>
8  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
9  * Hsinchu 300, Taiwan.
10  *
11  * Larry Finger <Larry.Finger@lwfinger.net>
12  *
13  *****************************************************************************/
14 
15 #include "../mp_precomp.h"
16 #include "../phydm_precomp.h"
17 
18 /* ======================================================================== */
19 /* These following functions can be used for PHY DM only*/
20 
21 static u32 reg82c_8822b;
22 static u32 reg838_8822b;
23 static u32 reg830_8822b;
24 static u32 reg83c_8822b;
25 static u32 rega20_8822b;
26 static u32 rega24_8822b;
27 static u32 rega28_8822b;
28 static enum odm_bw bw_8822b;
29 static u8 central_ch_8822b;
30 
31 static u32 cca_ifem_ccut[12][4] = {
32 	/*20M*/
33 	{0x75D97010, 0x75D97010, 0x75D97010, 0x75D97010}, /*Reg82C*/
34 	{0x00000000, 0x79a0ea2c, 0x00000000, 0x00000000}, /*Reg830*/
35 	{0x00000000, 0x00000000, 0x00000000, 0x00000000}, /*Reg838*/
36 	{0x00000000, 0x00000000, 0x00000000, 0x00000000}, /*Reg83C*/
37 	/*40M*/
38 	{0x75D97010, 0x75D97010, 0x75D97010, 0x75D97010}, /*Reg82C*/
39 	{0x00000000, 0x79a0ea2c, 0x00000000, 0x79a0ea28}, /*Reg830*/
40 	{0x87765541, 0x87766341, 0x87765541, 0x87766341}, /*Reg838*/
41 	{0x00000000, 0x00000000, 0x00000000, 0x00000000}, /*Reg83C*/
42 	/*80M*/
43 	{0x75C97010, 0x75C97010, 0x75C97010, 0x75C97010}, /*Reg82C*/
44 	{0x00000000, 0x00000000, 0x00000000, 0x00000000}, /*Reg830*/
45 	{0x00000000, 0x87746641, 0x00000000, 0x87746641}, /*Reg838*/
46 	{0x00000000, 0x00000000, 0x00000000, 0x00000000},
47 }; /*Reg83C*/
48 static u32 cca_efem_ccut[12][4] = {
49 	/*20M*/
50 	{0x75A76010, 0x75A76010, 0x75A76010, 0x75A75010}, /*Reg82C*/
51 	{0x00000000, 0x79a0ea2c, 0x00000000, 0x00000000}, /*Reg830*/
52 	{0x87766651, 0x87766431, 0x87766451, 0x87766431}, /*Reg838*/
53 	{0x9194b2b9, 0x9194b2b9, 0x9194b2b9, 0x9194b2b9}, /*Reg83C*/
54 	/*40M*/
55 	{0x75A85010, 0x75A75010, 0x75A85010, 0x75A75010}, /*Reg82C*/
56 	{0x00000000, 0x79a0ea2c, 0x00000000, 0x00000000}, /*Reg830*/
57 	{0x87766431, 0x87766431, 0x87766431, 0x87766431}, /*Reg838*/
58 	{0x00000000, 0x00000000, 0x00000000, 0x00000000}, /*Reg83C*/
59 	/*80M*/
60 	{0x76BA7010, 0x75BA7010, 0x76BA7010, 0x75BA7010}, /*Reg82C*/
61 	{0x79a0ea28, 0x00000000, 0x79a0ea28, 0x00000000}, /*Reg830*/
62 	{0x87766431, 0x87766431, 0x87766431, 0x87766431}, /*Reg838*/
63 	{0x00000000, 0x00000000, 0x00000000, 0x00000000},
64 }; /*Reg83C*/
65 static u32 cca_ifem_ccut_rfetype5[12][4] = {
66 	/*20M*/
67 	{0x75D97010, 0x75D97010, 0x75D97010, 0x75D97010}, /*Reg82C*/
68 	{0x00000000, 0x79a0ea2c, 0x00000000, 0x00000000}, /*Reg830*/
69 	{0x00000000, 0x00000000, 0x87766461, 0x87766461}, /*Reg838*/
70 	{0x00000000, 0x00000000, 0x00000000, 0x00000000}, /*Reg83C*/
71 	/*40M*/
72 	{0x75D97010, 0x75D97010, 0x75D97010, 0x75D97010}, /*Reg82C*/
73 	{0x00000000, 0x79a0ea2c, 0x00000000, 0x79a0ea28}, /*Reg830*/
74 	{0x87765541, 0x87766341, 0x87765541, 0x87766341}, /*Reg838*/
75 	{0x00000000, 0x00000000, 0x00000000, 0x00000000}, /*Reg83C*/
76 	/*80M*/
77 	{0x75C97010, 0x75C97010, 0x75C97010, 0x75C97010}, /*Reg82C*/
78 	{0x00000000, 0x00000000, 0x00000000, 0x00000000}, /*Reg830*/
79 	{0x00000000, 0x76666641, 0x00000000, 0x76666641}, /*Reg838*/
80 	{0x00000000, 0x00000000, 0x00000000, 0x00000000},
81 }; /*Reg83C*/
82 static u32 cca_ifem_ccut_rfetype3[12][4] = {
83 	/*20M*/
84 	{0x75D97010, 0x75D97010, 0x75D97010, 0x75D97010}, /*Reg82C*/
85 	{0x00000000, 0x79a0ea2c, 0x00000000, 0x00000000}, /*Reg830*/
86 	{0x00000000, 0x00000000, 0x87766461, 0x87766461}, /*Reg838*/
87 	{0x00000000, 0x00000000, 0x00000000, 0x00000000}, /*Reg83C*/
88 	/*40M*/
89 	{0x75D97010, 0x75D97010, 0x75D97010, 0x75D97010}, /*Reg82C*/
90 	{0x00000000, 0x79a0ea2c, 0x00000000, 0x79a0ea28}, /*Reg830*/
91 	{0x87765541, 0x87766341, 0x87765541, 0x87766341}, /*Reg838*/
92 	{0x00000000, 0x00000000, 0x00000000, 0x00000000}, /*Reg83C*/
93 	/*80M*/
94 	{0x75C97010, 0x75C97010, 0x75C97010, 0x75C97010}, /*Reg82C*/
95 	{0x00000000, 0x00000000, 0x00000000, 0x00000000}, /*Reg830*/
96 	{0x00000000, 0x76666641, 0x00000000, 0x76666641}, /*Reg838*/
97 	{0x00000000, 0x00000000, 0x00000000, 0x00000000},
98 }; /*Reg83C*/
99 
phydm_check_bit_mask(u32 bit_mask,u32 data_original,u32 data)100 static inline u32 phydm_check_bit_mask(u32 bit_mask, u32 data_original,
101 				       u32 data)
102 {
103 	u8 bit_shift;
104 
105 	if (bit_mask != 0xfffff) {
106 		for (bit_shift = 0; bit_shift <= 19; bit_shift++) {
107 			if (((bit_mask >> bit_shift) & 0x1) == 1)
108 				break;
109 		}
110 		return ((data_original) & (~bit_mask)) | (data << bit_shift);
111 	}
112 	return data;
113 }
114 
phydm_rfe_8822b(struct phy_dm_struct * dm,u8 channel)115 static bool phydm_rfe_8822b(struct phy_dm_struct *dm, u8 channel)
116 {
117 	if (dm->rfe_type == 4) {
118 		/* Default setting is in PHY parameters */
119 
120 		if (channel <= 14) {
121 			/* signal source */
122 			odm_set_bb_reg(dm, 0xcb0, (MASKBYTE2 | MASKLWORD),
123 				       0x745774);
124 			odm_set_bb_reg(dm, 0xeb0, (MASKBYTE2 | MASKLWORD),
125 				       0x745774);
126 			odm_set_bb_reg(dm, 0xcb4, MASKBYTE1, 0x57);
127 			odm_set_bb_reg(dm, 0xeb4, MASKBYTE1, 0x57);
128 
129 			/* inverse or not */
130 			odm_set_bb_reg(dm, 0xcbc, (BIT(5) | BIT(4) | BIT(3) |
131 						   BIT(2) | BIT(1) | BIT(0)),
132 				       0x8);
133 			odm_set_bb_reg(dm, 0xcbc, (BIT(11) | BIT(10)), 0x2);
134 			odm_set_bb_reg(dm, 0xebc, (BIT(5) | BIT(4) | BIT(3) |
135 						   BIT(2) | BIT(1) | BIT(0)),
136 				       0x8);
137 			odm_set_bb_reg(dm, 0xebc, (BIT(11) | BIT(10)), 0x2);
138 
139 			/* antenna switch table */
140 			if ((dm->rx_ant_status == (ODM_RF_A | ODM_RF_B)) ||
141 			    (dm->tx_ant_status == (ODM_RF_A | ODM_RF_B))) {
142 				/* 2TX or 2RX */
143 				odm_set_bb_reg(dm, 0xca0, MASKLWORD, 0xf050);
144 				odm_set_bb_reg(dm, 0xea0, MASKLWORD, 0xf050);
145 			} else if (dm->rx_ant_status == dm->tx_ant_status) {
146 				/* TXA+RXA or TXB+RXB */
147 				odm_set_bb_reg(dm, 0xca0, MASKLWORD, 0xf055);
148 				odm_set_bb_reg(dm, 0xea0, MASKLWORD, 0xf055);
149 			} else {
150 				/* TXB+RXA or TXA+RXB */
151 				odm_set_bb_reg(dm, 0xca0, MASKLWORD, 0xf550);
152 				odm_set_bb_reg(dm, 0xea0, MASKLWORD, 0xf550);
153 			}
154 
155 		} else if (channel > 35) {
156 			/* signal source */
157 			odm_set_bb_reg(dm, 0xcb0, (MASKBYTE2 | MASKLWORD),
158 				       0x477547);
159 			odm_set_bb_reg(dm, 0xeb0, (MASKBYTE2 | MASKLWORD),
160 				       0x477547);
161 			odm_set_bb_reg(dm, 0xcb4, MASKBYTE1, 0x75);
162 			odm_set_bb_reg(dm, 0xeb4, MASKBYTE1, 0x75);
163 
164 			/* inverse or not */
165 			odm_set_bb_reg(dm, 0xcbc, (BIT(5) | BIT(4) | BIT(3) |
166 						   BIT(2) | BIT(1) | BIT(0)),
167 				       0x0);
168 			odm_set_bb_reg(dm, 0xcbc, (BIT(11) | BIT(10)), 0x0);
169 			odm_set_bb_reg(dm, 0xebc, (BIT(5) | BIT(4) | BIT(3) |
170 						   BIT(2) | BIT(1) | BIT(0)),
171 				       0x0);
172 			odm_set_bb_reg(dm, 0xebc, (BIT(11) | BIT(10)), 0x0);
173 
174 			/* antenna switch table */
175 			if ((dm->rx_ant_status == (ODM_RF_A | ODM_RF_B)) ||
176 			    (dm->tx_ant_status == (ODM_RF_A | ODM_RF_B))) {
177 				/* 2TX or 2RX */
178 				odm_set_bb_reg(dm, 0xca0, MASKLWORD, 0xa501);
179 				odm_set_bb_reg(dm, 0xea0, MASKLWORD, 0xa501);
180 			} else if (dm->rx_ant_status == dm->tx_ant_status) {
181 				/* TXA+RXA or TXB+RXB */
182 				odm_set_bb_reg(dm, 0xca0, MASKLWORD, 0xa500);
183 				odm_set_bb_reg(dm, 0xea0, MASKLWORD, 0xa500);
184 			} else {
185 				/* TXB+RXA or TXA+RXB */
186 				odm_set_bb_reg(dm, 0xca0, MASKLWORD, 0xa005);
187 				odm_set_bb_reg(dm, 0xea0, MASKLWORD, 0xa005);
188 			}
189 		} else {
190 			return false;
191 		}
192 
193 	} else if ((dm->rfe_type == 1) || (dm->rfe_type == 2) ||
194 		   (dm->rfe_type == 7) || (dm->rfe_type == 9)) {
195 		/* eFem */
196 		if (((dm->cut_version == ODM_CUT_A) ||
197 		     (dm->cut_version == ODM_CUT_B)) &&
198 		    (dm->rfe_type < 2)) {
199 			if (channel <= 14) {
200 				/* signal source */
201 				odm_set_bb_reg(dm, 0xcb0,
202 					       (MASKBYTE2 | MASKLWORD),
203 					       0x704570);
204 				odm_set_bb_reg(dm, 0xeb0,
205 					       (MASKBYTE2 | MASKLWORD),
206 					       0x704570);
207 				odm_set_bb_reg(dm, 0xcb4, MASKBYTE1, 0x45);
208 				odm_set_bb_reg(dm, 0xeb4, MASKBYTE1, 0x45);
209 			} else if (channel > 35) {
210 				odm_set_bb_reg(dm, 0xcb0,
211 					       (MASKBYTE2 | MASKLWORD),
212 					       0x174517);
213 				odm_set_bb_reg(dm, 0xeb0,
214 					       (MASKBYTE2 | MASKLWORD),
215 					       0x174517);
216 				odm_set_bb_reg(dm, 0xcb4, MASKBYTE1, 0x45);
217 				odm_set_bb_reg(dm, 0xeb4, MASKBYTE1, 0x45);
218 			} else {
219 				return false;
220 			}
221 
222 			/* delay 400ns for PAPE */
223 			odm_set_bb_reg(dm, 0x810,
224 				       MASKBYTE3 | BIT(20) | BIT(21) | BIT(22) |
225 					       BIT(23),
226 				       0x211);
227 
228 			/* antenna switch table */
229 			odm_set_bb_reg(dm, 0xca0, MASKLWORD, 0xa555);
230 			odm_set_bb_reg(dm, 0xea0, MASKLWORD, 0xa555);
231 
232 			/* inverse or not */
233 			odm_set_bb_reg(dm, 0xcbc, (BIT(5) | BIT(4) | BIT(3) |
234 						   BIT(2) | BIT(1) | BIT(0)),
235 				       0x0);
236 			odm_set_bb_reg(dm, 0xcbc, (BIT(11) | BIT(10)), 0x0);
237 			odm_set_bb_reg(dm, 0xebc, (BIT(5) | BIT(4) | BIT(3) |
238 						   BIT(2) | BIT(1) | BIT(0)),
239 				       0x0);
240 			odm_set_bb_reg(dm, 0xebc, (BIT(11) | BIT(10)), 0x0);
241 
242 			ODM_RT_TRACE(
243 				dm, ODM_PHY_CONFIG,
244 				"%s: Using old RFE control pin setting for A-cut and B-cut\n",
245 				__func__);
246 		} else {
247 			if (channel <= 14) {
248 				/* signal source */
249 				odm_set_bb_reg(dm, 0xcb0,
250 					       (MASKBYTE2 | MASKLWORD),
251 					       0x705770);
252 				odm_set_bb_reg(dm, 0xeb0,
253 					       (MASKBYTE2 | MASKLWORD),
254 					       0x705770);
255 				odm_set_bb_reg(dm, 0xcb4, MASKBYTE1, 0x57);
256 				odm_set_bb_reg(dm, 0xeb4, MASKBYTE1, 0x57);
257 				odm_set_bb_reg(dm, 0xcb8, BIT(4), 0);
258 				odm_set_bb_reg(dm, 0xeb8, BIT(4), 0);
259 			} else if (channel > 35) {
260 				/* signal source */
261 				odm_set_bb_reg(dm, 0xcb0,
262 					       (MASKBYTE2 | MASKLWORD),
263 					       0x177517);
264 				odm_set_bb_reg(dm, 0xeb0,
265 					       (MASKBYTE2 | MASKLWORD),
266 					       0x177517);
267 				odm_set_bb_reg(dm, 0xcb4, MASKBYTE1, 0x75);
268 				odm_set_bb_reg(dm, 0xeb4, MASKBYTE1, 0x75);
269 				odm_set_bb_reg(dm, 0xcb8, BIT(5), 0);
270 				odm_set_bb_reg(dm, 0xeb8, BIT(5), 0);
271 			} else {
272 				return false;
273 			}
274 
275 			/* inverse or not */
276 			odm_set_bb_reg(dm, 0xcbc, (BIT(5) | BIT(4) | BIT(3) |
277 						   BIT(2) | BIT(1) | BIT(0)),
278 				       0x0);
279 			odm_set_bb_reg(dm, 0xcbc, (BIT(11) | BIT(10)), 0x0);
280 			odm_set_bb_reg(dm, 0xebc, (BIT(5) | BIT(4) | BIT(3) |
281 						   BIT(2) | BIT(1) | BIT(0)),
282 				       0x0);
283 			odm_set_bb_reg(dm, 0xebc, (BIT(11) | BIT(10)), 0x0);
284 
285 			/* antenna switch table */
286 			if ((dm->rx_ant_status == (ODM_RF_A | ODM_RF_B)) ||
287 			    (dm->tx_ant_status == (ODM_RF_A | ODM_RF_B))) {
288 				/* 2TX or 2RX */
289 				odm_set_bb_reg(dm, 0xca0, MASKLWORD, 0xa501);
290 				odm_set_bb_reg(dm, 0xea0, MASKLWORD, 0xa501);
291 			} else if (dm->rx_ant_status == dm->tx_ant_status) {
292 				/* TXA+RXA or TXB+RXB */
293 				odm_set_bb_reg(dm, 0xca0, MASKLWORD, 0xa500);
294 				odm_set_bb_reg(dm, 0xea0, MASKLWORD, 0xa500);
295 			} else {
296 				/* TXB+RXA or TXA+RXB */
297 				odm_set_bb_reg(dm, 0xca0, MASKLWORD, 0xa005);
298 				odm_set_bb_reg(dm, 0xea0, MASKLWORD, 0xa005);
299 			}
300 		}
301 	} else if ((dm->rfe_type == 0) || (dm->rfe_type == 3) ||
302 		   (dm->rfe_type == 5) || (dm->rfe_type == 6) ||
303 		   (dm->rfe_type == 8) || (dm->rfe_type == 10)) {
304 		/* iFEM */
305 		if (channel <= 14) {
306 			/* signal source */
307 
308 			odm_set_bb_reg(dm, 0xcb0, (MASKBYTE2 | MASKLWORD),
309 				       0x745774);
310 			odm_set_bb_reg(dm, 0xeb0, (MASKBYTE2 | MASKLWORD),
311 				       0x745774);
312 			odm_set_bb_reg(dm, 0xcb4, MASKBYTE1, 0x57);
313 			odm_set_bb_reg(dm, 0xeb4, MASKBYTE1, 0x57);
314 
315 		} else if (channel > 35) {
316 			/* signal source */
317 
318 			odm_set_bb_reg(dm, 0xcb0, (MASKBYTE2 | MASKLWORD),
319 				       0x477547);
320 			odm_set_bb_reg(dm, 0xeb0, (MASKBYTE2 | MASKLWORD),
321 				       0x477547);
322 			odm_set_bb_reg(dm, 0xcb4, MASKBYTE1, 0x75);
323 			odm_set_bb_reg(dm, 0xeb4, MASKBYTE1, 0x75);
324 
325 		} else {
326 			return false;
327 		}
328 
329 		/* inverse or not */
330 		odm_set_bb_reg(dm, 0xcbc, (BIT(5) | BIT(4) | BIT(3) | BIT(2) |
331 					   BIT(1) | BIT(0)),
332 			       0x0);
333 		odm_set_bb_reg(dm, 0xcbc, (BIT(11) | BIT(10)), 0x0);
334 		odm_set_bb_reg(dm, 0xebc, (BIT(5) | BIT(4) | BIT(3) | BIT(2) |
335 					   BIT(1) | BIT(0)),
336 			       0x0);
337 		odm_set_bb_reg(dm, 0xebc, (BIT(11) | BIT(10)), 0x0);
338 
339 		/* antenna switch table */
340 		if (channel <= 14) {
341 			if ((dm->rx_ant_status == (ODM_RF_A | ODM_RF_B)) ||
342 			    (dm->tx_ant_status == (ODM_RF_A | ODM_RF_B))) {
343 				/* 2TX or 2RX */
344 				odm_set_bb_reg(dm, 0xca0, MASKLWORD, 0xa501);
345 				odm_set_bb_reg(dm, 0xea0, MASKLWORD, 0xa501);
346 			} else if (dm->rx_ant_status == dm->tx_ant_status) {
347 				/* TXA+RXA or TXB+RXB */
348 				odm_set_bb_reg(dm, 0xca0, MASKLWORD, 0xa500);
349 				odm_set_bb_reg(dm, 0xea0, MASKLWORD, 0xa500);
350 			} else {
351 				/* TXB+RXA or TXA+RXB */
352 				odm_set_bb_reg(dm, 0xca0, MASKLWORD, 0xa005);
353 				odm_set_bb_reg(dm, 0xea0, MASKLWORD, 0xa005);
354 			}
355 		} else if (channel > 35) {
356 			odm_set_bb_reg(dm, 0xca0, MASKLWORD, 0xa5a5);
357 			odm_set_bb_reg(dm, 0xea0, MASKLWORD, 0xa5a5);
358 		}
359 	}
360 
361 	/* chip top mux */
362 	odm_set_bb_reg(dm, 0x64, BIT(29) | BIT(28), 0x3);
363 	odm_set_bb_reg(dm, 0x4c, BIT(26) | BIT(25), 0x0);
364 	odm_set_bb_reg(dm, 0x40, BIT(2), 0x1);
365 
366 	/* from s0 or s1 */
367 	odm_set_bb_reg(dm, 0x1990,
368 		       (BIT(5) | BIT(4) | BIT(3) | BIT(2) | BIT(1) | BIT(0)),
369 		       0x30);
370 	odm_set_bb_reg(dm, 0x1990, (BIT(11) | BIT(10)), 0x3);
371 
372 	/* input or output */
373 	odm_set_bb_reg(dm, 0x974,
374 		       (BIT(5) | BIT(4) | BIT(3) | BIT(2) | BIT(1) | BIT(0)),
375 		       0x3f);
376 	odm_set_bb_reg(dm, 0x974, (BIT(11) | BIT(10)), 0x3);
377 
378 	ODM_RT_TRACE(
379 		dm, ODM_PHY_CONFIG,
380 		"%s: Update RFE control pin setting (ch%d, tx_path 0x%x, rx_path 0x%x)\n",
381 		__func__, channel, dm->tx_ant_status, dm->rx_ant_status);
382 
383 	return true;
384 }
385 
phydm_ccapar_by_rfe_8822b(struct phy_dm_struct * dm)386 static void phydm_ccapar_by_rfe_8822b(struct phy_dm_struct *dm)
387 {
388 	u32 cca_ifem[12][4], cca_efem[12][4];
389 	u8 row, col;
390 	u32 reg82c, reg830, reg838, reg83c;
391 
392 	if (dm->cut_version == ODM_CUT_A)
393 		return;
394 	{
395 		odm_move_memory(dm, cca_efem, cca_efem_ccut, 48 * 4);
396 		if (dm->rfe_type == 5)
397 			odm_move_memory(dm, cca_ifem, cca_ifem_ccut_rfetype5,
398 					48 * 4);
399 		else if (dm->rfe_type == 3)
400 			odm_move_memory(dm, cca_ifem, cca_ifem_ccut_rfetype3,
401 					48 * 4);
402 		else
403 			odm_move_memory(dm, cca_ifem, cca_ifem_ccut, 48 * 4);
404 
405 		ODM_RT_TRACE(dm, ODM_PHY_CONFIG,
406 			     "%s: Update CCA parameters for Ccut\n", __func__);
407 	}
408 
409 	if (bw_8822b == ODM_BW20M)
410 		row = 0;
411 	else if (bw_8822b == ODM_BW40M)
412 		row = 4;
413 	else
414 		row = 8;
415 
416 	if (central_ch_8822b <= 14) {
417 		if ((dm->rx_ant_status == ODM_RF_A) ||
418 		    (dm->rx_ant_status == ODM_RF_B))
419 			col = 0;
420 		else
421 			col = 1;
422 	} else {
423 		if ((dm->rx_ant_status == ODM_RF_A) ||
424 		    (dm->rx_ant_status == ODM_RF_B))
425 			col = 2;
426 		else
427 			col = 3;
428 	}
429 
430 	if ((dm->rfe_type == 1) || (dm->rfe_type == 4) || (dm->rfe_type == 6) ||
431 	    (dm->rfe_type == 7)) {
432 		/*eFEM => RFE type 1 & RFE type 4 & RFE type 6 & RFE type 7*/
433 		reg82c = (cca_efem[row][col] != 0) ? cca_efem[row][col] :
434 						     reg82c_8822b;
435 		reg830 = (cca_efem[row + 1][col] != 0) ?
436 				 cca_efem[row + 1][col] :
437 				 reg830_8822b;
438 		reg838 = (cca_efem[row + 2][col] != 0) ?
439 				 cca_efem[row + 2][col] :
440 				 reg838_8822b;
441 		reg83c = (cca_efem[row + 3][col] != 0) ?
442 				 cca_efem[row + 3][col] :
443 				 reg83c_8822b;
444 	} else if ((dm->rfe_type == 2) || (dm->rfe_type == 9)) {
445 		/*5G eFEM, 2G iFEM => RFE type 2, 5G eFEM => RFE type 9 */
446 		if (central_ch_8822b <= 14) {
447 			reg82c = (cca_ifem[row][col] != 0) ?
448 					 cca_ifem[row][col] :
449 					 reg82c_8822b;
450 			reg830 = (cca_ifem[row + 1][col] != 0) ?
451 					 cca_ifem[row + 1][col] :
452 					 reg830_8822b;
453 			reg838 = (cca_ifem[row + 2][col] != 0) ?
454 					 cca_ifem[row + 2][col] :
455 					 reg838_8822b;
456 			reg83c = (cca_ifem[row + 3][col] != 0) ?
457 					 cca_ifem[row + 3][col] :
458 					 reg83c_8822b;
459 		} else {
460 			reg82c = (cca_efem[row][col] != 0) ?
461 					 cca_efem[row][col] :
462 					 reg82c_8822b;
463 			reg830 = (cca_efem[row + 1][col] != 0) ?
464 					 cca_efem[row + 1][col] :
465 					 reg830_8822b;
466 			reg838 = (cca_efem[row + 2][col] != 0) ?
467 					 cca_efem[row + 2][col] :
468 					 reg838_8822b;
469 			reg83c = (cca_efem[row + 3][col] != 0) ?
470 					 cca_efem[row + 3][col] :
471 					 reg83c_8822b;
472 		}
473 	} else {
474 		/* iFEM =>RFE type 3 & RFE type 5 & RFE type 0 & RFE type 8 &
475 		 * RFE type 10
476 		 */
477 		reg82c = (cca_ifem[row][col] != 0) ? cca_ifem[row][col] :
478 						     reg82c_8822b;
479 		reg830 = (cca_ifem[row + 1][col] != 0) ?
480 				 cca_ifem[row + 1][col] :
481 				 reg830_8822b;
482 		reg838 = (cca_ifem[row + 2][col] != 0) ?
483 				 cca_ifem[row + 2][col] :
484 				 reg838_8822b;
485 		reg83c = (cca_ifem[row + 3][col] != 0) ?
486 				 cca_ifem[row + 3][col] :
487 				 reg83c_8822b;
488 	}
489 
490 	odm_set_bb_reg(dm, 0x82c, MASKDWORD, reg82c);
491 	odm_set_bb_reg(dm, 0x830, MASKDWORD, reg830);
492 	odm_set_bb_reg(dm, 0x838, MASKDWORD, reg838);
493 	odm_set_bb_reg(dm, 0x83c, MASKDWORD, reg83c);
494 	ODM_RT_TRACE(dm, ODM_PHY_CONFIG,
495 		     "%s: (Pkt%d, Intf%d, RFE%d), row = %d, col = %d\n",
496 		     __func__, dm->package_type, dm->support_interface,
497 		     dm->rfe_type, row, col);
498 }
499 
phydm_ccapar_by_bw_8822b(struct phy_dm_struct * dm,enum odm_bw bandwidth)500 static void phydm_ccapar_by_bw_8822b(struct phy_dm_struct *dm,
501 				     enum odm_bw bandwidth)
502 {
503 	u32 reg82c;
504 
505 	if (dm->cut_version != ODM_CUT_A)
506 		return;
507 
508 	/* A-cut */
509 	reg82c = odm_get_bb_reg(dm, 0x82c, MASKDWORD);
510 
511 	if (bandwidth == ODM_BW20M) {
512 		/* 82c[15:12] = 4 */
513 		/* 82c[27:24] = 6 */
514 
515 		reg82c &= (~(0x0f00f000));
516 		reg82c |= ((0x4) << 12);
517 		reg82c |= ((0x6) << 24);
518 	} else if (bandwidth == ODM_BW40M) {
519 		/* 82c[19:16] = 9 */
520 		/* 82c[27:24] = 6 */
521 
522 		reg82c &= (~(0x0f0f0000));
523 		reg82c |= ((0x9) << 16);
524 		reg82c |= ((0x6) << 24);
525 	} else if (bandwidth == ODM_BW80M) {
526 		/* 82c[15:12] 7 */
527 		/* 82c[19:16] b */
528 		/* 82c[23:20] d */
529 		/* 82c[27:24] 3 */
530 
531 		reg82c &= (~(0x0ffff000));
532 		reg82c |= ((0xdb7) << 12);
533 		reg82c |= ((0x3) << 24);
534 	}
535 
536 	odm_set_bb_reg(dm, 0x82c, MASKDWORD, reg82c);
537 	ODM_RT_TRACE(dm, ODM_PHY_CONFIG,
538 		     "%s(): Update CCA parameters for Acut\n", __func__);
539 }
540 
phydm_ccapar_by_rxpath_8822b(struct phy_dm_struct * dm)541 static void phydm_ccapar_by_rxpath_8822b(struct phy_dm_struct *dm)
542 {
543 	if (dm->cut_version != ODM_CUT_A)
544 		return;
545 
546 	if ((dm->rx_ant_status == ODM_RF_A) ||
547 	    (dm->rx_ant_status == ODM_RF_B)) {
548 		/* 838[7:4] = 8 */
549 		/* 838[11:8] = 7 */
550 		/* 838[15:12] = 6 */
551 		/* 838[19:16] = 7 */
552 		/* 838[23:20] = 7 */
553 		/* 838[27:24] = 7 */
554 		odm_set_bb_reg(dm, 0x838, 0x0ffffff0, 0x777678);
555 	} else {
556 		/* 838[7:4] = 3 */
557 		/* 838[11:8] = 3 */
558 		/* 838[15:12] = 6 */
559 		/* 838[19:16] = 6 */
560 		/* 838[23:20] = 7 */
561 		/* 838[27:24] = 7 */
562 		odm_set_bb_reg(dm, 0x838, 0x0ffffff0, 0x776633);
563 	}
564 	ODM_RT_TRACE(dm, ODM_PHY_CONFIG,
565 		     "%s(): Update CCA parameters for Acut\n", __func__);
566 }
567 
phydm_rxdfirpar_by_bw_8822b(struct phy_dm_struct * dm,enum odm_bw bandwidth)568 static void phydm_rxdfirpar_by_bw_8822b(struct phy_dm_struct *dm,
569 					enum odm_bw bandwidth)
570 {
571 	if (bandwidth == ODM_BW40M) {
572 		/* RX DFIR for BW40 */
573 		odm_set_bb_reg(dm, 0x948, BIT(29) | BIT(28), 0x1);
574 		odm_set_bb_reg(dm, 0x94c, BIT(29) | BIT(28), 0x0);
575 		odm_set_bb_reg(dm, 0xc20, BIT(31), 0x0);
576 		odm_set_bb_reg(dm, 0xe20, BIT(31), 0x0);
577 	} else if (bandwidth == ODM_BW80M) {
578 		/* RX DFIR for BW80 */
579 		odm_set_bb_reg(dm, 0x948, BIT(29) | BIT(28), 0x2);
580 		odm_set_bb_reg(dm, 0x94c, BIT(29) | BIT(28), 0x1);
581 		odm_set_bb_reg(dm, 0xc20, BIT(31), 0x0);
582 		odm_set_bb_reg(dm, 0xe20, BIT(31), 0x0);
583 	} else {
584 		/* RX DFIR for BW20, BW10 and BW5*/
585 		odm_set_bb_reg(dm, 0x948, BIT(29) | BIT(28), 0x2);
586 		odm_set_bb_reg(dm, 0x94c, BIT(29) | BIT(28), 0x2);
587 		odm_set_bb_reg(dm, 0xc20, BIT(31), 0x1);
588 		odm_set_bb_reg(dm, 0xe20, BIT(31), 0x1);
589 	}
590 }
591 
phydm_write_txagc_1byte_8822b(struct phy_dm_struct * dm,u32 power_index,enum odm_rf_radio_path path,u8 hw_rate)592 bool phydm_write_txagc_1byte_8822b(struct phy_dm_struct *dm, u32 power_index,
593 				   enum odm_rf_radio_path path, u8 hw_rate)
594 {
595 	u32 offset_txagc[2] = {0x1d00, 0x1d80};
596 	u8 rate_idx = (hw_rate & 0xfc), i;
597 	u8 rate_offset = (hw_rate & 0x3);
598 	u32 txagc_content = 0x0;
599 
600 	/* For debug command only!!!! */
601 
602 	/* Error handling */
603 	if ((path > ODM_RF_PATH_B) || (hw_rate > 0x53)) {
604 		ODM_RT_TRACE(dm, ODM_PHY_CONFIG,
605 			     "%s(): unsupported path (%d)\n", __func__, path);
606 		return false;
607 	}
608 
609 	/* For HW limitation, We can't write TXAGC once a byte. */
610 	for (i = 0; i < 4; i++) {
611 		if (i != rate_offset)
612 			txagc_content =
613 				txagc_content | (config_phydm_read_txagc_8822b(
614 							 dm, path, rate_idx + i)
615 						 << (i << 3));
616 		else
617 			txagc_content = txagc_content |
618 					((power_index & 0x3f) << (i << 3));
619 	}
620 	odm_set_bb_reg(dm, (offset_txagc[path] + rate_idx), MASKDWORD,
621 		       txagc_content);
622 
623 	ODM_RT_TRACE(dm, ODM_PHY_CONFIG,
624 		     "%s(): path-%d rate index 0x%x (0x%x) = 0x%x\n", __func__,
625 		     path, hw_rate, (offset_txagc[path] + hw_rate),
626 		     power_index);
627 	return true;
628 }
629 
phydm_init_hw_info_by_rfe_type_8822b(struct phy_dm_struct * dm)630 void phydm_init_hw_info_by_rfe_type_8822b(struct phy_dm_struct *dm)
631 {
632 	u16 mask_path_a = 0x0303;
633 	u16 mask_path_b = 0x0c0c;
634 	/*u16	mask_path_c = 0x3030;*/
635 	/*u16	mask_path_d = 0xc0c0;*/
636 
637 	dm->is_init_hw_info_by_rfe = false;
638 
639 	if ((dm->rfe_type == 1) || (dm->rfe_type == 6) || (dm->rfe_type == 7)) {
640 		odm_cmn_info_init(dm, ODM_CMNINFO_BOARD_TYPE,
641 				  (ODM_BOARD_EXT_LNA | ODM_BOARD_EXT_LNA_5G |
642 				   ODM_BOARD_EXT_PA | ODM_BOARD_EXT_PA_5G));
643 
644 		if (dm->rfe_type == 6) {
645 			odm_cmn_info_init(
646 				dm, ODM_CMNINFO_GPA,
647 				(TYPE_GPA1 & (mask_path_a | mask_path_b)));
648 			odm_cmn_info_init(
649 				dm, ODM_CMNINFO_APA,
650 				(TYPE_APA1 & (mask_path_a | mask_path_b)));
651 			odm_cmn_info_init(
652 				dm, ODM_CMNINFO_GLNA,
653 				(TYPE_GLNA1 & (mask_path_a | mask_path_b)));
654 			odm_cmn_info_init(
655 				dm, ODM_CMNINFO_ALNA,
656 				(TYPE_ALNA1 & (mask_path_a | mask_path_b)));
657 		} else if (dm->rfe_type == 7) {
658 			odm_cmn_info_init(
659 				dm, ODM_CMNINFO_GPA,
660 				(TYPE_GPA2 & (mask_path_a | mask_path_b)));
661 			odm_cmn_info_init(
662 				dm, ODM_CMNINFO_APA,
663 				(TYPE_APA2 & (mask_path_a | mask_path_b)));
664 			odm_cmn_info_init(
665 				dm, ODM_CMNINFO_GLNA,
666 				(TYPE_GLNA2 & (mask_path_a | mask_path_b)));
667 			odm_cmn_info_init(
668 				dm, ODM_CMNINFO_ALNA,
669 				(TYPE_ALNA2 & (mask_path_a | mask_path_b)));
670 		} else {
671 			odm_cmn_info_init(
672 				dm, ODM_CMNINFO_GPA,
673 				(TYPE_GPA0 & (mask_path_a | mask_path_b)));
674 			odm_cmn_info_init(
675 				dm, ODM_CMNINFO_APA,
676 				(TYPE_APA0 & (mask_path_a | mask_path_b)));
677 			odm_cmn_info_init(
678 				dm, ODM_CMNINFO_GLNA,
679 				(TYPE_GLNA0 & (mask_path_a | mask_path_b)));
680 			odm_cmn_info_init(
681 				dm, ODM_CMNINFO_ALNA,
682 				(TYPE_ALNA0 & (mask_path_a | mask_path_b)));
683 		}
684 
685 		odm_cmn_info_init(dm, ODM_CMNINFO_PACKAGE_TYPE, 1);
686 
687 		odm_cmn_info_init(dm, ODM_CMNINFO_EXT_LNA, true);
688 		odm_cmn_info_init(dm, ODM_CMNINFO_5G_EXT_LNA, true);
689 		odm_cmn_info_init(dm, ODM_CMNINFO_EXT_PA, true);
690 		odm_cmn_info_init(dm, ODM_CMNINFO_5G_EXT_PA, true);
691 	} else if (dm->rfe_type == 2) {
692 		odm_cmn_info_init(dm, ODM_CMNINFO_BOARD_TYPE,
693 				  (ODM_BOARD_EXT_LNA_5G | ODM_BOARD_EXT_PA_5G));
694 		odm_cmn_info_init(dm, ODM_CMNINFO_APA,
695 				  (TYPE_APA0 & (mask_path_a | mask_path_b)));
696 		odm_cmn_info_init(dm, ODM_CMNINFO_ALNA,
697 				  (TYPE_ALNA0 & (mask_path_a | mask_path_b)));
698 
699 		odm_cmn_info_init(dm, ODM_CMNINFO_PACKAGE_TYPE, 2);
700 
701 		odm_cmn_info_init(dm, ODM_CMNINFO_EXT_LNA, false);
702 		odm_cmn_info_init(dm, ODM_CMNINFO_5G_EXT_LNA, true);
703 		odm_cmn_info_init(dm, ODM_CMNINFO_EXT_PA, false);
704 		odm_cmn_info_init(dm, ODM_CMNINFO_5G_EXT_PA, true);
705 	} else if (dm->rfe_type == 9) {
706 		odm_cmn_info_init(dm, ODM_CMNINFO_BOARD_TYPE,
707 				  (ODM_BOARD_EXT_LNA_5G));
708 		odm_cmn_info_init(dm, ODM_CMNINFO_ALNA,
709 				  (TYPE_ALNA0 & (mask_path_a | mask_path_b)));
710 
711 		odm_cmn_info_init(dm, ODM_CMNINFO_PACKAGE_TYPE, 1);
712 
713 		odm_cmn_info_init(dm, ODM_CMNINFO_EXT_LNA, false);
714 		odm_cmn_info_init(dm, ODM_CMNINFO_5G_EXT_LNA, true);
715 		odm_cmn_info_init(dm, ODM_CMNINFO_EXT_PA, false);
716 		odm_cmn_info_init(dm, ODM_CMNINFO_5G_EXT_PA, false);
717 	} else if ((dm->rfe_type == 3) || (dm->rfe_type == 5)) {
718 		/* RFE type 3: 8822BS\8822BU TFBGA iFEM */
719 		/* RFE type 5: 8822BE TFBGA iFEM */
720 		odm_cmn_info_init(dm, ODM_CMNINFO_BOARD_TYPE, 0);
721 
722 		odm_cmn_info_init(dm, ODM_CMNINFO_PACKAGE_TYPE, 2);
723 
724 		odm_cmn_info_init(dm, ODM_CMNINFO_EXT_LNA, false);
725 		odm_cmn_info_init(dm, ODM_CMNINFO_5G_EXT_LNA, false);
726 		odm_cmn_info_init(dm, ODM_CMNINFO_EXT_PA, false);
727 		odm_cmn_info_init(dm, ODM_CMNINFO_5G_EXT_PA, false);
728 	} else if (dm->rfe_type == 4) {
729 		odm_cmn_info_init(dm, ODM_CMNINFO_BOARD_TYPE,
730 				  (ODM_BOARD_EXT_LNA | ODM_BOARD_EXT_LNA_5G |
731 				   ODM_BOARD_EXT_PA | ODM_BOARD_EXT_PA_5G));
732 		odm_cmn_info_init(dm, ODM_CMNINFO_GPA,
733 				  (TYPE_GPA0 & (mask_path_a | mask_path_b)));
734 		odm_cmn_info_init(dm, ODM_CMNINFO_APA,
735 				  (TYPE_APA0 & (mask_path_a | mask_path_b)));
736 		odm_cmn_info_init(dm, ODM_CMNINFO_GLNA,
737 				  (TYPE_GLNA0 & (mask_path_a | mask_path_b)));
738 		odm_cmn_info_init(dm, ODM_CMNINFO_ALNA,
739 				  (TYPE_ALNA0 & (mask_path_a | mask_path_b)));
740 
741 		odm_cmn_info_init(dm, ODM_CMNINFO_PACKAGE_TYPE, 2);
742 
743 		odm_cmn_info_init(dm, ODM_CMNINFO_EXT_LNA, true);
744 		odm_cmn_info_init(dm, ODM_CMNINFO_5G_EXT_LNA, true);
745 		odm_cmn_info_init(dm, ODM_CMNINFO_EXT_PA, true);
746 		odm_cmn_info_init(dm, ODM_CMNINFO_5G_EXT_PA, true);
747 	} else if (dm->rfe_type == 8) {
748 		/* RFE type 8: TFBGA iFEM AP */
749 		odm_cmn_info_init(dm, ODM_CMNINFO_BOARD_TYPE, 0);
750 
751 		odm_cmn_info_init(dm, ODM_CMNINFO_PACKAGE_TYPE, 2);
752 
753 		odm_cmn_info_init(dm, ODM_CMNINFO_EXT_LNA, false);
754 		odm_cmn_info_init(dm, ODM_CMNINFO_5G_EXT_LNA, false);
755 		odm_cmn_info_init(dm, ODM_CMNINFO_EXT_PA, false);
756 		odm_cmn_info_init(dm, ODM_CMNINFO_5G_EXT_PA, false);
757 	} else {
758 		/* RFE Type 0 & 9 & 10: QFN iFEM */
759 		odm_cmn_info_init(dm, ODM_CMNINFO_BOARD_TYPE, 0);
760 
761 		odm_cmn_info_init(dm, ODM_CMNINFO_PACKAGE_TYPE, 1);
762 
763 		odm_cmn_info_init(dm, ODM_CMNINFO_EXT_LNA, false);
764 		odm_cmn_info_init(dm, ODM_CMNINFO_5G_EXT_LNA, false);
765 		odm_cmn_info_init(dm, ODM_CMNINFO_EXT_PA, false);
766 		odm_cmn_info_init(dm, ODM_CMNINFO_5G_EXT_PA, false);
767 	}
768 
769 	dm->is_init_hw_info_by_rfe = true;
770 
771 	ODM_RT_TRACE(
772 		dm, ODM_PHY_CONFIG,
773 		"%s(): RFE type (%d), Board type (0x%x), Package type (%d)\n",
774 		__func__, dm->rfe_type, dm->board_type, dm->package_type);
775 	ODM_RT_TRACE(
776 		dm, ODM_PHY_CONFIG,
777 		"%s(): 5G ePA (%d), 5G eLNA (%d), 2G ePA (%d), 2G eLNA (%d)\n",
778 		__func__, dm->ext_pa_5g, dm->ext_lna_5g, dm->ext_pa,
779 		dm->ext_lna);
780 	ODM_RT_TRACE(
781 		dm, ODM_PHY_CONFIG,
782 		"%s(): 5G PA type (%d), 5G LNA type (%d), 2G PA type (%d), 2G LNA type (%d)\n",
783 		__func__, dm->type_apa, dm->type_alna, dm->type_gpa,
784 		dm->type_glna);
785 }
786 
phydm_get_condition_number_8822B(struct phy_dm_struct * dm)787 s32 phydm_get_condition_number_8822B(struct phy_dm_struct *dm)
788 {
789 	s32 ret_val;
790 
791 	odm_set_bb_reg(dm, 0x1988, BIT(22), 0x1);
792 	ret_val =
793 		(s32)odm_get_bb_reg(dm, 0xf84, (BIT(17) | BIT(16) | MASKLWORD));
794 
795 	if (bw_8822b == 0) {
796 		ret_val = ret_val << (8 - 4);
797 		ret_val = ret_val / 234;
798 	} else if (bw_8822b == 1) {
799 		ret_val = ret_val << (7 - 4);
800 		ret_val = ret_val / 108;
801 	} else if (bw_8822b == 2) {
802 		ret_val = ret_val << (6 - 4);
803 		ret_val = ret_val / 52;
804 	}
805 
806 	return ret_val;
807 }
808 
809 /* ======================================================================== */
810 
811 /* ======================================================================== */
812 /* These following functions can be used by driver*/
813 
config_phydm_read_rf_reg_8822b(struct phy_dm_struct * dm,enum odm_rf_radio_path rf_path,u32 reg_addr,u32 bit_mask)814 u32 config_phydm_read_rf_reg_8822b(struct phy_dm_struct *dm,
815 				   enum odm_rf_radio_path rf_path, u32 reg_addr,
816 				   u32 bit_mask)
817 {
818 	u32 readback_value, direct_addr;
819 	u32 offset_read_rf[2] = {0x2800, 0x2c00};
820 	u32 power_RF[2] = {0x1c, 0xec};
821 
822 	/* Error handling.*/
823 	if (rf_path > ODM_RF_PATH_B) {
824 		ODM_RT_TRACE(dm, ODM_PHY_CONFIG,
825 			     "%s(): unsupported path (%d)\n", __func__,
826 			     rf_path);
827 		return INVALID_RF_DATA;
828 	}
829 
830 	/*  Error handling. Check if RF power is enable or not */
831 	/*  0xffffffff means RF power is disable */
832 	if (odm_get_mac_reg(dm, power_RF[rf_path], MASKBYTE3) != 0x7) {
833 		ODM_RT_TRACE(dm, ODM_PHY_CONFIG,
834 			     "%s(): Read fail, RF is disabled\n", __func__);
835 		return INVALID_RF_DATA;
836 	}
837 
838 	/* Calculate offset */
839 	reg_addr &= 0xff;
840 	direct_addr = offset_read_rf[rf_path] + (reg_addr << 2);
841 
842 	/* RF register only has 20bits */
843 	bit_mask &= RFREGOFFSETMASK;
844 
845 	/* Read RF register directly */
846 	readback_value = odm_get_bb_reg(dm, direct_addr, bit_mask);
847 	ODM_RT_TRACE(dm, ODM_PHY_CONFIG,
848 		     "%s(): RF-%d 0x%x = 0x%x, bit mask = 0x%x\n", __func__,
849 		     rf_path, reg_addr, readback_value, bit_mask);
850 	return readback_value;
851 }
852 
config_phydm_write_rf_reg_8822b(struct phy_dm_struct * dm,enum odm_rf_radio_path rf_path,u32 reg_addr,u32 bit_mask,u32 data)853 bool config_phydm_write_rf_reg_8822b(struct phy_dm_struct *dm,
854 				     enum odm_rf_radio_path rf_path,
855 				     u32 reg_addr, u32 bit_mask, u32 data)
856 {
857 	u32 data_and_addr = 0, data_original = 0;
858 	u32 offset_write_rf[2] = {0xc90, 0xe90};
859 	u32 power_RF[2] = {0x1c, 0xec};
860 
861 	/* Error handling.*/
862 	if (rf_path > ODM_RF_PATH_B) {
863 		ODM_RT_TRACE(dm, ODM_PHY_CONFIG,
864 			     "%s(): unsupported path (%d)\n", __func__,
865 			     rf_path);
866 		return false;
867 	}
868 
869 	/* Read RF register content first */
870 	reg_addr &= 0xff;
871 	bit_mask = bit_mask & RFREGOFFSETMASK;
872 
873 	if (bit_mask != RFREGOFFSETMASK) {
874 		data_original = config_phydm_read_rf_reg_8822b(
875 			dm, rf_path, reg_addr, RFREGOFFSETMASK);
876 
877 		/* Error handling. RF is disabled */
878 		if (!config_phydm_read_rf_check_8822b(data_original)) {
879 			ODM_RT_TRACE(dm, ODM_PHY_CONFIG,
880 				     "%s(): Write fail, RF is disable\n",
881 				     __func__);
882 			return false;
883 		}
884 
885 		/* check bit mask */
886 		data = phydm_check_bit_mask(bit_mask, data_original, data);
887 	} else if (odm_get_mac_reg(dm, power_RF[rf_path], MASKBYTE3) != 0x7) {
888 		ODM_RT_TRACE(dm, ODM_PHY_CONFIG,
889 			     "%s(): Write fail, RF is disabled\n", __func__);
890 		return false;
891 	}
892 
893 	/* Put write addr in [27:20]  and write data in [19:00] */
894 	data_and_addr = ((reg_addr << 20) | (data & 0x000fffff)) & 0x0fffffff;
895 
896 	/* Write operation */
897 	odm_set_bb_reg(dm, offset_write_rf[rf_path], MASKDWORD, data_and_addr);
898 	ODM_RT_TRACE(
899 		dm, ODM_PHY_CONFIG,
900 		"%s(): RF-%d 0x%x = 0x%x (original: 0x%x), bit mask = 0x%x\n",
901 		__func__, rf_path, reg_addr, data, data_original, bit_mask);
902 	return true;
903 }
904 
config_phydm_write_txagc_8822b(struct phy_dm_struct * dm,u32 power_index,enum odm_rf_radio_path path,u8 hw_rate)905 bool config_phydm_write_txagc_8822b(struct phy_dm_struct *dm, u32 power_index,
906 				    enum odm_rf_radio_path path, u8 hw_rate)
907 {
908 	u32 offset_txagc[2] = {0x1d00, 0x1d80};
909 	u8 rate_idx = (hw_rate & 0xfc);
910 
911 	/* Input need to be HW rate index, not driver rate index!!!! */
912 
913 	if (dm->is_disable_phy_api) {
914 		ODM_RT_TRACE(dm, ODM_PHY_CONFIG,
915 			     "%s(): disable PHY API for debug!!\n", __func__);
916 		return true;
917 	}
918 
919 	/* Error handling */
920 	if ((path > ODM_RF_PATH_B) || (hw_rate > 0x53)) {
921 		ODM_RT_TRACE(dm, ODM_PHY_CONFIG,
922 			     "%s(): unsupported path (%d)\n", __func__, path);
923 		return false;
924 	}
925 
926 	/* driver need to construct a 4-byte power index */
927 	odm_set_bb_reg(dm, (offset_txagc[path] + rate_idx), MASKDWORD,
928 		       power_index);
929 
930 	ODM_RT_TRACE(dm, ODM_PHY_CONFIG,
931 		     "%s(): path-%d rate index 0x%x (0x%x) = 0x%x\n", __func__,
932 		     path, hw_rate, (offset_txagc[path] + hw_rate),
933 		     power_index);
934 	return true;
935 }
936 
config_phydm_read_txagc_8822b(struct phy_dm_struct * dm,enum odm_rf_radio_path path,u8 hw_rate)937 u8 config_phydm_read_txagc_8822b(struct phy_dm_struct *dm,
938 				 enum odm_rf_radio_path path, u8 hw_rate)
939 {
940 	u8 read_back_data;
941 
942 	/* Input need to be HW rate index, not driver rate index!!!! */
943 
944 	/* Error handling */
945 	if ((path > ODM_RF_PATH_B) || (hw_rate > 0x53)) {
946 		ODM_RT_TRACE(dm, ODM_PHY_CONFIG,
947 			     "%s(): unsupported path (%d)\n", __func__, path);
948 		return INVALID_TXAGC_DATA;
949 	}
950 
951 	/* Disable TX AGC report */
952 	odm_set_bb_reg(dm, 0x1998, BIT(16), 0x0); /* need to check */
953 
954 	/* Set data rate index (bit0~6) and path index (bit7) */
955 	odm_set_bb_reg(dm, 0x1998, MASKBYTE0, (hw_rate | (path << 7)));
956 
957 	/* Enable TXAGC report */
958 	odm_set_bb_reg(dm, 0x1998, BIT(16), 0x1);
959 
960 	/* Read TX AGC report */
961 	read_back_data = (u8)odm_get_bb_reg(dm, 0xd30, 0x7f0000);
962 
963 	/* Driver have to disable TXAGC report after reading TXAGC
964 	 * (ref. user guide v11)
965 	 */
966 	odm_set_bb_reg(dm, 0x1998, BIT(16), 0x0);
967 
968 	ODM_RT_TRACE(dm, ODM_PHY_CONFIG,
969 		     "%s(): path-%d rate index 0x%x = 0x%x\n", __func__, path,
970 		     hw_rate, read_back_data);
971 	return read_back_data;
972 }
973 
config_phydm_switch_band_8822b(struct phy_dm_struct * dm,u8 central_ch)974 bool config_phydm_switch_band_8822b(struct phy_dm_struct *dm, u8 central_ch)
975 {
976 	u32 rf_reg18;
977 	bool rf_reg_status = true;
978 
979 	ODM_RT_TRACE(dm, ODM_PHY_CONFIG, "%s()======================>\n",
980 		     __func__);
981 
982 	if (dm->is_disable_phy_api) {
983 		ODM_RT_TRACE(dm, ODM_PHY_CONFIG,
984 			     "%s(): disable PHY API for debug!!\n", __func__);
985 		return true;
986 	}
987 
988 	rf_reg18 = config_phydm_read_rf_reg_8822b(dm, ODM_RF_PATH_A, 0x18,
989 						  RFREGOFFSETMASK);
990 	rf_reg_status =
991 		rf_reg_status & config_phydm_read_rf_check_8822b(rf_reg18);
992 
993 	if (central_ch <= 14) {
994 		/* 2.4G */
995 
996 		/* Enable CCK block */
997 		odm_set_bb_reg(dm, 0x808, BIT(28), 0x1);
998 
999 		/* Disable MAC CCK check */
1000 		odm_set_bb_reg(dm, 0x454, BIT(7), 0x0);
1001 
1002 		/* Disable BB CCK check */
1003 		odm_set_bb_reg(dm, 0xa80, BIT(18), 0x0);
1004 
1005 		/*CCA Mask*/
1006 		odm_set_bb_reg(dm, 0x814, 0x0000FC00, 15); /*default value*/
1007 
1008 		/* RF band */
1009 		rf_reg18 = (rf_reg18 & (~(BIT(16) | BIT(9) | BIT(8))));
1010 
1011 		/* RxHP dynamic control */
1012 		if ((dm->rfe_type == 2) || (dm->rfe_type == 3) ||
1013 		    (dm->rfe_type == 5)) {
1014 			odm_set_bb_reg(dm, 0x8cc, MASKDWORD, 0x08108492);
1015 			odm_set_bb_reg(dm, 0x8d8, MASKDWORD, 0x29095612);
1016 		}
1017 
1018 	} else if (central_ch > 35) {
1019 		/* 5G */
1020 
1021 		/* Enable BB CCK check */
1022 		odm_set_bb_reg(dm, 0xa80, BIT(18), 0x1);
1023 
1024 		/* Enable CCK check */
1025 		odm_set_bb_reg(dm, 0x454, BIT(7), 0x1);
1026 
1027 		/* Disable CCK block */
1028 		odm_set_bb_reg(dm, 0x808, BIT(28), 0x0);
1029 
1030 		/*CCA Mask*/
1031 		odm_set_bb_reg(dm, 0x814, 0x0000FC00, 15); /*default value*/
1032 
1033 		/* RF band */
1034 		rf_reg18 = (rf_reg18 & (~(BIT(16) | BIT(9) | BIT(8))));
1035 		rf_reg18 = (rf_reg18 | BIT(8) | BIT(16));
1036 
1037 		/* RxHP dynamic control */
1038 		if ((dm->rfe_type == 2) || (dm->rfe_type == 3) ||
1039 		    (dm->rfe_type == 5)) {
1040 			odm_set_bb_reg(dm, 0x8cc, MASKDWORD, 0x08100000);
1041 			odm_set_bb_reg(dm, 0x8d8, MASKDWORD, 0x21095612);
1042 		}
1043 
1044 	} else {
1045 		ODM_RT_TRACE(dm, ODM_PHY_CONFIG,
1046 			     "%s(): Fail to switch band (ch: %d)\n", __func__,
1047 			     central_ch);
1048 		return false;
1049 	}
1050 
1051 	rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(
1052 						dm, ODM_RF_PATH_A, 0x18,
1053 						RFREGOFFSETMASK, rf_reg18);
1054 
1055 	if (dm->rf_type > ODM_1T1R)
1056 		rf_reg_status =
1057 			rf_reg_status & config_phydm_write_rf_reg_8822b(
1058 						dm, ODM_RF_PATH_B, 0x18,
1059 						RFREGOFFSETMASK, rf_reg18);
1060 
1061 	if (!phydm_rfe_8822b(dm, central_ch))
1062 		return false;
1063 
1064 	if (!rf_reg_status) {
1065 		ODM_RT_TRACE(
1066 			dm, ODM_PHY_CONFIG,
1067 			"%s(): Fail to switch band (ch: %d), because writing RF register is fail\n",
1068 			__func__, central_ch);
1069 		return false;
1070 	}
1071 
1072 	ODM_RT_TRACE(dm, ODM_PHY_CONFIG,
1073 		     "%s(): Success to switch band (ch: %d)\n", __func__,
1074 		     central_ch);
1075 	return true;
1076 }
1077 
config_phydm_switch_channel_8822b(struct phy_dm_struct * dm,u8 central_ch)1078 bool config_phydm_switch_channel_8822b(struct phy_dm_struct *dm, u8 central_ch)
1079 {
1080 	struct dig_thres *dig_tab = &dm->dm_dig_table;
1081 	u32 rf_reg18 = 0, rf_reg_b8 = 0, rf_reg_be = 0xff;
1082 	bool rf_reg_status = true;
1083 	u8 low_band[15] = {0x7, 0x6, 0x6, 0x5, 0x0, 0x0, 0x7, 0xff,
1084 			   0x6, 0x5, 0x0, 0x0, 0x7, 0x6, 0x6};
1085 	u8 middle_band[23] = {0x6, 0x5, 0x0, 0x0, 0x7, 0x6, 0x6, 0xff,
1086 			      0x0, 0x0, 0x7, 0x6, 0x6, 0x5, 0x0, 0xff,
1087 			      0x7, 0x6, 0x6, 0x5, 0x0, 0x0, 0x7};
1088 	u8 high_band[15] = {0x5, 0x5, 0x0, 0x7, 0x7, 0x6, 0x5, 0xff,
1089 			    0x0, 0x7, 0x7, 0x6, 0x5, 0x5, 0x0};
1090 
1091 	ODM_RT_TRACE(dm, ODM_PHY_CONFIG, "%s()====================>\n",
1092 		     __func__);
1093 
1094 	if (dm->is_disable_phy_api) {
1095 		ODM_RT_TRACE(dm, ODM_PHY_CONFIG,
1096 			     "%s(): disable PHY API for debug!!\n", __func__);
1097 		return true;
1098 	}
1099 
1100 	central_ch_8822b = central_ch;
1101 	rf_reg18 = config_phydm_read_rf_reg_8822b(dm, ODM_RF_PATH_A, 0x18,
1102 						  RFREGOFFSETMASK);
1103 	rf_reg_status =
1104 		rf_reg_status & config_phydm_read_rf_check_8822b(rf_reg18);
1105 	rf_reg18 = (rf_reg18 & (~(BIT(18) | BIT(17) | MASKBYTE0)));
1106 
1107 	if (dm->cut_version == ODM_CUT_A) {
1108 		rf_reg_b8 = config_phydm_read_rf_reg_8822b(
1109 			dm, ODM_RF_PATH_A, 0xb8, RFREGOFFSETMASK);
1110 		rf_reg_status = rf_reg_status &
1111 				config_phydm_read_rf_check_8822b(rf_reg_b8);
1112 	}
1113 
1114 	/* Switch band and channel */
1115 	if (central_ch <= 14) {
1116 		/* 2.4G */
1117 
1118 		/* 1. RF band and channel*/
1119 		rf_reg18 = (rf_reg18 | central_ch);
1120 
1121 		/* 2. AGC table selection */
1122 		odm_set_bb_reg(dm, 0x958, 0x1f, 0x0);
1123 		dig_tab->agc_table_idx = 0x0;
1124 
1125 		/* 3. Set central frequency for clock offset tracking */
1126 		odm_set_bb_reg(dm, 0x860, 0x1ffe0000, 0x96a);
1127 
1128 		/* Fix A-cut LCK fail issue @ 5285MHz~5375MHz, 0xb8[19]=0x0 */
1129 		if (dm->cut_version == ODM_CUT_A)
1130 			rf_reg_b8 = rf_reg_b8 | BIT(19);
1131 
1132 		/* CCK TX filter parameters */
1133 		if (central_ch == 14) {
1134 			odm_set_bb_reg(dm, 0xa20, MASKHWORD, 0x8488);
1135 			odm_set_bb_reg(dm, 0xa24, MASKDWORD, 0x00006577);
1136 			odm_set_bb_reg(dm, 0xa28, MASKLWORD, 0x0000);
1137 		} else {
1138 			odm_set_bb_reg(dm, 0xa20, MASKHWORD,
1139 				       (rega20_8822b >> 16));
1140 			odm_set_bb_reg(dm, 0xa24, MASKDWORD, rega24_8822b);
1141 			odm_set_bb_reg(dm, 0xa28, MASKLWORD,
1142 				       (rega28_8822b & MASKLWORD));
1143 		}
1144 
1145 	} else if (central_ch > 35) {
1146 		/* 5G */
1147 
1148 		/* 1. RF band and channel*/
1149 		rf_reg18 = (rf_reg18 | central_ch);
1150 
1151 		/* 2. AGC table selection */
1152 		if ((central_ch >= 36) && (central_ch <= 64)) {
1153 			odm_set_bb_reg(dm, 0x958, 0x1f, 0x1);
1154 			dig_tab->agc_table_idx = 0x1;
1155 		} else if ((central_ch >= 100) && (central_ch <= 144)) {
1156 			odm_set_bb_reg(dm, 0x958, 0x1f, 0x2);
1157 			dig_tab->agc_table_idx = 0x2;
1158 		} else if (central_ch >= 149) {
1159 			odm_set_bb_reg(dm, 0x958, 0x1f, 0x3);
1160 			dig_tab->agc_table_idx = 0x3;
1161 		} else {
1162 			ODM_RT_TRACE(
1163 				dm, ODM_PHY_CONFIG,
1164 				"%s(): Fail to switch channel (AGC) (ch: %d)\n",
1165 				__func__, central_ch);
1166 			return false;
1167 		}
1168 
1169 		/* 3. Set central frequency for clock offset tracking */
1170 		if ((central_ch >= 36) && (central_ch <= 48)) {
1171 			odm_set_bb_reg(dm, 0x860, 0x1ffe0000, 0x494);
1172 		} else if ((central_ch >= 52) && (central_ch <= 64)) {
1173 			odm_set_bb_reg(dm, 0x860, 0x1ffe0000, 0x453);
1174 		} else if ((central_ch >= 100) && (central_ch <= 116)) {
1175 			odm_set_bb_reg(dm, 0x860, 0x1ffe0000, 0x452);
1176 		} else if ((central_ch >= 118) && (central_ch <= 177)) {
1177 			odm_set_bb_reg(dm, 0x860, 0x1ffe0000, 0x412);
1178 		} else {
1179 			ODM_RT_TRACE(
1180 				dm, ODM_PHY_CONFIG,
1181 				"%s(): Fail to switch channel (fc_area) (ch: %d)\n",
1182 				__func__, central_ch);
1183 			return false;
1184 		}
1185 
1186 		/* Fix A-cut LCK fail issue @ 5285MHz~5375MHz, 0xb8[19]=0x0 */
1187 		if (dm->cut_version == ODM_CUT_A) {
1188 			if ((central_ch >= 57) && (central_ch <= 75))
1189 				rf_reg_b8 = rf_reg_b8 & (~BIT(19));
1190 			else
1191 				rf_reg_b8 = rf_reg_b8 | BIT(19);
1192 		}
1193 	} else {
1194 		ODM_RT_TRACE(dm, ODM_PHY_CONFIG,
1195 			     "%s(): Fail to switch channel (ch: %d)\n",
1196 			     __func__, central_ch);
1197 		return false;
1198 	}
1199 
1200 	/* Modify IGI for MP driver to aviod PCIE interference */
1201 	if (dm->mp_mode && ((dm->rfe_type == 3) || (dm->rfe_type == 5))) {
1202 		if (central_ch == 14)
1203 			odm_write_dig(dm, 0x26);
1204 		else
1205 			odm_write_dig(dm, 0x20);
1206 	}
1207 
1208 	/* Modify the setting of register 0xBE to reduce phase noise */
1209 	if (central_ch <= 14)
1210 		rf_reg_be = 0x0;
1211 	else if ((central_ch >= 36) && (central_ch <= 64))
1212 		rf_reg_be = low_band[(central_ch - 36) >> 1];
1213 	else if ((central_ch >= 100) && (central_ch <= 144))
1214 		rf_reg_be = middle_band[(central_ch - 100) >> 1];
1215 	else if ((central_ch >= 149) && (central_ch <= 177))
1216 		rf_reg_be = high_band[(central_ch - 149) >> 1];
1217 	else
1218 		rf_reg_be = 0xff;
1219 
1220 	if (rf_reg_be != 0xff) {
1221 		rf_reg_status =
1222 			rf_reg_status & config_phydm_write_rf_reg_8822b(
1223 						dm, ODM_RF_PATH_A, 0xbe,
1224 						(BIT(17) | BIT(16) | BIT(15)),
1225 						rf_reg_be);
1226 	} else {
1227 		ODM_RT_TRACE(
1228 			dm, ODM_PHY_CONFIG,
1229 			"%s(): Fail to switch channel (ch: %d, Phase noise)\n",
1230 			__func__, central_ch);
1231 		return false;
1232 	}
1233 
1234 	/* Fix channel 144 issue, ask by RFSI Alvin*/
1235 	/* 00 when freq < 5400;  01 when 5400<=freq<=5720; 10 when freq > 5720;
1236 	 * 2G don't care
1237 	 */
1238 	/* need to set 0xdf[18]=1 before writing RF18 when channel 144 */
1239 	if (central_ch == 144) {
1240 		rf_reg_status = rf_reg_status &
1241 				config_phydm_write_rf_reg_8822b(
1242 					dm, ODM_RF_PATH_A, 0xdf, BIT(18), 0x1);
1243 		rf_reg18 = (rf_reg18 | BIT(17));
1244 	} else {
1245 		rf_reg_status = rf_reg_status &
1246 				config_phydm_write_rf_reg_8822b(
1247 					dm, ODM_RF_PATH_A, 0xdf, BIT(18), 0x0);
1248 
1249 		if (central_ch > 144)
1250 			rf_reg18 = (rf_reg18 | BIT(18));
1251 		else if (central_ch >= 80)
1252 			rf_reg18 = (rf_reg18 | BIT(17));
1253 	}
1254 
1255 	rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(
1256 						dm, ODM_RF_PATH_A, 0x18,
1257 						RFREGOFFSETMASK, rf_reg18);
1258 
1259 	if (dm->cut_version == ODM_CUT_A)
1260 		rf_reg_status =
1261 			rf_reg_status & config_phydm_write_rf_reg_8822b(
1262 						dm, ODM_RF_PATH_A, 0xb8,
1263 						RFREGOFFSETMASK, rf_reg_b8);
1264 
1265 	if (dm->rf_type > ODM_1T1R) {
1266 		rf_reg_status =
1267 			rf_reg_status & config_phydm_write_rf_reg_8822b(
1268 						dm, ODM_RF_PATH_B, 0x18,
1269 						RFREGOFFSETMASK, rf_reg18);
1270 
1271 		if (dm->cut_version == ODM_CUT_A)
1272 			rf_reg_status = rf_reg_status &
1273 					config_phydm_write_rf_reg_8822b(
1274 						dm, ODM_RF_PATH_B, 0xb8,
1275 						RFREGOFFSETMASK, rf_reg_b8);
1276 	}
1277 
1278 	if (!rf_reg_status) {
1279 		ODM_RT_TRACE(
1280 			dm, ODM_PHY_CONFIG,
1281 			"%s(): Fail to switch channel (ch: %d), because writing RF register is fail\n",
1282 			__func__, central_ch);
1283 		return false;
1284 	}
1285 
1286 	phydm_ccapar_by_rfe_8822b(dm);
1287 	ODM_RT_TRACE(dm, ODM_PHY_CONFIG,
1288 		     "%s(): Success to switch channel (ch: %d)\n", __func__,
1289 		     central_ch);
1290 	return true;
1291 }
1292 
config_phydm_switch_bandwidth_8822b(struct phy_dm_struct * dm,u8 primary_ch_idx,enum odm_bw bandwidth)1293 bool config_phydm_switch_bandwidth_8822b(struct phy_dm_struct *dm,
1294 					 u8 primary_ch_idx,
1295 					 enum odm_bw bandwidth)
1296 {
1297 	u32 rf_reg18;
1298 	bool rf_reg_status = true;
1299 	u8 IGI = 0;
1300 
1301 	ODM_RT_TRACE(dm, ODM_PHY_CONFIG, "%s()===================>\n",
1302 		     __func__);
1303 
1304 	if (dm->is_disable_phy_api) {
1305 		ODM_RT_TRACE(dm, ODM_PHY_CONFIG,
1306 			     "%s(): disable PHY API for debug!!\n", __func__);
1307 		return true;
1308 	}
1309 
1310 	/* Error handling */
1311 	if ((bandwidth >= ODM_BW_MAX) ||
1312 	    ((bandwidth == ODM_BW40M) && (primary_ch_idx > 2)) ||
1313 	    ((bandwidth == ODM_BW80M) && (primary_ch_idx > 4))) {
1314 		ODM_RT_TRACE(
1315 			dm, ODM_PHY_CONFIG,
1316 			"%s(): Fail to switch bandwidth (bw: %d, primary ch: %d)\n",
1317 			__func__, bandwidth, primary_ch_idx);
1318 		return false;
1319 	}
1320 
1321 	bw_8822b = bandwidth;
1322 	rf_reg18 = config_phydm_read_rf_reg_8822b(dm, ODM_RF_PATH_A, 0x18,
1323 						  RFREGOFFSETMASK);
1324 	rf_reg_status =
1325 		rf_reg_status & config_phydm_read_rf_check_8822b(rf_reg18);
1326 
1327 	/* Switch bandwidth */
1328 	switch (bandwidth) {
1329 	case ODM_BW20M: {
1330 		/* Small BW([7:6]) = 0, primary channel ([5:2]) = 0,
1331 		 * rf mode([1:0]) = 20M
1332 		 */
1333 		odm_set_bb_reg(dm, 0x8ac, MASKBYTE0, ODM_BW20M);
1334 
1335 		/* ADC clock = 160M clock for BW20 */
1336 		odm_set_bb_reg(dm, 0x8ac, (BIT(9) | BIT(8)), 0x0);
1337 		odm_set_bb_reg(dm, 0x8ac, BIT(16), 0x1);
1338 
1339 		/* DAC clock = 160M clock for BW20 */
1340 		odm_set_bb_reg(dm, 0x8ac, (BIT(21) | BIT(20)), 0x0);
1341 		odm_set_bb_reg(dm, 0x8ac, BIT(28), 0x1);
1342 
1343 		/* ADC buffer clock */
1344 		odm_set_bb_reg(dm, 0x8c4, BIT(30), 0x1);
1345 
1346 		/* RF bandwidth */
1347 		rf_reg18 = (rf_reg18 | BIT(11) | BIT(10));
1348 
1349 		break;
1350 	}
1351 	case ODM_BW40M: {
1352 		/* Small BW([7:6]) = 0, primary channel ([5:2]) = sub-channel,
1353 		 * rf mode([1:0]) = 40M
1354 		 */
1355 		odm_set_bb_reg(dm, 0x8ac, MASKBYTE0,
1356 			       (((primary_ch_idx & 0xf) << 2) | ODM_BW40M));
1357 
1358 		/* CCK primary channel */
1359 		if (primary_ch_idx == 1)
1360 			odm_set_bb_reg(dm, 0xa00, BIT(4), primary_ch_idx);
1361 		else
1362 			odm_set_bb_reg(dm, 0xa00, BIT(4), 0);
1363 
1364 		/* ADC clock = 160M clock for BW40 */
1365 		odm_set_bb_reg(dm, 0x8ac, (BIT(11) | BIT(10)), 0x0);
1366 		odm_set_bb_reg(dm, 0x8ac, BIT(17), 0x1);
1367 
1368 		/* DAC clock = 160M clock for BW20 */
1369 		odm_set_bb_reg(dm, 0x8ac, (BIT(23) | BIT(22)), 0x0);
1370 		odm_set_bb_reg(dm, 0x8ac, BIT(29), 0x1);
1371 
1372 		/* ADC buffer clock */
1373 		odm_set_bb_reg(dm, 0x8c4, BIT(30), 0x1);
1374 
1375 		/* RF bandwidth */
1376 		rf_reg18 = (rf_reg18 & (~(BIT(11) | BIT(10))));
1377 		rf_reg18 = (rf_reg18 | BIT(11));
1378 
1379 		break;
1380 	}
1381 	case ODM_BW80M: {
1382 		/* Small BW([7:6]) = 0, primary channel ([5:2]) = sub-channel,
1383 		 * rf mode([1:0]) = 80M
1384 		 */
1385 		odm_set_bb_reg(dm, 0x8ac, MASKBYTE0,
1386 			       (((primary_ch_idx & 0xf) << 2) | ODM_BW80M));
1387 
1388 		/* ADC clock = 160M clock for BW80 */
1389 		odm_set_bb_reg(dm, 0x8ac, (BIT(13) | BIT(12)), 0x0);
1390 		odm_set_bb_reg(dm, 0x8ac, BIT(18), 0x1);
1391 
1392 		/* DAC clock = 160M clock for BW20 */
1393 		odm_set_bb_reg(dm, 0x8ac, (BIT(25) | BIT(24)), 0x0);
1394 		odm_set_bb_reg(dm, 0x8ac, BIT(30), 0x1);
1395 
1396 		/* ADC buffer clock */
1397 		odm_set_bb_reg(dm, 0x8c4, BIT(30), 0x1);
1398 
1399 		/* RF bandwidth */
1400 		rf_reg18 = (rf_reg18 & (~(BIT(11) | BIT(10))));
1401 		rf_reg18 = (rf_reg18 | BIT(10));
1402 
1403 		break;
1404 	}
1405 	case ODM_BW5M: {
1406 		/* Small BW([7:6]) = 1, primary channel ([5:2]) = 0,
1407 		 * rf mode([1:0]) = 20M
1408 		 */
1409 		odm_set_bb_reg(dm, 0x8ac, MASKBYTE0, (BIT(6) | ODM_BW20M));
1410 
1411 		/* ADC clock = 40M clock */
1412 		odm_set_bb_reg(dm, 0x8ac, (BIT(9) | BIT(8)), 0x2);
1413 		odm_set_bb_reg(dm, 0x8ac, BIT(16), 0x0);
1414 
1415 		/* DAC clock = 160M clock for BW20 */
1416 		odm_set_bb_reg(dm, 0x8ac, (BIT(21) | BIT(20)), 0x2);
1417 		odm_set_bb_reg(dm, 0x8ac, BIT(28), 0x0);
1418 
1419 		/* ADC buffer clock */
1420 		odm_set_bb_reg(dm, 0x8c4, BIT(30), 0x0);
1421 		odm_set_bb_reg(dm, 0x8c8, BIT(31), 0x1);
1422 
1423 		/* RF bandwidth */
1424 		rf_reg18 = (rf_reg18 | BIT(11) | BIT(10));
1425 
1426 		break;
1427 	}
1428 	case ODM_BW10M: {
1429 		/* Small BW([7:6]) = 1, primary channel ([5:2]) = 0,
1430 		 * rf mode([1:0]) = 20M
1431 		 */
1432 		odm_set_bb_reg(dm, 0x8ac, MASKBYTE0, (BIT(7) | ODM_BW20M));
1433 
1434 		/* ADC clock = 80M clock */
1435 		odm_set_bb_reg(dm, 0x8ac, (BIT(9) | BIT(8)), 0x3);
1436 		odm_set_bb_reg(dm, 0x8ac, BIT(16), 0x0);
1437 
1438 		/* DAC clock = 160M clock for BW20 */
1439 		odm_set_bb_reg(dm, 0x8ac, (BIT(21) | BIT(20)), 0x3);
1440 		odm_set_bb_reg(dm, 0x8ac, BIT(28), 0x0);
1441 
1442 		/* ADC buffer clock */
1443 		odm_set_bb_reg(dm, 0x8c4, BIT(30), 0x0);
1444 		odm_set_bb_reg(dm, 0x8c8, BIT(31), 0x1);
1445 
1446 		/* RF bandwidth */
1447 		rf_reg18 = (rf_reg18 | BIT(11) | BIT(10));
1448 
1449 		break;
1450 	}
1451 	default:
1452 		ODM_RT_TRACE(
1453 			dm, ODM_PHY_CONFIG,
1454 			"%s(): Fail to switch bandwidth (bw: %d, primary ch: %d)\n",
1455 			__func__, bandwidth, primary_ch_idx);
1456 	}
1457 
1458 	/* Write RF register */
1459 	rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(
1460 						dm, ODM_RF_PATH_A, 0x18,
1461 						RFREGOFFSETMASK, rf_reg18);
1462 
1463 	if (dm->rf_type > ODM_1T1R)
1464 		rf_reg_status =
1465 			rf_reg_status & config_phydm_write_rf_reg_8822b(
1466 						dm, ODM_RF_PATH_B, 0x18,
1467 						RFREGOFFSETMASK, rf_reg18);
1468 
1469 	if (!rf_reg_status) {
1470 		ODM_RT_TRACE(
1471 			dm, ODM_PHY_CONFIG,
1472 			"%s(): Fail to switch bandwidth (bw: %d, primary ch: %d), because writing RF register is fail\n",
1473 			__func__, bandwidth, primary_ch_idx);
1474 		return false;
1475 	}
1476 
1477 	/* Modify RX DFIR parameters */
1478 	phydm_rxdfirpar_by_bw_8822b(dm, bandwidth);
1479 
1480 	/* Modify CCA parameters */
1481 	phydm_ccapar_by_bw_8822b(dm, bandwidth);
1482 	phydm_ccapar_by_rfe_8822b(dm);
1483 
1484 	/* Toggle RX path to avoid RX dead zone issue */
1485 	odm_set_bb_reg(dm, 0x808, MASKBYTE0, 0x0);
1486 	odm_set_bb_reg(dm, 0x808, MASKBYTE0,
1487 		       (dm->rx_ant_status | (dm->rx_ant_status << 4)));
1488 
1489 	/* Toggle IGI to let RF enter RX mode */
1490 	IGI = (u8)odm_get_bb_reg(dm, ODM_REG(IGI_A, dm), ODM_BIT(IGI, dm));
1491 	odm_set_bb_reg(dm, ODM_REG(IGI_A, dm), ODM_BIT(IGI, dm), IGI - 2);
1492 	odm_set_bb_reg(dm, ODM_REG(IGI_B, dm), ODM_BIT(IGI, dm), IGI - 2);
1493 	odm_set_bb_reg(dm, ODM_REG(IGI_A, dm), ODM_BIT(IGI, dm), IGI);
1494 	odm_set_bb_reg(dm, ODM_REG(IGI_B, dm), ODM_BIT(IGI, dm), IGI);
1495 
1496 	ODM_RT_TRACE(
1497 		dm, ODM_PHY_CONFIG,
1498 		"%s(): Success to switch bandwidth (bw: %d, primary ch: %d)\n",
1499 		__func__, bandwidth, primary_ch_idx);
1500 	return true;
1501 }
1502 
config_phydm_switch_channel_bw_8822b(struct phy_dm_struct * dm,u8 central_ch,u8 primary_ch_idx,enum odm_bw bandwidth)1503 bool config_phydm_switch_channel_bw_8822b(struct phy_dm_struct *dm,
1504 					  u8 central_ch, u8 primary_ch_idx,
1505 					  enum odm_bw bandwidth)
1506 {
1507 	/* Switch band */
1508 	if (!config_phydm_switch_band_8822b(dm, central_ch))
1509 		return false;
1510 
1511 	/* Switch channel */
1512 	if (!config_phydm_switch_channel_8822b(dm, central_ch))
1513 		return false;
1514 
1515 	/* Switch bandwidth */
1516 	if (!config_phydm_switch_bandwidth_8822b(dm, primary_ch_idx, bandwidth))
1517 		return false;
1518 
1519 	return true;
1520 }
1521 
config_phydm_trx_mode_8822b(struct phy_dm_struct * dm,enum odm_rf_path tx_path,enum odm_rf_path rx_path,bool is_tx2_path)1522 bool config_phydm_trx_mode_8822b(struct phy_dm_struct *dm,
1523 				 enum odm_rf_path tx_path,
1524 				 enum odm_rf_path rx_path, bool is_tx2_path)
1525 {
1526 	bool rf_reg_status = true;
1527 	u8 IGI;
1528 	u32 rf_reg33 = 0;
1529 	u16 counter = 0;
1530 
1531 	ODM_RT_TRACE(dm, ODM_PHY_CONFIG, "%s()=====================>\n",
1532 		     __func__);
1533 
1534 	if (dm->is_disable_phy_api) {
1535 		ODM_RT_TRACE(dm, ODM_PHY_CONFIG,
1536 			     "%s(): disable PHY API for debug!!\n", __func__);
1537 		return true;
1538 	}
1539 
1540 	if ((tx_path & (~(ODM_RF_A | ODM_RF_B))) != 0) {
1541 		ODM_RT_TRACE(dm, ODM_PHY_CONFIG,
1542 			     "%s(): Wrong TX setting (TX: 0x%x)\n", __func__,
1543 			     tx_path);
1544 		return false;
1545 	}
1546 
1547 	if ((rx_path & (~(ODM_RF_A | ODM_RF_B))) != 0) {
1548 		ODM_RT_TRACE(dm, ODM_PHY_CONFIG,
1549 			     "%s(): Wrong RX setting (RX: 0x%x)\n", __func__,
1550 			     rx_path);
1551 		return false;
1552 	}
1553 
1554 	/* RF mode of path-A and path-B */
1555 	/* Cannot shut down path-A, beacause synthesizer will be shut down when
1556 	 * path-A is in shut down mode
1557 	 */
1558 	if ((tx_path | rx_path) & ODM_RF_A)
1559 		odm_set_bb_reg(dm, 0xc08, MASKLWORD, 0x3231);
1560 	else
1561 		odm_set_bb_reg(dm, 0xc08, MASKLWORD, 0x1111);
1562 
1563 	if ((tx_path | rx_path) & ODM_RF_B)
1564 		odm_set_bb_reg(dm, 0xe08, MASKLWORD, 0x3231);
1565 	else
1566 		odm_set_bb_reg(dm, 0xe08, MASKLWORD, 0x1111);
1567 
1568 	/* Set TX antenna by Nsts */
1569 	odm_set_bb_reg(dm, 0x93c, (BIT(19) | BIT(18)), 0x3);
1570 	odm_set_bb_reg(dm, 0x80c, (BIT(29) | BIT(28)), 0x1);
1571 
1572 	/* Control CCK TX path by 0xa07[7] */
1573 	odm_set_bb_reg(dm, 0x80c, BIT(30), 0x1);
1574 
1575 	/* TX logic map and TX path en for Nsts = 1, and CCK TX path*/
1576 	if (tx_path & ODM_RF_A) {
1577 		odm_set_bb_reg(dm, 0x93c, 0xfff00000, 0x001);
1578 		odm_set_bb_reg(dm, 0xa04, 0xf0000000, 0x8);
1579 	} else if (tx_path & ODM_RF_B) {
1580 		odm_set_bb_reg(dm, 0x93c, 0xfff00000, 0x002);
1581 		odm_set_bb_reg(dm, 0xa04, 0xf0000000, 0x4);
1582 	}
1583 
1584 	/* TX logic map and TX path en for Nsts = 2*/
1585 	if ((tx_path == ODM_RF_A) || (tx_path == ODM_RF_B))
1586 		odm_set_bb_reg(dm, 0x940, 0xfff0, 0x01);
1587 	else
1588 		odm_set_bb_reg(dm, 0x940, 0xfff0, 0x43);
1589 
1590 	/* TX path enable */
1591 	odm_set_bb_reg(dm, 0x80c, MASKBYTE0, ((tx_path << 4) | tx_path));
1592 
1593 	/* Tx2path for 1ss */
1594 	if (!((tx_path == ODM_RF_A) || (tx_path == ODM_RF_B))) {
1595 		if (is_tx2_path || dm->mp_mode) {
1596 			/* 2Tx for OFDM */
1597 			odm_set_bb_reg(dm, 0x93c, 0xfff00000, 0x043);
1598 
1599 			/* 2Tx for CCK */
1600 			odm_set_bb_reg(dm, 0xa04, 0xf0000000, 0xc);
1601 		}
1602 	}
1603 
1604 	/* Always disable MRC for CCK CCA */
1605 	odm_set_bb_reg(dm, 0xa2c, BIT(22), 0x0);
1606 
1607 	/* Always disable MRC for CCK barker */
1608 	odm_set_bb_reg(dm, 0xa2c, BIT(18), 0x0);
1609 
1610 	/* CCK RX 1st and 2nd path setting*/
1611 	if (rx_path & ODM_RF_A)
1612 		odm_set_bb_reg(dm, 0xa04, 0x0f000000, 0x0);
1613 	else if (rx_path & ODM_RF_B)
1614 		odm_set_bb_reg(dm, 0xa04, 0x0f000000, 0x5);
1615 
1616 	/* RX path enable */
1617 	odm_set_bb_reg(dm, 0x808, MASKBYTE0, ((rx_path << 4) | rx_path));
1618 
1619 	if ((rx_path == ODM_RF_A) || (rx_path == ODM_RF_B)) {
1620 		/* 1R */
1621 
1622 		/* Disable MRC for CCA */
1623 		/* odm_set_bb_reg(dm, 0xa2c, BIT22, 0x0); */
1624 
1625 		/* Disable MRC for barker */
1626 		/* odm_set_bb_reg(dm, 0xa2c, BIT18, 0x0); */
1627 
1628 		/* Disable CCK antenna diversity */
1629 		/* odm_set_bb_reg(dm, 0xa00, BIT15, 0x0); */
1630 
1631 		/* Disable Antenna weighting */
1632 		odm_set_bb_reg(dm, 0x1904, BIT(16), 0x0);
1633 		odm_set_bb_reg(dm, 0x800, BIT(28), 0x0);
1634 		odm_set_bb_reg(dm, 0x850, BIT(23), 0x0);
1635 	} else {
1636 		/* 2R */
1637 
1638 		/* Enable MRC for CCA */
1639 		/* odm_set_bb_reg(dm, 0xa2c, BIT22, 0x1); */
1640 
1641 		/* Enable MRC for barker */
1642 		/* odm_set_bb_reg(dm, 0xa2c, BIT18, 0x1); */
1643 
1644 		/* Disable CCK antenna diversity */
1645 		/* odm_set_bb_reg(dm, 0xa00, BIT15, 0x0); */
1646 
1647 		/* Enable Antenna weighting */
1648 		odm_set_bb_reg(dm, 0x1904, BIT(16), 0x1);
1649 		odm_set_bb_reg(dm, 0x800, BIT(28), 0x1);
1650 		odm_set_bb_reg(dm, 0x850, BIT(23), 0x1);
1651 	}
1652 
1653 	/* Update TXRX antenna status for PHYDM */
1654 	dm->tx_ant_status = (tx_path & 0x3);
1655 	dm->rx_ant_status = (rx_path & 0x3);
1656 
1657 	/* MP driver need to support path-B TX\RX */
1658 
1659 	while (1) {
1660 		counter++;
1661 		rf_reg_status =
1662 			rf_reg_status & config_phydm_write_rf_reg_8822b(
1663 						dm, ODM_RF_PATH_A, 0xef,
1664 						RFREGOFFSETMASK, 0x80000);
1665 		rf_reg_status =
1666 			rf_reg_status & config_phydm_write_rf_reg_8822b(
1667 						dm, ODM_RF_PATH_A, 0x33,
1668 						RFREGOFFSETMASK, 0x00001);
1669 
1670 		ODM_delay_us(2);
1671 		rf_reg33 = config_phydm_read_rf_reg_8822b(
1672 			dm, ODM_RF_PATH_A, 0x33, RFREGOFFSETMASK);
1673 
1674 		if ((rf_reg33 == 0x00001) &&
1675 		    (config_phydm_read_rf_check_8822b(rf_reg33)))
1676 			break;
1677 		else if (counter == 100) {
1678 			ODM_RT_TRACE(
1679 				dm, ODM_PHY_CONFIG,
1680 				"%s(): Fail to set TRx mode setting, because writing RF mode table is fail\n",
1681 				__func__);
1682 			return false;
1683 		}
1684 	}
1685 
1686 	if ((dm->mp_mode) || *dm->antenna_test || (dm->normal_rx_path)) {
1687 		/* 0xef 0x80000  0x33 0x00001  0x3e 0x00034  0x3f 0x4080e
1688 		 * 0xef 0x00000    suggested by Lucas
1689 		 */
1690 		rf_reg_status =
1691 			rf_reg_status & config_phydm_write_rf_reg_8822b(
1692 						dm, ODM_RF_PATH_A, 0xef,
1693 						RFREGOFFSETMASK, 0x80000);
1694 		rf_reg_status =
1695 			rf_reg_status & config_phydm_write_rf_reg_8822b(
1696 						dm, ODM_RF_PATH_A, 0x33,
1697 						RFREGOFFSETMASK, 0x00001);
1698 		rf_reg_status =
1699 			rf_reg_status & config_phydm_write_rf_reg_8822b(
1700 						dm, ODM_RF_PATH_A, 0x3e,
1701 						RFREGOFFSETMASK, 0x00034);
1702 		rf_reg_status =
1703 			rf_reg_status & config_phydm_write_rf_reg_8822b(
1704 						dm, ODM_RF_PATH_A, 0x3f,
1705 						RFREGOFFSETMASK, 0x4080e);
1706 		rf_reg_status =
1707 			rf_reg_status & config_phydm_write_rf_reg_8822b(
1708 						dm, ODM_RF_PATH_A, 0xef,
1709 						RFREGOFFSETMASK, 0x00000);
1710 		ODM_RT_TRACE(
1711 			dm, ODM_PHY_CONFIG,
1712 			"%s(): MP mode or Antenna test mode!! support path-B TX and RX\n",
1713 			__func__);
1714 	} else {
1715 		/* 0xef 0x80000  0x33 0x00001  0x3e 0x00034  0x3f 0x4080c
1716 		 * 0xef 0x00000
1717 		 */
1718 		rf_reg_status =
1719 			rf_reg_status & config_phydm_write_rf_reg_8822b(
1720 						dm, ODM_RF_PATH_A, 0xef,
1721 						RFREGOFFSETMASK, 0x80000);
1722 		rf_reg_status =
1723 			rf_reg_status & config_phydm_write_rf_reg_8822b(
1724 						dm, ODM_RF_PATH_A, 0x33,
1725 						RFREGOFFSETMASK, 0x00001);
1726 		rf_reg_status =
1727 			rf_reg_status & config_phydm_write_rf_reg_8822b(
1728 						dm, ODM_RF_PATH_A, 0x3e,
1729 						RFREGOFFSETMASK, 0x00034);
1730 		rf_reg_status =
1731 			rf_reg_status & config_phydm_write_rf_reg_8822b(
1732 						dm, ODM_RF_PATH_A, 0x3f,
1733 						RFREGOFFSETMASK, 0x4080c);
1734 		rf_reg_status =
1735 			rf_reg_status & config_phydm_write_rf_reg_8822b(
1736 						dm, ODM_RF_PATH_A, 0xef,
1737 						RFREGOFFSETMASK, 0x00000);
1738 		ODM_RT_TRACE(
1739 			dm, ODM_PHY_CONFIG,
1740 			"%s(): Normal mode!! Do not support path-B TX and RX\n",
1741 			__func__);
1742 	}
1743 
1744 	rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(
1745 						dm, ODM_RF_PATH_A, 0xef,
1746 						RFREGOFFSETMASK, 0x00000);
1747 
1748 	if (!rf_reg_status) {
1749 		ODM_RT_TRACE(
1750 			dm, ODM_PHY_CONFIG,
1751 			"%s(): Fail to set TRx mode setting (TX: 0x%x, RX: 0x%x), because writing RF register is fail\n",
1752 			__func__, tx_path, rx_path);
1753 		return false;
1754 	}
1755 
1756 	/* Toggle IGI to let RF enter RX mode,
1757 	 * because BB doesn't send 3-wire command when RX path is enable
1758 	 */
1759 	IGI = (u8)odm_get_bb_reg(dm, ODM_REG(IGI_A, dm), ODM_BIT(IGI, dm));
1760 	odm_write_dig(dm, IGI - 2);
1761 	odm_write_dig(dm, IGI);
1762 
1763 	/* Modify CCA parameters */
1764 	phydm_ccapar_by_rxpath_8822b(dm);
1765 	phydm_ccapar_by_rfe_8822b(dm);
1766 	phydm_rfe_8822b(dm, central_ch_8822b);
1767 
1768 	ODM_RT_TRACE(
1769 		dm, ODM_PHY_CONFIG,
1770 		"%s(): Success to set TRx mode setting (TX: 0x%x, RX: 0x%x)\n",
1771 		__func__, tx_path, rx_path);
1772 	return true;
1773 }
1774 
config_phydm_parameter_init(struct phy_dm_struct * dm,enum odm_parameter_init type)1775 bool config_phydm_parameter_init(struct phy_dm_struct *dm,
1776 				 enum odm_parameter_init type)
1777 {
1778 	if (type == ODM_PRE_SETTING) {
1779 		odm_set_bb_reg(dm, 0x808, (BIT(28) | BIT(29)), 0x0);
1780 		ODM_RT_TRACE(dm, ODM_PHY_CONFIG,
1781 			     "%s(): Pre setting: disable OFDM and CCK block\n",
1782 			     __func__);
1783 	} else if (type == ODM_POST_SETTING) {
1784 		odm_set_bb_reg(dm, 0x808, (BIT(28) | BIT(29)), 0x3);
1785 		ODM_RT_TRACE(dm, ODM_PHY_CONFIG,
1786 			     "%s(): Post setting: enable OFDM and CCK block\n",
1787 			     __func__);
1788 		reg82c_8822b = odm_get_bb_reg(dm, 0x82c, MASKDWORD);
1789 		reg838_8822b = odm_get_bb_reg(dm, 0x838, MASKDWORD);
1790 		reg830_8822b = odm_get_bb_reg(dm, 0x830, MASKDWORD);
1791 		reg83c_8822b = odm_get_bb_reg(dm, 0x83c, MASKDWORD);
1792 		rega20_8822b = odm_get_bb_reg(dm, 0xa20, MASKDWORD);
1793 		rega24_8822b = odm_get_bb_reg(dm, 0xa24, MASKDWORD);
1794 		rega28_8822b = odm_get_bb_reg(dm, 0xa28, MASKDWORD);
1795 	} else {
1796 		ODM_RT_TRACE(dm, ODM_PHY_CONFIG, "%s(): Wrong type!!\n",
1797 			     __func__);
1798 		return false;
1799 	}
1800 
1801 	return true;
1802 }
1803 
1804 /* ======================================================================== */
1805