1 /*
2 * Copyright 2012-15 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include <drm/display/drm_dp_helper.h>
27 #include <drm/display/drm_dp_mst_helper.h>
28 #include <drm/drm_atomic.h>
29 #include <drm/drm_atomic_helper.h>
30 #include "dm_services.h"
31 #include "amdgpu.h"
32 #include "amdgpu_dm.h"
33 #include "amdgpu_dm_mst_types.h"
34
35 #include "dc.h"
36 #include "dm_helpers.h"
37
38 #include "dc_link_ddc.h"
39 #include "dc_link_dp.h"
40 #include "ddc_service_types.h"
41 #include "dpcd_defs.h"
42
43 #include "i2caux_interface.h"
44 #include "dmub_cmd.h"
45 #if defined(CONFIG_DEBUG_FS)
46 #include "amdgpu_dm_debugfs.h"
47 #endif
48
49 #include "dc/dcn20/dcn20_resource.h"
50 bool is_timing_changed(struct dc_stream_state *cur_stream,
51 struct dc_stream_state *new_stream);
52
53
dm_dp_aux_transfer(struct drm_dp_aux * aux,struct drm_dp_aux_msg * msg)54 static ssize_t dm_dp_aux_transfer(struct drm_dp_aux *aux,
55 struct drm_dp_aux_msg *msg)
56 {
57 ssize_t result = 0;
58 struct aux_payload payload;
59 enum aux_return_code_type operation_result;
60 struct amdgpu_device *adev;
61 struct ddc_service *ddc;
62
63 if (WARN_ON(msg->size > 16))
64 return -E2BIG;
65
66 payload.address = msg->address;
67 payload.data = msg->buffer;
68 payload.length = msg->size;
69 payload.reply = &msg->reply;
70 payload.i2c_over_aux = (msg->request & DP_AUX_NATIVE_WRITE) == 0;
71 payload.write = (msg->request & DP_AUX_I2C_READ) == 0;
72 payload.mot = (msg->request & DP_AUX_I2C_MOT) != 0;
73 payload.write_status_update =
74 (msg->request & DP_AUX_I2C_WRITE_STATUS_UPDATE) != 0;
75 payload.defer_delay = 0;
76
77 result = dc_link_aux_transfer_raw(TO_DM_AUX(aux)->ddc_service, &payload,
78 &operation_result);
79
80 /*
81 * w/a on certain intel platform where hpd is unexpected to pull low during
82 * 1st sideband message transaction by return AUX_RET_ERROR_HPD_DISCON
83 * aux transaction is succuess in such case, therefore bypass the error
84 */
85 ddc = TO_DM_AUX(aux)->ddc_service;
86 adev = ddc->ctx->driver_context;
87 if (adev->dm.aux_hpd_discon_quirk) {
88 if (msg->address == DP_SIDEBAND_MSG_DOWN_REQ_BASE &&
89 operation_result == AUX_RET_ERROR_HPD_DISCON) {
90 result = 0;
91 operation_result = AUX_RET_SUCCESS;
92 }
93 }
94
95 if (payload.write && result >= 0)
96 result = msg->size;
97
98 if (result < 0)
99 switch (operation_result) {
100 case AUX_RET_SUCCESS:
101 break;
102 case AUX_RET_ERROR_HPD_DISCON:
103 case AUX_RET_ERROR_UNKNOWN:
104 case AUX_RET_ERROR_INVALID_OPERATION:
105 case AUX_RET_ERROR_PROTOCOL_ERROR:
106 result = -EIO;
107 break;
108 case AUX_RET_ERROR_INVALID_REPLY:
109 case AUX_RET_ERROR_ENGINE_ACQUIRE:
110 result = -EBUSY;
111 break;
112 case AUX_RET_ERROR_TIMEOUT:
113 result = -ETIMEDOUT;
114 break;
115 }
116
117 return result;
118 }
119
120 static void
dm_dp_mst_connector_destroy(struct drm_connector * connector)121 dm_dp_mst_connector_destroy(struct drm_connector *connector)
122 {
123 struct amdgpu_dm_connector *aconnector =
124 to_amdgpu_dm_connector(connector);
125
126 if (aconnector->dc_sink) {
127 dc_link_remove_remote_sink(aconnector->dc_link,
128 aconnector->dc_sink);
129 dc_sink_release(aconnector->dc_sink);
130 }
131
132 kfree(aconnector->edid);
133
134 drm_connector_cleanup(connector);
135 drm_dp_mst_put_port_malloc(aconnector->port);
136 kfree(aconnector);
137 }
138
139 static int
amdgpu_dm_mst_connector_late_register(struct drm_connector * connector)140 amdgpu_dm_mst_connector_late_register(struct drm_connector *connector)
141 {
142 struct amdgpu_dm_connector *amdgpu_dm_connector =
143 to_amdgpu_dm_connector(connector);
144 int r;
145
146 r = drm_dp_mst_connector_late_register(connector,
147 amdgpu_dm_connector->port);
148 if (r < 0)
149 return r;
150
151 #if defined(CONFIG_DEBUG_FS)
152 connector_debugfs_init(amdgpu_dm_connector);
153 #endif
154
155 return 0;
156 }
157
158 static void
amdgpu_dm_mst_connector_early_unregister(struct drm_connector * connector)159 amdgpu_dm_mst_connector_early_unregister(struct drm_connector *connector)
160 {
161 struct amdgpu_dm_connector *aconnector =
162 to_amdgpu_dm_connector(connector);
163 struct drm_dp_mst_port *port = aconnector->port;
164 struct amdgpu_dm_connector *root = aconnector->mst_port;
165 struct dc_link *dc_link = aconnector->dc_link;
166 struct dc_sink *dc_sink = aconnector->dc_sink;
167
168 drm_dp_mst_connector_early_unregister(connector, port);
169
170 /*
171 * Release dc_sink for connector which its attached port is
172 * no longer in the mst topology
173 */
174 drm_modeset_lock(&root->mst_mgr.base.lock, NULL);
175 if (dc_sink) {
176 if (dc_link->sink_count)
177 dc_link_remove_remote_sink(dc_link, dc_sink);
178
179 dc_sink_release(dc_sink);
180 aconnector->dc_sink = NULL;
181 aconnector->edid = NULL;
182 }
183
184 aconnector->mst_status = MST_STATUS_DEFAULT;
185 drm_modeset_unlock(&root->mst_mgr.base.lock);
186 }
187
188 static const struct drm_connector_funcs dm_dp_mst_connector_funcs = {
189 .fill_modes = drm_helper_probe_single_connector_modes,
190 .destroy = dm_dp_mst_connector_destroy,
191 .reset = amdgpu_dm_connector_funcs_reset,
192 .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state,
193 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
194 .atomic_set_property = amdgpu_dm_connector_atomic_set_property,
195 .atomic_get_property = amdgpu_dm_connector_atomic_get_property,
196 .late_register = amdgpu_dm_mst_connector_late_register,
197 .early_unregister = amdgpu_dm_mst_connector_early_unregister,
198 };
199
200 #if defined(CONFIG_DRM_AMD_DC_DCN)
needs_dsc_aux_workaround(struct dc_link * link)201 bool needs_dsc_aux_workaround(struct dc_link *link)
202 {
203 if (link->dpcd_caps.branch_dev_id == DP_BRANCH_DEVICE_ID_90CC24 &&
204 (link->dpcd_caps.dpcd_rev.raw == DPCD_REV_14 || link->dpcd_caps.dpcd_rev.raw == DPCD_REV_12) &&
205 link->dpcd_caps.sink_count.bits.SINK_COUNT >= 2)
206 return true;
207
208 return false;
209 }
210
validate_dsc_caps_on_connector(struct amdgpu_dm_connector * aconnector)211 static bool validate_dsc_caps_on_connector(struct amdgpu_dm_connector *aconnector)
212 {
213 struct dc_sink *dc_sink = aconnector->dc_sink;
214 struct drm_dp_mst_port *port = aconnector->port;
215 u8 dsc_caps[16] = { 0 };
216 u8 dsc_branch_dec_caps_raw[3] = { 0 }; // DSC branch decoder caps 0xA0 ~ 0xA2
217 u8 *dsc_branch_dec_caps = NULL;
218
219 aconnector->dsc_aux = drm_dp_mst_dsc_aux_for_port(port);
220
221 /*
222 * drm_dp_mst_dsc_aux_for_port() will return NULL for certain configs
223 * because it only check the dsc/fec caps of the "port variable" and not the dock
224 *
225 * This case will return NULL: DSC capabe MST dock connected to a non fec/dsc capable display
226 *
227 * Workaround: explicitly check the use case above and use the mst dock's aux as dsc_aux
228 *
229 */
230 if (!aconnector->dsc_aux && !port->parent->port_parent &&
231 needs_dsc_aux_workaround(aconnector->dc_link))
232 aconnector->dsc_aux = &aconnector->mst_port->dm_dp_aux.aux;
233
234 if (!aconnector->dsc_aux)
235 return false;
236
237 if (drm_dp_dpcd_read(aconnector->dsc_aux, DP_DSC_SUPPORT, dsc_caps, 16) < 0)
238 return false;
239
240 if (drm_dp_dpcd_read(aconnector->dsc_aux,
241 DP_DSC_BRANCH_OVERALL_THROUGHPUT_0, dsc_branch_dec_caps_raw, 3) == 3)
242 dsc_branch_dec_caps = dsc_branch_dec_caps_raw;
243
244 if (!dc_dsc_parse_dsc_dpcd(aconnector->dc_link->ctx->dc,
245 dsc_caps, dsc_branch_dec_caps,
246 &dc_sink->dsc_caps.dsc_dec_caps))
247 return false;
248
249 return true;
250 }
251
retrieve_downstream_port_device(struct amdgpu_dm_connector * aconnector)252 static bool retrieve_downstream_port_device(struct amdgpu_dm_connector *aconnector)
253 {
254 union dp_downstream_port_present ds_port_present;
255
256 if (!aconnector->dsc_aux)
257 return false;
258
259 if (drm_dp_dpcd_read(aconnector->dsc_aux, DP_DOWNSTREAMPORT_PRESENT, &ds_port_present, 1) < 0) {
260 DRM_INFO("Failed to read downstream_port_present 0x05 from DFP of branch device\n");
261 return false;
262 }
263
264 aconnector->mst_downstream_port_present = ds_port_present;
265 DRM_INFO("Downstream port present %d, type %d\n",
266 ds_port_present.fields.PORT_PRESENT, ds_port_present.fields.PORT_TYPE);
267
268 return true;
269 }
270 #endif
271
dm_dp_mst_get_modes(struct drm_connector * connector)272 static int dm_dp_mst_get_modes(struct drm_connector *connector)
273 {
274 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
275 int ret = 0;
276
277 if (!aconnector)
278 return drm_add_edid_modes(connector, NULL);
279
280 if (!aconnector->edid) {
281 struct edid *edid;
282 edid = drm_dp_mst_get_edid(connector, &aconnector->mst_port->mst_mgr, aconnector->port);
283
284 if (!edid) {
285 amdgpu_dm_set_mst_status(&aconnector->mst_status,
286 MST_REMOTE_EDID, false);
287
288 drm_connector_update_edid_property(
289 &aconnector->base,
290 NULL);
291
292 DRM_DEBUG_KMS("Can't get EDID of %s. Add default remote sink.", connector->name);
293 if (!aconnector->dc_sink) {
294 struct dc_sink *dc_sink;
295 struct dc_sink_init_data init_params = {
296 .link = aconnector->dc_link,
297 .sink_signal = SIGNAL_TYPE_DISPLAY_PORT_MST };
298
299 dc_sink = dc_link_add_remote_sink(
300 aconnector->dc_link,
301 NULL,
302 0,
303 &init_params);
304
305 if (!dc_sink) {
306 DRM_ERROR("Unable to add a remote sink\n");
307 return 0;
308 }
309
310 dc_sink->priv = aconnector;
311 aconnector->dc_sink = dc_sink;
312 }
313
314 return ret;
315 }
316
317 aconnector->edid = edid;
318 amdgpu_dm_set_mst_status(&aconnector->mst_status,
319 MST_REMOTE_EDID, true);
320 }
321
322 if (aconnector->dc_sink && aconnector->dc_sink->sink_signal == SIGNAL_TYPE_VIRTUAL) {
323 dc_sink_release(aconnector->dc_sink);
324 aconnector->dc_sink = NULL;
325 }
326
327 if (!aconnector->dc_sink) {
328 struct dc_sink *dc_sink;
329 struct dc_sink_init_data init_params = {
330 .link = aconnector->dc_link,
331 .sink_signal = SIGNAL_TYPE_DISPLAY_PORT_MST };
332 dc_sink = dc_link_add_remote_sink(
333 aconnector->dc_link,
334 (uint8_t *)aconnector->edid,
335 (aconnector->edid->extensions + 1) * EDID_LENGTH,
336 &init_params);
337
338 if (!dc_sink) {
339 DRM_ERROR("Unable to add a remote sink\n");
340 return 0;
341 }
342
343 dc_sink->priv = aconnector;
344 /* dc_link_add_remote_sink returns a new reference */
345 aconnector->dc_sink = dc_sink;
346
347 if (aconnector->dc_sink) {
348 amdgpu_dm_update_freesync_caps(
349 connector, aconnector->edid);
350
351 #if defined(CONFIG_DRM_AMD_DC_DCN)
352 if (!validate_dsc_caps_on_connector(aconnector))
353 memset(&aconnector->dc_sink->dsc_caps,
354 0, sizeof(aconnector->dc_sink->dsc_caps));
355
356 if (!retrieve_downstream_port_device(aconnector))
357 memset(&aconnector->mst_downstream_port_present,
358 0, sizeof(aconnector->mst_downstream_port_present));
359 #endif
360 }
361 }
362
363 drm_connector_update_edid_property(
364 &aconnector->base, aconnector->edid);
365
366 ret = drm_add_edid_modes(connector, aconnector->edid);
367
368 return ret;
369 }
370
371 static struct drm_encoder *
dm_mst_atomic_best_encoder(struct drm_connector * connector,struct drm_atomic_state * state)372 dm_mst_atomic_best_encoder(struct drm_connector *connector,
373 struct drm_atomic_state *state)
374 {
375 struct drm_connector_state *connector_state = drm_atomic_get_new_connector_state(state,
376 connector);
377 struct drm_device *dev = connector->dev;
378 struct amdgpu_device *adev = drm_to_adev(dev);
379 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(connector_state->crtc);
380
381 return &adev->dm.mst_encoders[acrtc->crtc_id].base;
382 }
383
384 static int
dm_dp_mst_detect(struct drm_connector * connector,struct drm_modeset_acquire_ctx * ctx,bool force)385 dm_dp_mst_detect(struct drm_connector *connector,
386 struct drm_modeset_acquire_ctx *ctx, bool force)
387 {
388 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
389 struct amdgpu_dm_connector *master = aconnector->mst_port;
390 struct drm_dp_mst_port *port = aconnector->port;
391 int connection_status;
392
393 if (drm_connector_is_unregistered(connector))
394 return connector_status_disconnected;
395
396 connection_status = drm_dp_mst_detect_port(connector, ctx, &master->mst_mgr,
397 aconnector->port);
398
399 if (port->pdt != DP_PEER_DEVICE_NONE && !port->dpcd_rev) {
400 uint8_t dpcd_rev;
401 int ret;
402
403 ret = drm_dp_dpcd_readb(&port->aux, DP_DP13_DPCD_REV, &dpcd_rev);
404
405 if (ret == 1) {
406 port->dpcd_rev = dpcd_rev;
407
408 /* Could be DP1.2 DP Rx case*/
409 if (!dpcd_rev) {
410 ret = drm_dp_dpcd_readb(&port->aux, DP_DPCD_REV, &dpcd_rev);
411
412 if (ret == 1)
413 port->dpcd_rev = dpcd_rev;
414 }
415
416 if (!dpcd_rev)
417 DRM_DEBUG_KMS("Can't decide DPCD revision number!");
418 }
419
420 /*
421 * Could be legacy sink, logical port etc on DP1.2.
422 * Will get Nack under these cases when issue remote
423 * DPCD read.
424 */
425 if (ret != 1)
426 DRM_DEBUG_KMS("Can't access DPCD");
427 } else if (port->pdt == DP_PEER_DEVICE_NONE) {
428 port->dpcd_rev = 0;
429 }
430
431 /*
432 * Release dc_sink for connector which unplug event is notified by CSN msg
433 */
434 if (connection_status == connector_status_disconnected && aconnector->dc_sink) {
435 if (aconnector->dc_link->sink_count)
436 dc_link_remove_remote_sink(aconnector->dc_link, aconnector->dc_sink);
437
438 dc_sink_release(aconnector->dc_sink);
439 aconnector->dc_sink = NULL;
440 aconnector->edid = NULL;
441
442 amdgpu_dm_set_mst_status(&aconnector->mst_status,
443 MST_REMOTE_EDID | MST_ALLOCATE_NEW_PAYLOAD | MST_CLEAR_ALLOCATED_PAYLOAD,
444 false);
445 }
446
447 return connection_status;
448 }
449
dm_dp_mst_atomic_check(struct drm_connector * connector,struct drm_atomic_state * state)450 static int dm_dp_mst_atomic_check(struct drm_connector *connector,
451 struct drm_atomic_state *state)
452 {
453 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
454 struct drm_dp_mst_topology_mgr *mst_mgr = &aconnector->mst_port->mst_mgr;
455 struct drm_dp_mst_port *mst_port = aconnector->port;
456
457 return drm_dp_atomic_release_time_slots(state, mst_mgr, mst_port);
458 }
459
460 static const struct drm_connector_helper_funcs dm_dp_mst_connector_helper_funcs = {
461 .get_modes = dm_dp_mst_get_modes,
462 .mode_valid = amdgpu_dm_connector_mode_valid,
463 .atomic_best_encoder = dm_mst_atomic_best_encoder,
464 .detect_ctx = dm_dp_mst_detect,
465 .atomic_check = dm_dp_mst_atomic_check,
466 };
467
amdgpu_dm_encoder_destroy(struct drm_encoder * encoder)468 static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder)
469 {
470 drm_encoder_cleanup(encoder);
471 kfree(encoder);
472 }
473
474 static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = {
475 .destroy = amdgpu_dm_encoder_destroy,
476 };
477
478 void
dm_dp_create_fake_mst_encoders(struct amdgpu_device * adev)479 dm_dp_create_fake_mst_encoders(struct amdgpu_device *adev)
480 {
481 struct drm_device *dev = adev_to_drm(adev);
482 int i;
483
484 for (i = 0; i < adev->dm.display_indexes_num; i++) {
485 struct amdgpu_encoder *amdgpu_encoder = &adev->dm.mst_encoders[i];
486 struct drm_encoder *encoder = &amdgpu_encoder->base;
487
488 encoder->possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev);
489
490 drm_encoder_init(
491 dev,
492 &amdgpu_encoder->base,
493 &amdgpu_dm_encoder_funcs,
494 DRM_MODE_ENCODER_DPMST,
495 NULL);
496
497 drm_encoder_helper_add(encoder, &amdgpu_dm_encoder_helper_funcs);
498 }
499 }
500
501 static struct drm_connector *
dm_dp_add_mst_connector(struct drm_dp_mst_topology_mgr * mgr,struct drm_dp_mst_port * port,const char * pathprop)502 dm_dp_add_mst_connector(struct drm_dp_mst_topology_mgr *mgr,
503 struct drm_dp_mst_port *port,
504 const char *pathprop)
505 {
506 struct amdgpu_dm_connector *master = container_of(mgr, struct amdgpu_dm_connector, mst_mgr);
507 struct drm_device *dev = master->base.dev;
508 struct amdgpu_device *adev = drm_to_adev(dev);
509 struct amdgpu_dm_connector *aconnector;
510 struct drm_connector *connector;
511 int i;
512
513 aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL);
514 if (!aconnector)
515 return NULL;
516
517 connector = &aconnector->base;
518 aconnector->port = port;
519 aconnector->mst_port = master;
520 amdgpu_dm_set_mst_status(&aconnector->mst_status,
521 MST_PROBE, true);
522
523 if (drm_connector_init(
524 dev,
525 connector,
526 &dm_dp_mst_connector_funcs,
527 DRM_MODE_CONNECTOR_DisplayPort)) {
528 kfree(aconnector);
529 return NULL;
530 }
531 drm_connector_helper_add(connector, &dm_dp_mst_connector_helper_funcs);
532
533 amdgpu_dm_connector_init_helper(
534 &adev->dm,
535 aconnector,
536 DRM_MODE_CONNECTOR_DisplayPort,
537 master->dc_link,
538 master->connector_id);
539
540 for (i = 0; i < adev->dm.display_indexes_num; i++) {
541 drm_connector_attach_encoder(&aconnector->base,
542 &adev->dm.mst_encoders[i].base);
543 }
544
545 connector->max_bpc_property = master->base.max_bpc_property;
546 if (connector->max_bpc_property)
547 drm_connector_attach_max_bpc_property(connector, 8, 16);
548
549 connector->vrr_capable_property = master->base.vrr_capable_property;
550 if (connector->vrr_capable_property)
551 drm_connector_attach_vrr_capable_property(connector);
552
553 drm_object_attach_property(
554 &connector->base,
555 dev->mode_config.path_property,
556 0);
557 drm_object_attach_property(
558 &connector->base,
559 dev->mode_config.tile_property,
560 0);
561
562 drm_connector_set_path_property(connector, pathprop);
563
564 /*
565 * Initialize connector state before adding the connectror to drm and
566 * framebuffer lists
567 */
568 amdgpu_dm_connector_funcs_reset(connector);
569
570 drm_dp_mst_get_port_malloc(port);
571
572 return connector;
573 }
574
575 static const struct drm_dp_mst_topology_cbs dm_mst_cbs = {
576 .add_connector = dm_dp_add_mst_connector,
577 };
578
amdgpu_dm_initialize_dp_connector(struct amdgpu_display_manager * dm,struct amdgpu_dm_connector * aconnector,int link_index)579 void amdgpu_dm_initialize_dp_connector(struct amdgpu_display_manager *dm,
580 struct amdgpu_dm_connector *aconnector,
581 int link_index)
582 {
583 struct dc_link_settings max_link_enc_cap = {0};
584
585 aconnector->dm_dp_aux.aux.name =
586 kasprintf(GFP_KERNEL, "AMDGPU DM aux hw bus %d",
587 link_index);
588 aconnector->dm_dp_aux.aux.transfer = dm_dp_aux_transfer;
589 aconnector->dm_dp_aux.aux.drm_dev = dm->ddev;
590 aconnector->dm_dp_aux.ddc_service = aconnector->dc_link->ddc;
591
592 drm_dp_aux_init(&aconnector->dm_dp_aux.aux);
593 drm_dp_cec_register_connector(&aconnector->dm_dp_aux.aux,
594 &aconnector->base);
595
596 if (aconnector->base.connector_type == DRM_MODE_CONNECTOR_eDP)
597 return;
598
599 dc_link_dp_get_max_link_enc_cap(aconnector->dc_link, &max_link_enc_cap);
600 aconnector->mst_mgr.cbs = &dm_mst_cbs;
601 drm_dp_mst_topology_mgr_init(&aconnector->mst_mgr, adev_to_drm(dm->adev),
602 &aconnector->dm_dp_aux.aux, 16, 4, aconnector->connector_id);
603
604 drm_connector_attach_dp_subconnector_property(&aconnector->base);
605 }
606
dm_mst_get_pbn_divider(struct dc_link * link)607 int dm_mst_get_pbn_divider(struct dc_link *link)
608 {
609 if (!link)
610 return 0;
611
612 return dc_link_bandwidth_kbps(link,
613 dc_link_get_link_cap(link)) / (8 * 1000 * 54);
614 }
615
616 #if defined(CONFIG_DRM_AMD_DC_DCN)
617
618 struct dsc_mst_fairness_params {
619 struct dc_crtc_timing *timing;
620 struct dc_sink *sink;
621 struct dc_dsc_bw_range bw_range;
622 bool compression_possible;
623 struct drm_dp_mst_port *port;
624 enum dsc_clock_force_state clock_force_enable;
625 uint32_t num_slices_h;
626 uint32_t num_slices_v;
627 uint32_t bpp_overwrite;
628 struct amdgpu_dm_connector *aconnector;
629 };
630
kbps_to_peak_pbn(int kbps)631 static int kbps_to_peak_pbn(int kbps)
632 {
633 u64 peak_kbps = kbps;
634
635 peak_kbps *= 1006;
636 peak_kbps = div_u64(peak_kbps, 1000);
637 return (int) DIV64_U64_ROUND_UP(peak_kbps * 64, (54 * 8 * 1000));
638 }
639
set_dsc_configs_from_fairness_vars(struct dsc_mst_fairness_params * params,struct dsc_mst_fairness_vars * vars,int count,int k)640 static void set_dsc_configs_from_fairness_vars(struct dsc_mst_fairness_params *params,
641 struct dsc_mst_fairness_vars *vars,
642 int count,
643 int k)
644 {
645 int i;
646
647 for (i = 0; i < count; i++) {
648 memset(¶ms[i].timing->dsc_cfg, 0, sizeof(params[i].timing->dsc_cfg));
649 if (vars[i + k].dsc_enabled && dc_dsc_compute_config(
650 params[i].sink->ctx->dc->res_pool->dscs[0],
651 ¶ms[i].sink->dsc_caps.dsc_dec_caps,
652 params[i].sink->ctx->dc->debug.dsc_min_slice_height_override,
653 params[i].sink->edid_caps.panel_patch.max_dsc_target_bpp_limit,
654 0,
655 params[i].timing,
656 ¶ms[i].timing->dsc_cfg)) {
657 params[i].timing->flags.DSC = 1;
658
659 if (params[i].bpp_overwrite)
660 params[i].timing->dsc_cfg.bits_per_pixel = params[i].bpp_overwrite;
661 else
662 params[i].timing->dsc_cfg.bits_per_pixel = vars[i + k].bpp_x16;
663
664 if (params[i].num_slices_h)
665 params[i].timing->dsc_cfg.num_slices_h = params[i].num_slices_h;
666
667 if (params[i].num_slices_v)
668 params[i].timing->dsc_cfg.num_slices_v = params[i].num_slices_v;
669 } else {
670 params[i].timing->flags.DSC = 0;
671 }
672 params[i].timing->dsc_cfg.mst_pbn = vars[i + k].pbn;
673 }
674
675 for (i = 0; i < count; i++) {
676 if (params[i].sink) {
677 if (params[i].sink->sink_signal != SIGNAL_TYPE_VIRTUAL &&
678 params[i].sink->sink_signal != SIGNAL_TYPE_NONE)
679 DRM_DEBUG_DRIVER("%s i=%d dispname=%s\n", __func__, i,
680 params[i].sink->edid_caps.display_name);
681 }
682
683 DRM_DEBUG_DRIVER("dsc=%d bits_per_pixel=%d pbn=%d\n",
684 params[i].timing->flags.DSC,
685 params[i].timing->dsc_cfg.bits_per_pixel,
686 vars[i + k].pbn);
687 }
688 }
689
bpp_x16_from_pbn(struct dsc_mst_fairness_params param,int pbn)690 static int bpp_x16_from_pbn(struct dsc_mst_fairness_params param, int pbn)
691 {
692 struct dc_dsc_config dsc_config;
693 u64 kbps;
694
695 kbps = div_u64((u64)pbn * 994 * 8 * 54, 64);
696 dc_dsc_compute_config(
697 param.sink->ctx->dc->res_pool->dscs[0],
698 ¶m.sink->dsc_caps.dsc_dec_caps,
699 param.sink->ctx->dc->debug.dsc_min_slice_height_override,
700 param.sink->edid_caps.panel_patch.max_dsc_target_bpp_limit,
701 (int) kbps, param.timing, &dsc_config);
702
703 return dsc_config.bits_per_pixel;
704 }
705
increase_dsc_bpp(struct drm_atomic_state * state,struct drm_dp_mst_topology_state * mst_state,struct dc_link * dc_link,struct dsc_mst_fairness_params * params,struct dsc_mst_fairness_vars * vars,int count,int k)706 static int increase_dsc_bpp(struct drm_atomic_state *state,
707 struct drm_dp_mst_topology_state *mst_state,
708 struct dc_link *dc_link,
709 struct dsc_mst_fairness_params *params,
710 struct dsc_mst_fairness_vars *vars,
711 int count,
712 int k)
713 {
714 int i;
715 bool bpp_increased[MAX_PIPES];
716 int initial_slack[MAX_PIPES];
717 int min_initial_slack;
718 int next_index;
719 int remaining_to_increase = 0;
720 int link_timeslots_used;
721 int fair_pbn_alloc;
722 int ret = 0;
723
724 for (i = 0; i < count; i++) {
725 if (vars[i + k].dsc_enabled) {
726 initial_slack[i] =
727 kbps_to_peak_pbn(params[i].bw_range.max_kbps) - vars[i + k].pbn;
728 bpp_increased[i] = false;
729 remaining_to_increase += 1;
730 } else {
731 initial_slack[i] = 0;
732 bpp_increased[i] = true;
733 }
734 }
735
736 while (remaining_to_increase) {
737 next_index = -1;
738 min_initial_slack = -1;
739 for (i = 0; i < count; i++) {
740 if (!bpp_increased[i]) {
741 if (min_initial_slack == -1 || min_initial_slack > initial_slack[i]) {
742 min_initial_slack = initial_slack[i];
743 next_index = i;
744 }
745 }
746 }
747
748 if (next_index == -1)
749 break;
750
751 link_timeslots_used = 0;
752
753 for (i = 0; i < count; i++)
754 link_timeslots_used += DIV_ROUND_UP(vars[i + k].pbn, mst_state->pbn_div);
755
756 fair_pbn_alloc =
757 (63 - link_timeslots_used) / remaining_to_increase * mst_state->pbn_div;
758
759 if (initial_slack[next_index] > fair_pbn_alloc) {
760 vars[next_index].pbn += fair_pbn_alloc;
761 ret = drm_dp_atomic_find_time_slots(state,
762 params[next_index].port->mgr,
763 params[next_index].port,
764 vars[next_index].pbn);
765 if (ret < 0)
766 return ret;
767
768 ret = drm_dp_mst_atomic_check(state);
769 if (ret == 0) {
770 vars[next_index].bpp_x16 = bpp_x16_from_pbn(params[next_index], vars[next_index].pbn);
771 } else {
772 vars[next_index].pbn -= fair_pbn_alloc;
773 ret = drm_dp_atomic_find_time_slots(state,
774 params[next_index].port->mgr,
775 params[next_index].port,
776 vars[next_index].pbn);
777 if (ret < 0)
778 return ret;
779 }
780 } else {
781 vars[next_index].pbn += initial_slack[next_index];
782 ret = drm_dp_atomic_find_time_slots(state,
783 params[next_index].port->mgr,
784 params[next_index].port,
785 vars[next_index].pbn);
786 if (ret < 0)
787 return ret;
788
789 ret = drm_dp_mst_atomic_check(state);
790 if (ret == 0) {
791 vars[next_index].bpp_x16 = params[next_index].bw_range.max_target_bpp_x16;
792 } else {
793 vars[next_index].pbn -= initial_slack[next_index];
794 ret = drm_dp_atomic_find_time_slots(state,
795 params[next_index].port->mgr,
796 params[next_index].port,
797 vars[next_index].pbn);
798 if (ret < 0)
799 return ret;
800 }
801 }
802
803 bpp_increased[next_index] = true;
804 remaining_to_increase--;
805 }
806 return 0;
807 }
808
try_disable_dsc(struct drm_atomic_state * state,struct dc_link * dc_link,struct dsc_mst_fairness_params * params,struct dsc_mst_fairness_vars * vars,int count,int k)809 static int try_disable_dsc(struct drm_atomic_state *state,
810 struct dc_link *dc_link,
811 struct dsc_mst_fairness_params *params,
812 struct dsc_mst_fairness_vars *vars,
813 int count,
814 int k)
815 {
816 int i;
817 bool tried[MAX_PIPES];
818 int kbps_increase[MAX_PIPES];
819 int max_kbps_increase;
820 int next_index;
821 int remaining_to_try = 0;
822 int ret;
823
824 for (i = 0; i < count; i++) {
825 if (vars[i + k].dsc_enabled
826 && vars[i + k].bpp_x16 == params[i].bw_range.max_target_bpp_x16
827 && params[i].clock_force_enable == DSC_CLK_FORCE_DEFAULT) {
828 kbps_increase[i] = params[i].bw_range.stream_kbps - params[i].bw_range.max_kbps;
829 tried[i] = false;
830 remaining_to_try += 1;
831 } else {
832 kbps_increase[i] = 0;
833 tried[i] = true;
834 }
835 }
836
837 while (remaining_to_try) {
838 next_index = -1;
839 max_kbps_increase = -1;
840 for (i = 0; i < count; i++) {
841 if (!tried[i]) {
842 if (max_kbps_increase == -1 || max_kbps_increase < kbps_increase[i]) {
843 max_kbps_increase = kbps_increase[i];
844 next_index = i;
845 }
846 }
847 }
848
849 if (next_index == -1)
850 break;
851
852 vars[next_index].pbn = kbps_to_peak_pbn(params[next_index].bw_range.stream_kbps);
853 ret = drm_dp_atomic_find_time_slots(state,
854 params[next_index].port->mgr,
855 params[next_index].port,
856 vars[next_index].pbn);
857 if (ret < 0)
858 return ret;
859
860 ret = drm_dp_mst_atomic_check(state);
861 if (ret == 0) {
862 vars[next_index].dsc_enabled = false;
863 vars[next_index].bpp_x16 = 0;
864 } else {
865 vars[next_index].pbn = kbps_to_peak_pbn(params[next_index].bw_range.max_kbps);
866 ret = drm_dp_atomic_find_time_slots(state,
867 params[next_index].port->mgr,
868 params[next_index].port,
869 vars[next_index].pbn);
870 if (ret < 0)
871 return ret;
872 }
873
874 tried[next_index] = true;
875 remaining_to_try--;
876 }
877 return 0;
878 }
879
compute_mst_dsc_configs_for_link(struct drm_atomic_state * state,struct dc_state * dc_state,struct dc_link * dc_link,struct dsc_mst_fairness_vars * vars,struct drm_dp_mst_topology_mgr * mgr,int * link_vars_start_index)880 static int compute_mst_dsc_configs_for_link(struct drm_atomic_state *state,
881 struct dc_state *dc_state,
882 struct dc_link *dc_link,
883 struct dsc_mst_fairness_vars *vars,
884 struct drm_dp_mst_topology_mgr *mgr,
885 int *link_vars_start_index)
886 {
887 struct dc_stream_state *stream;
888 struct dsc_mst_fairness_params params[MAX_PIPES];
889 struct amdgpu_dm_connector *aconnector;
890 struct drm_dp_mst_topology_state *mst_state = drm_atomic_get_mst_topology_state(state, mgr);
891 int count = 0;
892 int i, k, ret;
893 bool debugfs_overwrite = false;
894
895 memset(params, 0, sizeof(params));
896
897 if (IS_ERR(mst_state))
898 return PTR_ERR(mst_state);
899
900 mst_state->pbn_div = dm_mst_get_pbn_divider(dc_link);
901 #if defined(CONFIG_DRM_AMD_DC_DCN)
902 drm_dp_mst_update_slots(mst_state, dc_link_dp_mst_decide_link_encoding_format(dc_link));
903 #endif
904
905 /* Set up params */
906 for (i = 0; i < dc_state->stream_count; i++) {
907 struct dc_dsc_policy dsc_policy = {0};
908
909 stream = dc_state->streams[i];
910
911 if (stream->link != dc_link)
912 continue;
913
914 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
915 if (!aconnector)
916 continue;
917
918 if (!aconnector->port)
919 continue;
920
921 stream->timing.flags.DSC = 0;
922
923 params[count].timing = &stream->timing;
924 params[count].sink = stream->sink;
925 params[count].aconnector = aconnector;
926 params[count].port = aconnector->port;
927 params[count].clock_force_enable = aconnector->dsc_settings.dsc_force_enable;
928 if (params[count].clock_force_enable == DSC_CLK_FORCE_ENABLE)
929 debugfs_overwrite = true;
930 params[count].num_slices_h = aconnector->dsc_settings.dsc_num_slices_h;
931 params[count].num_slices_v = aconnector->dsc_settings.dsc_num_slices_v;
932 params[count].bpp_overwrite = aconnector->dsc_settings.dsc_bits_per_pixel;
933 params[count].compression_possible = stream->sink->dsc_caps.dsc_dec_caps.is_dsc_supported;
934 dc_dsc_get_policy_for_timing(params[count].timing, 0, &dsc_policy);
935 if (!dc_dsc_compute_bandwidth_range(
936 stream->sink->ctx->dc->res_pool->dscs[0],
937 stream->sink->ctx->dc->debug.dsc_min_slice_height_override,
938 dsc_policy.min_target_bpp * 16,
939 dsc_policy.max_target_bpp * 16,
940 &stream->sink->dsc_caps.dsc_dec_caps,
941 &stream->timing, ¶ms[count].bw_range))
942 params[count].bw_range.stream_kbps = dc_bandwidth_in_kbps_from_timing(&stream->timing);
943
944 count++;
945 }
946
947 if (count == 0) {
948 ASSERT(0);
949 return 0;
950 }
951
952 /* k is start index of vars for current phy link used by mst hub */
953 k = *link_vars_start_index;
954 /* set vars start index for next mst hub phy link */
955 *link_vars_start_index += count;
956
957 /* Try no compression */
958 for (i = 0; i < count; i++) {
959 vars[i + k].aconnector = params[i].aconnector;
960 vars[i + k].pbn = kbps_to_peak_pbn(params[i].bw_range.stream_kbps);
961 vars[i + k].dsc_enabled = false;
962 vars[i + k].bpp_x16 = 0;
963 ret = drm_dp_atomic_find_time_slots(state, params[i].port->mgr, params[i].port,
964 vars[i + k].pbn);
965 if (ret < 0)
966 return ret;
967 }
968 ret = drm_dp_mst_atomic_check(state);
969 if (ret == 0 && !debugfs_overwrite) {
970 set_dsc_configs_from_fairness_vars(params, vars, count, k);
971 return 0;
972 } else if (ret != -ENOSPC) {
973 return ret;
974 }
975
976 /* Try max compression */
977 for (i = 0; i < count; i++) {
978 if (params[i].compression_possible && params[i].clock_force_enable != DSC_CLK_FORCE_DISABLE) {
979 vars[i + k].pbn = kbps_to_peak_pbn(params[i].bw_range.min_kbps);
980 vars[i + k].dsc_enabled = true;
981 vars[i + k].bpp_x16 = params[i].bw_range.min_target_bpp_x16;
982 ret = drm_dp_atomic_find_time_slots(state, params[i].port->mgr,
983 params[i].port, vars[i + k].pbn);
984 if (ret < 0)
985 return ret;
986 } else {
987 vars[i + k].pbn = kbps_to_peak_pbn(params[i].bw_range.stream_kbps);
988 vars[i + k].dsc_enabled = false;
989 vars[i + k].bpp_x16 = 0;
990 ret = drm_dp_atomic_find_time_slots(state, params[i].port->mgr,
991 params[i].port, vars[i + k].pbn);
992 if (ret < 0)
993 return ret;
994 }
995 }
996 ret = drm_dp_mst_atomic_check(state);
997 if (ret != 0)
998 return ret;
999
1000 /* Optimize degree of compression */
1001 ret = increase_dsc_bpp(state, mst_state, dc_link, params, vars, count, k);
1002 if (ret < 0)
1003 return ret;
1004
1005 ret = try_disable_dsc(state, dc_link, params, vars, count, k);
1006 if (ret < 0)
1007 return ret;
1008
1009 set_dsc_configs_from_fairness_vars(params, vars, count, k);
1010
1011 return 0;
1012 }
1013
is_dsc_need_re_compute(struct drm_atomic_state * state,struct dc_state * dc_state,struct dc_link * dc_link)1014 static bool is_dsc_need_re_compute(
1015 struct drm_atomic_state *state,
1016 struct dc_state *dc_state,
1017 struct dc_link *dc_link)
1018 {
1019 int i, j;
1020 bool is_dsc_need_re_compute = false;
1021 struct amdgpu_dm_connector *stream_on_link[MAX_PIPES];
1022 int new_stream_on_link_num = 0;
1023 struct amdgpu_dm_connector *aconnector;
1024 struct dc_stream_state *stream;
1025 const struct dc *dc = dc_link->dc;
1026
1027 /* only check phy used by dsc mst branch */
1028 if (dc_link->type != dc_connection_mst_branch)
1029 return false;
1030
1031 if (!(dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_SUPPORT ||
1032 dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_PASSTHROUGH_SUPPORT))
1033 return false;
1034
1035 for (i = 0; i < MAX_PIPES; i++)
1036 stream_on_link[i] = NULL;
1037
1038 /* check if there is mode change in new request */
1039 for (i = 0; i < dc_state->stream_count; i++) {
1040 struct drm_crtc_state *new_crtc_state;
1041 struct drm_connector_state *new_conn_state;
1042
1043 stream = dc_state->streams[i];
1044 if (!stream)
1045 continue;
1046
1047 /* check if stream using the same link for mst */
1048 if (stream->link != dc_link)
1049 continue;
1050
1051 aconnector = (struct amdgpu_dm_connector *) stream->dm_stream_context;
1052 if (!aconnector)
1053 continue;
1054
1055 stream_on_link[new_stream_on_link_num] = aconnector;
1056 new_stream_on_link_num++;
1057
1058 new_conn_state = drm_atomic_get_new_connector_state(state, &aconnector->base);
1059 if (!new_conn_state)
1060 continue;
1061
1062 if (IS_ERR(new_conn_state))
1063 continue;
1064
1065 if (!new_conn_state->crtc)
1066 continue;
1067
1068 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_conn_state->crtc);
1069 if (!new_crtc_state)
1070 continue;
1071
1072 if (IS_ERR(new_crtc_state))
1073 continue;
1074
1075 if (new_crtc_state->enable && new_crtc_state->active) {
1076 if (new_crtc_state->mode_changed || new_crtc_state->active_changed ||
1077 new_crtc_state->connectors_changed)
1078 return true;
1079 }
1080 }
1081
1082 /* check current_state if there stream on link but it is not in
1083 * new request state
1084 */
1085 for (i = 0; i < dc->current_state->stream_count; i++) {
1086 stream = dc->current_state->streams[i];
1087 /* only check stream on the mst hub */
1088 if (stream->link != dc_link)
1089 continue;
1090
1091 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
1092 if (!aconnector)
1093 continue;
1094
1095 for (j = 0; j < new_stream_on_link_num; j++) {
1096 if (stream_on_link[j]) {
1097 if (aconnector == stream_on_link[j])
1098 break;
1099 }
1100 }
1101
1102 if (j == new_stream_on_link_num) {
1103 /* not in new state */
1104 is_dsc_need_re_compute = true;
1105 break;
1106 }
1107 }
1108
1109 return is_dsc_need_re_compute;
1110 }
1111
compute_mst_dsc_configs_for_state(struct drm_atomic_state * state,struct dc_state * dc_state,struct dsc_mst_fairness_vars * vars)1112 int compute_mst_dsc_configs_for_state(struct drm_atomic_state *state,
1113 struct dc_state *dc_state,
1114 struct dsc_mst_fairness_vars *vars)
1115 {
1116 int i, j;
1117 struct dc_stream_state *stream;
1118 bool computed_streams[MAX_PIPES];
1119 struct amdgpu_dm_connector *aconnector;
1120 struct drm_dp_mst_topology_mgr *mst_mgr;
1121 int link_vars_start_index = 0;
1122 int ret = 0;
1123
1124 for (i = 0; i < dc_state->stream_count; i++)
1125 computed_streams[i] = false;
1126
1127 for (i = 0; i < dc_state->stream_count; i++) {
1128 stream = dc_state->streams[i];
1129
1130 if (stream->signal != SIGNAL_TYPE_DISPLAY_PORT_MST)
1131 continue;
1132
1133 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
1134
1135 if (!aconnector || !aconnector->dc_sink || !aconnector->port)
1136 continue;
1137
1138 if (!aconnector->dc_sink->dsc_caps.dsc_dec_caps.is_dsc_supported)
1139 continue;
1140
1141 if (computed_streams[i])
1142 continue;
1143
1144 if (dcn20_remove_stream_from_ctx(stream->ctx->dc, dc_state, stream) != DC_OK)
1145 return -EINVAL;
1146
1147 if (!is_dsc_need_re_compute(state, dc_state, stream->link))
1148 continue;
1149
1150 mst_mgr = aconnector->port->mgr;
1151 ret = compute_mst_dsc_configs_for_link(state, dc_state, stream->link, vars, mst_mgr,
1152 &link_vars_start_index);
1153 if (ret != 0)
1154 return ret;
1155
1156 for (j = 0; j < dc_state->stream_count; j++) {
1157 if (dc_state->streams[j]->link == stream->link)
1158 computed_streams[j] = true;
1159 }
1160 }
1161
1162 for (i = 0; i < dc_state->stream_count; i++) {
1163 stream = dc_state->streams[i];
1164
1165 if (stream->timing.flags.DSC == 1)
1166 if (dc_stream_add_dsc_to_resource(stream->ctx->dc, dc_state, stream) != DC_OK)
1167 return -EINVAL;
1168 }
1169
1170 return ret;
1171 }
1172
pre_compute_mst_dsc_configs_for_state(struct drm_atomic_state * state,struct dc_state * dc_state,struct dsc_mst_fairness_vars * vars)1173 static int pre_compute_mst_dsc_configs_for_state(struct drm_atomic_state *state,
1174 struct dc_state *dc_state,
1175 struct dsc_mst_fairness_vars *vars)
1176 {
1177 int i, j;
1178 struct dc_stream_state *stream;
1179 bool computed_streams[MAX_PIPES];
1180 struct amdgpu_dm_connector *aconnector;
1181 struct drm_dp_mst_topology_mgr *mst_mgr;
1182 int link_vars_start_index = 0;
1183 int ret = 0;
1184
1185 for (i = 0; i < dc_state->stream_count; i++)
1186 computed_streams[i] = false;
1187
1188 for (i = 0; i < dc_state->stream_count; i++) {
1189 stream = dc_state->streams[i];
1190
1191 if (stream->signal != SIGNAL_TYPE_DISPLAY_PORT_MST)
1192 continue;
1193
1194 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
1195
1196 if (!aconnector || !aconnector->dc_sink || !aconnector->port)
1197 continue;
1198
1199 if (!aconnector->dc_sink->dsc_caps.dsc_dec_caps.is_dsc_supported)
1200 continue;
1201
1202 if (computed_streams[i])
1203 continue;
1204
1205 if (!is_dsc_need_re_compute(state, dc_state, stream->link))
1206 continue;
1207
1208 mst_mgr = aconnector->port->mgr;
1209 ret = compute_mst_dsc_configs_for_link(state, dc_state, stream->link, vars, mst_mgr,
1210 &link_vars_start_index);
1211 if (ret != 0)
1212 return ret;
1213
1214 for (j = 0; j < dc_state->stream_count; j++) {
1215 if (dc_state->streams[j]->link == stream->link)
1216 computed_streams[j] = true;
1217 }
1218 }
1219
1220 return ret;
1221 }
1222
find_crtc_index_in_state_by_stream(struct drm_atomic_state * state,struct dc_stream_state * stream)1223 static int find_crtc_index_in_state_by_stream(struct drm_atomic_state *state,
1224 struct dc_stream_state *stream)
1225 {
1226 int i;
1227 struct drm_crtc *crtc;
1228 struct drm_crtc_state *new_state, *old_state;
1229
1230 for_each_oldnew_crtc_in_state(state, crtc, old_state, new_state, i) {
1231 struct dm_crtc_state *dm_state = to_dm_crtc_state(new_state);
1232
1233 if (dm_state->stream == stream)
1234 return i;
1235 }
1236 return -1;
1237 }
1238
is_link_to_dschub(struct dc_link * dc_link)1239 static bool is_link_to_dschub(struct dc_link *dc_link)
1240 {
1241 union dpcd_dsc_basic_capabilities *dsc_caps =
1242 &dc_link->dpcd_caps.dsc_caps.dsc_basic_caps;
1243
1244 /* only check phy used by dsc mst branch */
1245 if (dc_link->type != dc_connection_mst_branch)
1246 return false;
1247
1248 if (!(dsc_caps->fields.dsc_support.DSC_SUPPORT ||
1249 dsc_caps->fields.dsc_support.DSC_PASSTHROUGH_SUPPORT))
1250 return false;
1251 return true;
1252 }
1253
is_dsc_precompute_needed(struct drm_atomic_state * state)1254 static bool is_dsc_precompute_needed(struct drm_atomic_state *state)
1255 {
1256 int i;
1257 struct drm_crtc *crtc;
1258 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
1259 bool ret = false;
1260
1261 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
1262 struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(new_crtc_state);
1263
1264 if (!amdgpu_dm_find_first_crtc_matching_connector(state, crtc)) {
1265 ret = false;
1266 break;
1267 }
1268 if (dm_crtc_state->stream && dm_crtc_state->stream->link)
1269 if (is_link_to_dschub(dm_crtc_state->stream->link))
1270 ret = true;
1271 }
1272 return ret;
1273 }
1274
pre_validate_dsc(struct drm_atomic_state * state,struct dm_atomic_state ** dm_state_ptr,struct dsc_mst_fairness_vars * vars)1275 int pre_validate_dsc(struct drm_atomic_state *state,
1276 struct dm_atomic_state **dm_state_ptr,
1277 struct dsc_mst_fairness_vars *vars)
1278 {
1279 int i;
1280 struct dm_atomic_state *dm_state;
1281 struct dc_state *local_dc_state = NULL;
1282 int ret = 0;
1283
1284 if (!is_dsc_precompute_needed(state)) {
1285 DRM_INFO_ONCE("DSC precompute is not needed.\n");
1286 return 0;
1287 }
1288 ret = dm_atomic_get_state(state, dm_state_ptr);
1289 if (ret != 0) {
1290 DRM_INFO_ONCE("dm_atomic_get_state() failed\n");
1291 return ret;
1292 }
1293 dm_state = *dm_state_ptr;
1294
1295 /*
1296 * create local vailable for dc_state. copy content of streams of dm_state->context
1297 * to local variable. make sure stream pointer of local variable not the same as stream
1298 * from dm_state->context.
1299 */
1300
1301 local_dc_state = kmemdup(dm_state->context, sizeof(struct dc_state), GFP_KERNEL);
1302 if (!local_dc_state)
1303 return -ENOMEM;
1304
1305 for (i = 0; i < local_dc_state->stream_count; i++) {
1306 struct dc_stream_state *stream = dm_state->context->streams[i];
1307 int ind = find_crtc_index_in_state_by_stream(state, stream);
1308
1309 if (ind >= 0) {
1310 struct amdgpu_dm_connector *aconnector;
1311 struct drm_connector_state *drm_new_conn_state;
1312 struct dm_connector_state *dm_new_conn_state;
1313 struct dm_crtc_state *dm_old_crtc_state;
1314
1315 aconnector =
1316 amdgpu_dm_find_first_crtc_matching_connector(state,
1317 state->crtcs[ind].ptr);
1318 drm_new_conn_state =
1319 drm_atomic_get_new_connector_state(state,
1320 &aconnector->base);
1321 dm_new_conn_state = to_dm_connector_state(drm_new_conn_state);
1322 dm_old_crtc_state = to_dm_crtc_state(state->crtcs[ind].old_state);
1323
1324 local_dc_state->streams[i] =
1325 create_validate_stream_for_sink(aconnector,
1326 &state->crtcs[ind].new_state->mode,
1327 dm_new_conn_state,
1328 dm_old_crtc_state->stream);
1329 if (local_dc_state->streams[i] == NULL) {
1330 ret = -EINVAL;
1331 break;
1332 }
1333 }
1334 }
1335
1336 if (ret != 0)
1337 goto clean_exit;
1338
1339 ret = pre_compute_mst_dsc_configs_for_state(state, local_dc_state, vars);
1340 if (ret != 0) {
1341 DRM_INFO_ONCE("pre_compute_mst_dsc_configs_for_state() failed\n");
1342 goto clean_exit;
1343 }
1344
1345 /*
1346 * compare local_streams -> timing with dm_state->context,
1347 * if the same set crtc_state->mode-change = 0;
1348 */
1349 for (i = 0; i < local_dc_state->stream_count; i++) {
1350 struct dc_stream_state *stream = dm_state->context->streams[i];
1351
1352 if (local_dc_state->streams[i] &&
1353 is_timing_changed(stream, local_dc_state->streams[i])) {
1354 DRM_INFO_ONCE("crtc[%d] needs mode_changed\n", i);
1355 } else {
1356 int ind = find_crtc_index_in_state_by_stream(state, stream);
1357
1358 if (ind >= 0)
1359 state->crtcs[ind].new_state->mode_changed = 0;
1360 }
1361 }
1362 clean_exit:
1363 for (i = 0; i < local_dc_state->stream_count; i++) {
1364 struct dc_stream_state *stream = dm_state->context->streams[i];
1365
1366 if (local_dc_state->streams[i] != stream)
1367 dc_stream_release(local_dc_state->streams[i]);
1368 }
1369
1370 kfree(local_dc_state);
1371
1372 return ret;
1373 }
1374
kbps_from_pbn(unsigned int pbn)1375 static unsigned int kbps_from_pbn(unsigned int pbn)
1376 {
1377 unsigned int kbps = pbn;
1378
1379 kbps *= (1000000 / PEAK_FACTOR_X1000);
1380 kbps *= 8;
1381 kbps *= 54;
1382 kbps /= 64;
1383
1384 return kbps;
1385 }
1386
is_dsc_common_config_possible(struct dc_stream_state * stream,struct dc_dsc_bw_range * bw_range)1387 static bool is_dsc_common_config_possible(struct dc_stream_state *stream,
1388 struct dc_dsc_bw_range *bw_range)
1389 {
1390 struct dc_dsc_policy dsc_policy = {0};
1391
1392 dc_dsc_get_policy_for_timing(&stream->timing, 0, &dsc_policy);
1393 dc_dsc_compute_bandwidth_range(stream->sink->ctx->dc->res_pool->dscs[0],
1394 stream->sink->ctx->dc->debug.dsc_min_slice_height_override,
1395 dsc_policy.min_target_bpp * 16,
1396 dsc_policy.max_target_bpp * 16,
1397 &stream->sink->dsc_caps.dsc_dec_caps,
1398 &stream->timing, bw_range);
1399
1400 return bw_range->max_target_bpp_x16 && bw_range->min_target_bpp_x16;
1401 }
1402 #endif /* CONFIG_DRM_AMD_DC_DCN */
1403
dm_dp_mst_is_port_support_mode(struct amdgpu_dm_connector * aconnector,struct dc_stream_state * stream)1404 enum dc_status dm_dp_mst_is_port_support_mode(
1405 struct amdgpu_dm_connector *aconnector,
1406 struct dc_stream_state *stream)
1407 {
1408 int bpp, pbn, branch_max_throughput_mps = 0;
1409 #if defined(CONFIG_DRM_AMD_DC_DCN)
1410 struct dc_link_settings cur_link_settings;
1411 unsigned int end_to_end_bw_in_kbps = 0;
1412 unsigned int upper_link_bw_in_kbps = 0, down_link_bw_in_kbps = 0;
1413 unsigned int max_compressed_bw_in_kbps = 0;
1414 struct dc_dsc_bw_range bw_range = {0};
1415 struct drm_dp_mst_topology_mgr *mst_mgr;
1416
1417 /*
1418 * check if the mode could be supported if DSC pass-through is supported
1419 * AND check if there enough bandwidth available to support the mode
1420 * with DSC enabled.
1421 */
1422 if (is_dsc_common_config_possible(stream, &bw_range) &&
1423 aconnector->port->passthrough_aux) {
1424 mst_mgr = aconnector->port->mgr;
1425 mutex_lock(&mst_mgr->lock);
1426
1427 cur_link_settings = stream->link->verified_link_cap;
1428
1429 upper_link_bw_in_kbps = dc_link_bandwidth_kbps(aconnector->dc_link,
1430 &cur_link_settings
1431 );
1432 down_link_bw_in_kbps = kbps_from_pbn(aconnector->port->full_pbn);
1433
1434 /* pick the bottleneck */
1435 end_to_end_bw_in_kbps = min(upper_link_bw_in_kbps,
1436 down_link_bw_in_kbps);
1437
1438 mutex_unlock(&mst_mgr->lock);
1439
1440 /*
1441 * use the maximum dsc compression bandwidth as the required
1442 * bandwidth for the mode
1443 */
1444 max_compressed_bw_in_kbps = bw_range.min_kbps;
1445
1446 if (end_to_end_bw_in_kbps < max_compressed_bw_in_kbps) {
1447 DRM_DEBUG_DRIVER("Mode does not fit into DSC pass-through bandwidth validation\n");
1448 return DC_FAIL_BANDWIDTH_VALIDATE;
1449 }
1450 } else {
1451 #endif
1452 /* check if mode could be supported within full_pbn */
1453 bpp = convert_dc_color_depth_into_bpc(stream->timing.display_color_depth) * 3;
1454 pbn = drm_dp_calc_pbn_mode(stream->timing.pix_clk_100hz / 10, bpp, false);
1455
1456 if (pbn > aconnector->port->full_pbn)
1457 return DC_FAIL_BANDWIDTH_VALIDATE;
1458 #if defined(CONFIG_DRM_AMD_DC_DCN)
1459 }
1460 #endif
1461
1462 /* check is mst dsc output bandwidth branch_overall_throughput_0_mps */
1463 switch (stream->timing.pixel_encoding) {
1464 case PIXEL_ENCODING_RGB:
1465 case PIXEL_ENCODING_YCBCR444:
1466 branch_max_throughput_mps =
1467 aconnector->dc_sink->dsc_caps.dsc_dec_caps.branch_overall_throughput_0_mps;
1468 break;
1469 case PIXEL_ENCODING_YCBCR422:
1470 case PIXEL_ENCODING_YCBCR420:
1471 branch_max_throughput_mps =
1472 aconnector->dc_sink->dsc_caps.dsc_dec_caps.branch_overall_throughput_1_mps;
1473 break;
1474 default:
1475 break;
1476 }
1477
1478 if (branch_max_throughput_mps != 0 &&
1479 ((stream->timing.pix_clk_100hz / 10) > branch_max_throughput_mps * 1000))
1480 return DC_FAIL_BANDWIDTH_VALIDATE;
1481
1482 return DC_OK;
1483 }
1484
