1 /*
2 * Copyright (c) 2014, The Linux Foundation. All rights reserved.
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14 #include <linux/kernel.h>
15 #include <linux/bitops.h>
16 #include <linux/regmap.h>
17 #include <linux/export.h>
18
19 #include "clk-regmap-divider.h"
20
to_clk_regmap_div(struct clk_hw * hw)21 static inline struct clk_regmap_div *to_clk_regmap_div(struct clk_hw *hw)
22 {
23 return container_of(to_clk_regmap(hw), struct clk_regmap_div, clkr);
24 }
25
div_round_ro_rate(struct clk_hw * hw,unsigned long rate,unsigned long * prate)26 static long div_round_ro_rate(struct clk_hw *hw, unsigned long rate,
27 unsigned long *prate)
28 {
29 struct clk_regmap_div *divider = to_clk_regmap_div(hw);
30 struct clk_regmap *clkr = ÷r->clkr;
31 u32 val;
32
33 regmap_read(clkr->regmap, divider->reg, &val);
34 val >>= divider->shift;
35 val &= BIT(divider->width) - 1;
36
37 return divider_ro_round_rate(hw, rate, prate, NULL, divider->width,
38 CLK_DIVIDER_ROUND_CLOSEST, val);
39 }
40
div_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * prate)41 static long div_round_rate(struct clk_hw *hw, unsigned long rate,
42 unsigned long *prate)
43 {
44 struct clk_regmap_div *divider = to_clk_regmap_div(hw);
45
46 return divider_round_rate(hw, rate, prate, NULL, divider->width,
47 CLK_DIVIDER_ROUND_CLOSEST);
48 }
49
div_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)50 static int div_set_rate(struct clk_hw *hw, unsigned long rate,
51 unsigned long parent_rate)
52 {
53 struct clk_regmap_div *divider = to_clk_regmap_div(hw);
54 struct clk_regmap *clkr = ÷r->clkr;
55 u32 div;
56
57 div = divider_get_val(rate, parent_rate, NULL, divider->width,
58 CLK_DIVIDER_ROUND_CLOSEST);
59
60 return regmap_update_bits(clkr->regmap, divider->reg,
61 (BIT(divider->width) - 1) << divider->shift,
62 div << divider->shift);
63 }
64
div_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)65 static unsigned long div_recalc_rate(struct clk_hw *hw,
66 unsigned long parent_rate)
67 {
68 struct clk_regmap_div *divider = to_clk_regmap_div(hw);
69 struct clk_regmap *clkr = ÷r->clkr;
70 u32 div;
71
72 regmap_read(clkr->regmap, divider->reg, &div);
73 div >>= divider->shift;
74 div &= BIT(divider->width) - 1;
75
76 return divider_recalc_rate(hw, parent_rate, div, NULL,
77 CLK_DIVIDER_ROUND_CLOSEST, divider->width);
78 }
79
80 const struct clk_ops clk_regmap_div_ops = {
81 .round_rate = div_round_rate,
82 .set_rate = div_set_rate,
83 .recalc_rate = div_recalc_rate,
84 };
85 EXPORT_SYMBOL_GPL(clk_regmap_div_ops);
86
87 const struct clk_ops clk_regmap_div_ro_ops = {
88 .round_rate = div_round_ro_rate,
89 .recalc_rate = div_recalc_rate,
90 };
91 EXPORT_SYMBOL_GPL(clk_regmap_div_ro_ops);
92
