1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * core.c - ChipIdea USB IP core family device controller
4 *
5 * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
6 *
7 * Author: David Lopo
8 */
9
10 /*
11 * Description: ChipIdea USB IP core family device controller
12 *
13 * This driver is composed of several blocks:
14 * - HW: hardware interface
15 * - DBG: debug facilities (optional)
16 * - UTIL: utilities
17 * - ISR: interrupts handling
18 * - ENDPT: endpoint operations (Gadget API)
19 * - GADGET: gadget operations (Gadget API)
20 * - BUS: bus glue code, bus abstraction layer
21 *
22 * Compile Options
23 * - STALL_IN: non-empty bulk-in pipes cannot be halted
24 * if defined mass storage compliance succeeds but with warnings
25 * => case 4: Hi > Dn
26 * => case 5: Hi > Di
27 * => case 8: Hi <> Do
28 * if undefined usbtest 13 fails
29 * - TRACE: enable function tracing (depends on DEBUG)
30 *
31 * Main Features
32 * - Chapter 9 & Mass Storage Compliance with Gadget File Storage
33 * - Chapter 9 Compliance with Gadget Zero (STALL_IN undefined)
34 * - Normal & LPM support
35 *
36 * USBTEST Report
37 * - OK: 0-12, 13 (STALL_IN defined) & 14
38 * - Not Supported: 15 & 16 (ISO)
39 *
40 * TODO List
41 * - Suspend & Remote Wakeup
42 */
43 #include <linux/delay.h>
44 #include <linux/device.h>
45 #include <linux/dma-mapping.h>
46 #include <linux/extcon.h>
47 #include <linux/phy/phy.h>
48 #include <linux/platform_device.h>
49 #include <linux/module.h>
50 #include <linux/idr.h>
51 #include <linux/interrupt.h>
52 #include <linux/io.h>
53 #include <linux/kernel.h>
54 #include <linux/slab.h>
55 #include <linux/pm_runtime.h>
56 #include <linux/pinctrl/consumer.h>
57 #include <linux/usb/ch9.h>
58 #include <linux/usb/gadget.h>
59 #include <linux/usb/otg.h>
60 #include <linux/usb/chipidea.h>
61 #include <linux/usb/of.h>
62 #include <linux/of.h>
63 #include <linux/regulator/consumer.h>
64 #include <linux/usb/ehci_def.h>
65
66 #include "ci.h"
67 #include "udc.h"
68 #include "bits.h"
69 #include "host.h"
70 #include "otg.h"
71 #include "otg_fsm.h"
72
73 /* Controller register map */
74 static const u8 ci_regs_nolpm[] = {
75 [CAP_CAPLENGTH] = 0x00U,
76 [CAP_HCCPARAMS] = 0x08U,
77 [CAP_DCCPARAMS] = 0x24U,
78 [CAP_TESTMODE] = 0x38U,
79 [OP_USBCMD] = 0x00U,
80 [OP_USBSTS] = 0x04U,
81 [OP_USBINTR] = 0x08U,
82 [OP_DEVICEADDR] = 0x14U,
83 [OP_ENDPTLISTADDR] = 0x18U,
84 [OP_TTCTRL] = 0x1CU,
85 [OP_BURSTSIZE] = 0x20U,
86 [OP_ULPI_VIEWPORT] = 0x30U,
87 [OP_PORTSC] = 0x44U,
88 [OP_DEVLC] = 0x84U,
89 [OP_OTGSC] = 0x64U,
90 [OP_USBMODE] = 0x68U,
91 [OP_ENDPTSETUPSTAT] = 0x6CU,
92 [OP_ENDPTPRIME] = 0x70U,
93 [OP_ENDPTFLUSH] = 0x74U,
94 [OP_ENDPTSTAT] = 0x78U,
95 [OP_ENDPTCOMPLETE] = 0x7CU,
96 [OP_ENDPTCTRL] = 0x80U,
97 };
98
99 static const u8 ci_regs_lpm[] = {
100 [CAP_CAPLENGTH] = 0x00U,
101 [CAP_HCCPARAMS] = 0x08U,
102 [CAP_DCCPARAMS] = 0x24U,
103 [CAP_TESTMODE] = 0xFCU,
104 [OP_USBCMD] = 0x00U,
105 [OP_USBSTS] = 0x04U,
106 [OP_USBINTR] = 0x08U,
107 [OP_DEVICEADDR] = 0x14U,
108 [OP_ENDPTLISTADDR] = 0x18U,
109 [OP_TTCTRL] = 0x1CU,
110 [OP_BURSTSIZE] = 0x20U,
111 [OP_ULPI_VIEWPORT] = 0x30U,
112 [OP_PORTSC] = 0x44U,
113 [OP_DEVLC] = 0x84U,
114 [OP_OTGSC] = 0xC4U,
115 [OP_USBMODE] = 0xC8U,
116 [OP_ENDPTSETUPSTAT] = 0xD8U,
117 [OP_ENDPTPRIME] = 0xDCU,
118 [OP_ENDPTFLUSH] = 0xE0U,
119 [OP_ENDPTSTAT] = 0xE4U,
120 [OP_ENDPTCOMPLETE] = 0xE8U,
121 [OP_ENDPTCTRL] = 0xECU,
122 };
123
hw_alloc_regmap(struct ci_hdrc * ci,bool is_lpm)124 static void hw_alloc_regmap(struct ci_hdrc *ci, bool is_lpm)
125 {
126 int i;
127
128 for (i = 0; i < OP_ENDPTCTRL; i++)
129 ci->hw_bank.regmap[i] =
130 (i <= CAP_LAST ? ci->hw_bank.cap : ci->hw_bank.op) +
131 (is_lpm ? ci_regs_lpm[i] : ci_regs_nolpm[i]);
132
133 for (; i <= OP_LAST; i++)
134 ci->hw_bank.regmap[i] = ci->hw_bank.op +
135 4 * (i - OP_ENDPTCTRL) +
136 (is_lpm
137 ? ci_regs_lpm[OP_ENDPTCTRL]
138 : ci_regs_nolpm[OP_ENDPTCTRL]);
139
140 }
141
ci_get_revision(struct ci_hdrc * ci)142 static enum ci_revision ci_get_revision(struct ci_hdrc *ci)
143 {
144 int ver = hw_read_id_reg(ci, ID_ID, VERSION) >> __ffs(VERSION);
145 enum ci_revision rev = CI_REVISION_UNKNOWN;
146
147 if (ver == 0x2) {
148 rev = hw_read_id_reg(ci, ID_ID, REVISION)
149 >> __ffs(REVISION);
150 rev += CI_REVISION_20;
151 } else if (ver == 0x0) {
152 rev = CI_REVISION_1X;
153 }
154
155 return rev;
156 }
157
158 /**
159 * hw_read_intr_enable: returns interrupt enable register
160 *
161 * @ci: the controller
162 *
163 * This function returns register data
164 */
hw_read_intr_enable(struct ci_hdrc * ci)165 u32 hw_read_intr_enable(struct ci_hdrc *ci)
166 {
167 return hw_read(ci, OP_USBINTR, ~0);
168 }
169
170 /**
171 * hw_read_intr_status: returns interrupt status register
172 *
173 * @ci: the controller
174 *
175 * This function returns register data
176 */
hw_read_intr_status(struct ci_hdrc * ci)177 u32 hw_read_intr_status(struct ci_hdrc *ci)
178 {
179 return hw_read(ci, OP_USBSTS, ~0);
180 }
181
182 /**
183 * hw_port_test_set: writes port test mode (execute without interruption)
184 * @mode: new value
185 *
186 * This function returns an error code
187 */
hw_port_test_set(struct ci_hdrc * ci,u8 mode)188 int hw_port_test_set(struct ci_hdrc *ci, u8 mode)
189 {
190 const u8 TEST_MODE_MAX = 7;
191
192 if (mode > TEST_MODE_MAX)
193 return -EINVAL;
194
195 hw_write(ci, OP_PORTSC, PORTSC_PTC, mode << __ffs(PORTSC_PTC));
196 return 0;
197 }
198
199 /**
200 * hw_port_test_get: reads port test mode value
201 *
202 * @ci: the controller
203 *
204 * This function returns port test mode value
205 */
hw_port_test_get(struct ci_hdrc * ci)206 u8 hw_port_test_get(struct ci_hdrc *ci)
207 {
208 return hw_read(ci, OP_PORTSC, PORTSC_PTC) >> __ffs(PORTSC_PTC);
209 }
210
hw_wait_phy_stable(void)211 static void hw_wait_phy_stable(void)
212 {
213 /*
214 * The phy needs some delay to output the stable status from low
215 * power mode. And for OTGSC, the status inputs are debounced
216 * using a 1 ms time constant, so, delay 2ms for controller to get
217 * the stable status, like vbus and id when the phy leaves low power.
218 */
219 usleep_range(2000, 2500);
220 }
221
222 /* The PHY enters/leaves low power mode */
ci_hdrc_enter_lpm(struct ci_hdrc * ci,bool enable)223 static void ci_hdrc_enter_lpm(struct ci_hdrc *ci, bool enable)
224 {
225 enum ci_hw_regs reg = ci->hw_bank.lpm ? OP_DEVLC : OP_PORTSC;
226 bool lpm = !!(hw_read(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm)));
227
228 if (enable && !lpm)
229 hw_write(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm),
230 PORTSC_PHCD(ci->hw_bank.lpm));
231 else if (!enable && lpm)
232 hw_write(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm),
233 0);
234 }
235
hw_device_init(struct ci_hdrc * ci,void __iomem * base)236 static int hw_device_init(struct ci_hdrc *ci, void __iomem *base)
237 {
238 u32 reg;
239
240 /* bank is a module variable */
241 ci->hw_bank.abs = base;
242
243 ci->hw_bank.cap = ci->hw_bank.abs;
244 ci->hw_bank.cap += ci->platdata->capoffset;
245 ci->hw_bank.op = ci->hw_bank.cap + (ioread32(ci->hw_bank.cap) & 0xff);
246
247 hw_alloc_regmap(ci, false);
248 reg = hw_read(ci, CAP_HCCPARAMS, HCCPARAMS_LEN) >>
249 __ffs(HCCPARAMS_LEN);
250 ci->hw_bank.lpm = reg;
251 if (reg)
252 hw_alloc_regmap(ci, !!reg);
253 ci->hw_bank.size = ci->hw_bank.op - ci->hw_bank.abs;
254 ci->hw_bank.size += OP_LAST;
255 ci->hw_bank.size /= sizeof(u32);
256
257 reg = hw_read(ci, CAP_DCCPARAMS, DCCPARAMS_DEN) >>
258 __ffs(DCCPARAMS_DEN);
259 ci->hw_ep_max = reg * 2; /* cache hw ENDPT_MAX */
260
261 if (ci->hw_ep_max > ENDPT_MAX)
262 return -ENODEV;
263
264 ci_hdrc_enter_lpm(ci, false);
265
266 /* Disable all interrupts bits */
267 hw_write(ci, OP_USBINTR, 0xffffffff, 0);
268
269 /* Clear all interrupts status bits*/
270 hw_write(ci, OP_USBSTS, 0xffffffff, 0xffffffff);
271
272 ci->rev = ci_get_revision(ci);
273
274 dev_dbg(ci->dev,
275 "ChipIdea HDRC found, revision: %d, lpm: %d; cap: %p op: %p\n",
276 ci->rev, ci->hw_bank.lpm, ci->hw_bank.cap, ci->hw_bank.op);
277
278 /* setup lock mode ? */
279
280 /* ENDPTSETUPSTAT is '0' by default */
281
282 /* HCSPARAMS.bf.ppc SHOULD BE zero for device */
283
284 return 0;
285 }
286
hw_phymode_configure(struct ci_hdrc * ci)287 void hw_phymode_configure(struct ci_hdrc *ci)
288 {
289 u32 portsc, lpm, sts = 0;
290
291 switch (ci->platdata->phy_mode) {
292 case USBPHY_INTERFACE_MODE_UTMI:
293 portsc = PORTSC_PTS(PTS_UTMI);
294 lpm = DEVLC_PTS(PTS_UTMI);
295 break;
296 case USBPHY_INTERFACE_MODE_UTMIW:
297 portsc = PORTSC_PTS(PTS_UTMI) | PORTSC_PTW;
298 lpm = DEVLC_PTS(PTS_UTMI) | DEVLC_PTW;
299 break;
300 case USBPHY_INTERFACE_MODE_ULPI:
301 portsc = PORTSC_PTS(PTS_ULPI);
302 lpm = DEVLC_PTS(PTS_ULPI);
303 break;
304 case USBPHY_INTERFACE_MODE_SERIAL:
305 portsc = PORTSC_PTS(PTS_SERIAL);
306 lpm = DEVLC_PTS(PTS_SERIAL);
307 sts = 1;
308 break;
309 case USBPHY_INTERFACE_MODE_HSIC:
310 portsc = PORTSC_PTS(PTS_HSIC);
311 lpm = DEVLC_PTS(PTS_HSIC);
312 break;
313 default:
314 return;
315 }
316
317 if (ci->hw_bank.lpm) {
318 hw_write(ci, OP_DEVLC, DEVLC_PTS(7) | DEVLC_PTW, lpm);
319 if (sts)
320 hw_write(ci, OP_DEVLC, DEVLC_STS, DEVLC_STS);
321 } else {
322 hw_write(ci, OP_PORTSC, PORTSC_PTS(7) | PORTSC_PTW, portsc);
323 if (sts)
324 hw_write(ci, OP_PORTSC, PORTSC_STS, PORTSC_STS);
325 }
326 }
327 EXPORT_SYMBOL_GPL(hw_phymode_configure);
328
329 /**
330 * _ci_usb_phy_init: initialize phy taking in account both phy and usb_phy
331 * interfaces
332 * @ci: the controller
333 *
334 * This function returns an error code if the phy failed to init
335 */
_ci_usb_phy_init(struct ci_hdrc * ci)336 static int _ci_usb_phy_init(struct ci_hdrc *ci)
337 {
338 int ret;
339
340 if (ci->phy) {
341 ret = phy_init(ci->phy);
342 if (ret)
343 return ret;
344
345 ret = phy_power_on(ci->phy);
346 if (ret) {
347 phy_exit(ci->phy);
348 return ret;
349 }
350 } else {
351 ret = usb_phy_init(ci->usb_phy);
352 }
353
354 return ret;
355 }
356
357 /**
358 * _ci_usb_phy_exit: deinitialize phy taking in account both phy and usb_phy
359 * interfaces
360 * @ci: the controller
361 */
ci_usb_phy_exit(struct ci_hdrc * ci)362 static void ci_usb_phy_exit(struct ci_hdrc *ci)
363 {
364 if (ci->platdata->flags & CI_HDRC_OVERRIDE_PHY_CONTROL)
365 return;
366
367 if (ci->phy) {
368 phy_power_off(ci->phy);
369 phy_exit(ci->phy);
370 } else {
371 usb_phy_shutdown(ci->usb_phy);
372 }
373 }
374
375 /**
376 * ci_usb_phy_init: initialize phy according to different phy type
377 * @ci: the controller
378 *
379 * This function returns an error code if usb_phy_init has failed
380 */
ci_usb_phy_init(struct ci_hdrc * ci)381 static int ci_usb_phy_init(struct ci_hdrc *ci)
382 {
383 int ret;
384
385 if (ci->platdata->flags & CI_HDRC_OVERRIDE_PHY_CONTROL)
386 return 0;
387
388 switch (ci->platdata->phy_mode) {
389 case USBPHY_INTERFACE_MODE_UTMI:
390 case USBPHY_INTERFACE_MODE_UTMIW:
391 case USBPHY_INTERFACE_MODE_HSIC:
392 ret = _ci_usb_phy_init(ci);
393 if (!ret)
394 hw_wait_phy_stable();
395 else
396 return ret;
397 hw_phymode_configure(ci);
398 break;
399 case USBPHY_INTERFACE_MODE_ULPI:
400 case USBPHY_INTERFACE_MODE_SERIAL:
401 hw_phymode_configure(ci);
402 ret = _ci_usb_phy_init(ci);
403 if (ret)
404 return ret;
405 break;
406 default:
407 ret = _ci_usb_phy_init(ci);
408 if (!ret)
409 hw_wait_phy_stable();
410 }
411
412 return ret;
413 }
414
415
416 /**
417 * ci_platform_configure: do controller configure
418 * @ci: the controller
419 *
420 */
ci_platform_configure(struct ci_hdrc * ci)421 void ci_platform_configure(struct ci_hdrc *ci)
422 {
423 bool is_device_mode, is_host_mode;
424
425 is_device_mode = hw_read(ci, OP_USBMODE, USBMODE_CM) == USBMODE_CM_DC;
426 is_host_mode = hw_read(ci, OP_USBMODE, USBMODE_CM) == USBMODE_CM_HC;
427
428 if (is_device_mode) {
429 phy_set_mode(ci->phy, PHY_MODE_USB_DEVICE);
430
431 if (ci->platdata->flags & CI_HDRC_DISABLE_DEVICE_STREAMING)
432 hw_write(ci, OP_USBMODE, USBMODE_CI_SDIS,
433 USBMODE_CI_SDIS);
434 }
435
436 if (is_host_mode) {
437 phy_set_mode(ci->phy, PHY_MODE_USB_HOST);
438
439 if (ci->platdata->flags & CI_HDRC_DISABLE_HOST_STREAMING)
440 hw_write(ci, OP_USBMODE, USBMODE_CI_SDIS,
441 USBMODE_CI_SDIS);
442 }
443
444 if (ci->platdata->flags & CI_HDRC_FORCE_FULLSPEED) {
445 if (ci->hw_bank.lpm)
446 hw_write(ci, OP_DEVLC, DEVLC_PFSC, DEVLC_PFSC);
447 else
448 hw_write(ci, OP_PORTSC, PORTSC_PFSC, PORTSC_PFSC);
449 }
450
451 if (ci->platdata->flags & CI_HDRC_SET_NON_ZERO_TTHA)
452 hw_write(ci, OP_TTCTRL, TTCTRL_TTHA_MASK, TTCTRL_TTHA);
453
454 hw_write(ci, OP_USBCMD, 0xff0000, ci->platdata->itc_setting << 16);
455
456 if (ci->platdata->flags & CI_HDRC_OVERRIDE_AHB_BURST)
457 hw_write_id_reg(ci, ID_SBUSCFG, AHBBRST_MASK,
458 ci->platdata->ahb_burst_config);
459
460 /* override burst size, take effect only when ahb_burst_config is 0 */
461 if (!hw_read_id_reg(ci, ID_SBUSCFG, AHBBRST_MASK)) {
462 if (ci->platdata->flags & CI_HDRC_OVERRIDE_TX_BURST)
463 hw_write(ci, OP_BURSTSIZE, TX_BURST_MASK,
464 ci->platdata->tx_burst_size << __ffs(TX_BURST_MASK));
465
466 if (ci->platdata->flags & CI_HDRC_OVERRIDE_RX_BURST)
467 hw_write(ci, OP_BURSTSIZE, RX_BURST_MASK,
468 ci->platdata->rx_burst_size);
469 }
470 }
471
472 /**
473 * hw_controller_reset: do controller reset
474 * @ci: the controller
475 *
476 * This function returns an error code
477 */
hw_controller_reset(struct ci_hdrc * ci)478 static int hw_controller_reset(struct ci_hdrc *ci)
479 {
480 int count = 0;
481
482 hw_write(ci, OP_USBCMD, USBCMD_RST, USBCMD_RST);
483 while (hw_read(ci, OP_USBCMD, USBCMD_RST)) {
484 udelay(10);
485 if (count++ > 1000)
486 return -ETIMEDOUT;
487 }
488
489 return 0;
490 }
491
492 /**
493 * hw_device_reset: resets chip (execute without interruption)
494 * @ci: the controller
495 *
496 * This function returns an error code
497 */
hw_device_reset(struct ci_hdrc * ci)498 int hw_device_reset(struct ci_hdrc *ci)
499 {
500 int ret;
501
502 /* should flush & stop before reset */
503 hw_write(ci, OP_ENDPTFLUSH, ~0, ~0);
504 hw_write(ci, OP_USBCMD, USBCMD_RS, 0);
505
506 ret = hw_controller_reset(ci);
507 if (ret) {
508 dev_err(ci->dev, "error resetting controller, ret=%d\n", ret);
509 return ret;
510 }
511
512 if (ci->platdata->notify_event) {
513 ret = ci->platdata->notify_event(ci,
514 CI_HDRC_CONTROLLER_RESET_EVENT);
515 if (ret)
516 return ret;
517 }
518
519 /* USBMODE should be configured step by step */
520 hw_write(ci, OP_USBMODE, USBMODE_CM, USBMODE_CM_IDLE);
521 hw_write(ci, OP_USBMODE, USBMODE_CM, USBMODE_CM_DC);
522 /* HW >= 2.3 */
523 hw_write(ci, OP_USBMODE, USBMODE_SLOM, USBMODE_SLOM);
524
525 if (hw_read(ci, OP_USBMODE, USBMODE_CM) != USBMODE_CM_DC) {
526 dev_err(ci->dev, "cannot enter in %s device mode\n",
527 ci_role(ci)->name);
528 dev_err(ci->dev, "lpm = %i\n", ci->hw_bank.lpm);
529 return -ENODEV;
530 }
531
532 ci_platform_configure(ci);
533
534 return 0;
535 }
536
ci_irq(int irq,void * data)537 static irqreturn_t ci_irq(int irq, void *data)
538 {
539 struct ci_hdrc *ci = data;
540 irqreturn_t ret = IRQ_NONE;
541 u32 otgsc = 0;
542
543 if (ci->in_lpm) {
544 disable_irq_nosync(irq);
545 ci->wakeup_int = true;
546 pm_runtime_get(ci->dev);
547 return IRQ_HANDLED;
548 }
549
550 if (ci->is_otg) {
551 otgsc = hw_read_otgsc(ci, ~0);
552 if (ci_otg_is_fsm_mode(ci)) {
553 ret = ci_otg_fsm_irq(ci);
554 if (ret == IRQ_HANDLED)
555 return ret;
556 }
557 }
558
559 /*
560 * Handle id change interrupt, it indicates device/host function
561 * switch.
562 */
563 if (ci->is_otg && (otgsc & OTGSC_IDIE) && (otgsc & OTGSC_IDIS)) {
564 ci->id_event = true;
565 /* Clear ID change irq status */
566 hw_write_otgsc(ci, OTGSC_IDIS, OTGSC_IDIS);
567 ci_otg_queue_work(ci);
568 return IRQ_HANDLED;
569 }
570
571 /*
572 * Handle vbus change interrupt, it indicates device connection
573 * and disconnection events.
574 */
575 if (ci->is_otg && (otgsc & OTGSC_BSVIE) && (otgsc & OTGSC_BSVIS)) {
576 ci->b_sess_valid_event = true;
577 /* Clear BSV irq */
578 hw_write_otgsc(ci, OTGSC_BSVIS, OTGSC_BSVIS);
579 ci_otg_queue_work(ci);
580 return IRQ_HANDLED;
581 }
582
583 /* Handle device/host interrupt */
584 if (ci->role != CI_ROLE_END)
585 ret = ci_role(ci)->irq(ci);
586
587 return ret;
588 }
589
ci_cable_notifier(struct notifier_block * nb,unsigned long event,void * ptr)590 static int ci_cable_notifier(struct notifier_block *nb, unsigned long event,
591 void *ptr)
592 {
593 struct ci_hdrc_cable *cbl = container_of(nb, struct ci_hdrc_cable, nb);
594 struct ci_hdrc *ci = cbl->ci;
595
596 cbl->connected = event;
597 cbl->changed = true;
598
599 ci_irq(ci->irq, ci);
600 return NOTIFY_DONE;
601 }
602
ci_usb_role_switch_get(struct device * dev)603 static enum usb_role ci_usb_role_switch_get(struct device *dev)
604 {
605 struct ci_hdrc *ci = dev_get_drvdata(dev);
606 enum usb_role role;
607 unsigned long flags;
608
609 spin_lock_irqsave(&ci->lock, flags);
610 role = ci_role_to_usb_role(ci);
611 spin_unlock_irqrestore(&ci->lock, flags);
612
613 return role;
614 }
615
ci_usb_role_switch_set(struct device * dev,enum usb_role role)616 static int ci_usb_role_switch_set(struct device *dev, enum usb_role role)
617 {
618 struct ci_hdrc *ci = dev_get_drvdata(dev);
619 struct ci_hdrc_cable *cable = NULL;
620 enum usb_role current_role = ci_role_to_usb_role(ci);
621 unsigned long flags;
622
623 if (current_role == role)
624 return 0;
625
626 pm_runtime_get_sync(ci->dev);
627 /* Stop current role */
628 spin_lock_irqsave(&ci->lock, flags);
629 if (current_role == USB_ROLE_DEVICE)
630 cable = &ci->platdata->vbus_extcon;
631 else if (current_role == USB_ROLE_HOST)
632 cable = &ci->platdata->id_extcon;
633
634 if (cable) {
635 cable->changed = true;
636 cable->connected = false;
637 ci_irq(ci->irq, ci);
638 spin_unlock_irqrestore(&ci->lock, flags);
639 if (ci->wq && role != USB_ROLE_NONE)
640 flush_workqueue(ci->wq);
641 spin_lock_irqsave(&ci->lock, flags);
642 }
643
644 cable = NULL;
645
646 /* Start target role */
647 if (role == USB_ROLE_DEVICE)
648 cable = &ci->platdata->vbus_extcon;
649 else if (role == USB_ROLE_HOST)
650 cable = &ci->platdata->id_extcon;
651
652 if (cable) {
653 cable->changed = true;
654 cable->connected = true;
655 ci_irq(ci->irq, ci);
656 }
657 spin_unlock_irqrestore(&ci->lock, flags);
658 pm_runtime_put_sync(ci->dev);
659
660 return 0;
661 }
662
663 static struct usb_role_switch_desc ci_role_switch = {
664 .set = ci_usb_role_switch_set,
665 .get = ci_usb_role_switch_get,
666 };
667
ci_get_platdata(struct device * dev,struct ci_hdrc_platform_data * platdata)668 static int ci_get_platdata(struct device *dev,
669 struct ci_hdrc_platform_data *platdata)
670 {
671 struct extcon_dev *ext_vbus, *ext_id;
672 struct ci_hdrc_cable *cable;
673 int ret;
674
675 if (!platdata->phy_mode)
676 platdata->phy_mode = of_usb_get_phy_mode(dev->of_node);
677
678 if (!platdata->dr_mode)
679 platdata->dr_mode = usb_get_dr_mode(dev);
680
681 if (platdata->dr_mode == USB_DR_MODE_UNKNOWN)
682 platdata->dr_mode = USB_DR_MODE_OTG;
683
684 if (platdata->dr_mode != USB_DR_MODE_PERIPHERAL) {
685 /* Get the vbus regulator */
686 platdata->reg_vbus = devm_regulator_get(dev, "vbus");
687 if (PTR_ERR(platdata->reg_vbus) == -EPROBE_DEFER) {
688 return -EPROBE_DEFER;
689 } else if (PTR_ERR(platdata->reg_vbus) == -ENODEV) {
690 /* no vbus regulator is needed */
691 platdata->reg_vbus = NULL;
692 } else if (IS_ERR(platdata->reg_vbus)) {
693 dev_err(dev, "Getting regulator error: %ld\n",
694 PTR_ERR(platdata->reg_vbus));
695 return PTR_ERR(platdata->reg_vbus);
696 }
697 /* Get TPL support */
698 if (!platdata->tpl_support)
699 platdata->tpl_support =
700 of_usb_host_tpl_support(dev->of_node);
701 }
702
703 if (platdata->dr_mode == USB_DR_MODE_OTG) {
704 /* We can support HNP and SRP of OTG 2.0 */
705 platdata->ci_otg_caps.otg_rev = 0x0200;
706 platdata->ci_otg_caps.hnp_support = true;
707 platdata->ci_otg_caps.srp_support = true;
708
709 /* Update otg capabilities by DT properties */
710 ret = of_usb_update_otg_caps(dev->of_node,
711 &platdata->ci_otg_caps);
712 if (ret)
713 return ret;
714 }
715
716 if (usb_get_maximum_speed(dev) == USB_SPEED_FULL)
717 platdata->flags |= CI_HDRC_FORCE_FULLSPEED;
718
719 of_property_read_u32(dev->of_node, "phy-clkgate-delay-us",
720 &platdata->phy_clkgate_delay_us);
721
722 platdata->itc_setting = 1;
723
724 of_property_read_u32(dev->of_node, "itc-setting",
725 &platdata->itc_setting);
726
727 ret = of_property_read_u32(dev->of_node, "ahb-burst-config",
728 &platdata->ahb_burst_config);
729 if (!ret) {
730 platdata->flags |= CI_HDRC_OVERRIDE_AHB_BURST;
731 } else if (ret != -EINVAL) {
732 dev_err(dev, "failed to get ahb-burst-config\n");
733 return ret;
734 }
735
736 ret = of_property_read_u32(dev->of_node, "tx-burst-size-dword",
737 &platdata->tx_burst_size);
738 if (!ret) {
739 platdata->flags |= CI_HDRC_OVERRIDE_TX_BURST;
740 } else if (ret != -EINVAL) {
741 dev_err(dev, "failed to get tx-burst-size-dword\n");
742 return ret;
743 }
744
745 ret = of_property_read_u32(dev->of_node, "rx-burst-size-dword",
746 &platdata->rx_burst_size);
747 if (!ret) {
748 platdata->flags |= CI_HDRC_OVERRIDE_RX_BURST;
749 } else if (ret != -EINVAL) {
750 dev_err(dev, "failed to get rx-burst-size-dword\n");
751 return ret;
752 }
753
754 if (of_find_property(dev->of_node, "non-zero-ttctrl-ttha", NULL))
755 platdata->flags |= CI_HDRC_SET_NON_ZERO_TTHA;
756
757 ext_id = ERR_PTR(-ENODEV);
758 ext_vbus = ERR_PTR(-ENODEV);
759 if (of_property_read_bool(dev->of_node, "extcon")) {
760 /* Each one of them is not mandatory */
761 ext_vbus = extcon_get_edev_by_phandle(dev, 0);
762 if (IS_ERR(ext_vbus) && PTR_ERR(ext_vbus) != -ENODEV)
763 return PTR_ERR(ext_vbus);
764
765 ext_id = extcon_get_edev_by_phandle(dev, 1);
766 if (IS_ERR(ext_id) && PTR_ERR(ext_id) != -ENODEV)
767 return PTR_ERR(ext_id);
768 }
769
770 cable = &platdata->vbus_extcon;
771 cable->nb.notifier_call = ci_cable_notifier;
772 cable->edev = ext_vbus;
773
774 if (!IS_ERR(ext_vbus)) {
775 ret = extcon_get_state(cable->edev, EXTCON_USB);
776 if (ret)
777 cable->connected = true;
778 else
779 cable->connected = false;
780 }
781
782 cable = &platdata->id_extcon;
783 cable->nb.notifier_call = ci_cable_notifier;
784 cable->edev = ext_id;
785
786 if (!IS_ERR(ext_id)) {
787 ret = extcon_get_state(cable->edev, EXTCON_USB_HOST);
788 if (ret)
789 cable->connected = true;
790 else
791 cable->connected = false;
792 }
793
794 if (device_property_read_bool(dev, "usb-role-switch"))
795 ci_role_switch.fwnode = dev->fwnode;
796
797 platdata->pctl = devm_pinctrl_get(dev);
798 if (!IS_ERR(platdata->pctl)) {
799 struct pinctrl_state *p;
800
801 p = pinctrl_lookup_state(platdata->pctl, "default");
802 if (!IS_ERR(p))
803 platdata->pins_default = p;
804
805 p = pinctrl_lookup_state(platdata->pctl, "host");
806 if (!IS_ERR(p))
807 platdata->pins_host = p;
808
809 p = pinctrl_lookup_state(platdata->pctl, "device");
810 if (!IS_ERR(p))
811 platdata->pins_device = p;
812 }
813
814 return 0;
815 }
816
ci_extcon_register(struct ci_hdrc * ci)817 static int ci_extcon_register(struct ci_hdrc *ci)
818 {
819 struct ci_hdrc_cable *id, *vbus;
820 int ret;
821
822 id = &ci->platdata->id_extcon;
823 id->ci = ci;
824 if (!IS_ERR_OR_NULL(id->edev)) {
825 ret = devm_extcon_register_notifier(ci->dev, id->edev,
826 EXTCON_USB_HOST, &id->nb);
827 if (ret < 0) {
828 dev_err(ci->dev, "register ID failed\n");
829 return ret;
830 }
831 }
832
833 vbus = &ci->platdata->vbus_extcon;
834 vbus->ci = ci;
835 if (!IS_ERR_OR_NULL(vbus->edev)) {
836 ret = devm_extcon_register_notifier(ci->dev, vbus->edev,
837 EXTCON_USB, &vbus->nb);
838 if (ret < 0) {
839 dev_err(ci->dev, "register VBUS failed\n");
840 return ret;
841 }
842 }
843
844 return 0;
845 }
846
847 static DEFINE_IDA(ci_ida);
848
ci_hdrc_add_device(struct device * dev,struct resource * res,int nres,struct ci_hdrc_platform_data * platdata)849 struct platform_device *ci_hdrc_add_device(struct device *dev,
850 struct resource *res, int nres,
851 struct ci_hdrc_platform_data *platdata)
852 {
853 struct platform_device *pdev;
854 int id, ret;
855
856 ret = ci_get_platdata(dev, platdata);
857 if (ret)
858 return ERR_PTR(ret);
859
860 id = ida_simple_get(&ci_ida, 0, 0, GFP_KERNEL);
861 if (id < 0)
862 return ERR_PTR(id);
863
864 pdev = platform_device_alloc("ci_hdrc", id);
865 if (!pdev) {
866 ret = -ENOMEM;
867 goto put_id;
868 }
869
870 pdev->dev.parent = dev;
871
872 ret = platform_device_add_resources(pdev, res, nres);
873 if (ret)
874 goto err;
875
876 ret = platform_device_add_data(pdev, platdata, sizeof(*platdata));
877 if (ret)
878 goto err;
879
880 ret = platform_device_add(pdev);
881 if (ret)
882 goto err;
883
884 return pdev;
885
886 err:
887 platform_device_put(pdev);
888 put_id:
889 ida_simple_remove(&ci_ida, id);
890 return ERR_PTR(ret);
891 }
892 EXPORT_SYMBOL_GPL(ci_hdrc_add_device);
893
ci_hdrc_remove_device(struct platform_device * pdev)894 void ci_hdrc_remove_device(struct platform_device *pdev)
895 {
896 int id = pdev->id;
897 platform_device_unregister(pdev);
898 ida_simple_remove(&ci_ida, id);
899 }
900 EXPORT_SYMBOL_GPL(ci_hdrc_remove_device);
901
ci_role_destroy(struct ci_hdrc * ci)902 static inline void ci_role_destroy(struct ci_hdrc *ci)
903 {
904 ci_hdrc_gadget_destroy(ci);
905 ci_hdrc_host_destroy(ci);
906 if (ci->is_otg && ci->roles[CI_ROLE_GADGET])
907 ci_hdrc_otg_destroy(ci);
908 }
909
ci_get_otg_capable(struct ci_hdrc * ci)910 static void ci_get_otg_capable(struct ci_hdrc *ci)
911 {
912 if (ci->platdata->flags & CI_HDRC_DUAL_ROLE_NOT_OTG)
913 ci->is_otg = false;
914 else
915 ci->is_otg = (hw_read(ci, CAP_DCCPARAMS,
916 DCCPARAMS_DC | DCCPARAMS_HC)
917 == (DCCPARAMS_DC | DCCPARAMS_HC));
918 if (ci->is_otg) {
919 dev_dbg(ci->dev, "It is OTG capable controller\n");
920 /* Disable and clear all OTG irq */
921 hw_write_otgsc(ci, OTGSC_INT_EN_BITS | OTGSC_INT_STATUS_BITS,
922 OTGSC_INT_STATUS_BITS);
923 }
924 }
925
role_show(struct device * dev,struct device_attribute * attr,char * buf)926 static ssize_t role_show(struct device *dev, struct device_attribute *attr,
927 char *buf)
928 {
929 struct ci_hdrc *ci = dev_get_drvdata(dev);
930
931 if (ci->role != CI_ROLE_END)
932 return sprintf(buf, "%s\n", ci_role(ci)->name);
933
934 return 0;
935 }
936
role_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t n)937 static ssize_t role_store(struct device *dev,
938 struct device_attribute *attr, const char *buf, size_t n)
939 {
940 struct ci_hdrc *ci = dev_get_drvdata(dev);
941 enum ci_role role;
942 int ret;
943
944 if (!(ci->roles[CI_ROLE_HOST] && ci->roles[CI_ROLE_GADGET])) {
945 dev_warn(dev, "Current configuration is not dual-role, quit\n");
946 return -EPERM;
947 }
948
949 for (role = CI_ROLE_HOST; role < CI_ROLE_END; role++)
950 if (!strncmp(buf, ci->roles[role]->name,
951 strlen(ci->roles[role]->name)))
952 break;
953
954 if (role == CI_ROLE_END || role == ci->role)
955 return -EINVAL;
956
957 pm_runtime_get_sync(dev);
958 disable_irq(ci->irq);
959 ci_role_stop(ci);
960 ret = ci_role_start(ci, role);
961 if (!ret && ci->role == CI_ROLE_GADGET)
962 ci_handle_vbus_change(ci);
963 enable_irq(ci->irq);
964 pm_runtime_put_sync(dev);
965
966 return (ret == 0) ? n : ret;
967 }
968 static DEVICE_ATTR_RW(role);
969
970 static struct attribute *ci_attrs[] = {
971 &dev_attr_role.attr,
972 NULL,
973 };
974 ATTRIBUTE_GROUPS(ci);
975
ci_hdrc_probe(struct platform_device * pdev)976 static int ci_hdrc_probe(struct platform_device *pdev)
977 {
978 struct device *dev = &pdev->dev;
979 struct ci_hdrc *ci;
980 struct resource *res;
981 void __iomem *base;
982 int ret;
983 enum usb_dr_mode dr_mode;
984
985 if (!dev_get_platdata(dev)) {
986 dev_err(dev, "platform data missing\n");
987 return -ENODEV;
988 }
989
990 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
991 base = devm_ioremap_resource(dev, res);
992 if (IS_ERR(base))
993 return PTR_ERR(base);
994
995 ci = devm_kzalloc(dev, sizeof(*ci), GFP_KERNEL);
996 if (!ci)
997 return -ENOMEM;
998
999 spin_lock_init(&ci->lock);
1000 ci->dev = dev;
1001 ci->platdata = dev_get_platdata(dev);
1002 ci->imx28_write_fix = !!(ci->platdata->flags &
1003 CI_HDRC_IMX28_WRITE_FIX);
1004 ci->supports_runtime_pm = !!(ci->platdata->flags &
1005 CI_HDRC_SUPPORTS_RUNTIME_PM);
1006 platform_set_drvdata(pdev, ci);
1007
1008 ret = hw_device_init(ci, base);
1009 if (ret < 0) {
1010 dev_err(dev, "can't initialize hardware\n");
1011 return -ENODEV;
1012 }
1013
1014 ret = ci_ulpi_init(ci);
1015 if (ret)
1016 return ret;
1017
1018 if (ci->platdata->phy) {
1019 ci->phy = ci->platdata->phy;
1020 } else if (ci->platdata->usb_phy) {
1021 ci->usb_phy = ci->platdata->usb_phy;
1022 } else {
1023 /* Look for a generic PHY first */
1024 ci->phy = devm_phy_get(dev->parent, "usb-phy");
1025
1026 if (PTR_ERR(ci->phy) == -EPROBE_DEFER) {
1027 ret = -EPROBE_DEFER;
1028 goto ulpi_exit;
1029 } else if (IS_ERR(ci->phy)) {
1030 ci->phy = NULL;
1031 }
1032
1033 /* Look for a legacy USB PHY from device-tree next */
1034 if (!ci->phy) {
1035 ci->usb_phy = devm_usb_get_phy_by_phandle(dev->parent,
1036 "phys", 0);
1037
1038 if (PTR_ERR(ci->usb_phy) == -EPROBE_DEFER) {
1039 ret = -EPROBE_DEFER;
1040 goto ulpi_exit;
1041 } else if (IS_ERR(ci->usb_phy)) {
1042 ci->usb_phy = NULL;
1043 }
1044 }
1045
1046 /* Look for any registered legacy USB PHY as last resort */
1047 if (!ci->phy && !ci->usb_phy) {
1048 ci->usb_phy = devm_usb_get_phy(dev->parent,
1049 USB_PHY_TYPE_USB2);
1050
1051 if (PTR_ERR(ci->usb_phy) == -EPROBE_DEFER) {
1052 ret = -EPROBE_DEFER;
1053 goto ulpi_exit;
1054 } else if (IS_ERR(ci->usb_phy)) {
1055 ci->usb_phy = NULL;
1056 }
1057 }
1058
1059 /* No USB PHY was found in the end */
1060 if (!ci->phy && !ci->usb_phy) {
1061 ret = -ENXIO;
1062 goto ulpi_exit;
1063 }
1064 }
1065
1066 ret = ci_usb_phy_init(ci);
1067 if (ret) {
1068 dev_err(dev, "unable to init phy: %d\n", ret);
1069 return ret;
1070 }
1071
1072 ci->hw_bank.phys = res->start;
1073
1074 ci->irq = platform_get_irq(pdev, 0);
1075 if (ci->irq < 0) {
1076 ret = ci->irq;
1077 goto deinit_phy;
1078 }
1079
1080 ci_get_otg_capable(ci);
1081
1082 dr_mode = ci->platdata->dr_mode;
1083 /* initialize role(s) before the interrupt is requested */
1084 if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_HOST) {
1085 ret = ci_hdrc_host_init(ci);
1086 if (ret) {
1087 if (ret == -ENXIO)
1088 dev_info(dev, "doesn't support host\n");
1089 else
1090 goto deinit_phy;
1091 }
1092 }
1093
1094 if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_PERIPHERAL) {
1095 ret = ci_hdrc_gadget_init(ci);
1096 if (ret) {
1097 if (ret == -ENXIO)
1098 dev_info(dev, "doesn't support gadget\n");
1099 else
1100 goto deinit_host;
1101 }
1102 }
1103
1104 if (!ci->roles[CI_ROLE_HOST] && !ci->roles[CI_ROLE_GADGET]) {
1105 dev_err(dev, "no supported roles\n");
1106 ret = -ENODEV;
1107 goto deinit_gadget;
1108 }
1109
1110 if (ci->is_otg && ci->roles[CI_ROLE_GADGET]) {
1111 ret = ci_hdrc_otg_init(ci);
1112 if (ret) {
1113 dev_err(dev, "init otg fails, ret = %d\n", ret);
1114 goto deinit_gadget;
1115 }
1116 }
1117
1118 if (ci_role_switch.fwnode) {
1119 ci->role_switch = usb_role_switch_register(dev,
1120 &ci_role_switch);
1121 if (IS_ERR(ci->role_switch)) {
1122 ret = PTR_ERR(ci->role_switch);
1123 goto deinit_otg;
1124 }
1125 }
1126
1127 if (ci->roles[CI_ROLE_HOST] && ci->roles[CI_ROLE_GADGET]) {
1128 if (ci->is_otg) {
1129 ci->role = ci_otg_role(ci);
1130 /* Enable ID change irq */
1131 hw_write_otgsc(ci, OTGSC_IDIE, OTGSC_IDIE);
1132 } else {
1133 /*
1134 * If the controller is not OTG capable, but support
1135 * role switch, the defalt role is gadget, and the
1136 * user can switch it through debugfs.
1137 */
1138 ci->role = CI_ROLE_GADGET;
1139 }
1140 } else {
1141 ci->role = ci->roles[CI_ROLE_HOST]
1142 ? CI_ROLE_HOST
1143 : CI_ROLE_GADGET;
1144 }
1145
1146 if (!ci_otg_is_fsm_mode(ci)) {
1147 /* only update vbus status for peripheral */
1148 if (ci->role == CI_ROLE_GADGET)
1149 ci_handle_vbus_change(ci);
1150
1151 ret = ci_role_start(ci, ci->role);
1152 if (ret) {
1153 dev_err(dev, "can't start %s role\n",
1154 ci_role(ci)->name);
1155 goto stop;
1156 }
1157 }
1158
1159 ret = devm_request_irq(dev, ci->irq, ci_irq, IRQF_SHARED,
1160 ci->platdata->name, ci);
1161 if (ret)
1162 goto stop;
1163
1164 ret = ci_extcon_register(ci);
1165 if (ret)
1166 goto stop;
1167
1168 if (ci->supports_runtime_pm) {
1169 pm_runtime_set_active(&pdev->dev);
1170 pm_runtime_enable(&pdev->dev);
1171 pm_runtime_set_autosuspend_delay(&pdev->dev, 2000);
1172 pm_runtime_mark_last_busy(ci->dev);
1173 pm_runtime_use_autosuspend(&pdev->dev);
1174 }
1175
1176 if (ci_otg_is_fsm_mode(ci))
1177 ci_hdrc_otg_fsm_start(ci);
1178
1179 device_set_wakeup_capable(&pdev->dev, true);
1180 dbg_create_files(ci);
1181
1182 return 0;
1183
1184 stop:
1185 if (ci->role_switch)
1186 usb_role_switch_unregister(ci->role_switch);
1187 deinit_otg:
1188 if (ci->is_otg && ci->roles[CI_ROLE_GADGET])
1189 ci_hdrc_otg_destroy(ci);
1190 deinit_gadget:
1191 ci_hdrc_gadget_destroy(ci);
1192 deinit_host:
1193 ci_hdrc_host_destroy(ci);
1194 deinit_phy:
1195 ci_usb_phy_exit(ci);
1196 ulpi_exit:
1197 ci_ulpi_exit(ci);
1198
1199 return ret;
1200 }
1201
ci_hdrc_remove(struct platform_device * pdev)1202 static int ci_hdrc_remove(struct platform_device *pdev)
1203 {
1204 struct ci_hdrc *ci = platform_get_drvdata(pdev);
1205
1206 if (ci->role_switch)
1207 usb_role_switch_unregister(ci->role_switch);
1208
1209 if (ci->supports_runtime_pm) {
1210 pm_runtime_get_sync(&pdev->dev);
1211 pm_runtime_disable(&pdev->dev);
1212 pm_runtime_put_noidle(&pdev->dev);
1213 }
1214
1215 dbg_remove_files(ci);
1216 ci_role_destroy(ci);
1217 ci_hdrc_enter_lpm(ci, true);
1218 ci_usb_phy_exit(ci);
1219 ci_ulpi_exit(ci);
1220
1221 return 0;
1222 }
1223
1224 #ifdef CONFIG_PM
1225 /* Prepare wakeup by SRP before suspend */
ci_otg_fsm_suspend_for_srp(struct ci_hdrc * ci)1226 static void ci_otg_fsm_suspend_for_srp(struct ci_hdrc *ci)
1227 {
1228 if ((ci->fsm.otg->state == OTG_STATE_A_IDLE) &&
1229 !hw_read_otgsc(ci, OTGSC_ID)) {
1230 hw_write(ci, OP_PORTSC, PORTSC_W1C_BITS | PORTSC_PP,
1231 PORTSC_PP);
1232 hw_write(ci, OP_PORTSC, PORTSC_W1C_BITS | PORTSC_WKCN,
1233 PORTSC_WKCN);
1234 }
1235 }
1236
1237 /* Handle SRP when wakeup by data pulse */
ci_otg_fsm_wakeup_by_srp(struct ci_hdrc * ci)1238 static void ci_otg_fsm_wakeup_by_srp(struct ci_hdrc *ci)
1239 {
1240 if ((ci->fsm.otg->state == OTG_STATE_A_IDLE) &&
1241 (ci->fsm.a_bus_drop == 1) && (ci->fsm.a_bus_req == 0)) {
1242 if (!hw_read_otgsc(ci, OTGSC_ID)) {
1243 ci->fsm.a_srp_det = 1;
1244 ci->fsm.a_bus_drop = 0;
1245 } else {
1246 ci->fsm.id = 1;
1247 }
1248 ci_otg_queue_work(ci);
1249 }
1250 }
1251
ci_controller_suspend(struct ci_hdrc * ci)1252 static void ci_controller_suspend(struct ci_hdrc *ci)
1253 {
1254 disable_irq(ci->irq);
1255 ci_hdrc_enter_lpm(ci, true);
1256 if (ci->platdata->phy_clkgate_delay_us)
1257 usleep_range(ci->platdata->phy_clkgate_delay_us,
1258 ci->platdata->phy_clkgate_delay_us + 50);
1259 usb_phy_set_suspend(ci->usb_phy, 1);
1260 ci->in_lpm = true;
1261 enable_irq(ci->irq);
1262 }
1263
ci_controller_resume(struct device * dev)1264 static int ci_controller_resume(struct device *dev)
1265 {
1266 struct ci_hdrc *ci = dev_get_drvdata(dev);
1267 int ret;
1268
1269 dev_dbg(dev, "at %s\n", __func__);
1270
1271 if (!ci->in_lpm) {
1272 WARN_ON(1);
1273 return 0;
1274 }
1275
1276 ci_hdrc_enter_lpm(ci, false);
1277
1278 ret = ci_ulpi_resume(ci);
1279 if (ret)
1280 return ret;
1281
1282 if (ci->usb_phy) {
1283 usb_phy_set_suspend(ci->usb_phy, 0);
1284 usb_phy_set_wakeup(ci->usb_phy, false);
1285 hw_wait_phy_stable();
1286 }
1287
1288 ci->in_lpm = false;
1289 if (ci->wakeup_int) {
1290 ci->wakeup_int = false;
1291 pm_runtime_mark_last_busy(ci->dev);
1292 pm_runtime_put_autosuspend(ci->dev);
1293 enable_irq(ci->irq);
1294 if (ci_otg_is_fsm_mode(ci))
1295 ci_otg_fsm_wakeup_by_srp(ci);
1296 }
1297
1298 return 0;
1299 }
1300
1301 #ifdef CONFIG_PM_SLEEP
ci_suspend(struct device * dev)1302 static int ci_suspend(struct device *dev)
1303 {
1304 struct ci_hdrc *ci = dev_get_drvdata(dev);
1305
1306 if (ci->wq)
1307 flush_workqueue(ci->wq);
1308 /*
1309 * Controller needs to be active during suspend, otherwise the core
1310 * may run resume when the parent is at suspend if other driver's
1311 * suspend fails, it occurs before parent's suspend has not started,
1312 * but the core suspend has finished.
1313 */
1314 if (ci->in_lpm)
1315 pm_runtime_resume(dev);
1316
1317 if (ci->in_lpm) {
1318 WARN_ON(1);
1319 return 0;
1320 }
1321
1322 if (device_may_wakeup(dev)) {
1323 if (ci_otg_is_fsm_mode(ci))
1324 ci_otg_fsm_suspend_for_srp(ci);
1325
1326 usb_phy_set_wakeup(ci->usb_phy, true);
1327 enable_irq_wake(ci->irq);
1328 }
1329
1330 ci_controller_suspend(ci);
1331
1332 return 0;
1333 }
1334
ci_resume(struct device * dev)1335 static int ci_resume(struct device *dev)
1336 {
1337 struct ci_hdrc *ci = dev_get_drvdata(dev);
1338 int ret;
1339
1340 if (device_may_wakeup(dev))
1341 disable_irq_wake(ci->irq);
1342
1343 ret = ci_controller_resume(dev);
1344 if (ret)
1345 return ret;
1346
1347 if (ci->supports_runtime_pm) {
1348 pm_runtime_disable(dev);
1349 pm_runtime_set_active(dev);
1350 pm_runtime_enable(dev);
1351 }
1352
1353 return ret;
1354 }
1355 #endif /* CONFIG_PM_SLEEP */
1356
ci_runtime_suspend(struct device * dev)1357 static int ci_runtime_suspend(struct device *dev)
1358 {
1359 struct ci_hdrc *ci = dev_get_drvdata(dev);
1360
1361 dev_dbg(dev, "at %s\n", __func__);
1362
1363 if (ci->in_lpm) {
1364 WARN_ON(1);
1365 return 0;
1366 }
1367
1368 if (ci_otg_is_fsm_mode(ci))
1369 ci_otg_fsm_suspend_for_srp(ci);
1370
1371 usb_phy_set_wakeup(ci->usb_phy, true);
1372 ci_controller_suspend(ci);
1373
1374 return 0;
1375 }
1376
ci_runtime_resume(struct device * dev)1377 static int ci_runtime_resume(struct device *dev)
1378 {
1379 return ci_controller_resume(dev);
1380 }
1381
1382 #endif /* CONFIG_PM */
1383 static const struct dev_pm_ops ci_pm_ops = {
1384 SET_SYSTEM_SLEEP_PM_OPS(ci_suspend, ci_resume)
1385 SET_RUNTIME_PM_OPS(ci_runtime_suspend, ci_runtime_resume, NULL)
1386 };
1387
1388 static struct platform_driver ci_hdrc_driver = {
1389 .probe = ci_hdrc_probe,
1390 .remove = ci_hdrc_remove,
1391 .driver = {
1392 .name = "ci_hdrc",
1393 .pm = &ci_pm_ops,
1394 .dev_groups = ci_groups,
1395 },
1396 };
1397
ci_hdrc_platform_register(void)1398 static int __init ci_hdrc_platform_register(void)
1399 {
1400 ci_hdrc_host_driver_init();
1401 return platform_driver_register(&ci_hdrc_driver);
1402 }
1403 module_init(ci_hdrc_platform_register);
1404
ci_hdrc_platform_unregister(void)1405 static void __exit ci_hdrc_platform_unregister(void)
1406 {
1407 platform_driver_unregister(&ci_hdrc_driver);
1408 }
1409 module_exit(ci_hdrc_platform_unregister);
1410
1411 MODULE_ALIAS("platform:ci_hdrc");
1412 MODULE_LICENSE("GPL v2");
1413 MODULE_AUTHOR("David Lopo <dlopo@chipidea.mips.com>");
1414 MODULE_DESCRIPTION("ChipIdea HDRC Driver");
1415
