1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) 1995 Linus Torvalds
4 * Adapted from 'alpha' version by Gary Thomas
5 * Modified by Cort Dougan (cort@cs.nmt.edu)
6 */
7
8 /*
9 * bootup setup stuff..
10 */
11
12 #include <linux/errno.h>
13 #include <linux/sched.h>
14 #include <linux/kernel.h>
15 #include <linux/mm.h>
16 #include <linux/stddef.h>
17 #include <linux/unistd.h>
18 #include <linux/ptrace.h>
19 #include <linux/user.h>
20 #include <linux/tty.h>
21 #include <linux/major.h>
22 #include <linux/interrupt.h>
23 #include <linux/reboot.h>
24 #include <linux/init.h>
25 #include <linux/pci.h>
26 #include <generated/utsrelease.h>
27 #include <linux/adb.h>
28 #include <linux/module.h>
29 #include <linux/delay.h>
30 #include <linux/console.h>
31 #include <linux/seq_file.h>
32 #include <linux/root_dev.h>
33 #include <linux/initrd.h>
34 #include <linux/timer.h>
35
36 #include <asm/io.h>
37 #include <asm/pgtable.h>
38 #include <asm/prom.h>
39 #include <asm/pci-bridge.h>
40 #include <asm/dma.h>
41 #include <asm/machdep.h>
42 #include <asm/irq.h>
43 #include <asm/hydra.h>
44 #include <asm/sections.h>
45 #include <asm/time.h>
46 #include <asm/i8259.h>
47 #include <asm/mpic.h>
48 #include <asm/rtas.h>
49 #include <asm/xmon.h>
50
51 #include "chrp.h"
52 #include "gg2.h"
53
54 void rtas_indicator_progress(char *, unsigned short);
55
56 int _chrp_type;
57 EXPORT_SYMBOL(_chrp_type);
58
59 static struct mpic *chrp_mpic;
60
61 /* Used for doing CHRP event-scans */
62 DEFINE_PER_CPU(struct timer_list, heartbeat_timer);
63 unsigned long event_scan_interval;
64
65 extern unsigned long loops_per_jiffy;
66
67 /* To be replaced by RTAS when available */
68 static unsigned int __iomem *briq_SPOR;
69
70 #ifdef CONFIG_SMP
71 extern struct smp_ops_t chrp_smp_ops;
72 #endif
73
74 static const char *gg2_memtypes[4] = {
75 "FPM", "SDRAM", "EDO", "BEDO"
76 };
77 static const char *gg2_cachesizes[4] = {
78 "256 KB", "512 KB", "1 MB", "Reserved"
79 };
80 static const char *gg2_cachetypes[4] = {
81 "Asynchronous", "Reserved", "Flow-Through Synchronous",
82 "Pipelined Synchronous"
83 };
84 static const char *gg2_cachemodes[4] = {
85 "Disabled", "Write-Through", "Copy-Back", "Transparent Mode"
86 };
87
88 static const char *chrp_names[] = {
89 "Unknown",
90 "","","",
91 "Motorola",
92 "IBM or Longtrail",
93 "Genesi Pegasos",
94 "Total Impact Briq"
95 };
96
chrp_show_cpuinfo(struct seq_file * m)97 static void chrp_show_cpuinfo(struct seq_file *m)
98 {
99 int i, sdramen;
100 unsigned int t;
101 struct device_node *root;
102 const char *model = "";
103
104 root = of_find_node_by_path("/");
105 if (root)
106 model = of_get_property(root, "model", NULL);
107 seq_printf(m, "machine\t\t: CHRP %s\n", model);
108
109 /* longtrail (goldengate) stuff */
110 if (model && !strncmp(model, "IBM,LongTrail", 13)) {
111 /* VLSI VAS96011/12 `Golden Gate 2' */
112 /* Memory banks */
113 sdramen = (in_le32(gg2_pci_config_base + GG2_PCI_DRAM_CTRL)
114 >>31) & 1;
115 for (i = 0; i < (sdramen ? 4 : 6); i++) {
116 t = in_le32(gg2_pci_config_base+
117 GG2_PCI_DRAM_BANK0+
118 i*4);
119 if (!(t & 1))
120 continue;
121 switch ((t>>8) & 0x1f) {
122 case 0x1f:
123 model = "4 MB";
124 break;
125 case 0x1e:
126 model = "8 MB";
127 break;
128 case 0x1c:
129 model = "16 MB";
130 break;
131 case 0x18:
132 model = "32 MB";
133 break;
134 case 0x10:
135 model = "64 MB";
136 break;
137 case 0x00:
138 model = "128 MB";
139 break;
140 default:
141 model = "Reserved";
142 break;
143 }
144 seq_printf(m, "memory bank %d\t: %s %s\n", i, model,
145 gg2_memtypes[sdramen ? 1 : ((t>>1) & 3)]);
146 }
147 /* L2 cache */
148 t = in_le32(gg2_pci_config_base+GG2_PCI_CC_CTRL);
149 seq_printf(m, "board l2\t: %s %s (%s)\n",
150 gg2_cachesizes[(t>>7) & 3],
151 gg2_cachetypes[(t>>2) & 3],
152 gg2_cachemodes[t & 3]);
153 }
154 of_node_put(root);
155 }
156
157 /*
158 * Fixes for the National Semiconductor PC78308VUL SuperI/O
159 *
160 * Some versions of Open Firmware incorrectly initialize the IRQ settings
161 * for keyboard and mouse
162 */
sio_write(u8 val,u8 index)163 static inline void __init sio_write(u8 val, u8 index)
164 {
165 outb(index, 0x15c);
166 outb(val, 0x15d);
167 }
168
sio_read(u8 index)169 static inline u8 __init sio_read(u8 index)
170 {
171 outb(index, 0x15c);
172 return inb(0x15d);
173 }
174
sio_fixup_irq(const char * name,u8 device,u8 level,u8 type)175 static void __init sio_fixup_irq(const char *name, u8 device, u8 level,
176 u8 type)
177 {
178 u8 level0, type0, active;
179
180 /* select logical device */
181 sio_write(device, 0x07);
182 active = sio_read(0x30);
183 level0 = sio_read(0x70);
184 type0 = sio_read(0x71);
185 if (level0 != level || type0 != type || !active) {
186 printk(KERN_WARNING "sio: %s irq level %d, type %d, %sactive: "
187 "remapping to level %d, type %d, active\n",
188 name, level0, type0, !active ? "in" : "", level, type);
189 sio_write(0x01, 0x30);
190 sio_write(level, 0x70);
191 sio_write(type, 0x71);
192 }
193 }
194
sio_init(void)195 static void __init sio_init(void)
196 {
197 struct device_node *root;
198 const char *model;
199
200 root = of_find_node_by_path("/");
201 if (!root)
202 return;
203
204 model = of_get_property(root, "model", NULL);
205 if (model && !strncmp(model, "IBM,LongTrail", 13)) {
206 /* logical device 0 (KBC/Keyboard) */
207 sio_fixup_irq("keyboard", 0, 1, 2);
208 /* select logical device 1 (KBC/Mouse) */
209 sio_fixup_irq("mouse", 1, 12, 2);
210 }
211
212 of_node_put(root);
213 }
214
215
pegasos_set_l2cr(void)216 static void __init pegasos_set_l2cr(void)
217 {
218 struct device_node *np;
219
220 /* On Pegasos, enable the l2 cache if needed, as the OF forgets it */
221 if (_chrp_type != _CHRP_Pegasos)
222 return;
223
224 /* Enable L2 cache if needed */
225 np = of_find_node_by_type(NULL, "cpu");
226 if (np != NULL) {
227 const unsigned int *l2cr = of_get_property(np, "l2cr", NULL);
228 if (l2cr == NULL) {
229 printk ("Pegasos l2cr : no cpu l2cr property found\n");
230 goto out;
231 }
232 if (!((*l2cr) & 0x80000000)) {
233 printk ("Pegasos l2cr : L2 cache was not active, "
234 "activating\n");
235 _set_L2CR(0);
236 _set_L2CR((*l2cr) | 0x80000000);
237 }
238 }
239 out:
240 of_node_put(np);
241 }
242
briq_restart(char * cmd)243 static void __noreturn briq_restart(char *cmd)
244 {
245 local_irq_disable();
246 if (briq_SPOR)
247 out_be32(briq_SPOR, 0);
248 for(;;);
249 }
250
251 /*
252 * Per default, input/output-device points to the keyboard/screen
253 * If no card is installed, the built-in serial port is used as a fallback.
254 * But unfortunately, the firmware does not connect /chosen/{stdin,stdout}
255 * the the built-in serial node. Instead, a /failsafe node is created.
256 */
chrp_init(void)257 static __init void chrp_init(void)
258 {
259 struct device_node *node;
260 const char *property;
261
262 if (strstr(boot_command_line, "console="))
263 return;
264 /* find the boot console from /chosen/stdout */
265 if (!of_chosen)
266 return;
267 node = of_find_node_by_path("/");
268 if (!node)
269 return;
270 property = of_get_property(node, "model", NULL);
271 if (!property)
272 goto out_put;
273 if (strcmp(property, "Pegasos2"))
274 goto out_put;
275 /* this is a Pegasos2 */
276 property = of_get_property(of_chosen, "linux,stdout-path", NULL);
277 if (!property)
278 goto out_put;
279 of_node_put(node);
280 node = of_find_node_by_path(property);
281 if (!node)
282 return;
283 if (!of_node_is_type(node, "serial"))
284 goto out_put;
285 /*
286 * The 9pin connector is either /failsafe
287 * or /pci@80000000/isa@C/serial@i2F8
288 * The optional graphics card has also type 'serial' in VGA mode.
289 */
290 if (of_node_name_eq(node, "failsafe") || of_node_name_eq(node, "serial"))
291 add_preferred_console("ttyS", 0, NULL);
292 out_put:
293 of_node_put(node);
294 }
295
chrp_setup_arch(void)296 static void __init chrp_setup_arch(void)
297 {
298 struct device_node *root = of_find_node_by_path("/");
299 const char *machine = NULL;
300
301 /* init to some ~sane value until calibrate_delay() runs */
302 loops_per_jiffy = 50000000/HZ;
303
304 if (root)
305 machine = of_get_property(root, "model", NULL);
306 if (machine && strncmp(machine, "Pegasos", 7) == 0) {
307 _chrp_type = _CHRP_Pegasos;
308 } else if (machine && strncmp(machine, "IBM", 3) == 0) {
309 _chrp_type = _CHRP_IBM;
310 } else if (machine && strncmp(machine, "MOT", 3) == 0) {
311 _chrp_type = _CHRP_Motorola;
312 } else if (machine && strncmp(machine, "TotalImpact,BRIQ-1", 18) == 0) {
313 _chrp_type = _CHRP_briq;
314 /* Map the SPOR register on briq and change the restart hook */
315 briq_SPOR = ioremap(0xff0000e8, 4);
316 ppc_md.restart = briq_restart;
317 } else {
318 /* Let's assume it is an IBM chrp if all else fails */
319 _chrp_type = _CHRP_IBM;
320 }
321 of_node_put(root);
322 printk("chrp type = %x [%s]\n", _chrp_type, chrp_names[_chrp_type]);
323
324 rtas_initialize();
325 if (rtas_token("display-character") >= 0)
326 ppc_md.progress = rtas_progress;
327
328 /* use RTAS time-of-day routines if available */
329 if (rtas_token("get-time-of-day") != RTAS_UNKNOWN_SERVICE) {
330 ppc_md.get_boot_time = rtas_get_boot_time;
331 ppc_md.get_rtc_time = rtas_get_rtc_time;
332 ppc_md.set_rtc_time = rtas_set_rtc_time;
333 }
334
335 /* On pegasos, enable the L2 cache if not already done by OF */
336 pegasos_set_l2cr();
337
338 /* Lookup PCI host bridges */
339 chrp_find_bridges();
340
341 /*
342 * Temporary fixes for PCI devices.
343 * -- Geert
344 */
345 hydra_init(); /* Mac I/O */
346
347 /*
348 * Fix the Super I/O configuration
349 */
350 sio_init();
351
352 pci_create_OF_bus_map();
353
354 /*
355 * Print the banner, then scroll down so boot progress
356 * can be printed. -- Cort
357 */
358 if (ppc_md.progress) ppc_md.progress("Linux/PPC "UTS_RELEASE"\n", 0x0);
359 }
360
chrp_8259_cascade(struct irq_desc * desc)361 static void chrp_8259_cascade(struct irq_desc *desc)
362 {
363 struct irq_chip *chip = irq_desc_get_chip(desc);
364 unsigned int cascade_irq = i8259_irq();
365
366 if (cascade_irq)
367 generic_handle_irq(cascade_irq);
368
369 chip->irq_eoi(&desc->irq_data);
370 }
371
372 /*
373 * Finds the open-pic node and sets up the mpic driver.
374 */
chrp_find_openpic(void)375 static void __init chrp_find_openpic(void)
376 {
377 struct device_node *np, *root;
378 int len, i, j;
379 int isu_size;
380 const unsigned int *iranges, *opprop = NULL;
381 int oplen = 0;
382 unsigned long opaddr;
383 int na = 1;
384
385 np = of_find_node_by_type(NULL, "open-pic");
386 if (np == NULL)
387 return;
388 root = of_find_node_by_path("/");
389 if (root) {
390 opprop = of_get_property(root, "platform-open-pic", &oplen);
391 na = of_n_addr_cells(root);
392 }
393 if (opprop && oplen >= na * sizeof(unsigned int)) {
394 opaddr = opprop[na-1]; /* assume 32-bit */
395 oplen /= na * sizeof(unsigned int);
396 } else {
397 struct resource r;
398 if (of_address_to_resource(np, 0, &r)) {
399 goto bail;
400 }
401 opaddr = r.start;
402 oplen = 0;
403 }
404
405 printk(KERN_INFO "OpenPIC at %lx\n", opaddr);
406
407 iranges = of_get_property(np, "interrupt-ranges", &len);
408 if (iranges == NULL)
409 len = 0; /* non-distributed mpic */
410 else
411 len /= 2 * sizeof(unsigned int);
412
413 /*
414 * The first pair of cells in interrupt-ranges refers to the
415 * IDU; subsequent pairs refer to the ISUs.
416 */
417 if (oplen < len) {
418 printk(KERN_ERR "Insufficient addresses for distributed"
419 " OpenPIC (%d < %d)\n", oplen, len);
420 len = oplen;
421 }
422
423 isu_size = 0;
424 if (len > 0 && iranges[1] != 0) {
425 printk(KERN_INFO "OpenPIC irqs %d..%d in IDU\n",
426 iranges[0], iranges[0] + iranges[1] - 1);
427 }
428 if (len > 1)
429 isu_size = iranges[3];
430
431 chrp_mpic = mpic_alloc(np, opaddr, MPIC_NO_RESET,
432 isu_size, 0, " MPIC ");
433 if (chrp_mpic == NULL) {
434 printk(KERN_ERR "Failed to allocate MPIC structure\n");
435 goto bail;
436 }
437 j = na - 1;
438 for (i = 1; i < len; ++i) {
439 iranges += 2;
440 j += na;
441 printk(KERN_INFO "OpenPIC irqs %d..%d in ISU at %x\n",
442 iranges[0], iranges[0] + iranges[1] - 1,
443 opprop[j]);
444 mpic_assign_isu(chrp_mpic, i - 1, opprop[j]);
445 }
446
447 mpic_init(chrp_mpic);
448 ppc_md.get_irq = mpic_get_irq;
449 bail:
450 of_node_put(root);
451 of_node_put(np);
452 }
453
454 #if defined(CONFIG_VT) && defined(CONFIG_INPUT_ADBHID) && defined(CONFIG_XMON)
455 static struct irqaction xmon_irqaction = {
456 .handler = xmon_irq,
457 .name = "XMON break",
458 };
459 #endif
460
chrp_find_8259(void)461 static void __init chrp_find_8259(void)
462 {
463 struct device_node *np, *pic = NULL;
464 unsigned long chrp_int_ack = 0;
465 unsigned int cascade_irq;
466
467 /* Look for cascade */
468 for_each_node_by_type(np, "interrupt-controller")
469 if (of_device_is_compatible(np, "chrp,iic")) {
470 pic = np;
471 break;
472 }
473 /* Ok, 8259 wasn't found. We need to handle the case where
474 * we have a pegasos that claims to be chrp but doesn't have
475 * a proper interrupt tree
476 */
477 if (pic == NULL && chrp_mpic != NULL) {
478 printk(KERN_ERR "i8259: Not found in device-tree"
479 " assuming no legacy interrupts\n");
480 return;
481 }
482
483 /* Look for intack. In a perfect world, we would look for it on
484 * the ISA bus that holds the 8259 but heh... Works that way. If
485 * we ever see a problem, we can try to re-use the pSeries code here.
486 * Also, Pegasos-type platforms don't have a proper node to start
487 * from anyway
488 */
489 for_each_node_by_name(np, "pci") {
490 const unsigned int *addrp = of_get_property(np,
491 "8259-interrupt-acknowledge", NULL);
492
493 if (addrp == NULL)
494 continue;
495 chrp_int_ack = addrp[of_n_addr_cells(np)-1];
496 break;
497 }
498 of_node_put(np);
499 if (np == NULL)
500 printk(KERN_WARNING "Cannot find PCI interrupt acknowledge"
501 " address, polling\n");
502
503 i8259_init(pic, chrp_int_ack);
504 if (ppc_md.get_irq == NULL) {
505 ppc_md.get_irq = i8259_irq;
506 irq_set_default_host(i8259_get_host());
507 }
508 if (chrp_mpic != NULL) {
509 cascade_irq = irq_of_parse_and_map(pic, 0);
510 if (!cascade_irq)
511 printk(KERN_ERR "i8259: failed to map cascade irq\n");
512 else
513 irq_set_chained_handler(cascade_irq,
514 chrp_8259_cascade);
515 }
516 }
517
chrp_init_IRQ(void)518 static void __init chrp_init_IRQ(void)
519 {
520 #if defined(CONFIG_VT) && defined(CONFIG_INPUT_ADBHID) && defined(CONFIG_XMON)
521 struct device_node *kbd;
522 #endif
523 chrp_find_openpic();
524 chrp_find_8259();
525
526 #ifdef CONFIG_SMP
527 /* Pegasos has no MPIC, those ops would make it crash. It might be an
528 * option to move setting them to after we probe the PIC though
529 */
530 if (chrp_mpic != NULL)
531 smp_ops = &chrp_smp_ops;
532 #endif /* CONFIG_SMP */
533
534 if (_chrp_type == _CHRP_Pegasos)
535 ppc_md.get_irq = i8259_irq;
536
537 #if defined(CONFIG_VT) && defined(CONFIG_INPUT_ADBHID) && defined(CONFIG_XMON)
538 /* see if there is a keyboard in the device tree
539 with a parent of type "adb" */
540 for_each_node_by_name(kbd, "keyboard")
541 if (of_node_is_type(kbd->parent, "adb"))
542 break;
543 of_node_put(kbd);
544 if (kbd)
545 setup_irq(HYDRA_INT_ADB_NMI, &xmon_irqaction);
546 #endif
547 }
548
549 static void __init
chrp_init2(void)550 chrp_init2(void)
551 {
552 #if IS_ENABLED(CONFIG_NVRAM)
553 chrp_nvram_init();
554 #endif
555
556 request_region(0x20,0x20,"pic1");
557 request_region(0xa0,0x20,"pic2");
558 request_region(0x00,0x20,"dma1");
559 request_region(0x40,0x20,"timer");
560 request_region(0x80,0x10,"dma page reg");
561 request_region(0xc0,0x20,"dma2");
562
563 if (ppc_md.progress)
564 ppc_md.progress(" Have fun! ", 0x7777);
565 }
566
chrp_probe(void)567 static int __init chrp_probe(void)
568 {
569 const char *dtype = of_get_flat_dt_prop(of_get_flat_dt_root(),
570 "device_type", NULL);
571 if (dtype == NULL)
572 return 0;
573 if (strcmp(dtype, "chrp"))
574 return 0;
575
576 ISA_DMA_THRESHOLD = ~0L;
577 DMA_MODE_READ = 0x44;
578 DMA_MODE_WRITE = 0x48;
579
580 pm_power_off = rtas_power_off;
581
582 chrp_init();
583
584 return 1;
585 }
586
define_machine(chrp)587 define_machine(chrp) {
588 .name = "CHRP",
589 .probe = chrp_probe,
590 .setup_arch = chrp_setup_arch,
591 .init = chrp_init2,
592 .show_cpuinfo = chrp_show_cpuinfo,
593 .init_IRQ = chrp_init_IRQ,
594 .restart = rtas_restart,
595 .halt = rtas_halt,
596 .time_init = chrp_time_init,
597 .set_rtc_time = chrp_set_rtc_time,
598 .get_rtc_time = chrp_get_rtc_time,
599 .calibrate_decr = generic_calibrate_decr,
600 .phys_mem_access_prot = pci_phys_mem_access_prot,
601 };
602
