1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
4 */
5
6 #include <linux/seq_file.h>
7 #include <linux/fs.h>
8 #include <linux/delay.h>
9 #include <linux/root_dev.h>
10 #include <linux/clk.h>
11 #include <linux/clocksource.h>
12 #include <linux/console.h>
13 #include <linux/module.h>
14 #include <linux/sizes.h>
15 #include <linux/cpu.h>
16 #include <linux/of_clk.h>
17 #include <linux/of_fdt.h>
18 #include <linux/of.h>
19 #include <linux/cache.h>
20 #include <uapi/linux/mount.h>
21 #include <asm/sections.h>
22 #include <asm/arcregs.h>
23 #include <asm/asserts.h>
24 #include <asm/tlb.h>
25 #include <asm/setup.h>
26 #include <asm/page.h>
27 #include <asm/irq.h>
28 #include <asm/unwind.h>
29 #include <asm/mach_desc.h>
30 #include <asm/smp.h>
31 #include <asm/dsp-impl.h>
32 #include <soc/arc/mcip.h>
33
34 #define FIX_PTR(x) __asm__ __volatile__(";" : "+r"(x))
35
36 unsigned int intr_to_DE_cnt;
37
38 /* Part of U-boot ABI: see head.S */
39 int __initdata uboot_tag;
40 int __initdata uboot_magic;
41 char __initdata *uboot_arg;
42
43 const struct machine_desc *machine_desc;
44
45 struct task_struct *_current_task[NR_CPUS]; /* For stack switching */
46
47 struct cpuinfo_arc {
48 int arcver;
49 unsigned int t0:1, t1:1;
50 struct {
51 unsigned long base;
52 unsigned int sz;
53 } iccm, dccm;
54 };
55
56 #ifdef CONFIG_ISA_ARCV2
57
58 static const struct id_to_str arc_hs_rel[] = {
59 /* ID.ARCVER, Release */
60 { 0x51, "R2.0" },
61 { 0x52, "R2.1" },
62 { 0x53, "R3.0" },
63 };
64
65 static const struct id_to_str arc_hs_ver54_rel[] = {
66 /* UARCH.MAJOR, Release */
67 { 0, "R3.10a"},
68 { 1, "R3.50a"},
69 { 2, "R3.60a"},
70 { 3, "R4.00a"},
71 { 0xFF, NULL }
72 };
73 #endif
74
75 static int
arcompact_mumbojumbo(int c,struct cpuinfo_arc * info,char * buf,int len)76 arcompact_mumbojumbo(int c, struct cpuinfo_arc *info, char *buf, int len)
77 {
78 int n = 0;
79 #ifdef CONFIG_ISA_ARCOMPACT
80 char *cpu_nm, *isa_nm = "ARCompact";
81 struct bcr_fp_arcompact fpu_sp, fpu_dp;
82 int atomic = 0, be, present;
83 int bpu_full, bpu_cache, bpu_pred;
84 struct bcr_bpu_arcompact bpu;
85 struct bcr_iccm_arcompact iccm;
86 struct bcr_dccm_arcompact dccm;
87 struct bcr_generic isa;
88
89 READ_BCR(ARC_REG_ISA_CFG_BCR, isa);
90
91 if (!isa.ver) /* ISA BCR absent, use Kconfig info */
92 atomic = IS_ENABLED(CONFIG_ARC_HAS_LLSC);
93 else {
94 /* ARC700_BUILD only has 2 bits of isa info */
95 atomic = isa.info & 1;
96 }
97
98 be = IS_ENABLED(CONFIG_CPU_BIG_ENDIAN);
99
100 if (info->arcver < 0x34)
101 cpu_nm = "ARC750";
102 else
103 cpu_nm = "ARC770";
104
105 n += scnprintf(buf + n, len - n, "processor [%d]\t: %s (%s ISA) %s%s%s\n",
106 c, cpu_nm, isa_nm,
107 IS_AVAIL2(atomic, "atomic ", CONFIG_ARC_HAS_LLSC),
108 IS_AVAIL1(be, "[Big-Endian]"));
109
110 READ_BCR(ARC_REG_FP_BCR, fpu_sp);
111 READ_BCR(ARC_REG_DPFP_BCR, fpu_dp);
112
113 if (fpu_sp.ver | fpu_dp.ver)
114 n += scnprintf(buf + n, len - n, "FPU\t\t: %s%s\n",
115 IS_AVAIL1(fpu_sp.ver, "SP "),
116 IS_AVAIL1(fpu_dp.ver, "DP "));
117
118 READ_BCR(ARC_REG_BPU_BCR, bpu);
119 bpu_full = bpu.fam ? 1 : 0;
120 bpu_cache = 256 << (bpu.ent - 1);
121 bpu_pred = 256 << (bpu.ent - 1);
122
123 n += scnprintf(buf + n, len - n,
124 "BPU\t\t: %s%s match, cache:%d, Predict Table:%d\n",
125 IS_AVAIL1(bpu_full, "full"),
126 IS_AVAIL1(!bpu_full, "partial"),
127 bpu_cache, bpu_pred);
128
129 READ_BCR(ARC_REG_ICCM_BUILD, iccm);
130 if (iccm.ver) {
131 info->iccm.sz = 4096 << iccm.sz; /* 8K to 512K */
132 info->iccm.base = iccm.base << 16;
133 }
134
135 READ_BCR(ARC_REG_DCCM_BUILD, dccm);
136 if (dccm.ver) {
137 unsigned long base;
138 info->dccm.sz = 2048 << dccm.sz; /* 2K to 256K */
139
140 base = read_aux_reg(ARC_REG_DCCM_BASE_BUILD);
141 info->dccm.base = base & ~0xF;
142 }
143
144 /* ARCompact ISA specific sanity checks */
145 present = fpu_dp.ver; /* SP has no arch visible regs */
146 CHK_OPT_STRICT(CONFIG_ARC_FPU_SAVE_RESTORE, present);
147 #endif
148 return n;
149
150 }
151
arcv2_mumbojumbo(int c,struct cpuinfo_arc * info,char * buf,int len)152 static int arcv2_mumbojumbo(int c, struct cpuinfo_arc *info, char *buf, int len)
153 {
154 int n = 0;
155 #ifdef CONFIG_ISA_ARCV2
156 const char *release, *cpu_nm, *isa_nm = "ARCv2";
157 int dual_issue = 0, dual_enb = 0, mpy_opt, present;
158 int bpu_full, bpu_cache, bpu_pred, bpu_ret_stk;
159 char mpy_nm[16], lpb_nm[32];
160 struct bcr_isa_arcv2 isa;
161 struct bcr_mpy mpy;
162 struct bcr_fp_arcv2 fpu;
163 struct bcr_bpu_arcv2 bpu;
164 struct bcr_lpb lpb;
165 struct bcr_iccm_arcv2 iccm;
166 struct bcr_dccm_arcv2 dccm;
167 struct bcr_erp erp;
168
169 /*
170 * Initial HS cores bumped AUX IDENTITY.ARCVER for each release until
171 * ARCVER 0x54 which introduced AUX MICRO_ARCH_BUILD and subsequent
172 * releases only update it.
173 */
174
175 cpu_nm = "HS38";
176
177 if (info->arcver > 0x50 && info->arcver <= 0x53) {
178 release = arc_hs_rel[info->arcver - 0x51].str;
179 } else {
180 const struct id_to_str *tbl;
181 struct bcr_uarch_build uarch;
182
183 READ_BCR(ARC_REG_MICRO_ARCH_BCR, uarch);
184
185 for (tbl = &arc_hs_ver54_rel[0]; tbl->id != 0xFF; tbl++) {
186 if (uarch.maj == tbl->id) {
187 release = tbl->str;
188 break;
189 }
190 }
191 if (uarch.prod == 4) {
192 unsigned int exec_ctrl;
193
194 cpu_nm = "HS48";
195 dual_issue = 1;
196 /* if dual issue hardware, is it enabled ? */
197 READ_BCR(AUX_EXEC_CTRL, exec_ctrl);
198 dual_enb = !(exec_ctrl & 1);
199 }
200 }
201
202 READ_BCR(ARC_REG_ISA_CFG_BCR, isa);
203
204 n += scnprintf(buf + n, len - n, "processor [%d]\t: %s %s (%s ISA) %s%s%s\n",
205 c, cpu_nm, release, isa_nm,
206 IS_AVAIL1(isa.be, "[Big-Endian]"),
207 IS_AVAIL3(dual_issue, dual_enb, " Dual-Issue "));
208
209 READ_BCR(ARC_REG_MPY_BCR, mpy);
210 mpy_opt = 2; /* stock MPY/MPYH */
211 if (mpy.dsp) /* OPT 7-9 */
212 mpy_opt = mpy.dsp + 6;
213
214 scnprintf(mpy_nm, 16, "mpy[opt %d] ", mpy_opt);
215
216 READ_BCR(ARC_REG_FP_V2_BCR, fpu);
217
218 n += scnprintf(buf + n, len - n, "ISA Extn\t: %s%s%s%s%s%s%s%s%s%s%s\n",
219 IS_AVAIL2(isa.atomic, "atomic ", CONFIG_ARC_HAS_LLSC),
220 IS_AVAIL2(isa.ldd, "ll64 ", CONFIG_ARC_HAS_LL64),
221 IS_AVAIL2(isa.unalign, "unalign ", CONFIG_ARC_USE_UNALIGNED_MEM_ACCESS),
222 IS_AVAIL1(mpy.ver, mpy_nm),
223 IS_AVAIL1(isa.div_rem, "div_rem "),
224 IS_AVAIL1((fpu.sp | fpu.dp), " FPU:"),
225 IS_AVAIL1(fpu.sp, " sp"),
226 IS_AVAIL1(fpu.dp, " dp"));
227
228 READ_BCR(ARC_REG_BPU_BCR, bpu);
229 bpu_full = bpu.ft;
230 bpu_cache = 256 << bpu.bce;
231 bpu_pred = 2048 << bpu.pte;
232 bpu_ret_stk = 4 << bpu.rse;
233
234 READ_BCR(ARC_REG_LPB_BUILD, lpb);
235 if (lpb.ver) {
236 unsigned int ctl;
237 ctl = read_aux_reg(ARC_REG_LPB_CTRL);
238
239 scnprintf(lpb_nm, sizeof(lpb_nm), " Loop Buffer:%d %s",
240 lpb.entries, IS_DISABLED_RUN(!ctl));
241 }
242
243 n += scnprintf(buf + n, len - n,
244 "BPU\t\t: %s%s match, cache:%d, Predict Table:%d Return stk: %d%s\n",
245 IS_AVAIL1(bpu_full, "full"),
246 IS_AVAIL1(!bpu_full, "partial"),
247 bpu_cache, bpu_pred, bpu_ret_stk,
248 lpb_nm);
249
250 READ_BCR(ARC_REG_ICCM_BUILD, iccm);
251 if (iccm.ver) {
252 unsigned long base;
253 info->iccm.sz = 256 << iccm.sz00; /* 512B to 16M */
254 if (iccm.sz00 == 0xF && iccm.sz01 > 0)
255 info->iccm.sz <<= iccm.sz01;
256 base = read_aux_reg(ARC_REG_AUX_ICCM);
257 info->iccm.base = base & 0xF0000000;
258 }
259
260 READ_BCR(ARC_REG_DCCM_BUILD, dccm);
261 if (dccm.ver) {
262 unsigned long base;
263 info->dccm.sz = 256 << dccm.sz0;
264 if (dccm.sz0 == 0xF && dccm.sz1 > 0)
265 info->dccm.sz <<= dccm.sz1;
266 base = read_aux_reg(ARC_REG_AUX_DCCM);
267 info->dccm.base = base & 0xF0000000;
268 }
269
270 /* Error Protection: ECC/Parity */
271 READ_BCR(ARC_REG_ERP_BUILD, erp);
272 if (erp.ver) {
273 struct ctl_erp ctl;
274 READ_BCR(ARC_REG_ERP_CTRL, ctl);
275 /* inverted bits: 0 means enabled */
276 n += scnprintf(buf + n, len - n, "Extn [ECC]\t: %s%s%s%s%s%s\n",
277 IS_AVAIL3(erp.ic, !ctl.dpi, "IC "),
278 IS_AVAIL3(erp.dc, !ctl.dpd, "DC "),
279 IS_AVAIL3(erp.mmu, !ctl.mpd, "MMU "));
280 }
281
282 /* ARCv2 ISA specific sanity checks */
283 present = fpu.sp | fpu.dp | mpy.dsp; /* DSP and/or FPU */
284 CHK_OPT_STRICT(CONFIG_ARC_HAS_ACCL_REGS, present);
285
286 dsp_config_check();
287 #endif
288 return n;
289 }
290
arc_cpu_mumbojumbo(int c,struct cpuinfo_arc * info,char * buf,int len)291 static char *arc_cpu_mumbojumbo(int c, struct cpuinfo_arc *info, char *buf, int len)
292 {
293 struct bcr_identity ident;
294 struct bcr_timer timer;
295 struct bcr_generic bcr;
296 struct mcip_bcr mp;
297 struct bcr_actionpoint ap;
298 unsigned long vec_base;
299 int ap_num, ap_full, smart, rtt, n;
300
301 memset(info, 0, sizeof(struct cpuinfo_arc));
302
303 READ_BCR(AUX_IDENTITY, ident);
304 info->arcver = ident.family;
305
306 n = scnprintf(buf, len,
307 "\nIDENTITY\t: ARCVER [%#02x] ARCNUM [%#02x] CHIPID [%#4x]\n",
308 ident.family, ident.cpu_id, ident.chip_id);
309
310 if (is_isa_arcompact()) {
311 n += arcompact_mumbojumbo(c, info, buf + n, len - n);
312 } else if (is_isa_arcv2()){
313 n += arcv2_mumbojumbo(c, info, buf + n, len - n);
314 }
315
316 n += arc_mmu_mumbojumbo(c, buf + n, len - n);
317 n += arc_cache_mumbojumbo(c, buf + n, len - n);
318
319 READ_BCR(ARC_REG_TIMERS_BCR, timer);
320 info->t0 = timer.t0;
321 info->t1 = timer.t1;
322
323 READ_BCR(ARC_REG_MCIP_BCR, mp);
324 vec_base = read_aux_reg(AUX_INTR_VEC_BASE);
325
326 n += scnprintf(buf + n, len - n,
327 "Timers\t\t: %s%s%s%s%s%s\nVector Table\t: %#lx\n",
328 IS_AVAIL1(timer.t0, "Timer0 "),
329 IS_AVAIL1(timer.t1, "Timer1 "),
330 IS_AVAIL2(timer.rtc, "RTC [UP 64-bit] ", CONFIG_ARC_TIMERS_64BIT),
331 IS_AVAIL2(mp.gfrc, "GFRC [SMP 64-bit] ", CONFIG_ARC_TIMERS_64BIT),
332 vec_base);
333
334 READ_BCR(ARC_REG_AP_BCR, ap);
335 if (ap.ver) {
336 ap_num = 2 << ap.num;
337 ap_full = !ap.min;
338 }
339
340 READ_BCR(ARC_REG_SMART_BCR, bcr);
341 smart = bcr.ver ? 1 : 0;
342
343 READ_BCR(ARC_REG_RTT_BCR, bcr);
344 rtt = bcr.ver ? 1 : 0;
345
346 if (ap.ver | smart | rtt) {
347 n += scnprintf(buf + n, len - n, "DEBUG\t\t: %s%s",
348 IS_AVAIL1(smart, "smaRT "),
349 IS_AVAIL1(rtt, "RTT "));
350 if (ap.ver) {
351 n += scnprintf(buf + n, len - n, "ActionPoint %d/%s",
352 ap_num,
353 ap_full ? "full":"min");
354 }
355 n += scnprintf(buf + n, len - n, "\n");
356 }
357
358 if (info->dccm.sz || info->iccm.sz)
359 n += scnprintf(buf + n, len - n,
360 "Extn [CCM]\t: DCCM @ %lx, %d KB / ICCM: @ %lx, %d KB\n",
361 info->dccm.base, TO_KB(info->dccm.sz),
362 info->iccm.base, TO_KB(info->iccm.sz));
363
364 return buf;
365 }
366
chk_opt_strict(char * opt_name,bool hw_exists,bool opt_ena)367 void chk_opt_strict(char *opt_name, bool hw_exists, bool opt_ena)
368 {
369 if (hw_exists && !opt_ena)
370 pr_warn(" ! Enable %s for working apps\n", opt_name);
371 else if (!hw_exists && opt_ena)
372 panic("Disable %s, hardware NOT present\n", opt_name);
373 }
374
chk_opt_weak(char * opt_name,bool hw_exists,bool opt_ena)375 void chk_opt_weak(char *opt_name, bool hw_exists, bool opt_ena)
376 {
377 if (!hw_exists && opt_ena)
378 panic("Disable %s, hardware NOT present\n", opt_name);
379 }
380
381 /*
382 * ISA agnostic sanity checks
383 */
arc_chk_core_config(struct cpuinfo_arc * info)384 static void arc_chk_core_config(struct cpuinfo_arc *info)
385 {
386 if (!info->t0)
387 panic("Timer0 is not present!\n");
388
389 if (!info->t1)
390 panic("Timer1 is not present!\n");
391
392 #ifdef CONFIG_ARC_HAS_DCCM
393 /*
394 * DCCM can be arbit placed in hardware.
395 * Make sure it's placement/sz matches what Linux is built with
396 */
397 if ((unsigned int)__arc_dccm_base != info->dccm.base)
398 panic("Linux built with incorrect DCCM Base address\n");
399
400 if (CONFIG_ARC_DCCM_SZ * SZ_1K != info->dccm.sz)
401 panic("Linux built with incorrect DCCM Size\n");
402 #endif
403
404 #ifdef CONFIG_ARC_HAS_ICCM
405 if (CONFIG_ARC_ICCM_SZ * SZ_1K != info->iccm.sz)
406 panic("Linux built with incorrect ICCM Size\n");
407 #endif
408 }
409
410 /*
411 * Initialize and setup the processor core
412 * This is called by all the CPUs thus should not do special case stuff
413 * such as only for boot CPU etc
414 */
415
setup_processor(void)416 void setup_processor(void)
417 {
418 struct cpuinfo_arc info;
419 int c = smp_processor_id();
420 char str[512];
421
422 pr_info("%s", arc_cpu_mumbojumbo(c, &info, str, sizeof(str)));
423 pr_info("%s", arc_platform_smp_cpuinfo());
424
425 arc_chk_core_config(&info);
426
427 arc_init_IRQ();
428 arc_mmu_init();
429 arc_cache_init();
430
431 }
432
uboot_arg_invalid(unsigned long addr)433 static inline bool uboot_arg_invalid(unsigned long addr)
434 {
435 /*
436 * Check that it is a untranslated address (although MMU is not enabled
437 * yet, it being a high address ensures this is not by fluke)
438 */
439 if (addr < PAGE_OFFSET)
440 return true;
441
442 /* Check that address doesn't clobber resident kernel image */
443 return addr >= (unsigned long)_stext && addr <= (unsigned long)_end;
444 }
445
446 #define IGNORE_ARGS "Ignore U-boot args: "
447
448 /* uboot_tag values for U-boot - kernel ABI revision 0; see head.S */
449 #define UBOOT_TAG_NONE 0
450 #define UBOOT_TAG_CMDLINE 1
451 #define UBOOT_TAG_DTB 2
452 /* We always pass 0 as magic from U-boot */
453 #define UBOOT_MAGIC_VALUE 0
454
handle_uboot_args(void)455 void __init handle_uboot_args(void)
456 {
457 bool use_embedded_dtb = true;
458 bool append_cmdline = false;
459
460 /* check that we know this tag */
461 if (uboot_tag != UBOOT_TAG_NONE &&
462 uboot_tag != UBOOT_TAG_CMDLINE &&
463 uboot_tag != UBOOT_TAG_DTB) {
464 pr_warn(IGNORE_ARGS "invalid uboot tag: '%08x'\n", uboot_tag);
465 goto ignore_uboot_args;
466 }
467
468 if (uboot_magic != UBOOT_MAGIC_VALUE) {
469 pr_warn(IGNORE_ARGS "non zero uboot magic\n");
470 goto ignore_uboot_args;
471 }
472
473 if (uboot_tag != UBOOT_TAG_NONE &&
474 uboot_arg_invalid((unsigned long)uboot_arg)) {
475 pr_warn(IGNORE_ARGS "invalid uboot arg: '%px'\n", uboot_arg);
476 goto ignore_uboot_args;
477 }
478
479 /* see if U-boot passed an external Device Tree blob */
480 if (uboot_tag == UBOOT_TAG_DTB) {
481 machine_desc = setup_machine_fdt((void *)uboot_arg);
482
483 /* external Device Tree blob is invalid - use embedded one */
484 use_embedded_dtb = !machine_desc;
485 }
486
487 if (uboot_tag == UBOOT_TAG_CMDLINE)
488 append_cmdline = true;
489
490 ignore_uboot_args:
491
492 if (use_embedded_dtb) {
493 machine_desc = setup_machine_fdt(__dtb_start);
494 if (!machine_desc)
495 panic("Embedded DT invalid\n");
496 }
497
498 /*
499 * NOTE: @boot_command_line is populated by setup_machine_fdt() so this
500 * append processing can only happen after.
501 */
502 if (append_cmdline) {
503 /* Ensure a whitespace between the 2 cmdlines */
504 strlcat(boot_command_line, " ", COMMAND_LINE_SIZE);
505 strlcat(boot_command_line, uboot_arg, COMMAND_LINE_SIZE);
506 }
507 }
508
setup_arch(char ** cmdline_p)509 void __init setup_arch(char **cmdline_p)
510 {
511 handle_uboot_args();
512
513 /* Save unparsed command line copy for /proc/cmdline */
514 *cmdline_p = boot_command_line;
515
516 /* To force early parsing of things like mem=xxx */
517 parse_early_param();
518
519 /* Platform/board specific: e.g. early console registration */
520 if (machine_desc->init_early)
521 machine_desc->init_early();
522
523 smp_init_cpus();
524
525 setup_processor();
526 setup_arch_memory();
527
528 /* copy flat DT out of .init and then unflatten it */
529 unflatten_and_copy_device_tree();
530
531 /* Can be issue if someone passes cmd line arg "ro"
532 * But that is unlikely so keeping it as it is
533 */
534 root_mountflags &= ~MS_RDONLY;
535
536 arc_unwind_init();
537 }
538
539 /*
540 * Called from start_kernel() - boot CPU only
541 */
time_init(void)542 void __init time_init(void)
543 {
544 of_clk_init(NULL);
545 timer_probe();
546 }
547
customize_machine(void)548 static int __init customize_machine(void)
549 {
550 if (machine_desc->init_machine)
551 machine_desc->init_machine();
552
553 return 0;
554 }
555 arch_initcall(customize_machine);
556
init_late_machine(void)557 static int __init init_late_machine(void)
558 {
559 if (machine_desc->init_late)
560 machine_desc->init_late();
561
562 return 0;
563 }
564 late_initcall(init_late_machine);
565 /*
566 * Get CPU information for use by the procfs.
567 */
568
569 #define cpu_to_ptr(c) ((void *)(0xFFFF0000 | (unsigned int)(c)))
570 #define ptr_to_cpu(p) (~0xFFFF0000UL & (unsigned int)(p))
571
show_cpuinfo(struct seq_file * m,void * v)572 static int show_cpuinfo(struct seq_file *m, void *v)
573 {
574 char *str;
575 int cpu_id = ptr_to_cpu(v);
576 struct device *cpu_dev = get_cpu_device(cpu_id);
577 struct cpuinfo_arc info;
578 struct clk *cpu_clk;
579 unsigned long freq = 0;
580
581 if (!cpu_online(cpu_id)) {
582 seq_printf(m, "processor [%d]\t: Offline\n", cpu_id);
583 goto done;
584 }
585
586 str = (char *)__get_free_page(GFP_KERNEL);
587 if (!str)
588 goto done;
589
590 seq_printf(m, arc_cpu_mumbojumbo(cpu_id, &info, str, PAGE_SIZE));
591
592 cpu_clk = clk_get(cpu_dev, NULL);
593 if (IS_ERR(cpu_clk)) {
594 seq_printf(m, "CPU speed \t: Cannot get clock for processor [%d]\n",
595 cpu_id);
596 } else {
597 freq = clk_get_rate(cpu_clk);
598 }
599 if (freq)
600 seq_printf(m, "CPU speed\t: %lu.%02lu Mhz\n",
601 freq / 1000000, (freq / 10000) % 100);
602
603 seq_printf(m, "Bogo MIPS\t: %lu.%02lu\n",
604 loops_per_jiffy / (500000 / HZ),
605 (loops_per_jiffy / (5000 / HZ)) % 100);
606
607 seq_printf(m, arc_platform_smp_cpuinfo());
608
609 free_page((unsigned long)str);
610 done:
611 seq_printf(m, "\n");
612
613 return 0;
614 }
615
c_start(struct seq_file * m,loff_t * pos)616 static void *c_start(struct seq_file *m, loff_t *pos)
617 {
618 /*
619 * Callback returns cpu-id to iterator for show routine, NULL to stop.
620 * However since NULL is also a valid cpu-id (0), we use a round-about
621 * way to pass it w/o having to kmalloc/free a 2 byte string.
622 * Encode cpu-id as 0xFFcccc, which is decoded by show routine.
623 */
624 return *pos < nr_cpu_ids ? cpu_to_ptr(*pos) : NULL;
625 }
626
c_next(struct seq_file * m,void * v,loff_t * pos)627 static void *c_next(struct seq_file *m, void *v, loff_t *pos)
628 {
629 ++*pos;
630 return c_start(m, pos);
631 }
632
c_stop(struct seq_file * m,void * v)633 static void c_stop(struct seq_file *m, void *v)
634 {
635 }
636
637 const struct seq_operations cpuinfo_op = {
638 .start = c_start,
639 .next = c_next,
640 .stop = c_stop,
641 .show = show_cpuinfo
642 };
643
644 static DEFINE_PER_CPU(struct cpu, cpu_topology);
645
topology_init(void)646 static int __init topology_init(void)
647 {
648 int cpu;
649
650 for_each_present_cpu(cpu)
651 register_cpu(&per_cpu(cpu_topology, cpu), cpu);
652
653 return 0;
654 }
655
656 subsys_initcall(topology_init);
657
