1 // SPDX-License-Identifier: GPL-2.0
2 /* Marvell OcteonTx2 CGX driver
3 *
4 * Copyright (C) 2018 Marvell.
5 *
6 */
7
8 #include <linux/acpi.h>
9 #include <linux/module.h>
10 #include <linux/interrupt.h>
11 #include <linux/pci.h>
12 #include <linux/netdevice.h>
13 #include <linux/etherdevice.h>
14 #include <linux/ethtool.h>
15 #include <linux/phy.h>
16 #include <linux/of.h>
17 #include <linux/of_mdio.h>
18 #include <linux/of_net.h>
19
20 #include "cgx.h"
21 #include "rvu.h"
22 #include "lmac_common.h"
23
24 #define DRV_NAME "Marvell-CGX/RPM"
25 #define DRV_STRING "Marvell CGX/RPM Driver"
26
27 static LIST_HEAD(cgx_list);
28
29 /* Convert firmware speed encoding to user format(Mbps) */
30 static const u32 cgx_speed_mbps[CGX_LINK_SPEED_MAX] = {
31 [CGX_LINK_NONE] = 0,
32 [CGX_LINK_10M] = 10,
33 [CGX_LINK_100M] = 100,
34 [CGX_LINK_1G] = 1000,
35 [CGX_LINK_2HG] = 2500,
36 [CGX_LINK_5G] = 5000,
37 [CGX_LINK_10G] = 10000,
38 [CGX_LINK_20G] = 20000,
39 [CGX_LINK_25G] = 25000,
40 [CGX_LINK_40G] = 40000,
41 [CGX_LINK_50G] = 50000,
42 [CGX_LINK_80G] = 80000,
43 [CGX_LINK_100G] = 100000,
44 };
45
46 /* Convert firmware lmac type encoding to string */
47 static const char *cgx_lmactype_string[LMAC_MODE_MAX] = {
48 [LMAC_MODE_SGMII] = "SGMII",
49 [LMAC_MODE_XAUI] = "XAUI",
50 [LMAC_MODE_RXAUI] = "RXAUI",
51 [LMAC_MODE_10G_R] = "10G_R",
52 [LMAC_MODE_40G_R] = "40G_R",
53 [LMAC_MODE_QSGMII] = "QSGMII",
54 [LMAC_MODE_25G_R] = "25G_R",
55 [LMAC_MODE_50G_R] = "50G_R",
56 [LMAC_MODE_100G_R] = "100G_R",
57 [LMAC_MODE_USXGMII] = "USXGMII",
58 };
59
60 /* CGX PHY management internal APIs */
61 static int cgx_fwi_link_change(struct cgx *cgx, int lmac_id, bool en);
62
63 /* Supported devices */
64 static const struct pci_device_id cgx_id_table[] = {
65 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_CGX) },
66 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_CN10K_RPM) },
67 { 0, } /* end of table */
68 };
69
70 MODULE_DEVICE_TABLE(pci, cgx_id_table);
71
is_dev_rpm(void * cgxd)72 static bool is_dev_rpm(void *cgxd)
73 {
74 struct cgx *cgx = cgxd;
75
76 return (cgx->pdev->device == PCI_DEVID_CN10K_RPM);
77 }
78
is_lmac_valid(struct cgx * cgx,int lmac_id)79 bool is_lmac_valid(struct cgx *cgx, int lmac_id)
80 {
81 if (!cgx || lmac_id < 0 || lmac_id >= MAX_LMAC_PER_CGX)
82 return false;
83 return test_bit(lmac_id, &cgx->lmac_bmap);
84 }
85
86 /* Helper function to get sequential index
87 * given the enabled LMAC of a CGX
88 */
get_sequence_id_of_lmac(struct cgx * cgx,int lmac_id)89 static int get_sequence_id_of_lmac(struct cgx *cgx, int lmac_id)
90 {
91 int tmp, id = 0;
92
93 for_each_set_bit(tmp, &cgx->lmac_bmap, MAX_LMAC_PER_CGX) {
94 if (tmp == lmac_id)
95 break;
96 id++;
97 }
98
99 return id;
100 }
101
get_mac_ops(void * cgxd)102 struct mac_ops *get_mac_ops(void *cgxd)
103 {
104 if (!cgxd)
105 return cgxd;
106
107 return ((struct cgx *)cgxd)->mac_ops;
108 }
109
cgx_write(struct cgx * cgx,u64 lmac,u64 offset,u64 val)110 void cgx_write(struct cgx *cgx, u64 lmac, u64 offset, u64 val)
111 {
112 writeq(val, cgx->reg_base + (lmac << cgx->mac_ops->lmac_offset) +
113 offset);
114 }
115
cgx_read(struct cgx * cgx,u64 lmac,u64 offset)116 u64 cgx_read(struct cgx *cgx, u64 lmac, u64 offset)
117 {
118 return readq(cgx->reg_base + (lmac << cgx->mac_ops->lmac_offset) +
119 offset);
120 }
121
lmac_pdata(u8 lmac_id,struct cgx * cgx)122 struct lmac *lmac_pdata(u8 lmac_id, struct cgx *cgx)
123 {
124 if (!cgx || lmac_id >= MAX_LMAC_PER_CGX)
125 return NULL;
126
127 return cgx->lmac_idmap[lmac_id];
128 }
129
cgx_get_cgxcnt_max(void)130 int cgx_get_cgxcnt_max(void)
131 {
132 struct cgx *cgx_dev;
133 int idmax = -ENODEV;
134
135 list_for_each_entry(cgx_dev, &cgx_list, cgx_list)
136 if (cgx_dev->cgx_id > idmax)
137 idmax = cgx_dev->cgx_id;
138
139 if (idmax < 0)
140 return 0;
141
142 return idmax + 1;
143 }
144
cgx_get_lmac_cnt(void * cgxd)145 int cgx_get_lmac_cnt(void *cgxd)
146 {
147 struct cgx *cgx = cgxd;
148
149 if (!cgx)
150 return -ENODEV;
151
152 return cgx->lmac_count;
153 }
154
cgx_get_pdata(int cgx_id)155 void *cgx_get_pdata(int cgx_id)
156 {
157 struct cgx *cgx_dev;
158
159 list_for_each_entry(cgx_dev, &cgx_list, cgx_list) {
160 if (cgx_dev->cgx_id == cgx_id)
161 return cgx_dev;
162 }
163 return NULL;
164 }
165
cgx_lmac_write(int cgx_id,int lmac_id,u64 offset,u64 val)166 void cgx_lmac_write(int cgx_id, int lmac_id, u64 offset, u64 val)
167 {
168 struct cgx *cgx_dev = cgx_get_pdata(cgx_id);
169
170 cgx_write(cgx_dev, lmac_id, offset, val);
171 }
172
cgx_lmac_read(int cgx_id,int lmac_id,u64 offset)173 u64 cgx_lmac_read(int cgx_id, int lmac_id, u64 offset)
174 {
175 struct cgx *cgx_dev = cgx_get_pdata(cgx_id);
176
177 return cgx_read(cgx_dev, lmac_id, offset);
178 }
179
cgx_get_cgxid(void * cgxd)180 int cgx_get_cgxid(void *cgxd)
181 {
182 struct cgx *cgx = cgxd;
183
184 if (!cgx)
185 return -EINVAL;
186
187 return cgx->cgx_id;
188 }
189
cgx_lmac_get_p2x(int cgx_id,int lmac_id)190 u8 cgx_lmac_get_p2x(int cgx_id, int lmac_id)
191 {
192 struct cgx *cgx_dev = cgx_get_pdata(cgx_id);
193 u64 cfg;
194
195 cfg = cgx_read(cgx_dev, lmac_id, CGXX_CMRX_CFG);
196
197 return (cfg & CMR_P2X_SEL_MASK) >> CMR_P2X_SEL_SHIFT;
198 }
199
200 /* Ensure the required lock for event queue(where asynchronous events are
201 * posted) is acquired before calling this API. Else an asynchronous event(with
202 * latest link status) can reach the destination before this function returns
203 * and could make the link status appear wrong.
204 */
cgx_get_link_info(void * cgxd,int lmac_id,struct cgx_link_user_info * linfo)205 int cgx_get_link_info(void *cgxd, int lmac_id,
206 struct cgx_link_user_info *linfo)
207 {
208 struct lmac *lmac = lmac_pdata(lmac_id, cgxd);
209
210 if (!lmac)
211 return -ENODEV;
212
213 *linfo = lmac->link_info;
214 return 0;
215 }
216
mac2u64(u8 * mac_addr)217 static u64 mac2u64 (u8 *mac_addr)
218 {
219 u64 mac = 0;
220 int index;
221
222 for (index = ETH_ALEN - 1; index >= 0; index--)
223 mac |= ((u64)*mac_addr++) << (8 * index);
224 return mac;
225 }
226
cfg2mac(u64 cfg,u8 * mac_addr)227 static void cfg2mac(u64 cfg, u8 *mac_addr)
228 {
229 int i, index = 0;
230
231 for (i = ETH_ALEN - 1; i >= 0; i--, index++)
232 mac_addr[i] = (cfg >> (8 * index)) & 0xFF;
233 }
234
cgx_lmac_addr_set(u8 cgx_id,u8 lmac_id,u8 * mac_addr)235 int cgx_lmac_addr_set(u8 cgx_id, u8 lmac_id, u8 *mac_addr)
236 {
237 struct cgx *cgx_dev = cgx_get_pdata(cgx_id);
238 struct lmac *lmac = lmac_pdata(lmac_id, cgx_dev);
239 struct mac_ops *mac_ops;
240 int index, id;
241 u64 cfg;
242
243 /* access mac_ops to know csr_offset */
244 mac_ops = cgx_dev->mac_ops;
245
246 /* copy 6bytes from macaddr */
247 /* memcpy(&cfg, mac_addr, 6); */
248
249 cfg = mac2u64 (mac_addr);
250
251 id = get_sequence_id_of_lmac(cgx_dev, lmac_id);
252
253 index = id * lmac->mac_to_index_bmap.max;
254
255 cgx_write(cgx_dev, 0, (CGXX_CMRX_RX_DMAC_CAM0 + (index * 0x8)),
256 cfg | CGX_DMAC_CAM_ADDR_ENABLE | ((u64)lmac_id << 49));
257
258 cfg = cgx_read(cgx_dev, lmac_id, CGXX_CMRX_RX_DMAC_CTL0);
259 cfg |= (CGX_DMAC_CTL0_CAM_ENABLE | CGX_DMAC_BCAST_MODE |
260 CGX_DMAC_MCAST_MODE);
261 cgx_write(cgx_dev, lmac_id, CGXX_CMRX_RX_DMAC_CTL0, cfg);
262
263 return 0;
264 }
265
cgx_read_dmac_ctrl(void * cgxd,int lmac_id)266 u64 cgx_read_dmac_ctrl(void *cgxd, int lmac_id)
267 {
268 struct mac_ops *mac_ops;
269 struct cgx *cgx = cgxd;
270
271 if (!cgxd || !is_lmac_valid(cgxd, lmac_id))
272 return 0;
273
274 cgx = cgxd;
275 /* Get mac_ops to know csr offset */
276 mac_ops = cgx->mac_ops;
277
278 return cgx_read(cgxd, lmac_id, CGXX_CMRX_RX_DMAC_CTL0);
279 }
280
cgx_read_dmac_entry(void * cgxd,int index)281 u64 cgx_read_dmac_entry(void *cgxd, int index)
282 {
283 struct mac_ops *mac_ops;
284 struct cgx *cgx;
285
286 if (!cgxd)
287 return 0;
288
289 cgx = cgxd;
290 mac_ops = cgx->mac_ops;
291 return cgx_read(cgx, 0, (CGXX_CMRX_RX_DMAC_CAM0 + (index * 8)));
292 }
293
cgx_lmac_addr_add(u8 cgx_id,u8 lmac_id,u8 * mac_addr)294 int cgx_lmac_addr_add(u8 cgx_id, u8 lmac_id, u8 *mac_addr)
295 {
296 struct cgx *cgx_dev = cgx_get_pdata(cgx_id);
297 struct lmac *lmac = lmac_pdata(lmac_id, cgx_dev);
298 struct mac_ops *mac_ops;
299 int index, idx;
300 u64 cfg = 0;
301 int id;
302
303 if (!lmac)
304 return -ENODEV;
305
306 mac_ops = cgx_dev->mac_ops;
307 /* Get available index where entry is to be installed */
308 idx = rvu_alloc_rsrc(&lmac->mac_to_index_bmap);
309 if (idx < 0)
310 return idx;
311
312 id = get_sequence_id_of_lmac(cgx_dev, lmac_id);
313
314 index = id * lmac->mac_to_index_bmap.max + idx;
315
316 cfg = mac2u64 (mac_addr);
317 cfg |= CGX_DMAC_CAM_ADDR_ENABLE;
318 cfg |= ((u64)lmac_id << 49);
319 cgx_write(cgx_dev, 0, (CGXX_CMRX_RX_DMAC_CAM0 + (index * 0x8)), cfg);
320
321 cfg = cgx_read(cgx_dev, lmac_id, CGXX_CMRX_RX_DMAC_CTL0);
322 cfg |= (CGX_DMAC_BCAST_MODE | CGX_DMAC_CAM_ACCEPT);
323
324 if (is_multicast_ether_addr(mac_addr)) {
325 cfg &= ~GENMASK_ULL(2, 1);
326 cfg |= CGX_DMAC_MCAST_MODE_CAM;
327 lmac->mcast_filters_count++;
328 } else if (!lmac->mcast_filters_count) {
329 cfg |= CGX_DMAC_MCAST_MODE;
330 }
331
332 cgx_write(cgx_dev, lmac_id, CGXX_CMRX_RX_DMAC_CTL0, cfg);
333
334 return idx;
335 }
336
cgx_lmac_addr_reset(u8 cgx_id,u8 lmac_id)337 int cgx_lmac_addr_reset(u8 cgx_id, u8 lmac_id)
338 {
339 struct cgx *cgx_dev = cgx_get_pdata(cgx_id);
340 struct lmac *lmac = lmac_pdata(lmac_id, cgx_dev);
341 struct mac_ops *mac_ops;
342 u8 index = 0, id;
343 u64 cfg;
344
345 if (!lmac)
346 return -ENODEV;
347
348 mac_ops = cgx_dev->mac_ops;
349 /* Restore index 0 to its default init value as done during
350 * cgx_lmac_init
351 */
352 set_bit(0, lmac->mac_to_index_bmap.bmap);
353
354 id = get_sequence_id_of_lmac(cgx_dev, lmac_id);
355
356 index = id * lmac->mac_to_index_bmap.max + index;
357 cgx_write(cgx_dev, 0, (CGXX_CMRX_RX_DMAC_CAM0 + (index * 0x8)), 0);
358
359 /* Reset CGXX_CMRX_RX_DMAC_CTL0 register to default state */
360 cfg = cgx_read(cgx_dev, lmac_id, CGXX_CMRX_RX_DMAC_CTL0);
361 cfg &= ~CGX_DMAC_CAM_ACCEPT;
362 cfg |= (CGX_DMAC_BCAST_MODE | CGX_DMAC_MCAST_MODE);
363 cgx_write(cgx_dev, lmac_id, CGXX_CMRX_RX_DMAC_CTL0, cfg);
364
365 return 0;
366 }
367
368 /* Allows caller to change macaddress associated with index
369 * in dmac filter table including index 0 reserved for
370 * interface mac address
371 */
cgx_lmac_addr_update(u8 cgx_id,u8 lmac_id,u8 * mac_addr,u8 index)372 int cgx_lmac_addr_update(u8 cgx_id, u8 lmac_id, u8 *mac_addr, u8 index)
373 {
374 struct cgx *cgx_dev = cgx_get_pdata(cgx_id);
375 struct mac_ops *mac_ops;
376 struct lmac *lmac;
377 u64 cfg;
378 int id;
379
380 lmac = lmac_pdata(lmac_id, cgx_dev);
381 if (!lmac)
382 return -ENODEV;
383
384 mac_ops = cgx_dev->mac_ops;
385 /* Validate the index */
386 if (index >= lmac->mac_to_index_bmap.max)
387 return -EINVAL;
388
389 /* ensure index is already set */
390 if (!test_bit(index, lmac->mac_to_index_bmap.bmap))
391 return -EINVAL;
392
393 id = get_sequence_id_of_lmac(cgx_dev, lmac_id);
394
395 index = id * lmac->mac_to_index_bmap.max + index;
396
397 cfg = cgx_read(cgx_dev, 0, (CGXX_CMRX_RX_DMAC_CAM0 + (index * 0x8)));
398 cfg &= ~CGX_RX_DMAC_ADR_MASK;
399 cfg |= mac2u64 (mac_addr);
400
401 cgx_write(cgx_dev, 0, (CGXX_CMRX_RX_DMAC_CAM0 + (index * 0x8)), cfg);
402 return 0;
403 }
404
cgx_lmac_addr_del(u8 cgx_id,u8 lmac_id,u8 index)405 int cgx_lmac_addr_del(u8 cgx_id, u8 lmac_id, u8 index)
406 {
407 struct cgx *cgx_dev = cgx_get_pdata(cgx_id);
408 struct lmac *lmac = lmac_pdata(lmac_id, cgx_dev);
409 struct mac_ops *mac_ops;
410 u8 mac[ETH_ALEN];
411 u64 cfg;
412 int id;
413
414 if (!lmac)
415 return -ENODEV;
416
417 mac_ops = cgx_dev->mac_ops;
418 /* Validate the index */
419 if (index >= lmac->mac_to_index_bmap.max)
420 return -EINVAL;
421
422 /* Skip deletion for reserved index i.e. index 0 */
423 if (index == 0)
424 return 0;
425
426 rvu_free_rsrc(&lmac->mac_to_index_bmap, index);
427
428 id = get_sequence_id_of_lmac(cgx_dev, lmac_id);
429
430 index = id * lmac->mac_to_index_bmap.max + index;
431
432 /* Read MAC address to check whether it is ucast or mcast */
433 cfg = cgx_read(cgx_dev, 0, (CGXX_CMRX_RX_DMAC_CAM0 + (index * 0x8)));
434
435 cfg2mac(cfg, mac);
436 if (is_multicast_ether_addr(mac))
437 lmac->mcast_filters_count--;
438
439 if (!lmac->mcast_filters_count) {
440 cfg = cgx_read(cgx_dev, lmac_id, CGXX_CMRX_RX_DMAC_CTL0);
441 cfg &= ~GENMASK_ULL(2, 1);
442 cfg |= CGX_DMAC_MCAST_MODE;
443 cgx_write(cgx_dev, lmac_id, CGXX_CMRX_RX_DMAC_CTL0, cfg);
444 }
445
446 cgx_write(cgx_dev, 0, (CGXX_CMRX_RX_DMAC_CAM0 + (index * 0x8)), 0);
447
448 return 0;
449 }
450
cgx_lmac_addr_max_entries_get(u8 cgx_id,u8 lmac_id)451 int cgx_lmac_addr_max_entries_get(u8 cgx_id, u8 lmac_id)
452 {
453 struct cgx *cgx_dev = cgx_get_pdata(cgx_id);
454 struct lmac *lmac = lmac_pdata(lmac_id, cgx_dev);
455
456 if (lmac)
457 return lmac->mac_to_index_bmap.max;
458
459 return 0;
460 }
461
cgx_lmac_addr_get(u8 cgx_id,u8 lmac_id)462 u64 cgx_lmac_addr_get(u8 cgx_id, u8 lmac_id)
463 {
464 struct cgx *cgx_dev = cgx_get_pdata(cgx_id);
465 struct lmac *lmac = lmac_pdata(lmac_id, cgx_dev);
466 struct mac_ops *mac_ops;
467 int index;
468 u64 cfg;
469 int id;
470
471 mac_ops = cgx_dev->mac_ops;
472
473 id = get_sequence_id_of_lmac(cgx_dev, lmac_id);
474
475 index = id * lmac->mac_to_index_bmap.max;
476
477 cfg = cgx_read(cgx_dev, 0, CGXX_CMRX_RX_DMAC_CAM0 + index * 0x8);
478 return cfg & CGX_RX_DMAC_ADR_MASK;
479 }
480
cgx_set_pkind(void * cgxd,u8 lmac_id,int pkind)481 int cgx_set_pkind(void *cgxd, u8 lmac_id, int pkind)
482 {
483 struct cgx *cgx = cgxd;
484
485 if (!is_lmac_valid(cgx, lmac_id))
486 return -ENODEV;
487
488 cgx_write(cgx, lmac_id, CGXX_CMRX_RX_ID_MAP, (pkind & 0x3F));
489 return 0;
490 }
491
cgx_get_lmac_type(void * cgxd,int lmac_id)492 static u8 cgx_get_lmac_type(void *cgxd, int lmac_id)
493 {
494 struct cgx *cgx = cgxd;
495 u64 cfg;
496
497 cfg = cgx_read(cgx, lmac_id, CGXX_CMRX_CFG);
498 return (cfg >> CGX_LMAC_TYPE_SHIFT) & CGX_LMAC_TYPE_MASK;
499 }
500
cgx_get_lmac_fifo_len(void * cgxd,int lmac_id)501 static u32 cgx_get_lmac_fifo_len(void *cgxd, int lmac_id)
502 {
503 struct cgx *cgx = cgxd;
504 u8 num_lmacs;
505 u32 fifo_len;
506
507 fifo_len = cgx->mac_ops->fifo_len;
508 num_lmacs = cgx->mac_ops->get_nr_lmacs(cgx);
509
510 switch (num_lmacs) {
511 case 1:
512 return fifo_len;
513 case 2:
514 return fifo_len / 2;
515 case 3:
516 /* LMAC0 gets half of the FIFO, reset 1/4th */
517 if (lmac_id == 0)
518 return fifo_len / 2;
519 return fifo_len / 4;
520 case 4:
521 default:
522 return fifo_len / 4;
523 }
524 return 0;
525 }
526
527 /* Configure CGX LMAC in internal loopback mode */
cgx_lmac_internal_loopback(void * cgxd,int lmac_id,bool enable)528 int cgx_lmac_internal_loopback(void *cgxd, int lmac_id, bool enable)
529 {
530 struct cgx *cgx = cgxd;
531 u8 lmac_type;
532 u64 cfg;
533
534 if (!is_lmac_valid(cgx, lmac_id))
535 return -ENODEV;
536
537 lmac_type = cgx->mac_ops->get_lmac_type(cgx, lmac_id);
538 if (lmac_type == LMAC_MODE_SGMII || lmac_type == LMAC_MODE_QSGMII) {
539 cfg = cgx_read(cgx, lmac_id, CGXX_GMP_PCS_MRX_CTL);
540 if (enable)
541 cfg |= CGXX_GMP_PCS_MRX_CTL_LBK;
542 else
543 cfg &= ~CGXX_GMP_PCS_MRX_CTL_LBK;
544 cgx_write(cgx, lmac_id, CGXX_GMP_PCS_MRX_CTL, cfg);
545 } else {
546 cfg = cgx_read(cgx, lmac_id, CGXX_SPUX_CONTROL1);
547 if (enable)
548 cfg |= CGXX_SPUX_CONTROL1_LBK;
549 else
550 cfg &= ~CGXX_SPUX_CONTROL1_LBK;
551 cgx_write(cgx, lmac_id, CGXX_SPUX_CONTROL1, cfg);
552 }
553 return 0;
554 }
555
cgx_lmac_promisc_config(int cgx_id,int lmac_id,bool enable)556 void cgx_lmac_promisc_config(int cgx_id, int lmac_id, bool enable)
557 {
558 struct cgx *cgx = cgx_get_pdata(cgx_id);
559 struct lmac *lmac = lmac_pdata(lmac_id, cgx);
560 u16 max_dmac = lmac->mac_to_index_bmap.max;
561 struct mac_ops *mac_ops;
562 int index, i;
563 u64 cfg = 0;
564 int id;
565
566 if (!cgx)
567 return;
568
569 id = get_sequence_id_of_lmac(cgx, lmac_id);
570
571 mac_ops = cgx->mac_ops;
572 if (enable) {
573 /* Enable promiscuous mode on LMAC */
574 cfg = cgx_read(cgx, lmac_id, CGXX_CMRX_RX_DMAC_CTL0);
575 cfg &= ~CGX_DMAC_CAM_ACCEPT;
576 cfg |= (CGX_DMAC_BCAST_MODE | CGX_DMAC_MCAST_MODE);
577 cgx_write(cgx, lmac_id, CGXX_CMRX_RX_DMAC_CTL0, cfg);
578
579 for (i = 0; i < max_dmac; i++) {
580 index = id * max_dmac + i;
581 cfg = cgx_read(cgx, 0,
582 (CGXX_CMRX_RX_DMAC_CAM0 + index * 0x8));
583 cfg &= ~CGX_DMAC_CAM_ADDR_ENABLE;
584 cgx_write(cgx, 0,
585 (CGXX_CMRX_RX_DMAC_CAM0 + index * 0x8), cfg);
586 }
587 } else {
588 /* Disable promiscuous mode */
589 cfg = cgx_read(cgx, lmac_id, CGXX_CMRX_RX_DMAC_CTL0);
590 cfg |= CGX_DMAC_CAM_ACCEPT | CGX_DMAC_MCAST_MODE;
591 cgx_write(cgx, lmac_id, CGXX_CMRX_RX_DMAC_CTL0, cfg);
592 for (i = 0; i < max_dmac; i++) {
593 index = id * max_dmac + i;
594 cfg = cgx_read(cgx, 0,
595 (CGXX_CMRX_RX_DMAC_CAM0 + index * 0x8));
596 if ((cfg & CGX_RX_DMAC_ADR_MASK) != 0) {
597 cfg |= CGX_DMAC_CAM_ADDR_ENABLE;
598 cgx_write(cgx, 0,
599 (CGXX_CMRX_RX_DMAC_CAM0 +
600 index * 0x8),
601 cfg);
602 }
603 }
604 }
605 }
606
cgx_lmac_get_pause_frm_status(void * cgxd,int lmac_id,u8 * tx_pause,u8 * rx_pause)607 static int cgx_lmac_get_pause_frm_status(void *cgxd, int lmac_id,
608 u8 *tx_pause, u8 *rx_pause)
609 {
610 struct cgx *cgx = cgxd;
611 u64 cfg;
612
613 if (is_dev_rpm(cgx))
614 return 0;
615
616 if (!is_lmac_valid(cgx, lmac_id))
617 return -ENODEV;
618
619 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL);
620 *rx_pause = !!(cfg & CGX_SMUX_RX_FRM_CTL_CTL_BCK);
621
622 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_TX_CTL);
623 *tx_pause = !!(cfg & CGX_SMUX_TX_CTL_L2P_BP_CONV);
624 return 0;
625 }
626
627 /* Enable or disable forwarding received pause frames to Tx block */
cgx_lmac_enadis_rx_pause_fwding(void * cgxd,int lmac_id,bool enable)628 void cgx_lmac_enadis_rx_pause_fwding(void *cgxd, int lmac_id, bool enable)
629 {
630 struct cgx *cgx = cgxd;
631 u8 rx_pause, tx_pause;
632 bool is_pfc_enabled;
633 struct lmac *lmac;
634 u64 cfg;
635
636 if (!cgx)
637 return;
638
639 lmac = lmac_pdata(lmac_id, cgx);
640 if (!lmac)
641 return;
642
643 /* Pause frames are not enabled just return */
644 if (!bitmap_weight(lmac->rx_fc_pfvf_bmap.bmap, lmac->rx_fc_pfvf_bmap.max))
645 return;
646
647 cgx_lmac_get_pause_frm_status(cgx, lmac_id, &rx_pause, &tx_pause);
648 is_pfc_enabled = rx_pause ? false : true;
649
650 if (enable) {
651 if (!is_pfc_enabled) {
652 cfg = cgx_read(cgx, lmac_id, CGXX_GMP_GMI_RXX_FRM_CTL);
653 cfg |= CGX_GMP_GMI_RXX_FRM_CTL_CTL_BCK;
654 cgx_write(cgx, lmac_id, CGXX_GMP_GMI_RXX_FRM_CTL, cfg);
655
656 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL);
657 cfg |= CGX_SMUX_RX_FRM_CTL_CTL_BCK;
658 cgx_write(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL, cfg);
659 } else {
660 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_CBFC_CTL);
661 cfg |= CGXX_SMUX_CBFC_CTL_BCK_EN;
662 cgx_write(cgx, lmac_id, CGXX_SMUX_CBFC_CTL, cfg);
663 }
664 } else {
665
666 if (!is_pfc_enabled) {
667 cfg = cgx_read(cgx, lmac_id, CGXX_GMP_GMI_RXX_FRM_CTL);
668 cfg &= ~CGX_GMP_GMI_RXX_FRM_CTL_CTL_BCK;
669 cgx_write(cgx, lmac_id, CGXX_GMP_GMI_RXX_FRM_CTL, cfg);
670
671 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL);
672 cfg &= ~CGX_SMUX_RX_FRM_CTL_CTL_BCK;
673 cgx_write(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL, cfg);
674 } else {
675 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_CBFC_CTL);
676 cfg &= ~CGXX_SMUX_CBFC_CTL_BCK_EN;
677 cgx_write(cgx, lmac_id, CGXX_SMUX_CBFC_CTL, cfg);
678 }
679 }
680 }
681
cgx_get_rx_stats(void * cgxd,int lmac_id,int idx,u64 * rx_stat)682 int cgx_get_rx_stats(void *cgxd, int lmac_id, int idx, u64 *rx_stat)
683 {
684 struct cgx *cgx = cgxd;
685
686 if (!is_lmac_valid(cgx, lmac_id))
687 return -ENODEV;
688 *rx_stat = cgx_read(cgx, lmac_id, CGXX_CMRX_RX_STAT0 + (idx * 8));
689 return 0;
690 }
691
cgx_get_tx_stats(void * cgxd,int lmac_id,int idx,u64 * tx_stat)692 int cgx_get_tx_stats(void *cgxd, int lmac_id, int idx, u64 *tx_stat)
693 {
694 struct cgx *cgx = cgxd;
695
696 if (!is_lmac_valid(cgx, lmac_id))
697 return -ENODEV;
698 *tx_stat = cgx_read(cgx, lmac_id, CGXX_CMRX_TX_STAT0 + (idx * 8));
699 return 0;
700 }
701
cgx_features_get(void * cgxd)702 u64 cgx_features_get(void *cgxd)
703 {
704 return ((struct cgx *)cgxd)->hw_features;
705 }
706
cgx_set_fec_stats_count(struct cgx_link_user_info * linfo)707 static int cgx_set_fec_stats_count(struct cgx_link_user_info *linfo)
708 {
709 if (!linfo->fec)
710 return 0;
711
712 switch (linfo->lmac_type_id) {
713 case LMAC_MODE_SGMII:
714 case LMAC_MODE_XAUI:
715 case LMAC_MODE_RXAUI:
716 case LMAC_MODE_QSGMII:
717 return 0;
718 case LMAC_MODE_10G_R:
719 case LMAC_MODE_25G_R:
720 case LMAC_MODE_100G_R:
721 case LMAC_MODE_USXGMII:
722 return 1;
723 case LMAC_MODE_40G_R:
724 return 4;
725 case LMAC_MODE_50G_R:
726 if (linfo->fec == OTX2_FEC_BASER)
727 return 2;
728 else
729 return 1;
730 default:
731 return 0;
732 }
733 }
734
cgx_get_fec_stats(void * cgxd,int lmac_id,struct cgx_fec_stats_rsp * rsp)735 int cgx_get_fec_stats(void *cgxd, int lmac_id, struct cgx_fec_stats_rsp *rsp)
736 {
737 int stats, fec_stats_count = 0;
738 int corr_reg, uncorr_reg;
739 struct cgx *cgx = cgxd;
740
741 if (!cgx || lmac_id >= cgx->lmac_count)
742 return -ENODEV;
743 fec_stats_count =
744 cgx_set_fec_stats_count(&cgx->lmac_idmap[lmac_id]->link_info);
745 if (cgx->lmac_idmap[lmac_id]->link_info.fec == OTX2_FEC_BASER) {
746 corr_reg = CGXX_SPUX_LNX_FEC_CORR_BLOCKS;
747 uncorr_reg = CGXX_SPUX_LNX_FEC_UNCORR_BLOCKS;
748 } else {
749 corr_reg = CGXX_SPUX_RSFEC_CORR;
750 uncorr_reg = CGXX_SPUX_RSFEC_UNCORR;
751 }
752 for (stats = 0; stats < fec_stats_count; stats++) {
753 rsp->fec_corr_blks +=
754 cgx_read(cgx, lmac_id, corr_reg + (stats * 8));
755 rsp->fec_uncorr_blks +=
756 cgx_read(cgx, lmac_id, uncorr_reg + (stats * 8));
757 }
758 return 0;
759 }
760
cgx_lmac_rx_tx_enable(void * cgxd,int lmac_id,bool enable)761 int cgx_lmac_rx_tx_enable(void *cgxd, int lmac_id, bool enable)
762 {
763 struct cgx *cgx = cgxd;
764 u64 cfg;
765
766 if (!is_lmac_valid(cgx, lmac_id))
767 return -ENODEV;
768
769 cfg = cgx_read(cgx, lmac_id, CGXX_CMRX_CFG);
770 if (enable)
771 cfg |= CMR_EN | DATA_PKT_RX_EN | DATA_PKT_TX_EN;
772 else
773 cfg &= ~(CMR_EN | DATA_PKT_RX_EN | DATA_PKT_TX_EN);
774 cgx_write(cgx, lmac_id, CGXX_CMRX_CFG, cfg);
775 return 0;
776 }
777
cgx_lmac_tx_enable(void * cgxd,int lmac_id,bool enable)778 int cgx_lmac_tx_enable(void *cgxd, int lmac_id, bool enable)
779 {
780 struct cgx *cgx = cgxd;
781 u64 cfg, last;
782
783 if (!is_lmac_valid(cgx, lmac_id))
784 return -ENODEV;
785
786 cfg = cgx_read(cgx, lmac_id, CGXX_CMRX_CFG);
787 last = cfg;
788 if (enable)
789 cfg |= DATA_PKT_TX_EN;
790 else
791 cfg &= ~DATA_PKT_TX_EN;
792
793 if (cfg != last)
794 cgx_write(cgx, lmac_id, CGXX_CMRX_CFG, cfg);
795 return !!(last & DATA_PKT_TX_EN);
796 }
797
cgx_lmac_enadis_pause_frm(void * cgxd,int lmac_id,u8 tx_pause,u8 rx_pause)798 static int cgx_lmac_enadis_pause_frm(void *cgxd, int lmac_id,
799 u8 tx_pause, u8 rx_pause)
800 {
801 struct cgx *cgx = cgxd;
802 u64 cfg;
803
804 if (is_dev_rpm(cgx))
805 return 0;
806
807 if (!is_lmac_valid(cgx, lmac_id))
808 return -ENODEV;
809
810 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL);
811 cfg &= ~CGX_SMUX_RX_FRM_CTL_CTL_BCK;
812 cfg |= rx_pause ? CGX_SMUX_RX_FRM_CTL_CTL_BCK : 0x0;
813 cgx_write(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL, cfg);
814
815 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_TX_CTL);
816 cfg &= ~CGX_SMUX_TX_CTL_L2P_BP_CONV;
817 cfg |= tx_pause ? CGX_SMUX_TX_CTL_L2P_BP_CONV : 0x0;
818 cgx_write(cgx, lmac_id, CGXX_SMUX_TX_CTL, cfg);
819
820 cfg = cgx_read(cgx, 0, CGXX_CMR_RX_OVR_BP);
821 if (tx_pause) {
822 cfg &= ~CGX_CMR_RX_OVR_BP_EN(lmac_id);
823 } else {
824 cfg |= CGX_CMR_RX_OVR_BP_EN(lmac_id);
825 cfg &= ~CGX_CMR_RX_OVR_BP_BP(lmac_id);
826 }
827 cgx_write(cgx, 0, CGXX_CMR_RX_OVR_BP, cfg);
828 return 0;
829 }
830
cgx_lmac_pause_frm_config(void * cgxd,int lmac_id,bool enable)831 static void cgx_lmac_pause_frm_config(void *cgxd, int lmac_id, bool enable)
832 {
833 struct cgx *cgx = cgxd;
834 u64 cfg;
835
836 if (!is_lmac_valid(cgx, lmac_id))
837 return;
838
839 if (enable) {
840 /* Set pause time and interval */
841 cgx_write(cgx, lmac_id, CGXX_SMUX_TX_PAUSE_PKT_TIME,
842 DEFAULT_PAUSE_TIME);
843 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_TX_PAUSE_PKT_INTERVAL);
844 cfg &= ~0xFFFFULL;
845 cgx_write(cgx, lmac_id, CGXX_SMUX_TX_PAUSE_PKT_INTERVAL,
846 cfg | (DEFAULT_PAUSE_TIME / 2));
847
848 cgx_write(cgx, lmac_id, CGXX_GMP_GMI_TX_PAUSE_PKT_TIME,
849 DEFAULT_PAUSE_TIME);
850
851 cfg = cgx_read(cgx, lmac_id,
852 CGXX_GMP_GMI_TX_PAUSE_PKT_INTERVAL);
853 cfg &= ~0xFFFFULL;
854 cgx_write(cgx, lmac_id, CGXX_GMP_GMI_TX_PAUSE_PKT_INTERVAL,
855 cfg | (DEFAULT_PAUSE_TIME / 2));
856 }
857
858 /* ALL pause frames received are completely ignored */
859 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL);
860 cfg &= ~CGX_SMUX_RX_FRM_CTL_CTL_BCK;
861 cgx_write(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL, cfg);
862
863 cfg = cgx_read(cgx, lmac_id, CGXX_GMP_GMI_RXX_FRM_CTL);
864 cfg &= ~CGX_GMP_GMI_RXX_FRM_CTL_CTL_BCK;
865 cgx_write(cgx, lmac_id, CGXX_GMP_GMI_RXX_FRM_CTL, cfg);
866
867 /* Disable pause frames transmission */
868 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_TX_CTL);
869 cfg &= ~CGX_SMUX_TX_CTL_L2P_BP_CONV;
870 cgx_write(cgx, lmac_id, CGXX_SMUX_TX_CTL, cfg);
871
872 cfg = cgx_read(cgx, 0, CGXX_CMR_RX_OVR_BP);
873 cfg |= CGX_CMR_RX_OVR_BP_EN(lmac_id);
874 cfg &= ~CGX_CMR_RX_OVR_BP_BP(lmac_id);
875 cgx_write(cgx, 0, CGXX_CMR_RX_OVR_BP, cfg);
876
877 /* Disable all PFC classes by default */
878 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_CBFC_CTL);
879 cfg = FIELD_SET(CGX_PFC_CLASS_MASK, 0, cfg);
880 cgx_write(cgx, lmac_id, CGXX_SMUX_CBFC_CTL, cfg);
881 }
882
verify_lmac_fc_cfg(void * cgxd,int lmac_id,u8 tx_pause,u8 rx_pause,int pfvf_idx)883 int verify_lmac_fc_cfg(void *cgxd, int lmac_id, u8 tx_pause, u8 rx_pause,
884 int pfvf_idx)
885 {
886 struct cgx *cgx = cgxd;
887 struct lmac *lmac;
888
889 lmac = lmac_pdata(lmac_id, cgx);
890 if (!lmac)
891 return -ENODEV;
892
893 if (!rx_pause)
894 clear_bit(pfvf_idx, lmac->rx_fc_pfvf_bmap.bmap);
895 else
896 set_bit(pfvf_idx, lmac->rx_fc_pfvf_bmap.bmap);
897
898 if (!tx_pause)
899 clear_bit(pfvf_idx, lmac->tx_fc_pfvf_bmap.bmap);
900 else
901 set_bit(pfvf_idx, lmac->tx_fc_pfvf_bmap.bmap);
902
903 /* check if other pfvfs are using flow control */
904 if (!rx_pause && bitmap_weight(lmac->rx_fc_pfvf_bmap.bmap, lmac->rx_fc_pfvf_bmap.max)) {
905 dev_warn(&cgx->pdev->dev,
906 "Receive Flow control disable not permitted as its used by other PFVFs\n");
907 return -EPERM;
908 }
909
910 if (!tx_pause && bitmap_weight(lmac->tx_fc_pfvf_bmap.bmap, lmac->tx_fc_pfvf_bmap.max)) {
911 dev_warn(&cgx->pdev->dev,
912 "Transmit Flow control disable not permitted as its used by other PFVFs\n");
913 return -EPERM;
914 }
915
916 return 0;
917 }
918
cgx_lmac_pfc_config(void * cgxd,int lmac_id,u8 tx_pause,u8 rx_pause,u16 pfc_en)919 int cgx_lmac_pfc_config(void *cgxd, int lmac_id, u8 tx_pause,
920 u8 rx_pause, u16 pfc_en)
921 {
922 struct cgx *cgx = cgxd;
923 u64 cfg;
924
925 if (!is_lmac_valid(cgx, lmac_id))
926 return -ENODEV;
927
928 /* Return as no traffic classes are requested */
929 if (tx_pause && !pfc_en)
930 return 0;
931
932 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_CBFC_CTL);
933 pfc_en |= FIELD_GET(CGX_PFC_CLASS_MASK, cfg);
934
935 if (rx_pause) {
936 cfg |= (CGXX_SMUX_CBFC_CTL_RX_EN |
937 CGXX_SMUX_CBFC_CTL_BCK_EN |
938 CGXX_SMUX_CBFC_CTL_DRP_EN);
939 } else {
940 cfg &= ~(CGXX_SMUX_CBFC_CTL_RX_EN |
941 CGXX_SMUX_CBFC_CTL_BCK_EN |
942 CGXX_SMUX_CBFC_CTL_DRP_EN);
943 }
944
945 if (tx_pause) {
946 cfg |= CGXX_SMUX_CBFC_CTL_TX_EN;
947 cfg = FIELD_SET(CGX_PFC_CLASS_MASK, pfc_en, cfg);
948 } else {
949 cfg &= ~CGXX_SMUX_CBFC_CTL_TX_EN;
950 cfg = FIELD_SET(CGX_PFC_CLASS_MASK, 0, cfg);
951 }
952
953 cgx_write(cgx, lmac_id, CGXX_SMUX_CBFC_CTL, cfg);
954
955 /* Write source MAC address which will be filled into PFC packet */
956 cfg = cgx_lmac_addr_get(cgx->cgx_id, lmac_id);
957 cgx_write(cgx, lmac_id, CGXX_SMUX_SMAC, cfg);
958
959 return 0;
960 }
961
cgx_lmac_get_pfc_frm_cfg(void * cgxd,int lmac_id,u8 * tx_pause,u8 * rx_pause)962 int cgx_lmac_get_pfc_frm_cfg(void *cgxd, int lmac_id, u8 *tx_pause,
963 u8 *rx_pause)
964 {
965 struct cgx *cgx = cgxd;
966 u64 cfg;
967
968 if (!is_lmac_valid(cgx, lmac_id))
969 return -ENODEV;
970
971 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_CBFC_CTL);
972
973 *rx_pause = !!(cfg & CGXX_SMUX_CBFC_CTL_RX_EN);
974 *tx_pause = !!(cfg & CGXX_SMUX_CBFC_CTL_TX_EN);
975
976 return 0;
977 }
978
cgx_lmac_ptp_config(void * cgxd,int lmac_id,bool enable)979 void cgx_lmac_ptp_config(void *cgxd, int lmac_id, bool enable)
980 {
981 struct cgx *cgx = cgxd;
982 u64 cfg;
983
984 if (!cgx)
985 return;
986
987 if (enable) {
988 /* Enable inbound PTP timestamping */
989 cfg = cgx_read(cgx, lmac_id, CGXX_GMP_GMI_RXX_FRM_CTL);
990 cfg |= CGX_GMP_GMI_RXX_FRM_CTL_PTP_MODE;
991 cgx_write(cgx, lmac_id, CGXX_GMP_GMI_RXX_FRM_CTL, cfg);
992
993 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL);
994 cfg |= CGX_SMUX_RX_FRM_CTL_PTP_MODE;
995 cgx_write(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL, cfg);
996 } else {
997 /* Disable inbound PTP stamping */
998 cfg = cgx_read(cgx, lmac_id, CGXX_GMP_GMI_RXX_FRM_CTL);
999 cfg &= ~CGX_GMP_GMI_RXX_FRM_CTL_PTP_MODE;
1000 cgx_write(cgx, lmac_id, CGXX_GMP_GMI_RXX_FRM_CTL, cfg);
1001
1002 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL);
1003 cfg &= ~CGX_SMUX_RX_FRM_CTL_PTP_MODE;
1004 cgx_write(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL, cfg);
1005 }
1006 }
1007
1008 /* CGX Firmware interface low level support */
cgx_fwi_cmd_send(u64 req,u64 * resp,struct lmac * lmac)1009 int cgx_fwi_cmd_send(u64 req, u64 *resp, struct lmac *lmac)
1010 {
1011 struct cgx *cgx = lmac->cgx;
1012 struct device *dev;
1013 int err = 0;
1014 u64 cmd;
1015
1016 /* Ensure no other command is in progress */
1017 err = mutex_lock_interruptible(&lmac->cmd_lock);
1018 if (err)
1019 return err;
1020
1021 /* Ensure command register is free */
1022 cmd = cgx_read(cgx, lmac->lmac_id, CGX_COMMAND_REG);
1023 if (FIELD_GET(CMDREG_OWN, cmd) != CGX_CMD_OWN_NS) {
1024 err = -EBUSY;
1025 goto unlock;
1026 }
1027
1028 /* Update ownership in command request */
1029 req = FIELD_SET(CMDREG_OWN, CGX_CMD_OWN_FIRMWARE, req);
1030
1031 /* Mark this lmac as pending, before we start */
1032 lmac->cmd_pend = true;
1033
1034 /* Start command in hardware */
1035 cgx_write(cgx, lmac->lmac_id, CGX_COMMAND_REG, req);
1036
1037 /* Ensure command is completed without errors */
1038 if (!wait_event_timeout(lmac->wq_cmd_cmplt, !lmac->cmd_pend,
1039 msecs_to_jiffies(CGX_CMD_TIMEOUT))) {
1040 dev = &cgx->pdev->dev;
1041 dev_err(dev, "cgx port %d:%d cmd %lld timeout\n",
1042 cgx->cgx_id, lmac->lmac_id, FIELD_GET(CMDREG_ID, req));
1043 err = LMAC_AF_ERR_CMD_TIMEOUT;
1044 goto unlock;
1045 }
1046
1047 /* we have a valid command response */
1048 smp_rmb(); /* Ensure the latest updates are visible */
1049 *resp = lmac->resp;
1050
1051 unlock:
1052 mutex_unlock(&lmac->cmd_lock);
1053
1054 return err;
1055 }
1056
cgx_fwi_cmd_generic(u64 req,u64 * resp,struct cgx * cgx,int lmac_id)1057 int cgx_fwi_cmd_generic(u64 req, u64 *resp, struct cgx *cgx, int lmac_id)
1058 {
1059 struct lmac *lmac;
1060 int err;
1061
1062 lmac = lmac_pdata(lmac_id, cgx);
1063 if (!lmac)
1064 return -ENODEV;
1065
1066 err = cgx_fwi_cmd_send(req, resp, lmac);
1067
1068 /* Check for valid response */
1069 if (!err) {
1070 if (FIELD_GET(EVTREG_STAT, *resp) == CGX_STAT_FAIL)
1071 return -EIO;
1072 else
1073 return 0;
1074 }
1075
1076 return err;
1077 }
1078
cgx_link_usertable_index_map(int speed)1079 static int cgx_link_usertable_index_map(int speed)
1080 {
1081 switch (speed) {
1082 case SPEED_10:
1083 return CGX_LINK_10M;
1084 case SPEED_100:
1085 return CGX_LINK_100M;
1086 case SPEED_1000:
1087 return CGX_LINK_1G;
1088 case SPEED_2500:
1089 return CGX_LINK_2HG;
1090 case SPEED_5000:
1091 return CGX_LINK_5G;
1092 case SPEED_10000:
1093 return CGX_LINK_10G;
1094 case SPEED_20000:
1095 return CGX_LINK_20G;
1096 case SPEED_25000:
1097 return CGX_LINK_25G;
1098 case SPEED_40000:
1099 return CGX_LINK_40G;
1100 case SPEED_50000:
1101 return CGX_LINK_50G;
1102 case 80000:
1103 return CGX_LINK_80G;
1104 case SPEED_100000:
1105 return CGX_LINK_100G;
1106 case SPEED_UNKNOWN:
1107 return CGX_LINK_NONE;
1108 }
1109 return CGX_LINK_NONE;
1110 }
1111
set_mod_args(struct cgx_set_link_mode_args * args,u32 speed,u8 duplex,u8 autoneg,u64 mode)1112 static void set_mod_args(struct cgx_set_link_mode_args *args,
1113 u32 speed, u8 duplex, u8 autoneg, u64 mode)
1114 {
1115 /* Fill default values incase of user did not pass
1116 * valid parameters
1117 */
1118 if (args->duplex == DUPLEX_UNKNOWN)
1119 args->duplex = duplex;
1120 if (args->speed == SPEED_UNKNOWN)
1121 args->speed = speed;
1122 if (args->an == AUTONEG_UNKNOWN)
1123 args->an = autoneg;
1124 args->mode = mode;
1125 args->ports = 0;
1126 }
1127
otx2_map_ethtool_link_modes(u64 bitmask,struct cgx_set_link_mode_args * args)1128 static void otx2_map_ethtool_link_modes(u64 bitmask,
1129 struct cgx_set_link_mode_args *args)
1130 {
1131 switch (bitmask) {
1132 case ETHTOOL_LINK_MODE_10baseT_Half_BIT:
1133 set_mod_args(args, 10, 1, 1, BIT_ULL(CGX_MODE_SGMII));
1134 break;
1135 case ETHTOOL_LINK_MODE_10baseT_Full_BIT:
1136 set_mod_args(args, 10, 0, 1, BIT_ULL(CGX_MODE_SGMII));
1137 break;
1138 case ETHTOOL_LINK_MODE_100baseT_Half_BIT:
1139 set_mod_args(args, 100, 1, 1, BIT_ULL(CGX_MODE_SGMII));
1140 break;
1141 case ETHTOOL_LINK_MODE_100baseT_Full_BIT:
1142 set_mod_args(args, 100, 0, 1, BIT_ULL(CGX_MODE_SGMII));
1143 break;
1144 case ETHTOOL_LINK_MODE_1000baseT_Half_BIT:
1145 set_mod_args(args, 1000, 1, 1, BIT_ULL(CGX_MODE_SGMII));
1146 break;
1147 case ETHTOOL_LINK_MODE_1000baseT_Full_BIT:
1148 set_mod_args(args, 1000, 0, 1, BIT_ULL(CGX_MODE_SGMII));
1149 break;
1150 case ETHTOOL_LINK_MODE_1000baseX_Full_BIT:
1151 set_mod_args(args, 1000, 0, 0, BIT_ULL(CGX_MODE_1000_BASEX));
1152 break;
1153 case ETHTOOL_LINK_MODE_10000baseT_Full_BIT:
1154 set_mod_args(args, 1000, 0, 1, BIT_ULL(CGX_MODE_QSGMII));
1155 break;
1156 case ETHTOOL_LINK_MODE_10000baseSR_Full_BIT:
1157 set_mod_args(args, 10000, 0, 0, BIT_ULL(CGX_MODE_10G_C2C));
1158 break;
1159 case ETHTOOL_LINK_MODE_10000baseLR_Full_BIT:
1160 set_mod_args(args, 10000, 0, 0, BIT_ULL(CGX_MODE_10G_C2M));
1161 break;
1162 case ETHTOOL_LINK_MODE_10000baseKR_Full_BIT:
1163 set_mod_args(args, 10000, 0, 1, BIT_ULL(CGX_MODE_10G_KR));
1164 break;
1165 case ETHTOOL_LINK_MODE_25000baseSR_Full_BIT:
1166 set_mod_args(args, 25000, 0, 0, BIT_ULL(CGX_MODE_25G_C2C));
1167 break;
1168 case ETHTOOL_LINK_MODE_25000baseCR_Full_BIT:
1169 set_mod_args(args, 25000, 0, 1, BIT_ULL(CGX_MODE_25G_CR));
1170 break;
1171 case ETHTOOL_LINK_MODE_25000baseKR_Full_BIT:
1172 set_mod_args(args, 25000, 0, 1, BIT_ULL(CGX_MODE_25G_KR));
1173 break;
1174 case ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT:
1175 set_mod_args(args, 40000, 0, 0, BIT_ULL(CGX_MODE_40G_C2C));
1176 break;
1177 case ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT:
1178 set_mod_args(args, 40000, 0, 0, BIT_ULL(CGX_MODE_40G_C2M));
1179 break;
1180 case ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT:
1181 set_mod_args(args, 40000, 0, 1, BIT_ULL(CGX_MODE_40G_CR4));
1182 break;
1183 case ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT:
1184 set_mod_args(args, 40000, 0, 1, BIT_ULL(CGX_MODE_40G_KR4));
1185 break;
1186 case ETHTOOL_LINK_MODE_50000baseSR_Full_BIT:
1187 set_mod_args(args, 50000, 0, 0, BIT_ULL(CGX_MODE_50G_C2C));
1188 break;
1189 case ETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT:
1190 set_mod_args(args, 50000, 0, 0, BIT_ULL(CGX_MODE_50G_C2M));
1191 break;
1192 case ETHTOOL_LINK_MODE_50000baseCR_Full_BIT:
1193 set_mod_args(args, 50000, 0, 1, BIT_ULL(CGX_MODE_50G_CR));
1194 break;
1195 case ETHTOOL_LINK_MODE_50000baseKR_Full_BIT:
1196 set_mod_args(args, 50000, 0, 1, BIT_ULL(CGX_MODE_50G_KR));
1197 break;
1198 case ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT:
1199 set_mod_args(args, 100000, 0, 0, BIT_ULL(CGX_MODE_100G_C2C));
1200 break;
1201 case ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT:
1202 set_mod_args(args, 100000, 0, 0, BIT_ULL(CGX_MODE_100G_C2M));
1203 break;
1204 case ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT:
1205 set_mod_args(args, 100000, 0, 1, BIT_ULL(CGX_MODE_100G_CR4));
1206 break;
1207 case ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT:
1208 set_mod_args(args, 100000, 0, 1, BIT_ULL(CGX_MODE_100G_KR4));
1209 break;
1210 default:
1211 set_mod_args(args, 0, 1, 0, BIT_ULL(CGX_MODE_MAX));
1212 break;
1213 }
1214 }
1215
link_status_user_format(u64 lstat,struct cgx_link_user_info * linfo,struct cgx * cgx,u8 lmac_id)1216 static inline void link_status_user_format(u64 lstat,
1217 struct cgx_link_user_info *linfo,
1218 struct cgx *cgx, u8 lmac_id)
1219 {
1220 const char *lmac_string;
1221
1222 linfo->link_up = FIELD_GET(RESP_LINKSTAT_UP, lstat);
1223 linfo->full_duplex = FIELD_GET(RESP_LINKSTAT_FDUPLEX, lstat);
1224 linfo->speed = cgx_speed_mbps[FIELD_GET(RESP_LINKSTAT_SPEED, lstat)];
1225 linfo->an = FIELD_GET(RESP_LINKSTAT_AN, lstat);
1226 linfo->fec = FIELD_GET(RESP_LINKSTAT_FEC, lstat);
1227 linfo->lmac_type_id = cgx_get_lmac_type(cgx, lmac_id);
1228 lmac_string = cgx_lmactype_string[linfo->lmac_type_id];
1229 strncpy(linfo->lmac_type, lmac_string, LMACTYPE_STR_LEN - 1);
1230 }
1231
1232 /* Hardware event handlers */
cgx_link_change_handler(u64 lstat,struct lmac * lmac)1233 static inline void cgx_link_change_handler(u64 lstat,
1234 struct lmac *lmac)
1235 {
1236 struct cgx_link_user_info *linfo;
1237 struct cgx *cgx = lmac->cgx;
1238 struct cgx_link_event event;
1239 struct device *dev;
1240 int err_type;
1241
1242 dev = &cgx->pdev->dev;
1243
1244 link_status_user_format(lstat, &event.link_uinfo, cgx, lmac->lmac_id);
1245 err_type = FIELD_GET(RESP_LINKSTAT_ERRTYPE, lstat);
1246
1247 event.cgx_id = cgx->cgx_id;
1248 event.lmac_id = lmac->lmac_id;
1249
1250 /* update the local copy of link status */
1251 lmac->link_info = event.link_uinfo;
1252 linfo = &lmac->link_info;
1253
1254 if (err_type == CGX_ERR_SPEED_CHANGE_INVALID)
1255 return;
1256
1257 /* Ensure callback doesn't get unregistered until we finish it */
1258 spin_lock(&lmac->event_cb_lock);
1259
1260 if (!lmac->event_cb.notify_link_chg) {
1261 dev_dbg(dev, "cgx port %d:%d Link change handler null",
1262 cgx->cgx_id, lmac->lmac_id);
1263 if (err_type != CGX_ERR_NONE) {
1264 dev_err(dev, "cgx port %d:%d Link error %d\n",
1265 cgx->cgx_id, lmac->lmac_id, err_type);
1266 }
1267 dev_info(dev, "cgx port %d:%d Link is %s %d Mbps\n",
1268 cgx->cgx_id, lmac->lmac_id,
1269 linfo->link_up ? "UP" : "DOWN", linfo->speed);
1270 goto err;
1271 }
1272
1273 if (lmac->event_cb.notify_link_chg(&event, lmac->event_cb.data))
1274 dev_err(dev, "event notification failure\n");
1275 err:
1276 spin_unlock(&lmac->event_cb_lock);
1277 }
1278
cgx_cmdresp_is_linkevent(u64 event)1279 static inline bool cgx_cmdresp_is_linkevent(u64 event)
1280 {
1281 u8 id;
1282
1283 id = FIELD_GET(EVTREG_ID, event);
1284 if (id == CGX_CMD_LINK_BRING_UP ||
1285 id == CGX_CMD_LINK_BRING_DOWN ||
1286 id == CGX_CMD_MODE_CHANGE)
1287 return true;
1288 else
1289 return false;
1290 }
1291
cgx_event_is_linkevent(u64 event)1292 static inline bool cgx_event_is_linkevent(u64 event)
1293 {
1294 if (FIELD_GET(EVTREG_ID, event) == CGX_EVT_LINK_CHANGE)
1295 return true;
1296 else
1297 return false;
1298 }
1299
cgx_fwi_event_handler(int irq,void * data)1300 static irqreturn_t cgx_fwi_event_handler(int irq, void *data)
1301 {
1302 u64 event, offset, clear_bit;
1303 struct lmac *lmac = data;
1304 struct cgx *cgx;
1305
1306 cgx = lmac->cgx;
1307
1308 /* Clear SW_INT for RPM and CMR_INT for CGX */
1309 offset = cgx->mac_ops->int_register;
1310 clear_bit = cgx->mac_ops->int_ena_bit;
1311
1312 event = cgx_read(cgx, lmac->lmac_id, CGX_EVENT_REG);
1313
1314 if (!FIELD_GET(EVTREG_ACK, event))
1315 return IRQ_NONE;
1316
1317 switch (FIELD_GET(EVTREG_EVT_TYPE, event)) {
1318 case CGX_EVT_CMD_RESP:
1319 /* Copy the response. Since only one command is active at a
1320 * time, there is no way a response can get overwritten
1321 */
1322 lmac->resp = event;
1323 /* Ensure response is updated before thread context starts */
1324 smp_wmb();
1325
1326 /* There wont be separate events for link change initiated from
1327 * software; Hence report the command responses as events
1328 */
1329 if (cgx_cmdresp_is_linkevent(event))
1330 cgx_link_change_handler(event, lmac);
1331
1332 /* Release thread waiting for completion */
1333 lmac->cmd_pend = false;
1334 wake_up_interruptible(&lmac->wq_cmd_cmplt);
1335 break;
1336 case CGX_EVT_ASYNC:
1337 if (cgx_event_is_linkevent(event))
1338 cgx_link_change_handler(event, lmac);
1339 break;
1340 }
1341
1342 /* Any new event or command response will be posted by firmware
1343 * only after the current status is acked.
1344 * Ack the interrupt register as well.
1345 */
1346 cgx_write(lmac->cgx, lmac->lmac_id, CGX_EVENT_REG, 0);
1347 cgx_write(lmac->cgx, lmac->lmac_id, offset, clear_bit);
1348
1349 return IRQ_HANDLED;
1350 }
1351
1352 /* APIs for PHY management using CGX firmware interface */
1353
1354 /* callback registration for hardware events like link change */
cgx_lmac_evh_register(struct cgx_event_cb * cb,void * cgxd,int lmac_id)1355 int cgx_lmac_evh_register(struct cgx_event_cb *cb, void *cgxd, int lmac_id)
1356 {
1357 struct cgx *cgx = cgxd;
1358 struct lmac *lmac;
1359
1360 lmac = lmac_pdata(lmac_id, cgx);
1361 if (!lmac)
1362 return -ENODEV;
1363
1364 lmac->event_cb = *cb;
1365
1366 return 0;
1367 }
1368
cgx_lmac_evh_unregister(void * cgxd,int lmac_id)1369 int cgx_lmac_evh_unregister(void *cgxd, int lmac_id)
1370 {
1371 struct lmac *lmac;
1372 unsigned long flags;
1373 struct cgx *cgx = cgxd;
1374
1375 lmac = lmac_pdata(lmac_id, cgx);
1376 if (!lmac)
1377 return -ENODEV;
1378
1379 spin_lock_irqsave(&lmac->event_cb_lock, flags);
1380 lmac->event_cb.notify_link_chg = NULL;
1381 lmac->event_cb.data = NULL;
1382 spin_unlock_irqrestore(&lmac->event_cb_lock, flags);
1383
1384 return 0;
1385 }
1386
cgx_get_fwdata_base(u64 * base)1387 int cgx_get_fwdata_base(u64 *base)
1388 {
1389 u64 req = 0, resp;
1390 struct cgx *cgx;
1391 int first_lmac;
1392 int err;
1393
1394 cgx = list_first_entry_or_null(&cgx_list, struct cgx, cgx_list);
1395 if (!cgx)
1396 return -ENXIO;
1397
1398 first_lmac = find_first_bit(&cgx->lmac_bmap, MAX_LMAC_PER_CGX);
1399 req = FIELD_SET(CMDREG_ID, CGX_CMD_GET_FWD_BASE, req);
1400 err = cgx_fwi_cmd_generic(req, &resp, cgx, first_lmac);
1401 if (!err)
1402 *base = FIELD_GET(RESP_FWD_BASE, resp);
1403
1404 return err;
1405 }
1406
cgx_set_link_mode(void * cgxd,struct cgx_set_link_mode_args args,int cgx_id,int lmac_id)1407 int cgx_set_link_mode(void *cgxd, struct cgx_set_link_mode_args args,
1408 int cgx_id, int lmac_id)
1409 {
1410 struct cgx *cgx = cgxd;
1411 u64 req = 0, resp;
1412
1413 if (!cgx)
1414 return -ENODEV;
1415
1416 if (args.mode)
1417 otx2_map_ethtool_link_modes(args.mode, &args);
1418 if (!args.speed && args.duplex && !args.an)
1419 return -EINVAL;
1420
1421 req = FIELD_SET(CMDREG_ID, CGX_CMD_MODE_CHANGE, req);
1422 req = FIELD_SET(CMDMODECHANGE_SPEED,
1423 cgx_link_usertable_index_map(args.speed), req);
1424 req = FIELD_SET(CMDMODECHANGE_DUPLEX, args.duplex, req);
1425 req = FIELD_SET(CMDMODECHANGE_AN, args.an, req);
1426 req = FIELD_SET(CMDMODECHANGE_PORT, args.ports, req);
1427 req = FIELD_SET(CMDMODECHANGE_FLAGS, args.mode, req);
1428
1429 return cgx_fwi_cmd_generic(req, &resp, cgx, lmac_id);
1430 }
cgx_set_fec(u64 fec,int cgx_id,int lmac_id)1431 int cgx_set_fec(u64 fec, int cgx_id, int lmac_id)
1432 {
1433 u64 req = 0, resp;
1434 struct cgx *cgx;
1435 int err = 0;
1436
1437 cgx = cgx_get_pdata(cgx_id);
1438 if (!cgx)
1439 return -ENXIO;
1440
1441 req = FIELD_SET(CMDREG_ID, CGX_CMD_SET_FEC, req);
1442 req = FIELD_SET(CMDSETFEC, fec, req);
1443 err = cgx_fwi_cmd_generic(req, &resp, cgx, lmac_id);
1444 if (err)
1445 return err;
1446
1447 cgx->lmac_idmap[lmac_id]->link_info.fec =
1448 FIELD_GET(RESP_LINKSTAT_FEC, resp);
1449 return cgx->lmac_idmap[lmac_id]->link_info.fec;
1450 }
1451
cgx_get_phy_fec_stats(void * cgxd,int lmac_id)1452 int cgx_get_phy_fec_stats(void *cgxd, int lmac_id)
1453 {
1454 struct cgx *cgx = cgxd;
1455 u64 req = 0, resp;
1456
1457 if (!cgx)
1458 return -ENODEV;
1459
1460 req = FIELD_SET(CMDREG_ID, CGX_CMD_GET_PHY_FEC_STATS, req);
1461 return cgx_fwi_cmd_generic(req, &resp, cgx, lmac_id);
1462 }
1463
cgx_fwi_link_change(struct cgx * cgx,int lmac_id,bool enable)1464 static int cgx_fwi_link_change(struct cgx *cgx, int lmac_id, bool enable)
1465 {
1466 u64 req = 0;
1467 u64 resp;
1468
1469 if (enable) {
1470 req = FIELD_SET(CMDREG_ID, CGX_CMD_LINK_BRING_UP, req);
1471 /* On CN10K firmware offloads link bring up/down operations to ECP
1472 * On Octeontx2 link operations are handled by firmware itself
1473 * which can cause mbox errors so configure maximum time firmware
1474 * poll for Link as 1000 ms
1475 */
1476 if (!is_dev_rpm(cgx))
1477 req = FIELD_SET(LINKCFG_TIMEOUT, 1000, req);
1478
1479 } else {
1480 req = FIELD_SET(CMDREG_ID, CGX_CMD_LINK_BRING_DOWN, req);
1481 }
1482 return cgx_fwi_cmd_generic(req, &resp, cgx, lmac_id);
1483 }
1484
cgx_fwi_read_version(u64 * resp,struct cgx * cgx)1485 static inline int cgx_fwi_read_version(u64 *resp, struct cgx *cgx)
1486 {
1487 int first_lmac = find_first_bit(&cgx->lmac_bmap, MAX_LMAC_PER_CGX);
1488 u64 req = 0;
1489
1490 req = FIELD_SET(CMDREG_ID, CGX_CMD_GET_FW_VER, req);
1491 return cgx_fwi_cmd_generic(req, resp, cgx, first_lmac);
1492 }
1493
cgx_lmac_verify_fwi_version(struct cgx * cgx)1494 static int cgx_lmac_verify_fwi_version(struct cgx *cgx)
1495 {
1496 struct device *dev = &cgx->pdev->dev;
1497 int major_ver, minor_ver;
1498 u64 resp;
1499 int err;
1500
1501 if (!cgx->lmac_count)
1502 return 0;
1503
1504 err = cgx_fwi_read_version(&resp, cgx);
1505 if (err)
1506 return err;
1507
1508 major_ver = FIELD_GET(RESP_MAJOR_VER, resp);
1509 minor_ver = FIELD_GET(RESP_MINOR_VER, resp);
1510 dev_dbg(dev, "Firmware command interface version = %d.%d\n",
1511 major_ver, minor_ver);
1512 if (major_ver != CGX_FIRMWARE_MAJOR_VER)
1513 return -EIO;
1514 else
1515 return 0;
1516 }
1517
cgx_lmac_linkup_work(struct work_struct * work)1518 static void cgx_lmac_linkup_work(struct work_struct *work)
1519 {
1520 struct cgx *cgx = container_of(work, struct cgx, cgx_cmd_work);
1521 struct device *dev = &cgx->pdev->dev;
1522 int i, err;
1523
1524 /* Do Link up for all the enabled lmacs */
1525 for_each_set_bit(i, &cgx->lmac_bmap, MAX_LMAC_PER_CGX) {
1526 err = cgx_fwi_link_change(cgx, i, true);
1527 if (err)
1528 dev_info(dev, "cgx port %d:%d Link up command failed\n",
1529 cgx->cgx_id, i);
1530 }
1531 }
1532
cgx_lmac_linkup_start(void * cgxd)1533 int cgx_lmac_linkup_start(void *cgxd)
1534 {
1535 struct cgx *cgx = cgxd;
1536
1537 if (!cgx)
1538 return -ENODEV;
1539
1540 queue_work(cgx->cgx_cmd_workq, &cgx->cgx_cmd_work);
1541
1542 return 0;
1543 }
1544
cgx_lmac_get_fifolen(struct cgx * cgx)1545 static void cgx_lmac_get_fifolen(struct cgx *cgx)
1546 {
1547 u64 cfg;
1548
1549 cfg = cgx_read(cgx, 0, CGX_CONST);
1550 cgx->mac_ops->fifo_len = FIELD_GET(CGX_CONST_RXFIFO_SIZE, cfg);
1551 }
1552
cgx_configure_interrupt(struct cgx * cgx,struct lmac * lmac,int cnt,bool req_free)1553 static int cgx_configure_interrupt(struct cgx *cgx, struct lmac *lmac,
1554 int cnt, bool req_free)
1555 {
1556 struct mac_ops *mac_ops = cgx->mac_ops;
1557 u64 offset, ena_bit;
1558 unsigned int irq;
1559 int err;
1560
1561 irq = pci_irq_vector(cgx->pdev, mac_ops->lmac_fwi +
1562 cnt * mac_ops->irq_offset);
1563 offset = mac_ops->int_set_reg;
1564 ena_bit = mac_ops->int_ena_bit;
1565
1566 if (req_free) {
1567 free_irq(irq, lmac);
1568 return 0;
1569 }
1570
1571 err = request_irq(irq, cgx_fwi_event_handler, 0, lmac->name, lmac);
1572 if (err)
1573 return err;
1574
1575 /* Enable interrupt */
1576 cgx_write(cgx, lmac->lmac_id, offset, ena_bit);
1577 return 0;
1578 }
1579
cgx_get_nr_lmacs(void * cgxd)1580 int cgx_get_nr_lmacs(void *cgxd)
1581 {
1582 struct cgx *cgx = cgxd;
1583
1584 return cgx_read(cgx, 0, CGXX_CMRX_RX_LMACS) & 0x7ULL;
1585 }
1586
cgx_get_lmacid(void * cgxd,u8 lmac_index)1587 u8 cgx_get_lmacid(void *cgxd, u8 lmac_index)
1588 {
1589 struct cgx *cgx = cgxd;
1590
1591 return cgx->lmac_idmap[lmac_index]->lmac_id;
1592 }
1593
cgx_get_lmac_bmap(void * cgxd)1594 unsigned long cgx_get_lmac_bmap(void *cgxd)
1595 {
1596 struct cgx *cgx = cgxd;
1597
1598 return cgx->lmac_bmap;
1599 }
1600
cgx_lmac_init(struct cgx * cgx)1601 static int cgx_lmac_init(struct cgx *cgx)
1602 {
1603 struct lmac *lmac;
1604 u64 lmac_list;
1605 int i, err;
1606
1607 cgx_lmac_get_fifolen(cgx);
1608
1609 cgx->lmac_count = cgx->mac_ops->get_nr_lmacs(cgx);
1610 /* lmac_list specifies which lmacs are enabled
1611 * when bit n is set to 1, LMAC[n] is enabled
1612 */
1613 if (cgx->mac_ops->non_contiguous_serdes_lane)
1614 lmac_list = cgx_read(cgx, 0, CGXX_CMRX_RX_LMACS) & 0xFULL;
1615
1616 if (cgx->lmac_count > MAX_LMAC_PER_CGX)
1617 cgx->lmac_count = MAX_LMAC_PER_CGX;
1618
1619 for (i = 0; i < cgx->lmac_count; i++) {
1620 lmac = kzalloc(sizeof(struct lmac), GFP_KERNEL);
1621 if (!lmac)
1622 return -ENOMEM;
1623 lmac->name = kcalloc(1, sizeof("cgx_fwi_xxx_yyy"), GFP_KERNEL);
1624 if (!lmac->name) {
1625 err = -ENOMEM;
1626 goto err_lmac_free;
1627 }
1628 sprintf(lmac->name, "cgx_fwi_%d_%d", cgx->cgx_id, i);
1629 if (cgx->mac_ops->non_contiguous_serdes_lane) {
1630 lmac->lmac_id = __ffs64(lmac_list);
1631 lmac_list &= ~BIT_ULL(lmac->lmac_id);
1632 } else {
1633 lmac->lmac_id = i;
1634 }
1635
1636 lmac->cgx = cgx;
1637 lmac->mac_to_index_bmap.max =
1638 MAX_DMAC_ENTRIES_PER_CGX / cgx->lmac_count;
1639 err = rvu_alloc_bitmap(&lmac->mac_to_index_bmap);
1640 if (err)
1641 goto err_name_free;
1642
1643 /* Reserve first entry for default MAC address */
1644 set_bit(0, lmac->mac_to_index_bmap.bmap);
1645
1646 lmac->rx_fc_pfvf_bmap.max = 128;
1647 err = rvu_alloc_bitmap(&lmac->rx_fc_pfvf_bmap);
1648 if (err)
1649 goto err_dmac_bmap_free;
1650
1651 lmac->tx_fc_pfvf_bmap.max = 128;
1652 err = rvu_alloc_bitmap(&lmac->tx_fc_pfvf_bmap);
1653 if (err)
1654 goto err_rx_fc_bmap_free;
1655
1656 init_waitqueue_head(&lmac->wq_cmd_cmplt);
1657 mutex_init(&lmac->cmd_lock);
1658 spin_lock_init(&lmac->event_cb_lock);
1659 err = cgx_configure_interrupt(cgx, lmac, lmac->lmac_id, false);
1660 if (err)
1661 goto err_bitmap_free;
1662
1663 /* Add reference */
1664 cgx->lmac_idmap[lmac->lmac_id] = lmac;
1665 set_bit(lmac->lmac_id, &cgx->lmac_bmap);
1666 cgx->mac_ops->mac_pause_frm_config(cgx, lmac->lmac_id, true);
1667 }
1668
1669 return cgx_lmac_verify_fwi_version(cgx);
1670
1671 err_bitmap_free:
1672 rvu_free_bitmap(&lmac->tx_fc_pfvf_bmap);
1673 err_rx_fc_bmap_free:
1674 rvu_free_bitmap(&lmac->rx_fc_pfvf_bmap);
1675 err_dmac_bmap_free:
1676 rvu_free_bitmap(&lmac->mac_to_index_bmap);
1677 err_name_free:
1678 kfree(lmac->name);
1679 err_lmac_free:
1680 kfree(lmac);
1681 return err;
1682 }
1683
cgx_lmac_exit(struct cgx * cgx)1684 static int cgx_lmac_exit(struct cgx *cgx)
1685 {
1686 struct lmac *lmac;
1687 int i;
1688
1689 if (cgx->cgx_cmd_workq) {
1690 destroy_workqueue(cgx->cgx_cmd_workq);
1691 cgx->cgx_cmd_workq = NULL;
1692 }
1693
1694 /* Free all lmac related resources */
1695 for_each_set_bit(i, &cgx->lmac_bmap, MAX_LMAC_PER_CGX) {
1696 lmac = cgx->lmac_idmap[i];
1697 if (!lmac)
1698 continue;
1699 cgx->mac_ops->mac_pause_frm_config(cgx, lmac->lmac_id, false);
1700 cgx_configure_interrupt(cgx, lmac, lmac->lmac_id, true);
1701 kfree(lmac->mac_to_index_bmap.bmap);
1702 kfree(lmac->name);
1703 kfree(lmac);
1704 }
1705
1706 return 0;
1707 }
1708
cgx_populate_features(struct cgx * cgx)1709 static void cgx_populate_features(struct cgx *cgx)
1710 {
1711 if (is_dev_rpm(cgx))
1712 cgx->hw_features = (RVU_LMAC_FEAT_DMACF | RVU_MAC_RPM |
1713 RVU_LMAC_FEAT_FC | RVU_LMAC_FEAT_PTP);
1714 else
1715 cgx->hw_features = (RVU_LMAC_FEAT_FC | RVU_LMAC_FEAT_HIGIG2 |
1716 RVU_LMAC_FEAT_PTP | RVU_LMAC_FEAT_DMACF);
1717 }
1718
1719 static struct mac_ops cgx_mac_ops = {
1720 .name = "cgx",
1721 .csr_offset = 0,
1722 .lmac_offset = 18,
1723 .int_register = CGXX_CMRX_INT,
1724 .int_set_reg = CGXX_CMRX_INT_ENA_W1S,
1725 .irq_offset = 9,
1726 .int_ena_bit = FW_CGX_INT,
1727 .lmac_fwi = CGX_LMAC_FWI,
1728 .non_contiguous_serdes_lane = false,
1729 .rx_stats_cnt = 9,
1730 .tx_stats_cnt = 18,
1731 .get_nr_lmacs = cgx_get_nr_lmacs,
1732 .get_lmac_type = cgx_get_lmac_type,
1733 .lmac_fifo_len = cgx_get_lmac_fifo_len,
1734 .mac_lmac_intl_lbk = cgx_lmac_internal_loopback,
1735 .mac_get_rx_stats = cgx_get_rx_stats,
1736 .mac_get_tx_stats = cgx_get_tx_stats,
1737 .mac_enadis_rx_pause_fwding = cgx_lmac_enadis_rx_pause_fwding,
1738 .mac_get_pause_frm_status = cgx_lmac_get_pause_frm_status,
1739 .mac_enadis_pause_frm = cgx_lmac_enadis_pause_frm,
1740 .mac_pause_frm_config = cgx_lmac_pause_frm_config,
1741 .mac_enadis_ptp_config = cgx_lmac_ptp_config,
1742 .mac_rx_tx_enable = cgx_lmac_rx_tx_enable,
1743 .mac_tx_enable = cgx_lmac_tx_enable,
1744 .pfc_config = cgx_lmac_pfc_config,
1745 .mac_get_pfc_frm_cfg = cgx_lmac_get_pfc_frm_cfg,
1746 };
1747
cgx_probe(struct pci_dev * pdev,const struct pci_device_id * id)1748 static int cgx_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1749 {
1750 struct device *dev = &pdev->dev;
1751 struct cgx *cgx;
1752 int err, nvec;
1753
1754 cgx = devm_kzalloc(dev, sizeof(*cgx), GFP_KERNEL);
1755 if (!cgx)
1756 return -ENOMEM;
1757 cgx->pdev = pdev;
1758
1759 pci_set_drvdata(pdev, cgx);
1760
1761 /* Use mac_ops to get MAC specific features */
1762 if (pdev->device == PCI_DEVID_CN10K_RPM)
1763 cgx->mac_ops = rpm_get_mac_ops();
1764 else
1765 cgx->mac_ops = &cgx_mac_ops;
1766
1767 err = pci_enable_device(pdev);
1768 if (err) {
1769 dev_err(dev, "Failed to enable PCI device\n");
1770 pci_set_drvdata(pdev, NULL);
1771 return err;
1772 }
1773
1774 err = pci_request_regions(pdev, DRV_NAME);
1775 if (err) {
1776 dev_err(dev, "PCI request regions failed 0x%x\n", err);
1777 goto err_disable_device;
1778 }
1779
1780 /* MAP configuration registers */
1781 cgx->reg_base = pcim_iomap(pdev, PCI_CFG_REG_BAR_NUM, 0);
1782 if (!cgx->reg_base) {
1783 dev_err(dev, "CGX: Cannot map CSR memory space, aborting\n");
1784 err = -ENOMEM;
1785 goto err_release_regions;
1786 }
1787
1788 cgx->lmac_count = cgx->mac_ops->get_nr_lmacs(cgx);
1789 if (!cgx->lmac_count) {
1790 dev_notice(dev, "CGX %d LMAC count is zero, skipping probe\n", cgx->cgx_id);
1791 err = -EOPNOTSUPP;
1792 goto err_release_regions;
1793 }
1794
1795 nvec = pci_msix_vec_count(cgx->pdev);
1796 err = pci_alloc_irq_vectors(pdev, nvec, nvec, PCI_IRQ_MSIX);
1797 if (err < 0 || err != nvec) {
1798 dev_err(dev, "Request for %d msix vectors failed, err %d\n",
1799 nvec, err);
1800 goto err_release_regions;
1801 }
1802
1803 cgx->cgx_id = (pci_resource_start(pdev, PCI_CFG_REG_BAR_NUM) >> 24)
1804 & CGX_ID_MASK;
1805
1806 /* init wq for processing linkup requests */
1807 INIT_WORK(&cgx->cgx_cmd_work, cgx_lmac_linkup_work);
1808 cgx->cgx_cmd_workq = alloc_workqueue("cgx_cmd_workq", 0, 0);
1809 if (!cgx->cgx_cmd_workq) {
1810 dev_err(dev, "alloc workqueue failed for cgx cmd");
1811 err = -ENOMEM;
1812 goto err_free_irq_vectors;
1813 }
1814
1815 list_add(&cgx->cgx_list, &cgx_list);
1816
1817
1818 cgx_populate_features(cgx);
1819
1820 mutex_init(&cgx->lock);
1821
1822 err = cgx_lmac_init(cgx);
1823 if (err)
1824 goto err_release_lmac;
1825
1826 return 0;
1827
1828 err_release_lmac:
1829 cgx_lmac_exit(cgx);
1830 list_del(&cgx->cgx_list);
1831 err_free_irq_vectors:
1832 pci_free_irq_vectors(pdev);
1833 err_release_regions:
1834 pci_release_regions(pdev);
1835 err_disable_device:
1836 pci_disable_device(pdev);
1837 pci_set_drvdata(pdev, NULL);
1838 return err;
1839 }
1840
cgx_remove(struct pci_dev * pdev)1841 static void cgx_remove(struct pci_dev *pdev)
1842 {
1843 struct cgx *cgx = pci_get_drvdata(pdev);
1844
1845 if (cgx) {
1846 cgx_lmac_exit(cgx);
1847 list_del(&cgx->cgx_list);
1848 }
1849 pci_free_irq_vectors(pdev);
1850 pci_release_regions(pdev);
1851 pci_disable_device(pdev);
1852 pci_set_drvdata(pdev, NULL);
1853 }
1854
1855 struct pci_driver cgx_driver = {
1856 .name = DRV_NAME,
1857 .id_table = cgx_id_table,
1858 .probe = cgx_probe,
1859 .remove = cgx_remove,
1860 };
1861
