1 /****************************************************************************** 2 * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved. 3 * 4 * This program is distributed in the hope that it will be useful, but WITHOUT 5 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 6 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 7 * more details. 8 * 9 * The full GNU General Public License is included in this distribution in the 10 * file called LICENSE. 11 * 12 * Contact Information: 13 * wlanfae <wlanfae@realtek.com> 14 *****************************************************************************/ 15 #ifndef __R8192UDM_H__ 16 #define __R8192UDM_H__ 17 18 19 /*--------------------------Define Parameters-------------------------------*/ 20 #define OFDM_Table_Length 19 21 #define CCK_Table_length 12 22 23 #define DM_DIG_THRESH_HIGH 40 24 #define DM_DIG_THRESH_LOW 35 25 26 #define DM_DIG_HIGH_PWR_THRESH_HIGH 75 27 #define DM_DIG_HIGH_PWR_THRESH_LOW 70 28 29 #define BW_AUTO_SWITCH_HIGH_LOW 25 30 #define BW_AUTO_SWITCH_LOW_HIGH 30 31 32 #define DM_DIG_BACKOFF 12 33 #define DM_DIG_MAX 0x36 34 #define DM_DIG_MIN 0x1c 35 #define DM_DIG_MIN_Netcore 0x12 36 37 #define RxPathSelection_SS_TH_low 30 38 #define RxPathSelection_diff_TH 18 39 40 #define RateAdaptiveTH_High 50 41 #define RateAdaptiveTH_Low_20M 30 42 #define RateAdaptiveTH_Low_40M 10 43 #define VeryLowRSSI 15 44 45 #define WAIotTHVal 25 46 47 #define E_FOR_TX_POWER_TRACK 300 48 #define TX_POWER_NEAR_FIELD_THRESH_HIGH 68 49 #define TX_POWER_NEAR_FIELD_THRESH_LOW 62 50 #define TX_POWER_ATHEROAP_THRESH_HIGH 78 51 #define TX_POWER_ATHEROAP_THRESH_LOW 72 52 53 #define Current_Tx_Rate_Reg 0x1e0 54 #define Initial_Tx_Rate_Reg 0x1e1 55 #define Tx_Retry_Count_Reg 0x1ac 56 #define RegC38_TH 20 57 58 #define DM_Type_ByDriver 1 59 60 /*--------------------------Define Parameters-------------------------------*/ 61 62 63 /*------------------------------Define structure----------------------------*/ 64 struct dig_t { 65 u8 dig_enable_flag; 66 u8 dig_algorithm; 67 u8 dig_algorithm_switch; 68 69 long rssi_low_thresh; 70 long rssi_high_thresh; 71 72 long rssi_high_power_lowthresh; 73 long rssi_high_power_highthresh; 74 75 u8 dig_state; 76 u8 dig_highpwr_state; 77 u8 CurSTAConnectState; 78 u8 PreSTAConnectState; 79 80 u8 curpd_thstate; 81 u8 prepd_thstate; 82 u8 curcs_ratio_state; 83 u8 precs_ratio_state; 84 85 u32 pre_ig_value; 86 u32 cur_ig_value; 87 88 u8 backoff_val; 89 u8 rx_gain_range_max; 90 u8 rx_gain_range_min; 91 92 long rssi_val; 93 }; 94 95 enum dm_dig_sta { 96 DM_STA_DIG_OFF = 0, 97 DM_STA_DIG_ON, 98 DM_STA_DIG_MAX 99 }; 100 101 102 enum dm_ratr_sta { 103 DM_RATR_STA_HIGH = 0, 104 DM_RATR_STA_MIDDLE = 1, 105 DM_RATR_STA_LOW = 2, 106 DM_RATR_STA_MAX 107 }; 108 109 enum dm_dig_alg { 110 DIG_ALGO_BY_FALSE_ALARM = 0, 111 DIG_ALGO_BY_RSSI = 1, 112 DIG_ALGO_BEFORE_CONNECT_BY_RSSI_AND_ALARM = 2, 113 DIG_ALGO_BY_TOW_PORT = 3, 114 DIG_ALGO_MAX 115 }; 116 117 enum dm_dig_connect { 118 DIG_STA_DISCONNECT = 0, 119 DIG_STA_CONNECT = 1, 120 DIG_STA_BEFORE_CONNECT = 2, 121 DIG_AP_DISCONNECT = 3, 122 DIG_AP_CONNECT = 4, 123 DIG_AP_ADD_STATION = 5, 124 DIG_CONNECT_MAX 125 }; 126 127 enum dm_dig_pd_th { 128 DIG_PD_AT_LOW_POWER = 0, 129 DIG_PD_AT_NORMAL_POWER = 1, 130 DIG_PD_AT_HIGH_POWER = 2, 131 DIG_PD_MAX 132 }; 133 134 enum dm_dig_cs_ratio { 135 DIG_CS_RATIO_LOWER = 0, 136 DIG_CS_RATIO_HIGHER = 1, 137 DIG_CS_MAX 138 }; 139 140 struct drx_path_sel { 141 u8 Enable; 142 u8 cck_method; 143 u8 cck_Rx_path; 144 145 u8 SS_TH_low; 146 u8 diff_TH; 147 u8 disabledRF; 148 u8 reserved; 149 150 u8 rf_rssi[4]; 151 u8 rf_enable_rssi_th[4]; 152 long cck_pwdb_sta[4]; 153 }; 154 155 enum dm_cck_rx_path_method { 156 CCK_Rx_Version_1 = 0, 157 CCK_Rx_Version_2 = 1, 158 CCK_Rx_Version_MAX 159 }; 160 161 162 struct dcmd_txcmd { 163 u32 Op; 164 u32 Length; 165 u32 Value; 166 }; 167 /*------------------------------Define structure----------------------------*/ 168 169 170 /*------------------------Export global variable----------------------------*/ 171 extern struct dig_t dm_digtable; 172 extern struct drx_path_sel DM_RxPathSelTable; 173 174 /* Pre-calculated gain tables */ 175 extern const u32 dm_tx_bb_gain[TxBBGainTableLength]; 176 extern const u8 dm_cck_tx_bb_gain[CCKTxBBGainTableLength][8]; 177 extern const u8 dm_cck_tx_bb_gain_ch14[CCKTxBBGainTableLength][8]; 178 /* Maps table index to iq amplify gain (dB, 12 to -24dB) */ 179 #define dm_tx_bb_gain_idx_to_amplify(idx) (-idx + 12) 180 181 /*------------------------Export global variable----------------------------*/ 182 183 184 /*--------------------------Exported Function prototype---------------------*/ 185 /*--------------------------Exported Function prototype---------------------*/ 186 187 void rtl92e_dm_init(struct net_device *dev); 188 void rtl92e_dm_deinit(struct net_device *dev); 189 190 void rtl92e_dm_watchdog(struct net_device *dev); 191 192 193 void rtl92e_init_adaptive_rate(struct net_device *dev); 194 void rtl92e_dm_txpower_tracking_wq(void *data); 195 196 void rtl92e_dm_cck_txpower_adjust(struct net_device *dev, bool binch14); 197 198 void rtl92e_dm_restore_state(struct net_device *dev); 199 void rtl92e_dm_backup_state(struct net_device *dev); 200 void rtl92e_dm_init_edca_turbo(struct net_device *dev); 201 void rtl92e_dm_rf_pathcheck_wq(void *data); 202 void rtl92e_dm_init_txpower_tracking(struct net_device *dev); 203 #endif /*__R8192UDM_H__ */ 204
