1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Port on Texas Instruments TMS320C6x architecture
4 *
5 * Copyright (C) 2004, 2006, 2009, 2010, 2011 Texas Instruments Incorporated
6 * Author: Aurelien Jacquiot (aurelien.jacquiot@jaluna.com)
7 */
8 #include <linux/dma-mapping.h>
9 #include <linux/memblock.h>
10 #include <linux/seq_file.h>
11 #include <linux/clkdev.h>
12 #include <linux/initrd.h>
13 #include <linux/kernel.h>
14 #include <linux/module.h>
15 #include <linux/of_fdt.h>
16 #include <linux/string.h>
17 #include <linux/errno.h>
18 #include <linux/cache.h>
19 #include <linux/delay.h>
20 #include <linux/sched.h>
21 #include <linux/clk.h>
22 #include <linux/cpu.h>
23 #include <linux/fs.h>
24 #include <linux/of.h>
25 #include <linux/console.h>
26 #include <linux/screen_info.h>
27
28 #include <asm/sections.h>
29 #include <asm/div64.h>
30 #include <asm/setup.h>
31 #include <asm/dscr.h>
32 #include <asm/clock.h>
33 #include <asm/soc.h>
34 #include <asm/special_insns.h>
35
36 static const char *c6x_soc_name;
37
38 struct screen_info screen_info;
39
40 int c6x_num_cores;
41 EXPORT_SYMBOL_GPL(c6x_num_cores);
42
43 unsigned int c6x_silicon_rev;
44 EXPORT_SYMBOL_GPL(c6x_silicon_rev);
45
46 /*
47 * Device status register. This holds information
48 * about device configuration needed by some drivers.
49 */
50 unsigned int c6x_devstat;
51 EXPORT_SYMBOL_GPL(c6x_devstat);
52
53 /*
54 * Some SoCs have fuse registers holding a unique MAC
55 * address. This is parsed out of the device tree with
56 * the resulting MAC being held here.
57 */
58 unsigned char c6x_fuse_mac[6];
59
60 unsigned long memory_start;
61 unsigned long memory_end;
62 EXPORT_SYMBOL(memory_end);
63
64 unsigned long ram_start;
65 unsigned long ram_end;
66
67 /* Uncached memory for DMA consistent use (memdma=) */
68 static unsigned long dma_start __initdata;
69 static unsigned long dma_size __initdata;
70
71 struct cpuinfo_c6x {
72 const char *cpu_name;
73 const char *cpu_voltage;
74 const char *mmu;
75 const char *fpu;
76 char *cpu_rev;
77 unsigned int core_id;
78 char __cpu_rev[5];
79 };
80
81 static DEFINE_PER_CPU(struct cpuinfo_c6x, cpu_data);
82
83 unsigned int ticks_per_ns_scaled;
84 EXPORT_SYMBOL(ticks_per_ns_scaled);
85
86 unsigned int c6x_core_freq;
87
get_cpuinfo(void)88 static void __init get_cpuinfo(void)
89 {
90 unsigned cpu_id, rev_id, csr;
91 struct clk *coreclk = clk_get_sys(NULL, "core");
92 unsigned long core_khz;
93 u64 tmp;
94 struct cpuinfo_c6x *p;
95 struct device_node *node;
96
97 p = &per_cpu(cpu_data, smp_processor_id());
98
99 if (!IS_ERR(coreclk))
100 c6x_core_freq = clk_get_rate(coreclk);
101 else {
102 printk(KERN_WARNING
103 "Cannot find core clock frequency. Using 700MHz\n");
104 c6x_core_freq = 700000000;
105 }
106
107 core_khz = c6x_core_freq / 1000;
108
109 tmp = (uint64_t)core_khz << C6X_NDELAY_SCALE;
110 do_div(tmp, 1000000);
111 ticks_per_ns_scaled = tmp;
112
113 csr = get_creg(CSR);
114 cpu_id = csr >> 24;
115 rev_id = (csr >> 16) & 0xff;
116
117 p->mmu = "none";
118 p->fpu = "none";
119 p->cpu_voltage = "unknown";
120
121 switch (cpu_id) {
122 case 0:
123 p->cpu_name = "C67x";
124 p->fpu = "yes";
125 break;
126 case 2:
127 p->cpu_name = "C62x";
128 break;
129 case 8:
130 p->cpu_name = "C64x";
131 break;
132 case 12:
133 p->cpu_name = "C64x";
134 break;
135 case 16:
136 p->cpu_name = "C64x+";
137 p->cpu_voltage = "1.2";
138 break;
139 case 21:
140 p->cpu_name = "C66X";
141 p->cpu_voltage = "1.2";
142 break;
143 default:
144 p->cpu_name = "unknown";
145 break;
146 }
147
148 if (cpu_id < 16) {
149 switch (rev_id) {
150 case 0x1:
151 if (cpu_id > 8) {
152 p->cpu_rev = "DM640/DM641/DM642/DM643";
153 p->cpu_voltage = "1.2 - 1.4";
154 } else {
155 p->cpu_rev = "C6201";
156 p->cpu_voltage = "2.5";
157 }
158 break;
159 case 0x2:
160 p->cpu_rev = "C6201B/C6202/C6211";
161 p->cpu_voltage = "1.8";
162 break;
163 case 0x3:
164 p->cpu_rev = "C6202B/C6203/C6204/C6205";
165 p->cpu_voltage = "1.5";
166 break;
167 case 0x201:
168 p->cpu_rev = "C6701 revision 0 (early CPU)";
169 p->cpu_voltage = "1.8";
170 break;
171 case 0x202:
172 p->cpu_rev = "C6701/C6711/C6712";
173 p->cpu_voltage = "1.8";
174 break;
175 case 0x801:
176 p->cpu_rev = "C64x";
177 p->cpu_voltage = "1.5";
178 break;
179 default:
180 p->cpu_rev = "unknown";
181 }
182 } else {
183 p->cpu_rev = p->__cpu_rev;
184 snprintf(p->__cpu_rev, sizeof(p->__cpu_rev), "0x%x", cpu_id);
185 }
186
187 p->core_id = get_coreid();
188
189 for_each_of_cpu_node(node)
190 ++c6x_num_cores;
191
192 node = of_find_node_by_name(NULL, "soc");
193 if (node) {
194 if (of_property_read_string(node, "model", &c6x_soc_name))
195 c6x_soc_name = "unknown";
196 of_node_put(node);
197 } else
198 c6x_soc_name = "unknown";
199
200 printk(KERN_INFO "CPU%d: %s rev %s, %s volts, %uMHz\n",
201 p->core_id, p->cpu_name, p->cpu_rev,
202 p->cpu_voltage, c6x_core_freq / 1000000);
203 }
204
205 /*
206 * Early parsing of the command line
207 */
208 static u32 mem_size __initdata;
209
210 /* "mem=" parsing. */
early_mem(char * p)211 static int __init early_mem(char *p)
212 {
213 if (!p)
214 return -EINVAL;
215
216 mem_size = memparse(p, &p);
217 /* don't remove all of memory when handling "mem={invalid}" */
218 if (mem_size == 0)
219 return -EINVAL;
220
221 return 0;
222 }
223 early_param("mem", early_mem);
224
225 /* "memdma=<size>[@<address>]" parsing. */
early_memdma(char * p)226 static int __init early_memdma(char *p)
227 {
228 if (!p)
229 return -EINVAL;
230
231 dma_size = memparse(p, &p);
232 if (*p == '@')
233 dma_start = memparse(p, &p);
234
235 return 0;
236 }
237 early_param("memdma", early_memdma);
238
c6x_add_memory(phys_addr_t start,unsigned long size)239 int __init c6x_add_memory(phys_addr_t start, unsigned long size)
240 {
241 static int ram_found __initdata;
242
243 /* We only handle one bank (the one with PAGE_OFFSET) for now */
244 if (ram_found)
245 return -EINVAL;
246
247 if (start > PAGE_OFFSET || PAGE_OFFSET >= (start + size))
248 return 0;
249
250 ram_start = start;
251 ram_end = start + size;
252
253 ram_found = 1;
254 return 0;
255 }
256
257 /*
258 * Do early machine setup and device tree parsing. This is called very
259 * early on the boot process.
260 */
machine_init(unsigned long dt_ptr)261 notrace void __init machine_init(unsigned long dt_ptr)
262 {
263 void *dtb = __va(dt_ptr);
264 void *fdt = __dtb_start;
265
266 /* interrupts must be masked */
267 set_creg(IER, 2);
268
269 /*
270 * Set the Interrupt Service Table (IST) to the beginning of the
271 * vector table.
272 */
273 set_ist(_vectors_start);
274
275 /*
276 * dtb is passed in from bootloader.
277 * fdt is linked in blob.
278 */
279 if (dtb && dtb != fdt)
280 fdt = dtb;
281
282 /* Do some early initialization based on the flat device tree */
283 early_init_dt_scan(fdt);
284
285 parse_early_param();
286 }
287
setup_arch(char ** cmdline_p)288 void __init setup_arch(char **cmdline_p)
289 {
290 struct memblock_region *reg;
291
292 printk(KERN_INFO "Initializing kernel\n");
293
294 /* Initialize command line */
295 *cmdline_p = boot_command_line;
296
297 memory_end = ram_end;
298 memory_end &= ~(PAGE_SIZE - 1);
299
300 if (mem_size && (PAGE_OFFSET + PAGE_ALIGN(mem_size)) < memory_end)
301 memory_end = PAGE_OFFSET + PAGE_ALIGN(mem_size);
302
303 /* add block that this kernel can use */
304 memblock_add(PAGE_OFFSET, memory_end - PAGE_OFFSET);
305
306 /* reserve kernel text/data/bss */
307 memblock_reserve(PAGE_OFFSET,
308 PAGE_ALIGN((unsigned long)&_end - PAGE_OFFSET));
309
310 if (dma_size) {
311 /* align to cacheability granularity */
312 dma_size = CACHE_REGION_END(dma_size);
313
314 if (!dma_start)
315 dma_start = memory_end - dma_size;
316
317 /* align to cacheability granularity */
318 dma_start = CACHE_REGION_START(dma_start);
319
320 /* reserve DMA memory taken from kernel memory */
321 if (memblock_is_region_memory(dma_start, dma_size))
322 memblock_reserve(dma_start, dma_size);
323 }
324
325 memory_start = PAGE_ALIGN((unsigned int) &_end);
326
327 printk(KERN_INFO "Memory Start=%08lx, Memory End=%08lx\n",
328 memory_start, memory_end);
329
330 #ifdef CONFIG_BLK_DEV_INITRD
331 /*
332 * Reserve initrd memory if in kernel memory.
333 */
334 if (initrd_start < initrd_end)
335 if (memblock_is_region_memory(initrd_start,
336 initrd_end - initrd_start))
337 memblock_reserve(initrd_start,
338 initrd_end - initrd_start);
339 #endif
340
341 init_mm.start_code = (unsigned long) &_stext;
342 init_mm.end_code = (unsigned long) &_etext;
343 init_mm.end_data = memory_start;
344 init_mm.brk = memory_start;
345
346 unflatten_and_copy_device_tree();
347
348 c6x_cache_init();
349
350 /* Set the whole external memory as non-cacheable */
351 disable_caching(ram_start, ram_end - 1);
352
353 /* Set caching of external RAM used by Linux */
354 for_each_memblock(memory, reg)
355 enable_caching(CACHE_REGION_START(reg->base),
356 CACHE_REGION_START(reg->base + reg->size - 1));
357
358 #ifdef CONFIG_BLK_DEV_INITRD
359 /*
360 * Enable caching for initrd which falls outside kernel memory.
361 */
362 if (initrd_start < initrd_end) {
363 if (!memblock_is_region_memory(initrd_start,
364 initrd_end - initrd_start))
365 enable_caching(CACHE_REGION_START(initrd_start),
366 CACHE_REGION_START(initrd_end - 1));
367 }
368 #endif
369
370 /*
371 * Disable caching for dma coherent memory taken from kernel memory.
372 */
373 if (dma_size && memblock_is_region_memory(dma_start, dma_size))
374 disable_caching(dma_start,
375 CACHE_REGION_START(dma_start + dma_size - 1));
376
377 /* Initialize the coherent memory allocator */
378 coherent_mem_init(dma_start, dma_size);
379
380 max_low_pfn = PFN_DOWN(memory_end);
381 min_low_pfn = PFN_UP(memory_start);
382 max_pfn = max_low_pfn;
383 max_mapnr = max_low_pfn - min_low_pfn;
384
385 /* Get kmalloc into gear */
386 paging_init();
387
388 /*
389 * Probe for Device State Configuration Registers.
390 * We have to do this early in case timer needs to be enabled
391 * through DSCR.
392 */
393 dscr_probe();
394
395 /* We do this early for timer and core clock frequency */
396 c64x_setup_clocks();
397
398 /* Get CPU info */
399 get_cpuinfo();
400
401 #if defined(CONFIG_VT) && defined(CONFIG_DUMMY_CONSOLE)
402 conswitchp = &dummy_con;
403 #endif
404 }
405
406 #define cpu_to_ptr(n) ((void *)((long)(n)+1))
407 #define ptr_to_cpu(p) ((long)(p) - 1)
408
show_cpuinfo(struct seq_file * m,void * v)409 static int show_cpuinfo(struct seq_file *m, void *v)
410 {
411 int n = ptr_to_cpu(v);
412 struct cpuinfo_c6x *p = &per_cpu(cpu_data, n);
413
414 if (n == 0) {
415 seq_printf(m,
416 "soc\t\t: %s\n"
417 "soc revision\t: 0x%x\n"
418 "soc cores\t: %d\n",
419 c6x_soc_name, c6x_silicon_rev, c6x_num_cores);
420 }
421
422 seq_printf(m,
423 "\n"
424 "processor\t: %d\n"
425 "cpu\t\t: %s\n"
426 "core revision\t: %s\n"
427 "core voltage\t: %s\n"
428 "core id\t\t: %d\n"
429 "mmu\t\t: %s\n"
430 "fpu\t\t: %s\n"
431 "cpu MHz\t\t: %u\n"
432 "bogomips\t: %lu.%02lu\n\n",
433 n,
434 p->cpu_name, p->cpu_rev, p->cpu_voltage,
435 p->core_id, p->mmu, p->fpu,
436 (c6x_core_freq + 500000) / 1000000,
437 (loops_per_jiffy/(500000/HZ)),
438 (loops_per_jiffy/(5000/HZ))%100);
439
440 return 0;
441 }
442
c_start(struct seq_file * m,loff_t * pos)443 static void *c_start(struct seq_file *m, loff_t *pos)
444 {
445 return *pos < nr_cpu_ids ? cpu_to_ptr(*pos) : NULL;
446 }
c_next(struct seq_file * m,void * v,loff_t * pos)447 static void *c_next(struct seq_file *m, void *v, loff_t *pos)
448 {
449 ++*pos;
450 return NULL;
451 }
c_stop(struct seq_file * m,void * v)452 static void c_stop(struct seq_file *m, void *v)
453 {
454 }
455
456 const struct seq_operations cpuinfo_op = {
457 c_start,
458 c_stop,
459 c_next,
460 show_cpuinfo
461 };
462
463 static struct cpu cpu_devices[NR_CPUS];
464
topology_init(void)465 static int __init topology_init(void)
466 {
467 int i;
468
469 for_each_present_cpu(i)
470 register_cpu(&cpu_devices[i], i);
471
472 return 0;
473 }
474
475 subsys_initcall(topology_init);
476