1 /*
2 * Copyright (c) 2009-2010 Chelsio, Inc. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #include <linux/module.h>
34 #include <linux/moduleparam.h>
35 #include <rdma/ib_umem.h>
36 #include <linux/atomic.h>
37 #include <rdma/ib_user_verbs.h>
38
39 #include "iw_cxgb4.h"
40
41 int use_dsgl = 1;
42 module_param(use_dsgl, int, 0644);
43 MODULE_PARM_DESC(use_dsgl, "Use DSGL for PBL/FastReg (default=1) (DEPRECATED)");
44
45 #define T4_ULPTX_MIN_IO 32
46 #define C4IW_MAX_INLINE_SIZE 96
47 #define T4_ULPTX_MAX_DMA 1024
48 #define C4IW_INLINE_THRESHOLD 128
49
50 static int inline_threshold = C4IW_INLINE_THRESHOLD;
51 module_param(inline_threshold, int, 0644);
52 MODULE_PARM_DESC(inline_threshold, "inline vs dsgl threshold (default=128)");
53
mr_exceeds_hw_limits(struct c4iw_dev * dev,u64 length)54 static int mr_exceeds_hw_limits(struct c4iw_dev *dev, u64 length)
55 {
56 return (is_t4(dev->rdev.lldi.adapter_type) ||
57 is_t5(dev->rdev.lldi.adapter_type)) &&
58 length >= 8*1024*1024*1024ULL;
59 }
60
_c4iw_write_mem_dma_aligned(struct c4iw_rdev * rdev,u32 addr,u32 len,dma_addr_t data,struct sk_buff * skb,struct c4iw_wr_wait * wr_waitp)61 static int _c4iw_write_mem_dma_aligned(struct c4iw_rdev *rdev, u32 addr,
62 u32 len, dma_addr_t data,
63 struct sk_buff *skb,
64 struct c4iw_wr_wait *wr_waitp)
65 {
66 struct ulp_mem_io *req;
67 struct ulptx_sgl *sgl;
68 u8 wr_len;
69 int ret = 0;
70
71 addr &= 0x7FFFFFF;
72
73 if (wr_waitp)
74 c4iw_init_wr_wait(wr_waitp);
75 wr_len = roundup(sizeof(*req) + sizeof(*sgl), 16);
76
77 if (!skb) {
78 skb = alloc_skb(wr_len, GFP_KERNEL | __GFP_NOFAIL);
79 if (!skb)
80 return -ENOMEM;
81 }
82 set_wr_txq(skb, CPL_PRIORITY_CONTROL, 0);
83
84 req = __skb_put_zero(skb, wr_len);
85 INIT_ULPTX_WR(req, wr_len, 0, 0);
86 req->wr.wr_hi = cpu_to_be32(FW_WR_OP_V(FW_ULPTX_WR) |
87 (wr_waitp ? FW_WR_COMPL_F : 0));
88 req->wr.wr_lo = wr_waitp ? (__force __be64)(unsigned long)wr_waitp : 0L;
89 req->wr.wr_mid = cpu_to_be32(FW_WR_LEN16_V(DIV_ROUND_UP(wr_len, 16)));
90 req->cmd = cpu_to_be32(ULPTX_CMD_V(ULP_TX_MEM_WRITE) |
91 T5_ULP_MEMIO_ORDER_V(1) |
92 T5_ULP_MEMIO_FID_V(rdev->lldi.rxq_ids[0]));
93 req->dlen = cpu_to_be32(ULP_MEMIO_DATA_LEN_V(len>>5));
94 req->len16 = cpu_to_be32(DIV_ROUND_UP(wr_len-sizeof(req->wr), 16));
95 req->lock_addr = cpu_to_be32(ULP_MEMIO_ADDR_V(addr));
96
97 sgl = (struct ulptx_sgl *)(req + 1);
98 sgl->cmd_nsge = cpu_to_be32(ULPTX_CMD_V(ULP_TX_SC_DSGL) |
99 ULPTX_NSGE_V(1));
100 sgl->len0 = cpu_to_be32(len);
101 sgl->addr0 = cpu_to_be64(data);
102
103 if (wr_waitp)
104 ret = c4iw_ref_send_wait(rdev, skb, wr_waitp, 0, 0, __func__);
105 else
106 ret = c4iw_ofld_send(rdev, skb);
107 return ret;
108 }
109
_c4iw_write_mem_inline(struct c4iw_rdev * rdev,u32 addr,u32 len,void * data,struct sk_buff * skb,struct c4iw_wr_wait * wr_waitp)110 static int _c4iw_write_mem_inline(struct c4iw_rdev *rdev, u32 addr, u32 len,
111 void *data, struct sk_buff *skb,
112 struct c4iw_wr_wait *wr_waitp)
113 {
114 struct ulp_mem_io *req;
115 struct ulptx_idata *sc;
116 u8 wr_len, *to_dp, *from_dp;
117 int copy_len, num_wqe, i, ret = 0;
118 __be32 cmd = cpu_to_be32(ULPTX_CMD_V(ULP_TX_MEM_WRITE));
119
120 if (is_t4(rdev->lldi.adapter_type))
121 cmd |= cpu_to_be32(ULP_MEMIO_ORDER_F);
122 else
123 cmd |= cpu_to_be32(T5_ULP_MEMIO_IMM_F);
124
125 addr &= 0x7FFFFFF;
126 pr_debug("addr 0x%x len %u\n", addr, len);
127 num_wqe = DIV_ROUND_UP(len, C4IW_MAX_INLINE_SIZE);
128 c4iw_init_wr_wait(wr_waitp);
129 for (i = 0; i < num_wqe; i++) {
130
131 copy_len = len > C4IW_MAX_INLINE_SIZE ? C4IW_MAX_INLINE_SIZE :
132 len;
133 wr_len = roundup(sizeof(*req) + sizeof(*sc) +
134 roundup(copy_len, T4_ULPTX_MIN_IO),
135 16);
136
137 if (!skb) {
138 skb = alloc_skb(wr_len, GFP_KERNEL | __GFP_NOFAIL);
139 if (!skb)
140 return -ENOMEM;
141 }
142 set_wr_txq(skb, CPL_PRIORITY_CONTROL, 0);
143
144 req = __skb_put_zero(skb, wr_len);
145 INIT_ULPTX_WR(req, wr_len, 0, 0);
146
147 if (i == (num_wqe-1)) {
148 req->wr.wr_hi = cpu_to_be32(FW_WR_OP_V(FW_ULPTX_WR) |
149 FW_WR_COMPL_F);
150 req->wr.wr_lo = (__force __be64)(unsigned long)wr_waitp;
151 } else
152 req->wr.wr_hi = cpu_to_be32(FW_WR_OP_V(FW_ULPTX_WR));
153 req->wr.wr_mid = cpu_to_be32(
154 FW_WR_LEN16_V(DIV_ROUND_UP(wr_len, 16)));
155
156 req->cmd = cmd;
157 req->dlen = cpu_to_be32(ULP_MEMIO_DATA_LEN_V(
158 DIV_ROUND_UP(copy_len, T4_ULPTX_MIN_IO)));
159 req->len16 = cpu_to_be32(DIV_ROUND_UP(wr_len-sizeof(req->wr),
160 16));
161 req->lock_addr = cpu_to_be32(ULP_MEMIO_ADDR_V(addr + i * 3));
162
163 sc = (struct ulptx_idata *)(req + 1);
164 sc->cmd_more = cpu_to_be32(ULPTX_CMD_V(ULP_TX_SC_IMM));
165 sc->len = cpu_to_be32(roundup(copy_len, T4_ULPTX_MIN_IO));
166
167 to_dp = (u8 *)(sc + 1);
168 from_dp = (u8 *)data + i * C4IW_MAX_INLINE_SIZE;
169 if (data)
170 memcpy(to_dp, from_dp, copy_len);
171 else
172 memset(to_dp, 0, copy_len);
173 if (copy_len % T4_ULPTX_MIN_IO)
174 memset(to_dp + copy_len, 0, T4_ULPTX_MIN_IO -
175 (copy_len % T4_ULPTX_MIN_IO));
176 if (i == (num_wqe-1))
177 ret = c4iw_ref_send_wait(rdev, skb, wr_waitp, 0, 0,
178 __func__);
179 else
180 ret = c4iw_ofld_send(rdev, skb);
181 if (ret)
182 break;
183 skb = NULL;
184 len -= C4IW_MAX_INLINE_SIZE;
185 }
186
187 return ret;
188 }
189
_c4iw_write_mem_dma(struct c4iw_rdev * rdev,u32 addr,u32 len,void * data,struct sk_buff * skb,struct c4iw_wr_wait * wr_waitp)190 static int _c4iw_write_mem_dma(struct c4iw_rdev *rdev, u32 addr, u32 len,
191 void *data, struct sk_buff *skb,
192 struct c4iw_wr_wait *wr_waitp)
193 {
194 u32 remain = len;
195 u32 dmalen;
196 int ret = 0;
197 dma_addr_t daddr;
198 dma_addr_t save;
199
200 daddr = dma_map_single(&rdev->lldi.pdev->dev, data, len, DMA_TO_DEVICE);
201 if (dma_mapping_error(&rdev->lldi.pdev->dev, daddr))
202 return -1;
203 save = daddr;
204
205 while (remain > inline_threshold) {
206 if (remain < T4_ULPTX_MAX_DMA) {
207 if (remain & ~T4_ULPTX_MIN_IO)
208 dmalen = remain & ~(T4_ULPTX_MIN_IO-1);
209 else
210 dmalen = remain;
211 } else
212 dmalen = T4_ULPTX_MAX_DMA;
213 remain -= dmalen;
214 ret = _c4iw_write_mem_dma_aligned(rdev, addr, dmalen, daddr,
215 skb, remain ? NULL : wr_waitp);
216 if (ret)
217 goto out;
218 addr += dmalen >> 5;
219 data += dmalen;
220 daddr += dmalen;
221 }
222 if (remain)
223 ret = _c4iw_write_mem_inline(rdev, addr, remain, data, skb,
224 wr_waitp);
225 out:
226 dma_unmap_single(&rdev->lldi.pdev->dev, save, len, DMA_TO_DEVICE);
227 return ret;
228 }
229
230 /*
231 * write len bytes of data into addr (32B aligned address)
232 * If data is NULL, clear len byte of memory to zero.
233 */
write_adapter_mem(struct c4iw_rdev * rdev,u32 addr,u32 len,void * data,struct sk_buff * skb,struct c4iw_wr_wait * wr_waitp)234 static int write_adapter_mem(struct c4iw_rdev *rdev, u32 addr, u32 len,
235 void *data, struct sk_buff *skb,
236 struct c4iw_wr_wait *wr_waitp)
237 {
238 int ret;
239
240 if (!rdev->lldi.ulptx_memwrite_dsgl || !use_dsgl) {
241 ret = _c4iw_write_mem_inline(rdev, addr, len, data, skb,
242 wr_waitp);
243 goto out;
244 }
245
246 if (len <= inline_threshold) {
247 ret = _c4iw_write_mem_inline(rdev, addr, len, data, skb,
248 wr_waitp);
249 goto out;
250 }
251
252 ret = _c4iw_write_mem_dma(rdev, addr, len, data, skb, wr_waitp);
253 if (ret) {
254 pr_warn_ratelimited("%s: dma map failure (non fatal)\n",
255 pci_name(rdev->lldi.pdev));
256 ret = _c4iw_write_mem_inline(rdev, addr, len, data, skb,
257 wr_waitp);
258 }
259 out:
260 return ret;
261
262 }
263
264 /*
265 * Build and write a TPT entry.
266 * IN: stag key, pdid, perm, bind_enabled, zbva, to, len, page_size,
267 * pbl_size and pbl_addr
268 * OUT: stag index
269 */
write_tpt_entry(struct c4iw_rdev * rdev,u32 reset_tpt_entry,u32 * stag,u8 stag_state,u32 pdid,enum fw_ri_stag_type type,enum fw_ri_mem_perms perm,int bind_enabled,u32 zbva,u64 to,u64 len,u8 page_size,u32 pbl_size,u32 pbl_addr,struct sk_buff * skb,struct c4iw_wr_wait * wr_waitp)270 static int write_tpt_entry(struct c4iw_rdev *rdev, u32 reset_tpt_entry,
271 u32 *stag, u8 stag_state, u32 pdid,
272 enum fw_ri_stag_type type, enum fw_ri_mem_perms perm,
273 int bind_enabled, u32 zbva, u64 to,
274 u64 len, u8 page_size, u32 pbl_size, u32 pbl_addr,
275 struct sk_buff *skb, struct c4iw_wr_wait *wr_waitp)
276 {
277 int err;
278 struct fw_ri_tpte *tpt;
279 u32 stag_idx;
280 static atomic_t key;
281
282 if (c4iw_fatal_error(rdev))
283 return -EIO;
284
285 tpt = kmalloc(sizeof(*tpt), GFP_KERNEL);
286 if (!tpt)
287 return -ENOMEM;
288
289 stag_state = stag_state > 0;
290 stag_idx = (*stag) >> 8;
291
292 if ((!reset_tpt_entry) && (*stag == T4_STAG_UNSET)) {
293 stag_idx = c4iw_get_resource(&rdev->resource.tpt_table);
294 if (!stag_idx) {
295 mutex_lock(&rdev->stats.lock);
296 rdev->stats.stag.fail++;
297 mutex_unlock(&rdev->stats.lock);
298 kfree(tpt);
299 return -ENOMEM;
300 }
301 mutex_lock(&rdev->stats.lock);
302 rdev->stats.stag.cur += 32;
303 if (rdev->stats.stag.cur > rdev->stats.stag.max)
304 rdev->stats.stag.max = rdev->stats.stag.cur;
305 mutex_unlock(&rdev->stats.lock);
306 *stag = (stag_idx << 8) | (atomic_inc_return(&key) & 0xff);
307 }
308 pr_debug("stag_state 0x%0x type 0x%0x pdid 0x%0x, stag_idx 0x%x\n",
309 stag_state, type, pdid, stag_idx);
310
311 /* write TPT entry */
312 if (reset_tpt_entry)
313 memset(tpt, 0, sizeof(*tpt));
314 else {
315 tpt->valid_to_pdid = cpu_to_be32(FW_RI_TPTE_VALID_F |
316 FW_RI_TPTE_STAGKEY_V((*stag & FW_RI_TPTE_STAGKEY_M)) |
317 FW_RI_TPTE_STAGSTATE_V(stag_state) |
318 FW_RI_TPTE_STAGTYPE_V(type) | FW_RI_TPTE_PDID_V(pdid));
319 tpt->locread_to_qpid = cpu_to_be32(FW_RI_TPTE_PERM_V(perm) |
320 (bind_enabled ? FW_RI_TPTE_MWBINDEN_F : 0) |
321 FW_RI_TPTE_ADDRTYPE_V((zbva ? FW_RI_ZERO_BASED_TO :
322 FW_RI_VA_BASED_TO))|
323 FW_RI_TPTE_PS_V(page_size));
324 tpt->nosnoop_pbladdr = !pbl_size ? 0 : cpu_to_be32(
325 FW_RI_TPTE_PBLADDR_V(PBL_OFF(rdev, pbl_addr)>>3));
326 tpt->len_lo = cpu_to_be32((u32)(len & 0xffffffffUL));
327 tpt->va_hi = cpu_to_be32((u32)(to >> 32));
328 tpt->va_lo_fbo = cpu_to_be32((u32)(to & 0xffffffffUL));
329 tpt->dca_mwbcnt_pstag = cpu_to_be32(0);
330 tpt->len_hi = cpu_to_be32((u32)(len >> 32));
331 }
332 err = write_adapter_mem(rdev, stag_idx +
333 (rdev->lldi.vr->stag.start >> 5),
334 sizeof(*tpt), tpt, skb, wr_waitp);
335
336 if (reset_tpt_entry) {
337 c4iw_put_resource(&rdev->resource.tpt_table, stag_idx);
338 mutex_lock(&rdev->stats.lock);
339 rdev->stats.stag.cur -= 32;
340 mutex_unlock(&rdev->stats.lock);
341 }
342 kfree(tpt);
343 return err;
344 }
345
write_pbl(struct c4iw_rdev * rdev,__be64 * pbl,u32 pbl_addr,u32 pbl_size,struct c4iw_wr_wait * wr_waitp)346 static int write_pbl(struct c4iw_rdev *rdev, __be64 *pbl,
347 u32 pbl_addr, u32 pbl_size, struct c4iw_wr_wait *wr_waitp)
348 {
349 int err;
350
351 pr_debug("*pdb_addr 0x%x, pbl_base 0x%x, pbl_size %d\n",
352 pbl_addr, rdev->lldi.vr->pbl.start,
353 pbl_size);
354
355 err = write_adapter_mem(rdev, pbl_addr >> 5, pbl_size << 3, pbl, NULL,
356 wr_waitp);
357 return err;
358 }
359
dereg_mem(struct c4iw_rdev * rdev,u32 stag,u32 pbl_size,u32 pbl_addr,struct sk_buff * skb,struct c4iw_wr_wait * wr_waitp)360 static int dereg_mem(struct c4iw_rdev *rdev, u32 stag, u32 pbl_size,
361 u32 pbl_addr, struct sk_buff *skb,
362 struct c4iw_wr_wait *wr_waitp)
363 {
364 return write_tpt_entry(rdev, 1, &stag, 0, 0, 0, 0, 0, 0, 0UL, 0, 0,
365 pbl_size, pbl_addr, skb, wr_waitp);
366 }
367
allocate_window(struct c4iw_rdev * rdev,u32 * stag,u32 pdid,struct c4iw_wr_wait * wr_waitp)368 static int allocate_window(struct c4iw_rdev *rdev, u32 *stag, u32 pdid,
369 struct c4iw_wr_wait *wr_waitp)
370 {
371 *stag = T4_STAG_UNSET;
372 return write_tpt_entry(rdev, 0, stag, 0, pdid, FW_RI_STAG_MW, 0, 0, 0,
373 0UL, 0, 0, 0, 0, NULL, wr_waitp);
374 }
375
deallocate_window(struct c4iw_rdev * rdev,u32 stag,struct sk_buff * skb,struct c4iw_wr_wait * wr_waitp)376 static int deallocate_window(struct c4iw_rdev *rdev, u32 stag,
377 struct sk_buff *skb,
378 struct c4iw_wr_wait *wr_waitp)
379 {
380 return write_tpt_entry(rdev, 1, &stag, 0, 0, 0, 0, 0, 0, 0UL, 0, 0, 0,
381 0, skb, wr_waitp);
382 }
383
allocate_stag(struct c4iw_rdev * rdev,u32 * stag,u32 pdid,u32 pbl_size,u32 pbl_addr,struct c4iw_wr_wait * wr_waitp)384 static int allocate_stag(struct c4iw_rdev *rdev, u32 *stag, u32 pdid,
385 u32 pbl_size, u32 pbl_addr,
386 struct c4iw_wr_wait *wr_waitp)
387 {
388 *stag = T4_STAG_UNSET;
389 return write_tpt_entry(rdev, 0, stag, 0, pdid, FW_RI_STAG_NSMR, 0, 0, 0,
390 0UL, 0, 0, pbl_size, pbl_addr, NULL, wr_waitp);
391 }
392
finish_mem_reg(struct c4iw_mr * mhp,u32 stag)393 static int finish_mem_reg(struct c4iw_mr *mhp, u32 stag)
394 {
395 u32 mmid;
396
397 mhp->attr.state = 1;
398 mhp->attr.stag = stag;
399 mmid = stag >> 8;
400 mhp->ibmr.rkey = mhp->ibmr.lkey = stag;
401 mhp->ibmr.length = mhp->attr.len;
402 mhp->ibmr.iova = mhp->attr.va_fbo;
403 mhp->ibmr.page_size = 1U << (mhp->attr.page_size + 12);
404 pr_debug("mmid 0x%x mhp %p\n", mmid, mhp);
405 return xa_insert_irq(&mhp->rhp->mrs, mmid, mhp, GFP_KERNEL);
406 }
407
register_mem(struct c4iw_dev * rhp,struct c4iw_pd * php,struct c4iw_mr * mhp,int shift)408 static int register_mem(struct c4iw_dev *rhp, struct c4iw_pd *php,
409 struct c4iw_mr *mhp, int shift)
410 {
411 u32 stag = T4_STAG_UNSET;
412 int ret;
413
414 ret = write_tpt_entry(&rhp->rdev, 0, &stag, 1, mhp->attr.pdid,
415 FW_RI_STAG_NSMR, mhp->attr.len ?
416 mhp->attr.perms : 0,
417 mhp->attr.mw_bind_enable, mhp->attr.zbva,
418 mhp->attr.va_fbo, mhp->attr.len ?
419 mhp->attr.len : -1, shift - 12,
420 mhp->attr.pbl_size, mhp->attr.pbl_addr, NULL,
421 mhp->wr_waitp);
422 if (ret)
423 return ret;
424
425 ret = finish_mem_reg(mhp, stag);
426 if (ret) {
427 dereg_mem(&rhp->rdev, mhp->attr.stag, mhp->attr.pbl_size,
428 mhp->attr.pbl_addr, mhp->dereg_skb, mhp->wr_waitp);
429 mhp->dereg_skb = NULL;
430 }
431 return ret;
432 }
433
alloc_pbl(struct c4iw_mr * mhp,int npages)434 static int alloc_pbl(struct c4iw_mr *mhp, int npages)
435 {
436 mhp->attr.pbl_addr = c4iw_pblpool_alloc(&mhp->rhp->rdev,
437 npages << 3);
438
439 if (!mhp->attr.pbl_addr)
440 return -ENOMEM;
441
442 mhp->attr.pbl_size = npages;
443
444 return 0;
445 }
446
c4iw_get_dma_mr(struct ib_pd * pd,int acc)447 struct ib_mr *c4iw_get_dma_mr(struct ib_pd *pd, int acc)
448 {
449 struct c4iw_dev *rhp;
450 struct c4iw_pd *php;
451 struct c4iw_mr *mhp;
452 int ret;
453 u32 stag = T4_STAG_UNSET;
454
455 pr_debug("ib_pd %p\n", pd);
456 php = to_c4iw_pd(pd);
457 rhp = php->rhp;
458
459 mhp = kzalloc(sizeof(*mhp), GFP_KERNEL);
460 if (!mhp)
461 return ERR_PTR(-ENOMEM);
462 mhp->wr_waitp = c4iw_alloc_wr_wait(GFP_KERNEL);
463 if (!mhp->wr_waitp) {
464 ret = -ENOMEM;
465 goto err_free_mhp;
466 }
467 c4iw_init_wr_wait(mhp->wr_waitp);
468
469 mhp->dereg_skb = alloc_skb(SGE_MAX_WR_LEN, GFP_KERNEL);
470 if (!mhp->dereg_skb) {
471 ret = -ENOMEM;
472 goto err_free_wr_wait;
473 }
474
475 mhp->rhp = rhp;
476 mhp->attr.pdid = php->pdid;
477 mhp->attr.perms = c4iw_ib_to_tpt_access(acc);
478 mhp->attr.mw_bind_enable = (acc&IB_ACCESS_MW_BIND) == IB_ACCESS_MW_BIND;
479 mhp->attr.zbva = 0;
480 mhp->attr.va_fbo = 0;
481 mhp->attr.page_size = 0;
482 mhp->attr.len = ~0ULL;
483 mhp->attr.pbl_size = 0;
484
485 ret = write_tpt_entry(&rhp->rdev, 0, &stag, 1, php->pdid,
486 FW_RI_STAG_NSMR, mhp->attr.perms,
487 mhp->attr.mw_bind_enable, 0, 0, ~0ULL, 0, 0, 0,
488 NULL, mhp->wr_waitp);
489 if (ret)
490 goto err_free_skb;
491
492 ret = finish_mem_reg(mhp, stag);
493 if (ret)
494 goto err_dereg_mem;
495 return &mhp->ibmr;
496 err_dereg_mem:
497 dereg_mem(&rhp->rdev, mhp->attr.stag, mhp->attr.pbl_size,
498 mhp->attr.pbl_addr, mhp->dereg_skb, mhp->wr_waitp);
499 err_free_skb:
500 kfree_skb(mhp->dereg_skb);
501 err_free_wr_wait:
502 c4iw_put_wr_wait(mhp->wr_waitp);
503 err_free_mhp:
504 kfree(mhp);
505 return ERR_PTR(ret);
506 }
507
c4iw_reg_user_mr(struct ib_pd * pd,u64 start,u64 length,u64 virt,int acc,struct ib_udata * udata)508 struct ib_mr *c4iw_reg_user_mr(struct ib_pd *pd, u64 start, u64 length,
509 u64 virt, int acc, struct ib_udata *udata)
510 {
511 __be64 *pages;
512 int shift, n, i;
513 int err = -ENOMEM;
514 struct sg_dma_page_iter sg_iter;
515 struct c4iw_dev *rhp;
516 struct c4iw_pd *php;
517 struct c4iw_mr *mhp;
518
519 pr_debug("ib_pd %p\n", pd);
520
521 if (length == ~0ULL)
522 return ERR_PTR(-EINVAL);
523
524 if ((length + start) < start)
525 return ERR_PTR(-EINVAL);
526
527 php = to_c4iw_pd(pd);
528 rhp = php->rhp;
529
530 if (mr_exceeds_hw_limits(rhp, length))
531 return ERR_PTR(-EINVAL);
532
533 mhp = kzalloc(sizeof(*mhp), GFP_KERNEL);
534 if (!mhp)
535 return ERR_PTR(-ENOMEM);
536 mhp->wr_waitp = c4iw_alloc_wr_wait(GFP_KERNEL);
537 if (!mhp->wr_waitp)
538 goto err_free_mhp;
539
540 mhp->dereg_skb = alloc_skb(SGE_MAX_WR_LEN, GFP_KERNEL);
541 if (!mhp->dereg_skb)
542 goto err_free_wr_wait;
543
544 mhp->rhp = rhp;
545
546 mhp->umem = ib_umem_get(udata, start, length, acc, 0);
547 if (IS_ERR(mhp->umem))
548 goto err_free_skb;
549
550 shift = PAGE_SHIFT;
551
552 n = ib_umem_num_pages(mhp->umem);
553 err = alloc_pbl(mhp, n);
554 if (err)
555 goto err_umem_release;
556
557 pages = (__be64 *) __get_free_page(GFP_KERNEL);
558 if (!pages) {
559 err = -ENOMEM;
560 goto err_pbl_free;
561 }
562
563 i = n = 0;
564
565 for_each_sg_dma_page(mhp->umem->sg_head.sgl, &sg_iter, mhp->umem->nmap, 0) {
566 pages[i++] = cpu_to_be64(sg_page_iter_dma_address(&sg_iter));
567 if (i == PAGE_SIZE / sizeof(*pages)) {
568 err = write_pbl(&mhp->rhp->rdev, pages,
569 mhp->attr.pbl_addr + (n << 3), i,
570 mhp->wr_waitp);
571 if (err)
572 goto pbl_done;
573 n += i;
574 i = 0;
575 }
576 }
577
578 if (i)
579 err = write_pbl(&mhp->rhp->rdev, pages,
580 mhp->attr.pbl_addr + (n << 3), i,
581 mhp->wr_waitp);
582
583 pbl_done:
584 free_page((unsigned long) pages);
585 if (err)
586 goto err_pbl_free;
587
588 mhp->attr.pdid = php->pdid;
589 mhp->attr.zbva = 0;
590 mhp->attr.perms = c4iw_ib_to_tpt_access(acc);
591 mhp->attr.va_fbo = virt;
592 mhp->attr.page_size = shift - 12;
593 mhp->attr.len = length;
594
595 err = register_mem(rhp, php, mhp, shift);
596 if (err)
597 goto err_pbl_free;
598
599 return &mhp->ibmr;
600
601 err_pbl_free:
602 c4iw_pblpool_free(&mhp->rhp->rdev, mhp->attr.pbl_addr,
603 mhp->attr.pbl_size << 3);
604 err_umem_release:
605 ib_umem_release(mhp->umem);
606 err_free_skb:
607 kfree_skb(mhp->dereg_skb);
608 err_free_wr_wait:
609 c4iw_put_wr_wait(mhp->wr_waitp);
610 err_free_mhp:
611 kfree(mhp);
612 return ERR_PTR(err);
613 }
614
c4iw_alloc_mw(struct ib_pd * pd,enum ib_mw_type type,struct ib_udata * udata)615 struct ib_mw *c4iw_alloc_mw(struct ib_pd *pd, enum ib_mw_type type,
616 struct ib_udata *udata)
617 {
618 struct c4iw_dev *rhp;
619 struct c4iw_pd *php;
620 struct c4iw_mw *mhp;
621 u32 mmid;
622 u32 stag = 0;
623 int ret;
624
625 if (type != IB_MW_TYPE_1)
626 return ERR_PTR(-EINVAL);
627
628 php = to_c4iw_pd(pd);
629 rhp = php->rhp;
630 mhp = kzalloc(sizeof(*mhp), GFP_KERNEL);
631 if (!mhp)
632 return ERR_PTR(-ENOMEM);
633
634 mhp->wr_waitp = c4iw_alloc_wr_wait(GFP_KERNEL);
635 if (!mhp->wr_waitp) {
636 ret = -ENOMEM;
637 goto free_mhp;
638 }
639
640 mhp->dereg_skb = alloc_skb(SGE_MAX_WR_LEN, GFP_KERNEL);
641 if (!mhp->dereg_skb) {
642 ret = -ENOMEM;
643 goto free_wr_wait;
644 }
645
646 ret = allocate_window(&rhp->rdev, &stag, php->pdid, mhp->wr_waitp);
647 if (ret)
648 goto free_skb;
649 mhp->rhp = rhp;
650 mhp->attr.pdid = php->pdid;
651 mhp->attr.type = FW_RI_STAG_MW;
652 mhp->attr.stag = stag;
653 mmid = (stag) >> 8;
654 mhp->ibmw.rkey = stag;
655 if (xa_insert_irq(&rhp->mrs, mmid, mhp, GFP_KERNEL)) {
656 ret = -ENOMEM;
657 goto dealloc_win;
658 }
659 pr_debug("mmid 0x%x mhp %p stag 0x%x\n", mmid, mhp, stag);
660 return &(mhp->ibmw);
661
662 dealloc_win:
663 deallocate_window(&rhp->rdev, mhp->attr.stag, mhp->dereg_skb,
664 mhp->wr_waitp);
665 free_skb:
666 kfree_skb(mhp->dereg_skb);
667 free_wr_wait:
668 c4iw_put_wr_wait(mhp->wr_waitp);
669 free_mhp:
670 kfree(mhp);
671 return ERR_PTR(ret);
672 }
673
c4iw_dealloc_mw(struct ib_mw * mw)674 int c4iw_dealloc_mw(struct ib_mw *mw)
675 {
676 struct c4iw_dev *rhp;
677 struct c4iw_mw *mhp;
678 u32 mmid;
679
680 mhp = to_c4iw_mw(mw);
681 rhp = mhp->rhp;
682 mmid = (mw->rkey) >> 8;
683 xa_erase_irq(&rhp->mrs, mmid);
684 deallocate_window(&rhp->rdev, mhp->attr.stag, mhp->dereg_skb,
685 mhp->wr_waitp);
686 kfree_skb(mhp->dereg_skb);
687 c4iw_put_wr_wait(mhp->wr_waitp);
688 pr_debug("ib_mw %p mmid 0x%x ptr %p\n", mw, mmid, mhp);
689 kfree(mhp);
690 return 0;
691 }
692
c4iw_alloc_mr(struct ib_pd * pd,enum ib_mr_type mr_type,u32 max_num_sg,struct ib_udata * udata)693 struct ib_mr *c4iw_alloc_mr(struct ib_pd *pd, enum ib_mr_type mr_type,
694 u32 max_num_sg, struct ib_udata *udata)
695 {
696 struct c4iw_dev *rhp;
697 struct c4iw_pd *php;
698 struct c4iw_mr *mhp;
699 u32 mmid;
700 u32 stag = 0;
701 int ret = 0;
702 int length = roundup(max_num_sg * sizeof(u64), 32);
703
704 php = to_c4iw_pd(pd);
705 rhp = php->rhp;
706
707 if (mr_type != IB_MR_TYPE_MEM_REG ||
708 max_num_sg > t4_max_fr_depth(rhp->rdev.lldi.ulptx_memwrite_dsgl &&
709 use_dsgl))
710 return ERR_PTR(-EINVAL);
711
712 mhp = kzalloc(sizeof(*mhp), GFP_KERNEL);
713 if (!mhp) {
714 ret = -ENOMEM;
715 goto err;
716 }
717
718 mhp->wr_waitp = c4iw_alloc_wr_wait(GFP_KERNEL);
719 if (!mhp->wr_waitp) {
720 ret = -ENOMEM;
721 goto err_free_mhp;
722 }
723 c4iw_init_wr_wait(mhp->wr_waitp);
724
725 mhp->mpl = dma_alloc_coherent(&rhp->rdev.lldi.pdev->dev,
726 length, &mhp->mpl_addr, GFP_KERNEL);
727 if (!mhp->mpl) {
728 ret = -ENOMEM;
729 goto err_free_wr_wait;
730 }
731 mhp->max_mpl_len = length;
732
733 mhp->rhp = rhp;
734 ret = alloc_pbl(mhp, max_num_sg);
735 if (ret)
736 goto err_free_dma;
737 mhp->attr.pbl_size = max_num_sg;
738 ret = allocate_stag(&rhp->rdev, &stag, php->pdid,
739 mhp->attr.pbl_size, mhp->attr.pbl_addr,
740 mhp->wr_waitp);
741 if (ret)
742 goto err_free_pbl;
743 mhp->attr.pdid = php->pdid;
744 mhp->attr.type = FW_RI_STAG_NSMR;
745 mhp->attr.stag = stag;
746 mhp->attr.state = 0;
747 mmid = (stag) >> 8;
748 mhp->ibmr.rkey = mhp->ibmr.lkey = stag;
749 if (xa_insert_irq(&rhp->mrs, mmid, mhp, GFP_KERNEL)) {
750 ret = -ENOMEM;
751 goto err_dereg;
752 }
753
754 pr_debug("mmid 0x%x mhp %p stag 0x%x\n", mmid, mhp, stag);
755 return &(mhp->ibmr);
756 err_dereg:
757 dereg_mem(&rhp->rdev, stag, mhp->attr.pbl_size,
758 mhp->attr.pbl_addr, mhp->dereg_skb, mhp->wr_waitp);
759 err_free_pbl:
760 c4iw_pblpool_free(&mhp->rhp->rdev, mhp->attr.pbl_addr,
761 mhp->attr.pbl_size << 3);
762 err_free_dma:
763 dma_free_coherent(&mhp->rhp->rdev.lldi.pdev->dev,
764 mhp->max_mpl_len, mhp->mpl, mhp->mpl_addr);
765 err_free_wr_wait:
766 c4iw_put_wr_wait(mhp->wr_waitp);
767 err_free_mhp:
768 kfree(mhp);
769 err:
770 return ERR_PTR(ret);
771 }
772
c4iw_set_page(struct ib_mr * ibmr,u64 addr)773 static int c4iw_set_page(struct ib_mr *ibmr, u64 addr)
774 {
775 struct c4iw_mr *mhp = to_c4iw_mr(ibmr);
776
777 if (unlikely(mhp->mpl_len == mhp->attr.pbl_size))
778 return -ENOMEM;
779
780 mhp->mpl[mhp->mpl_len++] = addr;
781
782 return 0;
783 }
784
c4iw_map_mr_sg(struct ib_mr * ibmr,struct scatterlist * sg,int sg_nents,unsigned int * sg_offset)785 int c4iw_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg, int sg_nents,
786 unsigned int *sg_offset)
787 {
788 struct c4iw_mr *mhp = to_c4iw_mr(ibmr);
789
790 mhp->mpl_len = 0;
791
792 return ib_sg_to_pages(ibmr, sg, sg_nents, sg_offset, c4iw_set_page);
793 }
794
c4iw_dereg_mr(struct ib_mr * ib_mr,struct ib_udata * udata)795 int c4iw_dereg_mr(struct ib_mr *ib_mr, struct ib_udata *udata)
796 {
797 struct c4iw_dev *rhp;
798 struct c4iw_mr *mhp;
799 u32 mmid;
800
801 pr_debug("ib_mr %p\n", ib_mr);
802
803 mhp = to_c4iw_mr(ib_mr);
804 rhp = mhp->rhp;
805 mmid = mhp->attr.stag >> 8;
806 xa_erase_irq(&rhp->mrs, mmid);
807 if (mhp->mpl)
808 dma_free_coherent(&mhp->rhp->rdev.lldi.pdev->dev,
809 mhp->max_mpl_len, mhp->mpl, mhp->mpl_addr);
810 dereg_mem(&rhp->rdev, mhp->attr.stag, mhp->attr.pbl_size,
811 mhp->attr.pbl_addr, mhp->dereg_skb, mhp->wr_waitp);
812 if (mhp->attr.pbl_size)
813 c4iw_pblpool_free(&mhp->rhp->rdev, mhp->attr.pbl_addr,
814 mhp->attr.pbl_size << 3);
815 if (mhp->kva)
816 kfree((void *) (unsigned long) mhp->kva);
817 ib_umem_release(mhp->umem);
818 pr_debug("mmid 0x%x ptr %p\n", mmid, mhp);
819 c4iw_put_wr_wait(mhp->wr_waitp);
820 kfree(mhp);
821 return 0;
822 }
823
c4iw_invalidate_mr(struct c4iw_dev * rhp,u32 rkey)824 void c4iw_invalidate_mr(struct c4iw_dev *rhp, u32 rkey)
825 {
826 struct c4iw_mr *mhp;
827 unsigned long flags;
828
829 xa_lock_irqsave(&rhp->mrs, flags);
830 mhp = xa_load(&rhp->mrs, rkey >> 8);
831 if (mhp)
832 mhp->attr.state = 0;
833 xa_unlock_irqrestore(&rhp->mrs, flags);
834 }
835
