1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /****************************************************************************** 3 * 4 * Copyright(c) 2007 - 2016 Realtek Corporation. 5 * 6 * Contact Information: 7 * wlanfae <wlanfae@realtek.com> 8 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, 9 * Hsinchu 300, Taiwan. 10 * 11 * Larry Finger <Larry.Finger@lwfinger.net> 12 * 13 *****************************************************************************/ 14 15 #ifndef __PHYDMIQK_H__ 16 #define __PHYDMIQK_H__ 17 18 /*--------------------------Define Parameters-------------------------------*/ 19 #define LOK_delay 1 20 #define WBIQK_delay 10 21 #define TX_IQK 0 22 #define RX_IQK 1 23 #define TXIQK 0 24 #define RXIQK1 1 25 #define RXIQK2 2 26 #define GSRXK1 0 27 #define GSRXK2 1 28 #define kcount_limit_80m 2 29 #define kcount_limit_others 4 30 #define rxiqk_gs_limit 4 31 32 #define NUM 4 33 /*----------------------End Define Parameters-------------------------------*/ 34 35 struct dm_iqk_info { 36 bool lok_fail[NUM]; 37 bool iqk_fail[2][NUM]; 38 u32 iqc_matrix[2][NUM]; 39 u8 iqk_times; 40 u32 rf_reg18; 41 u32 lna_idx; 42 u8 rxiqk_step; 43 u8 tmp1bcc; 44 u8 kcount; 45 46 u32 iqk_channel[2]; 47 bool iqk_fail_report[2][4][2]; /*channel/path/TRX(TX:0, RX:1) */ 48 u32 iqk_cfir_real[2][4][2] 49 [8]; /*channel / path / TRX(TX:0, RX:1) / CFIR_real*/ 50 u32 iqk_cfir_imag[2][4][2] 51 [8]; /*channel / path / TRX(TX:0, RX:1) / CFIR_imag*/ 52 u8 retry_count[2][4][3]; /* channel / path / (TXK:0, RXK1:1, RXK2:2) */ 53 u8 gs_retry_count[2][4][2]; /* channel / path / (GSRXK1:0, GSRXK2:1) */ 54 u8 rxiqk_fail_code[2][4]; /* channel / path 55 * 0:SRXK1 fail, 1:RXK1 fail 2:RXK2 fail 56 */ 57 u32 lok_idac[2][4]; /*channel / path*/ 58 u16 rxiqk_agc[2][4]; /*channel / path*/ 59 u32 bypass_iqk[2][4]; /*channel / 0xc94/0xe94*/ 60 u32 tmp_gntwl; 61 bool is_btg; 62 bool isbnd; 63 }; 64 65 #endif 66
