1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * TI C64X clock definitions 4 * 5 * Copyright (C) 2010, 2011 Texas Instruments. 6 * Contributed by: Mark Salter <msalter@redhat.com> 7 * 8 * Copied heavily from arm/mach-davinci/clock.h, so: 9 * 10 * Copyright (C) 2006-2007 Texas Instruments. 11 * Copyright (C) 2008-2009 Deep Root Systems, LLC 12 */ 13 14 #ifndef _ASM_C6X_CLOCK_H 15 #define _ASM_C6X_CLOCK_H 16 17 #ifndef __ASSEMBLER__ 18 19 #include <linux/list.h> 20 21 /* PLL/Reset register offsets */ 22 #define PLLCTL 0x100 23 #define PLLM 0x110 24 #define PLLPRE 0x114 25 #define PLLDIV1 0x118 26 #define PLLDIV2 0x11c 27 #define PLLDIV3 0x120 28 #define PLLPOST 0x128 29 #define PLLCMD 0x138 30 #define PLLSTAT 0x13c 31 #define PLLALNCTL 0x140 32 #define PLLDCHANGE 0x144 33 #define PLLCKEN 0x148 34 #define PLLCKSTAT 0x14c 35 #define PLLSYSTAT 0x150 36 #define PLLDIV4 0x160 37 #define PLLDIV5 0x164 38 #define PLLDIV6 0x168 39 #define PLLDIV7 0x16c 40 #define PLLDIV8 0x170 41 #define PLLDIV9 0x174 42 #define PLLDIV10 0x178 43 #define PLLDIV11 0x17c 44 #define PLLDIV12 0x180 45 #define PLLDIV13 0x184 46 #define PLLDIV14 0x188 47 #define PLLDIV15 0x18c 48 #define PLLDIV16 0x190 49 50 /* PLLM register bits */ 51 #define PLLM_PLLM_MASK 0xff 52 #define PLLM_VAL(x) ((x) - 1) 53 54 /* PREDIV register bits */ 55 #define PLLPREDIV_EN BIT(15) 56 #define PLLPREDIV_VAL(x) ((x) - 1) 57 58 /* PLLCTL register bits */ 59 #define PLLCTL_PLLEN BIT(0) 60 #define PLLCTL_PLLPWRDN BIT(1) 61 #define PLLCTL_PLLRST BIT(3) 62 #define PLLCTL_PLLDIS BIT(4) 63 #define PLLCTL_PLLENSRC BIT(5) 64 #define PLLCTL_CLKMODE BIT(8) 65 66 /* PLLCMD register bits */ 67 #define PLLCMD_GOSTAT BIT(0) 68 69 /* PLLSTAT register bits */ 70 #define PLLSTAT_GOSTAT BIT(0) 71 72 /* PLLDIV register bits */ 73 #define PLLDIV_EN BIT(15) 74 #define PLLDIV_RATIO_MASK 0x1f 75 #define PLLDIV_RATIO(x) ((x) - 1) 76 77 struct pll_data; 78 79 struct clk { 80 struct list_head node; 81 struct module *owner; 82 const char *name; 83 unsigned long rate; 84 int usecount; 85 u32 flags; 86 struct clk *parent; 87 struct list_head children; /* list of children */ 88 struct list_head childnode; /* parent's child list node */ 89 struct pll_data *pll_data; 90 u32 div; 91 unsigned long (*recalc) (struct clk *); 92 int (*set_rate) (struct clk *clk, unsigned long rate); 93 int (*round_rate) (struct clk *clk, unsigned long rate); 94 }; 95 96 /* Clock flags: SoC-specific flags start at BIT(16) */ 97 #define ALWAYS_ENABLED BIT(1) 98 #define CLK_PLL BIT(2) /* PLL-derived clock */ 99 #define PRE_PLL BIT(3) /* source is before PLL mult/div */ 100 #define FIXED_DIV_PLL BIT(4) /* fixed divisor from PLL */ 101 #define FIXED_RATE_PLL BIT(5) /* fixed output rate PLL */ 102 103 #define MAX_PLL_SYSCLKS 16 104 105 struct pll_data { 106 void __iomem *base; 107 u32 num; 108 u32 flags; 109 u32 input_rate; 110 u32 bypass_delay; /* in loops */ 111 u32 reset_delay; /* in loops */ 112 u32 lock_delay; /* in loops */ 113 struct clk sysclks[MAX_PLL_SYSCLKS + 1]; 114 }; 115 116 /* pll_data flag bit */ 117 #define PLL_HAS_PRE BIT(0) 118 #define PLL_HAS_MUL BIT(1) 119 #define PLL_HAS_POST BIT(2) 120 121 #define CLK(dev, con, ck) \ 122 { \ 123 .dev_id = dev, \ 124 .con_id = con, \ 125 .clk = ck, \ 126 } \ 127 128 extern void c6x_clks_init(struct clk_lookup *clocks); 129 extern int clk_register(struct clk *clk); 130 extern void clk_unregister(struct clk *clk); 131 extern void c64x_setup_clocks(void); 132 133 extern struct pll_data c6x_soc_pll1; 134 135 extern struct clk clkin1; 136 extern struct clk c6x_core_clk; 137 extern struct clk c6x_i2c_clk; 138 extern struct clk c6x_watchdog_clk; 139 extern struct clk c6x_mcbsp1_clk; 140 extern struct clk c6x_mcbsp2_clk; 141 extern struct clk c6x_mdio_clk; 142 143 #endif 144 145 #endif /* _ASM_C6X_CLOCK_H */ 146
