1 /*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include <linux/slab.h>
27
28 #include "resource.h"
29 #include "dm_services.h"
30 #include "dce_calcs.h"
31 #include "dc.h"
32 #include "core_types.h"
33 #include "dal_asic_id.h"
34 #include "calcs_logger.h"
35
36 /*
37 * NOTE:
38 * This file is gcc-parseable HW gospel, coming straight from HW engineers.
39 *
40 * It doesn't adhere to Linux kernel style and sometimes will do things in odd
41 * ways. Unless there is something clearly wrong with it the code should
42 * remain as-is as it provides us with a guarantee from HW that it is correct.
43 */
44
45 /*******************************************************************************
46 * Private Functions
47 ******************************************************************************/
48
bw_calcs_version_from_asic_id(struct hw_asic_id asic_id)49 static enum bw_calcs_version bw_calcs_version_from_asic_id(struct hw_asic_id asic_id)
50 {
51 switch (asic_id.chip_family) {
52
53 case FAMILY_CZ:
54 if (ASIC_REV_IS_STONEY(asic_id.hw_internal_rev))
55 return BW_CALCS_VERSION_STONEY;
56 return BW_CALCS_VERSION_CARRIZO;
57
58 case FAMILY_VI:
59 if (ASIC_REV_IS_POLARIS12_V(asic_id.hw_internal_rev))
60 return BW_CALCS_VERSION_POLARIS12;
61 if (ASIC_REV_IS_POLARIS10_P(asic_id.hw_internal_rev))
62 return BW_CALCS_VERSION_POLARIS10;
63 if (ASIC_REV_IS_POLARIS11_M(asic_id.hw_internal_rev))
64 return BW_CALCS_VERSION_POLARIS11;
65 if (ASIC_REV_IS_VEGAM(asic_id.hw_internal_rev))
66 return BW_CALCS_VERSION_VEGAM;
67 return BW_CALCS_VERSION_INVALID;
68
69 case FAMILY_AI:
70 return BW_CALCS_VERSION_VEGA10;
71
72 default:
73 return BW_CALCS_VERSION_INVALID;
74 }
75 }
76
calculate_bandwidth(const struct bw_calcs_dceip * dceip,const struct bw_calcs_vbios * vbios,struct bw_calcs_data * data)77 static void calculate_bandwidth(
78 const struct bw_calcs_dceip *dceip,
79 const struct bw_calcs_vbios *vbios,
80 struct bw_calcs_data *data)
81
82 {
83 const int32_t pixels_per_chunk = 512;
84 const int32_t high = 2;
85 const int32_t mid = 1;
86 const int32_t low = 0;
87 const uint32_t s_low = 0;
88 const uint32_t s_mid1 = 1;
89 const uint32_t s_mid2 = 2;
90 const uint32_t s_mid3 = 3;
91 const uint32_t s_mid4 = 4;
92 const uint32_t s_mid5 = 5;
93 const uint32_t s_mid6 = 6;
94 const uint32_t s_high = 7;
95 const uint32_t dmif_chunk_buff_margin = 1;
96
97 uint32_t max_chunks_fbc_mode;
98 int32_t num_cursor_lines;
99
100 int32_t i, j, k;
101 struct bw_fixed yclk[3];
102 struct bw_fixed sclk[8];
103 bool d0_underlay_enable;
104 bool d1_underlay_enable;
105 bool fbc_enabled;
106 bool lpt_enabled;
107 enum bw_defines sclk_message;
108 enum bw_defines yclk_message;
109 enum bw_defines v_filter_init_mode[maximum_number_of_surfaces];
110 enum bw_defines tiling_mode[maximum_number_of_surfaces];
111 enum bw_defines surface_type[maximum_number_of_surfaces];
112 enum bw_defines voltage;
113 enum bw_defines pipe_check;
114 enum bw_defines hsr_check;
115 enum bw_defines vsr_check;
116 enum bw_defines lb_size_check;
117 enum bw_defines fbc_check;
118 enum bw_defines rotation_check;
119 enum bw_defines mode_check;
120 enum bw_defines nbp_state_change_enable_blank;
121 /*initialize variables*/
122 int32_t number_of_displays_enabled = 0;
123 int32_t number_of_displays_enabled_with_margin = 0;
124 int32_t number_of_aligned_displays_with_no_margin = 0;
125
126 yclk[low] = vbios->low_yclk;
127 yclk[mid] = vbios->mid_yclk;
128 yclk[high] = vbios->high_yclk;
129 sclk[s_low] = vbios->low_sclk;
130 sclk[s_mid1] = vbios->mid1_sclk;
131 sclk[s_mid2] = vbios->mid2_sclk;
132 sclk[s_mid3] = vbios->mid3_sclk;
133 sclk[s_mid4] = vbios->mid4_sclk;
134 sclk[s_mid5] = vbios->mid5_sclk;
135 sclk[s_mid6] = vbios->mid6_sclk;
136 sclk[s_high] = vbios->high_sclk;
137 /*''''''''''''''''''*/
138 /* surface assignment:*/
139 /* 0: d0 underlay or underlay luma*/
140 /* 1: d0 underlay chroma*/
141 /* 2: d1 underlay or underlay luma*/
142 /* 3: d1 underlay chroma*/
143 /* 4: d0 graphics*/
144 /* 5: d1 graphics*/
145 /* 6: d2 graphics*/
146 /* 7: d3 graphics, same mode as d2*/
147 /* 8: d4 graphics, same mode as d2*/
148 /* 9: d5 graphics, same mode as d2*/
149 /* ...*/
150 /* maximum_number_of_surfaces-2: d1 display_write_back420 luma*/
151 /* maximum_number_of_surfaces-1: d1 display_write_back420 chroma*/
152 /* underlay luma and chroma surface parameters from spreadsheet*/
153
154
155
156
157 if (data->d0_underlay_mode == bw_def_none)
158 d0_underlay_enable = false;
159 else
160 d0_underlay_enable = true;
161 if (data->d1_underlay_mode == bw_def_none)
162 d1_underlay_enable = false;
163 else
164 d1_underlay_enable = true;
165 data->number_of_underlay_surfaces = d0_underlay_enable + d1_underlay_enable;
166 switch (data->underlay_surface_type) {
167 case bw_def_420:
168 surface_type[0] = bw_def_underlay420_luma;
169 surface_type[2] = bw_def_underlay420_luma;
170 data->bytes_per_pixel[0] = 1;
171 data->bytes_per_pixel[2] = 1;
172 surface_type[1] = bw_def_underlay420_chroma;
173 surface_type[3] = bw_def_underlay420_chroma;
174 data->bytes_per_pixel[1] = 2;
175 data->bytes_per_pixel[3] = 2;
176 data->lb_size_per_component[0] = dceip->underlay420_luma_lb_size_per_component;
177 data->lb_size_per_component[1] = dceip->underlay420_chroma_lb_size_per_component;
178 data->lb_size_per_component[2] = dceip->underlay420_luma_lb_size_per_component;
179 data->lb_size_per_component[3] = dceip->underlay420_chroma_lb_size_per_component;
180 break;
181 case bw_def_422:
182 surface_type[0] = bw_def_underlay422;
183 surface_type[2] = bw_def_underlay422;
184 data->bytes_per_pixel[0] = 2;
185 data->bytes_per_pixel[2] = 2;
186 data->lb_size_per_component[0] = dceip->underlay422_lb_size_per_component;
187 data->lb_size_per_component[2] = dceip->underlay422_lb_size_per_component;
188 break;
189 default:
190 surface_type[0] = bw_def_underlay444;
191 surface_type[2] = bw_def_underlay444;
192 data->bytes_per_pixel[0] = 4;
193 data->bytes_per_pixel[2] = 4;
194 data->lb_size_per_component[0] = dceip->lb_size_per_component444;
195 data->lb_size_per_component[2] = dceip->lb_size_per_component444;
196 break;
197 }
198 if (d0_underlay_enable) {
199 switch (data->underlay_surface_type) {
200 case bw_def_420:
201 data->enable[0] = 1;
202 data->enable[1] = 1;
203 break;
204 default:
205 data->enable[0] = 1;
206 data->enable[1] = 0;
207 break;
208 }
209 }
210 else {
211 data->enable[0] = 0;
212 data->enable[1] = 0;
213 }
214 if (d1_underlay_enable) {
215 switch (data->underlay_surface_type) {
216 case bw_def_420:
217 data->enable[2] = 1;
218 data->enable[3] = 1;
219 break;
220 default:
221 data->enable[2] = 1;
222 data->enable[3] = 0;
223 break;
224 }
225 }
226 else {
227 data->enable[2] = 0;
228 data->enable[3] = 0;
229 }
230 data->use_alpha[0] = 0;
231 data->use_alpha[1] = 0;
232 data->use_alpha[2] = 0;
233 data->use_alpha[3] = 0;
234 data->scatter_gather_enable_for_pipe[0] = vbios->scatter_gather_enable;
235 data->scatter_gather_enable_for_pipe[1] = vbios->scatter_gather_enable;
236 data->scatter_gather_enable_for_pipe[2] = vbios->scatter_gather_enable;
237 data->scatter_gather_enable_for_pipe[3] = vbios->scatter_gather_enable;
238 /*underlay0 same and graphics display pipe0*/
239 data->interlace_mode[0] = data->interlace_mode[4];
240 data->interlace_mode[1] = data->interlace_mode[4];
241 /*underlay1 same and graphics display pipe1*/
242 data->interlace_mode[2] = data->interlace_mode[5];
243 data->interlace_mode[3] = data->interlace_mode[5];
244 /*underlay0 same and graphics display pipe0*/
245 data->h_total[0] = data->h_total[4];
246 data->v_total[0] = data->v_total[4];
247 data->h_total[1] = data->h_total[4];
248 data->v_total[1] = data->v_total[4];
249 /*underlay1 same and graphics display pipe1*/
250 data->h_total[2] = data->h_total[5];
251 data->v_total[2] = data->v_total[5];
252 data->h_total[3] = data->h_total[5];
253 data->v_total[3] = data->v_total[5];
254 /*underlay0 same and graphics display pipe0*/
255 data->pixel_rate[0] = data->pixel_rate[4];
256 data->pixel_rate[1] = data->pixel_rate[4];
257 /*underlay1 same and graphics display pipe1*/
258 data->pixel_rate[2] = data->pixel_rate[5];
259 data->pixel_rate[3] = data->pixel_rate[5];
260 if ((data->underlay_tiling_mode == bw_def_array_linear_general || data->underlay_tiling_mode == bw_def_array_linear_aligned)) {
261 tiling_mode[0] = bw_def_linear;
262 tiling_mode[1] = bw_def_linear;
263 tiling_mode[2] = bw_def_linear;
264 tiling_mode[3] = bw_def_linear;
265 }
266 else {
267 tiling_mode[0] = bw_def_landscape;
268 tiling_mode[1] = bw_def_landscape;
269 tiling_mode[2] = bw_def_landscape;
270 tiling_mode[3] = bw_def_landscape;
271 }
272 data->lb_bpc[0] = data->underlay_lb_bpc;
273 data->lb_bpc[1] = data->underlay_lb_bpc;
274 data->lb_bpc[2] = data->underlay_lb_bpc;
275 data->lb_bpc[3] = data->underlay_lb_bpc;
276 data->compression_rate[0] = bw_int_to_fixed(1);
277 data->compression_rate[1] = bw_int_to_fixed(1);
278 data->compression_rate[2] = bw_int_to_fixed(1);
279 data->compression_rate[3] = bw_int_to_fixed(1);
280 data->access_one_channel_only[0] = 0;
281 data->access_one_channel_only[1] = 0;
282 data->access_one_channel_only[2] = 0;
283 data->access_one_channel_only[3] = 0;
284 data->cursor_width_pixels[0] = bw_int_to_fixed(0);
285 data->cursor_width_pixels[1] = bw_int_to_fixed(0);
286 data->cursor_width_pixels[2] = bw_int_to_fixed(0);
287 data->cursor_width_pixels[3] = bw_int_to_fixed(0);
288 /* graphics surface parameters from spreadsheet*/
289 fbc_enabled = false;
290 lpt_enabled = false;
291 for (i = 4; i <= maximum_number_of_surfaces - 3; i++) {
292 if (i < data->number_of_displays + 4) {
293 if (i == 4 && data->d0_underlay_mode == bw_def_underlay_only) {
294 data->enable[i] = 0;
295 data->use_alpha[i] = 0;
296 }
297 else if (i == 4 && data->d0_underlay_mode == bw_def_blend) {
298 data->enable[i] = 1;
299 data->use_alpha[i] = 1;
300 }
301 else if (i == 4) {
302 data->enable[i] = 1;
303 data->use_alpha[i] = 0;
304 }
305 else if (i == 5 && data->d1_underlay_mode == bw_def_underlay_only) {
306 data->enable[i] = 0;
307 data->use_alpha[i] = 0;
308 }
309 else if (i == 5 && data->d1_underlay_mode == bw_def_blend) {
310 data->enable[i] = 1;
311 data->use_alpha[i] = 1;
312 }
313 else {
314 data->enable[i] = 1;
315 data->use_alpha[i] = 0;
316 }
317 }
318 else {
319 data->enable[i] = 0;
320 data->use_alpha[i] = 0;
321 }
322 data->scatter_gather_enable_for_pipe[i] = vbios->scatter_gather_enable;
323 surface_type[i] = bw_def_graphics;
324 data->lb_size_per_component[i] = dceip->lb_size_per_component444;
325 if (data->graphics_tiling_mode == bw_def_array_linear_general || data->graphics_tiling_mode == bw_def_array_linear_aligned) {
326 tiling_mode[i] = bw_def_linear;
327 }
328 else {
329 tiling_mode[i] = bw_def_tiled;
330 }
331 data->lb_bpc[i] = data->graphics_lb_bpc;
332 if ((data->fbc_en[i] == 1 && (dceip->argb_compression_support || data->d0_underlay_mode != bw_def_blended))) {
333 data->compression_rate[i] = bw_int_to_fixed(vbios->average_compression_rate);
334 data->access_one_channel_only[i] = data->lpt_en[i];
335 }
336 else {
337 data->compression_rate[i] = bw_int_to_fixed(1);
338 data->access_one_channel_only[i] = 0;
339 }
340 if (data->fbc_en[i] == 1) {
341 fbc_enabled = true;
342 if (data->lpt_en[i] == 1) {
343 lpt_enabled = true;
344 }
345 }
346 data->cursor_width_pixels[i] = bw_int_to_fixed(vbios->cursor_width);
347 }
348 /* display_write_back420*/
349 data->scatter_gather_enable_for_pipe[maximum_number_of_surfaces - 2] = 0;
350 data->scatter_gather_enable_for_pipe[maximum_number_of_surfaces - 1] = 0;
351 if (data->d1_display_write_back_dwb_enable == 1) {
352 data->enable[maximum_number_of_surfaces - 2] = 1;
353 data->enable[maximum_number_of_surfaces - 1] = 1;
354 }
355 else {
356 data->enable[maximum_number_of_surfaces - 2] = 0;
357 data->enable[maximum_number_of_surfaces - 1] = 0;
358 }
359 surface_type[maximum_number_of_surfaces - 2] = bw_def_display_write_back420_luma;
360 surface_type[maximum_number_of_surfaces - 1] = bw_def_display_write_back420_chroma;
361 data->lb_size_per_component[maximum_number_of_surfaces - 2] = dceip->underlay420_luma_lb_size_per_component;
362 data->lb_size_per_component[maximum_number_of_surfaces - 1] = dceip->underlay420_chroma_lb_size_per_component;
363 data->bytes_per_pixel[maximum_number_of_surfaces - 2] = 1;
364 data->bytes_per_pixel[maximum_number_of_surfaces - 1] = 2;
365 data->interlace_mode[maximum_number_of_surfaces - 2] = data->interlace_mode[5];
366 data->interlace_mode[maximum_number_of_surfaces - 1] = data->interlace_mode[5];
367 data->h_taps[maximum_number_of_surfaces - 2] = bw_int_to_fixed(1);
368 data->h_taps[maximum_number_of_surfaces - 1] = bw_int_to_fixed(1);
369 data->v_taps[maximum_number_of_surfaces - 2] = bw_int_to_fixed(1);
370 data->v_taps[maximum_number_of_surfaces - 1] = bw_int_to_fixed(1);
371 data->rotation_angle[maximum_number_of_surfaces - 2] = bw_int_to_fixed(0);
372 data->rotation_angle[maximum_number_of_surfaces - 1] = bw_int_to_fixed(0);
373 tiling_mode[maximum_number_of_surfaces - 2] = bw_def_linear;
374 tiling_mode[maximum_number_of_surfaces - 1] = bw_def_linear;
375 data->lb_bpc[maximum_number_of_surfaces - 2] = 8;
376 data->lb_bpc[maximum_number_of_surfaces - 1] = 8;
377 data->compression_rate[maximum_number_of_surfaces - 2] = bw_int_to_fixed(1);
378 data->compression_rate[maximum_number_of_surfaces - 1] = bw_int_to_fixed(1);
379 data->access_one_channel_only[maximum_number_of_surfaces - 2] = 0;
380 data->access_one_channel_only[maximum_number_of_surfaces - 1] = 0;
381 /*assume display pipe1 has dwb enabled*/
382 data->h_total[maximum_number_of_surfaces - 2] = data->h_total[5];
383 data->h_total[maximum_number_of_surfaces - 1] = data->h_total[5];
384 data->v_total[maximum_number_of_surfaces - 2] = data->v_total[5];
385 data->v_total[maximum_number_of_surfaces - 1] = data->v_total[5];
386 data->pixel_rate[maximum_number_of_surfaces - 2] = data->pixel_rate[5];
387 data->pixel_rate[maximum_number_of_surfaces - 1] = data->pixel_rate[5];
388 data->src_width[maximum_number_of_surfaces - 2] = data->src_width[5];
389 data->src_width[maximum_number_of_surfaces - 1] = data->src_width[5];
390 data->src_height[maximum_number_of_surfaces - 2] = data->src_height[5];
391 data->src_height[maximum_number_of_surfaces - 1] = data->src_height[5];
392 data->pitch_in_pixels[maximum_number_of_surfaces - 2] = data->src_width[5];
393 data->pitch_in_pixels[maximum_number_of_surfaces - 1] = data->src_width[5];
394 data->h_scale_ratio[maximum_number_of_surfaces - 2] = bw_int_to_fixed(1);
395 data->h_scale_ratio[maximum_number_of_surfaces - 1] = bw_int_to_fixed(1);
396 data->v_scale_ratio[maximum_number_of_surfaces - 2] = bw_int_to_fixed(1);
397 data->v_scale_ratio[maximum_number_of_surfaces - 1] = bw_int_to_fixed(1);
398 data->stereo_mode[maximum_number_of_surfaces - 2] = bw_def_mono;
399 data->stereo_mode[maximum_number_of_surfaces - 1] = bw_def_mono;
400 data->cursor_width_pixels[maximum_number_of_surfaces - 2] = bw_int_to_fixed(0);
401 data->cursor_width_pixels[maximum_number_of_surfaces - 1] = bw_int_to_fixed(0);
402 data->use_alpha[maximum_number_of_surfaces - 2] = 0;
403 data->use_alpha[maximum_number_of_surfaces - 1] = 0;
404 /*mode check calculations:*/
405 /* mode within dce ip capabilities*/
406 /* fbc*/
407 /* hsr*/
408 /* vsr*/
409 /* lb size*/
410 /*effective scaling source and ratios:*/
411 /*for graphics, non-stereo, non-interlace surfaces when the size of the source and destination are the same, only one tap is used*/
412 /*420 chroma has half the width, height, horizontal and vertical scaling ratios than luma*/
413 /*rotating a graphic or underlay surface swaps the width, height, horizontal and vertical scaling ratios*/
414 /*in top-bottom stereo mode there is 2:1 vertical downscaling for each eye*/
415 /*in side-by-side stereo mode there is 2:1 horizontal downscaling for each eye*/
416 /*in interlace mode there is 2:1 vertical downscaling for each field*/
417 /*in panning or bezel adjustment mode the source width has an extra 128 pixels*/
418 for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
419 if (data->enable[i]) {
420 if (bw_equ(data->h_scale_ratio[i], bw_int_to_fixed(1)) && bw_equ(data->v_scale_ratio[i], bw_int_to_fixed(1)) && surface_type[i] == bw_def_graphics && data->stereo_mode[i] == bw_def_mono && data->interlace_mode[i] == 0) {
421 data->h_taps[i] = bw_int_to_fixed(1);
422 data->v_taps[i] = bw_int_to_fixed(1);
423 }
424 if (surface_type[i] == bw_def_display_write_back420_chroma || surface_type[i] == bw_def_underlay420_chroma) {
425 data->pitch_in_pixels_after_surface_type[i] = bw_div(data->pitch_in_pixels[i], bw_int_to_fixed(2));
426 data->src_width_after_surface_type = bw_div(data->src_width[i], bw_int_to_fixed(2));
427 data->src_height_after_surface_type = bw_div(data->src_height[i], bw_int_to_fixed(2));
428 data->hsr_after_surface_type = bw_div(data->h_scale_ratio[i], bw_int_to_fixed(2));
429 data->vsr_after_surface_type = bw_div(data->v_scale_ratio[i], bw_int_to_fixed(2));
430 }
431 else {
432 data->pitch_in_pixels_after_surface_type[i] = data->pitch_in_pixels[i];
433 data->src_width_after_surface_type = data->src_width[i];
434 data->src_height_after_surface_type = data->src_height[i];
435 data->hsr_after_surface_type = data->h_scale_ratio[i];
436 data->vsr_after_surface_type = data->v_scale_ratio[i];
437 }
438 if ((bw_equ(data->rotation_angle[i], bw_int_to_fixed(90)) || bw_equ(data->rotation_angle[i], bw_int_to_fixed(270))) && surface_type[i] != bw_def_display_write_back420_luma && surface_type[i] != bw_def_display_write_back420_chroma) {
439 data->src_width_after_rotation = data->src_height_after_surface_type;
440 data->src_height_after_rotation = data->src_width_after_surface_type;
441 data->hsr_after_rotation = data->vsr_after_surface_type;
442 data->vsr_after_rotation = data->hsr_after_surface_type;
443 }
444 else {
445 data->src_width_after_rotation = data->src_width_after_surface_type;
446 data->src_height_after_rotation = data->src_height_after_surface_type;
447 data->hsr_after_rotation = data->hsr_after_surface_type;
448 data->vsr_after_rotation = data->vsr_after_surface_type;
449 }
450 switch (data->stereo_mode[i]) {
451 case bw_def_top_bottom:
452 data->source_width_pixels[i] = data->src_width_after_rotation;
453 data->source_height_pixels = bw_mul(bw_int_to_fixed(2), data->src_height_after_rotation);
454 data->hsr_after_stereo = data->hsr_after_rotation;
455 data->vsr_after_stereo = bw_mul(bw_int_to_fixed(1), data->vsr_after_rotation);
456 break;
457 case bw_def_side_by_side:
458 data->source_width_pixels[i] = bw_mul(bw_int_to_fixed(2), data->src_width_after_rotation);
459 data->source_height_pixels = data->src_height_after_rotation;
460 data->hsr_after_stereo = bw_mul(bw_int_to_fixed(1), data->hsr_after_rotation);
461 data->vsr_after_stereo = data->vsr_after_rotation;
462 break;
463 default:
464 data->source_width_pixels[i] = data->src_width_after_rotation;
465 data->source_height_pixels = data->src_height_after_rotation;
466 data->hsr_after_stereo = data->hsr_after_rotation;
467 data->vsr_after_stereo = data->vsr_after_rotation;
468 break;
469 }
470 data->hsr[i] = data->hsr_after_stereo;
471 if (data->interlace_mode[i]) {
472 data->vsr[i] = bw_mul(data->vsr_after_stereo, bw_int_to_fixed(2));
473 }
474 else {
475 data->vsr[i] = data->vsr_after_stereo;
476 }
477 if (data->panning_and_bezel_adjustment != bw_def_none) {
478 data->source_width_rounded_up_to_chunks[i] = bw_add(bw_floor2(bw_sub(data->source_width_pixels[i], bw_int_to_fixed(1)), bw_int_to_fixed(128)), bw_int_to_fixed(256));
479 }
480 else {
481 data->source_width_rounded_up_to_chunks[i] = bw_ceil2(data->source_width_pixels[i], bw_int_to_fixed(128));
482 }
483 data->source_height_rounded_up_to_chunks[i] = data->source_height_pixels;
484 }
485 }
486 /*mode support checks:*/
487 /*the number of graphics and underlay pipes is limited by the ip support*/
488 /*maximum horizontal and vertical scale ratio is 4, and should not exceed the number of taps*/
489 /*for downscaling with the pre-downscaler, the horizontal scale ratio must be more than the ceiling of one quarter of the number of taps*/
490 /*the pre-downscaler reduces the line buffer source by the horizontal scale ratio*/
491 /*the number of lines in the line buffer has to exceed the number of vertical taps*/
492 /*the size of the line in the line buffer is the product of the source width and the bits per component, rounded up to a multiple of 48*/
493 /*the size of the line in the line buffer in the case of 10 bit per component is the product of the source width rounded up to multiple of 8 and 30.023438 / 3, rounded up to a multiple of 48*/
494 /*the size of the line in the line buffer in the case of 8 bit per component is the product of the source width rounded up to multiple of 8 and 30.023438 / 3, rounded up to a multiple of 48*/
495 /*frame buffer compression is not supported with stereo mode, rotation, or non- 888 formats*/
496 /*rotation is not supported with linear of stereo modes*/
497 if (dceip->number_of_graphics_pipes >= data->number_of_displays && dceip->number_of_underlay_pipes >= data->number_of_underlay_surfaces && !(dceip->display_write_back_supported == 0 && data->d1_display_write_back_dwb_enable == 1)) {
498 pipe_check = bw_def_ok;
499 }
500 else {
501 pipe_check = bw_def_notok;
502 }
503 hsr_check = bw_def_ok;
504 for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
505 if (data->enable[i]) {
506 if (bw_neq(data->hsr[i], bw_int_to_fixed(1))) {
507 if (bw_mtn(data->hsr[i], bw_int_to_fixed(4))) {
508 hsr_check = bw_def_hsr_mtn_4;
509 }
510 else {
511 if (bw_mtn(data->hsr[i], data->h_taps[i])) {
512 hsr_check = bw_def_hsr_mtn_h_taps;
513 }
514 else {
515 if (dceip->pre_downscaler_enabled == 1 && bw_mtn(data->hsr[i], bw_int_to_fixed(1)) && bw_leq(data->hsr[i], bw_ceil2(bw_div(data->h_taps[i], bw_int_to_fixed(4)), bw_int_to_fixed(1)))) {
516 hsr_check = bw_def_ceiling__h_taps_div_4___meq_hsr;
517 }
518 }
519 }
520 }
521 }
522 }
523 vsr_check = bw_def_ok;
524 for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
525 if (data->enable[i]) {
526 if (bw_neq(data->vsr[i], bw_int_to_fixed(1))) {
527 if (bw_mtn(data->vsr[i], bw_int_to_fixed(4))) {
528 vsr_check = bw_def_vsr_mtn_4;
529 }
530 else {
531 if (bw_mtn(data->vsr[i], data->v_taps[i])) {
532 vsr_check = bw_def_vsr_mtn_v_taps;
533 }
534 }
535 }
536 }
537 }
538 lb_size_check = bw_def_ok;
539 for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
540 if (data->enable[i]) {
541 if ((dceip->pre_downscaler_enabled && bw_mtn(data->hsr[i], bw_int_to_fixed(1)))) {
542 data->source_width_in_lb = bw_div(data->source_width_pixels[i], data->hsr[i]);
543 }
544 else {
545 data->source_width_in_lb = data->source_width_pixels[i];
546 }
547 switch (data->lb_bpc[i]) {
548 case 8:
549 data->lb_line_pitch = bw_ceil2(bw_mul(bw_div(bw_frc_to_fixed(2401171875ul, 100000000), bw_int_to_fixed(3)), bw_ceil2(data->source_width_in_lb, bw_int_to_fixed(8))), bw_int_to_fixed(48));
550 break;
551 case 10:
552 data->lb_line_pitch = bw_ceil2(bw_mul(bw_div(bw_frc_to_fixed(300234375, 10000000), bw_int_to_fixed(3)), bw_ceil2(data->source_width_in_lb, bw_int_to_fixed(8))), bw_int_to_fixed(48));
553 break;
554 default:
555 data->lb_line_pitch = bw_ceil2(bw_mul(bw_int_to_fixed(data->lb_bpc[i]), data->source_width_in_lb), bw_int_to_fixed(48));
556 break;
557 }
558 data->lb_partitions[i] = bw_floor2(bw_div(data->lb_size_per_component[i], data->lb_line_pitch), bw_int_to_fixed(1));
559 /*clamp the partitions to the maxium number supported by the lb*/
560 if ((surface_type[i] != bw_def_graphics || dceip->graphics_lb_nodownscaling_multi_line_prefetching == 1)) {
561 data->lb_partitions_max[i] = bw_int_to_fixed(10);
562 }
563 else {
564 data->lb_partitions_max[i] = bw_int_to_fixed(7);
565 }
566 data->lb_partitions[i] = bw_min2(data->lb_partitions_max[i], data->lb_partitions[i]);
567 if (bw_mtn(bw_add(data->v_taps[i], bw_int_to_fixed(1)), data->lb_partitions[i])) {
568 lb_size_check = bw_def_notok;
569 }
570 }
571 }
572 fbc_check = bw_def_ok;
573 for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
574 if (data->enable[i] && data->fbc_en[i] == 1 && (bw_equ(data->rotation_angle[i], bw_int_to_fixed(90)) || bw_equ(data->rotation_angle[i], bw_int_to_fixed(270)) || data->stereo_mode[i] != bw_def_mono || data->bytes_per_pixel[i] != 4)) {
575 fbc_check = bw_def_invalid_rotation_or_bpp_or_stereo;
576 }
577 }
578 rotation_check = bw_def_ok;
579 for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
580 if (data->enable[i]) {
581 if ((bw_equ(data->rotation_angle[i], bw_int_to_fixed(90)) || bw_equ(data->rotation_angle[i], bw_int_to_fixed(270))) && (tiling_mode[i] == bw_def_linear || data->stereo_mode[i] != bw_def_mono)) {
582 rotation_check = bw_def_invalid_linear_or_stereo_mode;
583 }
584 }
585 }
586 if (pipe_check == bw_def_ok && hsr_check == bw_def_ok && vsr_check == bw_def_ok && lb_size_check == bw_def_ok && fbc_check == bw_def_ok && rotation_check == bw_def_ok) {
587 mode_check = bw_def_ok;
588 }
589 else {
590 mode_check = bw_def_notok;
591 }
592 /*number of memory channels for write-back client*/
593 data->number_of_dram_wrchannels = vbios->number_of_dram_channels;
594 data->number_of_dram_channels = vbios->number_of_dram_channels;
595 /*modify number of memory channels if lpt mode is enabled*/
596 /* low power tiling mode register*/
597 /* 0 = use channel 0*/
598 /* 1 = use channel 0 and 1*/
599 /* 2 = use channel 0,1,2,3*/
600 if ((fbc_enabled == 1 && lpt_enabled == 1)) {
601 if (vbios->memory_type == bw_def_hbm)
602 data->dram_efficiency = bw_frc_to_fixed(5, 10);
603 else
604 data->dram_efficiency = bw_int_to_fixed(1);
605
606
607 if (dceip->low_power_tiling_mode == 0) {
608 data->number_of_dram_channels = 1;
609 }
610 else if (dceip->low_power_tiling_mode == 1) {
611 data->number_of_dram_channels = 2;
612 }
613 else if (dceip->low_power_tiling_mode == 2) {
614 data->number_of_dram_channels = 4;
615 }
616 else {
617 data->number_of_dram_channels = 1;
618 }
619 }
620 else {
621 if (vbios->memory_type == bw_def_hbm)
622 data->dram_efficiency = bw_frc_to_fixed(5, 10);
623 else
624 data->dram_efficiency = bw_frc_to_fixed(8, 10);
625 }
626 /*memory request size and latency hiding:*/
627 /*request size is normally 64 byte, 2-line interleaved, with full latency hiding*/
628 /*the display write-back requests are single line*/
629 /*for tiled graphics surfaces, or undelay surfaces with width higher than the maximum size for full efficiency, request size is 32 byte in 8 and 16 bpp or if the rotation is orthogonal to the tiling grain. only half is useful of the bytes in the request size in 8 bpp or in 32 bpp if the rotation is orthogonal to the tiling grain.*/
630 /*for undelay surfaces with width lower than the maximum size for full efficiency, requests are 4-line interleaved in 16bpp if the rotation is parallel to the tiling grain, and 8-line interleaved with 4-line latency hiding in 8bpp or if the rotation is orthogonal to the tiling grain.*/
631 for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
632 if (data->enable[i]) {
633 if ((bw_equ(data->rotation_angle[i], bw_int_to_fixed(90)) || bw_equ(data->rotation_angle[i], bw_int_to_fixed(270)))) {
634 if ((i < 4)) {
635 /*underlay portrait tiling mode is not supported*/
636 data->orthogonal_rotation[i] = 1;
637 }
638 else {
639 /*graphics portrait tiling mode*/
640 if (data->graphics_micro_tile_mode == bw_def_rotated_micro_tiling) {
641 data->orthogonal_rotation[i] = 0;
642 }
643 else {
644 data->orthogonal_rotation[i] = 1;
645 }
646 }
647 }
648 else {
649 if ((i < 4)) {
650 /*underlay landscape tiling mode is only supported*/
651 if (data->underlay_micro_tile_mode == bw_def_display_micro_tiling) {
652 data->orthogonal_rotation[i] = 0;
653 }
654 else {
655 data->orthogonal_rotation[i] = 1;
656 }
657 }
658 else {
659 /*graphics landscape tiling mode*/
660 if (data->graphics_micro_tile_mode == bw_def_display_micro_tiling) {
661 data->orthogonal_rotation[i] = 0;
662 }
663 else {
664 data->orthogonal_rotation[i] = 1;
665 }
666 }
667 }
668 if (bw_equ(data->rotation_angle[i], bw_int_to_fixed(90)) || bw_equ(data->rotation_angle[i], bw_int_to_fixed(270))) {
669 data->underlay_maximum_source_efficient_for_tiling = dceip->underlay_maximum_height_efficient_for_tiling;
670 }
671 else {
672 data->underlay_maximum_source_efficient_for_tiling = dceip->underlay_maximum_width_efficient_for_tiling;
673 }
674 if (surface_type[i] == bw_def_display_write_back420_luma || surface_type[i] == bw_def_display_write_back420_chroma) {
675 data->bytes_per_request[i] = bw_int_to_fixed(64);
676 data->useful_bytes_per_request[i] = bw_int_to_fixed(64);
677 data->lines_interleaved_in_mem_access[i] = bw_int_to_fixed(1);
678 data->latency_hiding_lines[i] = bw_int_to_fixed(1);
679 }
680 else if (tiling_mode[i] == bw_def_linear) {
681 data->bytes_per_request[i] = bw_int_to_fixed(64);
682 data->useful_bytes_per_request[i] = bw_int_to_fixed(64);
683 data->lines_interleaved_in_mem_access[i] = bw_int_to_fixed(2);
684 data->latency_hiding_lines[i] = bw_int_to_fixed(2);
685 }
686 else {
687 if (surface_type[i] == bw_def_graphics || (bw_mtn(data->source_width_rounded_up_to_chunks[i], bw_ceil2(data->underlay_maximum_source_efficient_for_tiling, bw_int_to_fixed(256))))) {
688 switch (data->bytes_per_pixel[i]) {
689 case 8:
690 data->lines_interleaved_in_mem_access[i] = bw_int_to_fixed(2);
691 data->latency_hiding_lines[i] = bw_int_to_fixed(2);
692 if (data->orthogonal_rotation[i]) {
693 data->bytes_per_request[i] = bw_int_to_fixed(32);
694 data->useful_bytes_per_request[i] = bw_int_to_fixed(32);
695 }
696 else {
697 data->bytes_per_request[i] = bw_int_to_fixed(64);
698 data->useful_bytes_per_request[i] = bw_int_to_fixed(64);
699 }
700 break;
701 case 4:
702 if (data->orthogonal_rotation[i]) {
703 data->lines_interleaved_in_mem_access[i] = bw_int_to_fixed(2);
704 data->latency_hiding_lines[i] = bw_int_to_fixed(2);
705 data->bytes_per_request[i] = bw_int_to_fixed(32);
706 data->useful_bytes_per_request[i] = bw_int_to_fixed(16);
707 }
708 else {
709 data->lines_interleaved_in_mem_access[i] = bw_int_to_fixed(2);
710 data->latency_hiding_lines[i] = bw_int_to_fixed(2);
711 data->bytes_per_request[i] = bw_int_to_fixed(64);
712 data->useful_bytes_per_request[i] = bw_int_to_fixed(64);
713 }
714 break;
715 case 2:
716 data->lines_interleaved_in_mem_access[i] = bw_int_to_fixed(2);
717 data->latency_hiding_lines[i] = bw_int_to_fixed(2);
718 data->bytes_per_request[i] = bw_int_to_fixed(32);
719 data->useful_bytes_per_request[i] = bw_int_to_fixed(32);
720 break;
721 default:
722 data->lines_interleaved_in_mem_access[i] = bw_int_to_fixed(2);
723 data->latency_hiding_lines[i] = bw_int_to_fixed(2);
724 data->bytes_per_request[i] = bw_int_to_fixed(32);
725 data->useful_bytes_per_request[i] = bw_int_to_fixed(16);
726 break;
727 }
728 }
729 else {
730 data->bytes_per_request[i] = bw_int_to_fixed(64);
731 data->useful_bytes_per_request[i] = bw_int_to_fixed(64);
732 if (data->orthogonal_rotation[i]) {
733 data->lines_interleaved_in_mem_access[i] = bw_int_to_fixed(8);
734 data->latency_hiding_lines[i] = bw_int_to_fixed(4);
735 }
736 else {
737 switch (data->bytes_per_pixel[i]) {
738 case 4:
739 data->lines_interleaved_in_mem_access[i] = bw_int_to_fixed(2);
740 data->latency_hiding_lines[i] = bw_int_to_fixed(2);
741 break;
742 case 2:
743 data->lines_interleaved_in_mem_access[i] = bw_int_to_fixed(4);
744 data->latency_hiding_lines[i] = bw_int_to_fixed(4);
745 break;
746 default:
747 data->lines_interleaved_in_mem_access[i] = bw_int_to_fixed(8);
748 data->latency_hiding_lines[i] = bw_int_to_fixed(4);
749 break;
750 }
751 }
752 }
753 }
754 }
755 }
756 /*requested peak bandwidth:*/
757 /*the peak request-per-second bandwidth is the product of the maximum source lines in per line out in the beginning*/
758 /*and in the middle of the frame, the ratio of the source width to the line time, the ratio of line interleaving*/
759 /*in memory to lines of latency hiding, and the ratio of bytes per pixel to useful bytes per request.*/
760 /**/
761 /*if the dmif data buffer size holds more than vta_ps worth of source lines, then only vsr is used.*/
762 /*the peak bandwidth is the peak request-per-second bandwidth times the request size.*/
763 /**/
764 /*the line buffer lines in per line out in the beginning of the frame is the vertical filter initialization value*/
765 /*rounded up to even and divided by the line times for initialization, which is normally three.*/
766 /*the line buffer lines in per line out in the middle of the frame is at least one, or the vertical scale ratio,*/
767 /*rounded up to line pairs if not doing line buffer prefetching.*/
768 /**/
769 /*the non-prefetching rounding up of the vertical scale ratio can also be done up to 1 (for a 0,2 pattern), 4/3 (for a 0,2,2 pattern),*/
770 /*6/4 (for a 0,2,2,2 pattern), or 3 (for a 2,4 pattern).*/
771 /**/
772 /*the scaler vertical filter initialization value is calculated by the hardware as the floor of the average of the*/
773 /*vertical scale ratio and the number of vertical taps increased by one. add one more for possible odd line*/
774 /*panning/bezel adjustment mode.*/
775 /**/
776 /*for the bottom interlace field an extra 50% of the vertical scale ratio is considered for this calculation.*/
777 /*in top-bottom stereo mode software has to set the filter initialization value manually and explicitly limit it to 4.*/
778 /*furthermore, there is only one line time for initialization.*/
779 /**/
780 /*line buffer prefetching is done when the number of lines in the line buffer exceeds the number of taps plus*/
781 /*the ceiling of the vertical scale ratio.*/
782 /**/
783 /*multi-line buffer prefetching is only done in the graphics pipe when the scaler is disabled or when upscaling and the vsr <= 0.8.'*/
784 /**/
785 /*the horizontal blank and chunk granularity factor is indirectly used indicate the interval of time required to transfer the source pixels.*/
786 /*the denominator of this term represents the total number of destination output pixels required for the input source pixels.*/
787 /*it applies when the lines in per line out is not 2 or 4. it does not apply when there is a line buffer between the scl and blnd.*/
788 for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
789 if (data->enable[i]) {
790 data->v_filter_init[i] = bw_floor2(bw_div((bw_add(bw_add(bw_add(bw_int_to_fixed(1), data->v_taps[i]), data->vsr[i]), bw_mul(bw_mul(bw_int_to_fixed(data->interlace_mode[i]), bw_frc_to_fixed(5, 10)), data->vsr[i]))), bw_int_to_fixed(2)), bw_int_to_fixed(1));
791 if (data->panning_and_bezel_adjustment == bw_def_any_lines) {
792 data->v_filter_init[i] = bw_add(data->v_filter_init[i], bw_int_to_fixed(1));
793 }
794 if (data->stereo_mode[i] == bw_def_top_bottom) {
795 v_filter_init_mode[i] = bw_def_manual;
796 data->v_filter_init[i] = bw_min2(data->v_filter_init[i], bw_int_to_fixed(4));
797 }
798 else {
799 v_filter_init_mode[i] = bw_def_auto;
800 }
801 if (data->stereo_mode[i] == bw_def_top_bottom) {
802 data->num_lines_at_frame_start = bw_int_to_fixed(1);
803 }
804 else {
805 data->num_lines_at_frame_start = bw_int_to_fixed(3);
806 }
807 if ((bw_mtn(data->vsr[i], bw_int_to_fixed(1)) && surface_type[i] == bw_def_graphics) || data->panning_and_bezel_adjustment == bw_def_any_lines) {
808 data->line_buffer_prefetch[i] = 0;
809 }
810 else if ((((dceip->underlay_downscale_prefetch_enabled == 1 && surface_type[i] != bw_def_graphics) || surface_type[i] == bw_def_graphics) && (bw_mtn(data->lb_partitions[i], bw_add(data->v_taps[i], bw_ceil2(data->vsr[i], bw_int_to_fixed(1))))))) {
811 data->line_buffer_prefetch[i] = 1;
812 }
813 else {
814 data->line_buffer_prefetch[i] = 0;
815 }
816 data->lb_lines_in_per_line_out_in_beginning_of_frame[i] = bw_div(bw_ceil2(data->v_filter_init[i], bw_int_to_fixed(dceip->lines_interleaved_into_lb)), data->num_lines_at_frame_start);
817 if (data->line_buffer_prefetch[i] == 1) {
818 data->lb_lines_in_per_line_out_in_middle_of_frame[i] = bw_max2(bw_int_to_fixed(1), data->vsr[i]);
819 }
820 else if (bw_leq(data->vsr[i], bw_int_to_fixed(1))) {
821 data->lb_lines_in_per_line_out_in_middle_of_frame[i] = bw_int_to_fixed(1);
822 } else if (bw_leq(data->vsr[i],
823 bw_frc_to_fixed(4, 3))) {
824 data->lb_lines_in_per_line_out_in_middle_of_frame[i] = bw_div(bw_int_to_fixed(4), bw_int_to_fixed(3));
825 } else if (bw_leq(data->vsr[i],
826 bw_frc_to_fixed(6, 4))) {
827 data->lb_lines_in_per_line_out_in_middle_of_frame[i] = bw_div(bw_int_to_fixed(6), bw_int_to_fixed(4));
828 }
829 else if (bw_leq(data->vsr[i], bw_int_to_fixed(2))) {
830 data->lb_lines_in_per_line_out_in_middle_of_frame[i] = bw_int_to_fixed(2);
831 }
832 else if (bw_leq(data->vsr[i], bw_int_to_fixed(3))) {
833 data->lb_lines_in_per_line_out_in_middle_of_frame[i] = bw_int_to_fixed(3);
834 }
835 else {
836 data->lb_lines_in_per_line_out_in_middle_of_frame[i] = bw_int_to_fixed(4);
837 }
838 if (data->line_buffer_prefetch[i] == 1 || bw_equ(data->lb_lines_in_per_line_out_in_middle_of_frame[i], bw_int_to_fixed(2)) || bw_equ(data->lb_lines_in_per_line_out_in_middle_of_frame[i], bw_int_to_fixed(4))) {
839 data->horizontal_blank_and_chunk_granularity_factor[i] = bw_int_to_fixed(1);
840 }
841 else {
842 data->horizontal_blank_and_chunk_granularity_factor[i] = bw_div(data->h_total[i], (bw_div((bw_add(data->h_total[i], bw_div((bw_sub(data->source_width_pixels[i], bw_int_to_fixed(dceip->chunk_width))), data->hsr[i]))), bw_int_to_fixed(2))));
843 }
844 data->request_bandwidth[i] = bw_div(bw_mul(bw_div(bw_mul(bw_div(bw_mul(bw_max2(data->lb_lines_in_per_line_out_in_beginning_of_frame[i], data->lb_lines_in_per_line_out_in_middle_of_frame[i]), data->source_width_rounded_up_to_chunks[i]), (bw_div(data->h_total[i], data->pixel_rate[i]))), bw_int_to_fixed(data->bytes_per_pixel[i])), data->useful_bytes_per_request[i]), data->lines_interleaved_in_mem_access[i]), data->latency_hiding_lines[i]);
845 data->display_bandwidth[i] = bw_mul(data->request_bandwidth[i], data->bytes_per_request[i]);
846 }
847 }
848 /*outstanding chunk request limit*/
849 /*if underlay buffer sharing is enabled, the data buffer size for underlay in 422 or 444 is the sum of the luma and chroma data buffer sizes.*/
850 /*underlay buffer sharing mode is only permitted in orthogonal rotation modes.*/
851 /**/
852 /*if there is only one display enabled, the dmif data buffer size for the graphics surface is increased by concatenating the adjacent buffers.*/
853 /**/
854 /*the memory chunk size in bytes is 1024 for the writeback, and 256 times the memory line interleaving and the bytes per pixel for graphics*/
855 /*and underlay.*/
856 /**/
857 /*the pipe chunk size uses 2 for line interleaving, except for the write back, in which case it is 1.*/
858 /*graphics and underlay data buffer size is adjusted (limited) using the outstanding chunk request limit if there is more than one*/
859 /*display enabled or if the dmif request buffer is not large enough for the total data buffer size.*/
860 /*the outstanding chunk request limit is the ceiling of the adjusted data buffer size divided by the chunk size in bytes*/
861 /*the adjusted data buffer size is the product of the display bandwidth and the minimum effective data buffer size in terms of time,*/
862 /*rounded up to the chunk size in bytes, but should not exceed the original data buffer size*/
863 for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
864 if (data->enable[i]) {
865 if ((dceip->dmif_pipe_en_fbc_chunk_tracker + 3 == i && fbc_enabled == 0 && tiling_mode[i] != bw_def_linear)) {
866 data->max_chunks_non_fbc_mode[i] = 128 - dmif_chunk_buff_margin;
867 }
868 else {
869 data->max_chunks_non_fbc_mode[i] = 16 - dmif_chunk_buff_margin;
870 }
871 }
872 if (data->fbc_en[i] == 1) {
873 max_chunks_fbc_mode = 128 - dmif_chunk_buff_margin;
874 }
875 }
876 for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
877 if (data->enable[i]) {
878 switch (surface_type[i]) {
879 case bw_def_display_write_back420_luma:
880 data->data_buffer_size[i] = bw_int_to_fixed(dceip->display_write_back420_luma_mcifwr_buffer_size);
881 break;
882 case bw_def_display_write_back420_chroma:
883 data->data_buffer_size[i] = bw_int_to_fixed(dceip->display_write_back420_chroma_mcifwr_buffer_size);
884 break;
885 case bw_def_underlay420_luma:
886 data->data_buffer_size[i] = bw_int_to_fixed(dceip->underlay_luma_dmif_size);
887 break;
888 case bw_def_underlay420_chroma:
889 data->data_buffer_size[i] = bw_div(bw_int_to_fixed(dceip->underlay_chroma_dmif_size), bw_int_to_fixed(2));
890 break;
891 case bw_def_underlay422:case bw_def_underlay444:
892 if (data->orthogonal_rotation[i] == 0) {
893 data->data_buffer_size[i] = bw_int_to_fixed(dceip->underlay_luma_dmif_size);
894 }
895 else {
896 data->data_buffer_size[i] = bw_add(bw_int_to_fixed(dceip->underlay_luma_dmif_size), bw_int_to_fixed(dceip->underlay_chroma_dmif_size));
897 }
898 break;
899 default:
900 if (data->fbc_en[i] == 1) {
901 /*data_buffer_size(i) = max_dmif_buffer_allocated * graphics_dmif_size*/
902 if (data->number_of_displays == 1) {
903 data->data_buffer_size[i] = bw_min2(bw_mul(bw_mul(bw_int_to_fixed(max_chunks_fbc_mode), bw_int_to_fixed(pixels_per_chunk)), bw_int_to_fixed(data->bytes_per_pixel[i])), bw_mul(bw_int_to_fixed(dceip->max_dmif_buffer_allocated), bw_int_to_fixed(dceip->graphics_dmif_size)));
904 }
905 else {
906 data->data_buffer_size[i] = bw_min2(bw_mul(bw_mul(bw_int_to_fixed(max_chunks_fbc_mode), bw_int_to_fixed(pixels_per_chunk)), bw_int_to_fixed(data->bytes_per_pixel[i])), bw_int_to_fixed(dceip->graphics_dmif_size));
907 }
908 }
909 else {
910 /*the effective dmif buffer size in non-fbc mode is limited by the 16 entry chunk tracker*/
911 if (data->number_of_displays == 1) {
912 data->data_buffer_size[i] = bw_min2(bw_mul(bw_mul(bw_int_to_fixed(data->max_chunks_non_fbc_mode[i]), bw_int_to_fixed(pixels_per_chunk)), bw_int_to_fixed(data->bytes_per_pixel[i])), bw_mul(bw_int_to_fixed(dceip->max_dmif_buffer_allocated), bw_int_to_fixed(dceip->graphics_dmif_size)));
913 }
914 else {
915 data->data_buffer_size[i] = bw_min2(bw_mul(bw_mul(bw_int_to_fixed(data->max_chunks_non_fbc_mode[i]), bw_int_to_fixed(pixels_per_chunk)), bw_int_to_fixed(data->bytes_per_pixel[i])), bw_int_to_fixed(dceip->graphics_dmif_size));
916 }
917 }
918 break;
919 }
920 if (surface_type[i] == bw_def_display_write_back420_luma || surface_type[i] == bw_def_display_write_back420_chroma) {
921 data->memory_chunk_size_in_bytes[i] = bw_int_to_fixed(1024);
922 data->pipe_chunk_size_in_bytes[i] = bw_int_to_fixed(1024);
923 }
924 else {
925 data->memory_chunk_size_in_bytes[i] = bw_mul(bw_mul(bw_int_to_fixed(dceip->chunk_width), data->lines_interleaved_in_mem_access[i]), bw_int_to_fixed(data->bytes_per_pixel[i]));
926 data->pipe_chunk_size_in_bytes[i] = bw_mul(bw_mul(bw_int_to_fixed(dceip->chunk_width), bw_int_to_fixed(dceip->lines_interleaved_into_lb)), bw_int_to_fixed(data->bytes_per_pixel[i]));
927 }
928 }
929 }
930 data->min_dmif_size_in_time = bw_int_to_fixed(9999);
931 data->min_mcifwr_size_in_time = bw_int_to_fixed(9999);
932 for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
933 if (data->enable[i]) {
934 if (surface_type[i] != bw_def_display_write_back420_luma && surface_type[i] != bw_def_display_write_back420_chroma) {
935 if (bw_ltn(bw_div(bw_div(bw_mul(data->data_buffer_size[i], data->bytes_per_request[i]), data->useful_bytes_per_request[i]), data->display_bandwidth[i]), data->min_dmif_size_in_time)) {
936 data->min_dmif_size_in_time = bw_div(bw_div(bw_mul(data->data_buffer_size[i], data->bytes_per_request[i]), data->useful_bytes_per_request[i]), data->display_bandwidth[i]);
937 }
938 }
939 else {
940 if (bw_ltn(bw_div(bw_div(bw_mul(data->data_buffer_size[i], data->bytes_per_request[i]), data->useful_bytes_per_request[i]), data->display_bandwidth[i]), data->min_mcifwr_size_in_time)) {
941 data->min_mcifwr_size_in_time = bw_div(bw_div(bw_mul(data->data_buffer_size[i], data->bytes_per_request[i]), data->useful_bytes_per_request[i]), data->display_bandwidth[i]);
942 }
943 }
944 }
945 }
946 data->total_requests_for_dmif_size = bw_int_to_fixed(0);
947 for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
948 if (data->enable[i] && surface_type[i] != bw_def_display_write_back420_luma && surface_type[i] != bw_def_display_write_back420_chroma) {
949 data->total_requests_for_dmif_size = bw_add(data->total_requests_for_dmif_size, bw_div(data->data_buffer_size[i], data->useful_bytes_per_request[i]));
950 }
951 }
952 for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
953 if (data->enable[i]) {
954 if (surface_type[i] != bw_def_display_write_back420_luma && surface_type[i] != bw_def_display_write_back420_chroma && dceip->limit_excessive_outstanding_dmif_requests && (data->number_of_displays > 1 || bw_mtn(data->total_requests_for_dmif_size, dceip->dmif_request_buffer_size))) {
955 data->adjusted_data_buffer_size[i] = bw_min2(data->data_buffer_size[i], bw_ceil2(bw_mul(data->min_dmif_size_in_time, data->display_bandwidth[i]), data->memory_chunk_size_in_bytes[i]));
956 }
957 else {
958 data->adjusted_data_buffer_size[i] = data->data_buffer_size[i];
959 }
960 }
961 }
962 for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
963 if (data->enable[i]) {
964 if (data->number_of_displays == 1 && data->number_of_underlay_surfaces == 0) {
965 /*set maximum chunk limit if only one graphic pipe is enabled*/
966 data->outstanding_chunk_request_limit[i] = bw_int_to_fixed(127);
967 }
968 else {
969 data->outstanding_chunk_request_limit[i] = bw_ceil2(bw_div(data->adjusted_data_buffer_size[i], data->pipe_chunk_size_in_bytes[i]), bw_int_to_fixed(1));
970 /*clamp maximum chunk limit in the graphic display pipe*/
971 if (i >= 4) {
972 data->outstanding_chunk_request_limit[i] = bw_max2(bw_int_to_fixed(127), data->outstanding_chunk_request_limit[i]);
973 }
974 }
975 }
976 }
977 /*outstanding pte request limit*/
978 /*in tiling mode with no rotation the sg pte requests are 8 useful pt_es, the sg row height is the page height and the sg page width x height is 64x64 for 8bpp, 64x32 for 16 bpp, 32x32 for 32 bpp*/
979 /*in tiling mode with rotation the sg pte requests are only one useful pte, and the sg row height is also the page height, but the sg page width and height are swapped*/
980 /*in linear mode the pte requests are 8 useful pt_es, the sg page width is 4096 divided by the bytes per pixel, the sg page height is 1, but there is just one row whose height is the lines of pte prefetching*/
981 /*the outstanding pte request limit is obtained by multiplying the outstanding chunk request limit by the peak pte request to eviction limiting ratio, rounding up to integer, multiplying by the pte requests per chunk, and rounding up to integer again*/
982 /*if not using peak pte request to eviction limiting, the outstanding pte request limit is the pte requests in the vblank*/
983 /*the pte requests in the vblank is the product of the number of pte request rows times the number of pte requests in a row*/
984 /*the number of pte requests in a row is the quotient of the source width divided by 256, multiplied by the pte requests per chunk, rounded up to even, multiplied by the scatter-gather row height and divided by the scatter-gather page height*/
985 /*the pte requests per chunk is 256 divided by the scatter-gather page width and the useful pt_es per pte request*/
986 if (data->number_of_displays > 1 || (bw_neq(data->rotation_angle[4], bw_int_to_fixed(0)) && bw_neq(data->rotation_angle[4], bw_int_to_fixed(180)))) {
987 data->peak_pte_request_to_eviction_ratio_limiting = dceip->peak_pte_request_to_eviction_ratio_limiting_multiple_displays_or_single_rotated_display;
988 }
989 else {
990 data->peak_pte_request_to_eviction_ratio_limiting = dceip->peak_pte_request_to_eviction_ratio_limiting_single_display_no_rotation;
991 }
992 for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
993 if (data->enable[i] && data->scatter_gather_enable_for_pipe[i] == 1) {
994 if (tiling_mode[i] == bw_def_linear) {
995 data->useful_pte_per_pte_request = bw_int_to_fixed(8);
996 data->scatter_gather_page_width[i] = bw_div(bw_int_to_fixed(4096), bw_int_to_fixed(data->bytes_per_pixel[i]));
997 data->scatter_gather_page_height[i] = bw_int_to_fixed(1);
998 data->scatter_gather_pte_request_rows = bw_int_to_fixed(1);
999 data->scatter_gather_row_height = bw_int_to_fixed(dceip->scatter_gather_lines_of_pte_prefetching_in_linear_mode);
1000 }
1001 else if (bw_equ(data->rotation_angle[i], bw_int_to_fixed(0)) || bw_equ(data->rotation_angle[i], bw_int_to_fixed(180))) {
1002 data->useful_pte_per_pte_request = bw_int_to_fixed(8);
1003 switch (data->bytes_per_pixel[i]) {
1004 case 4:
1005 data->scatter_gather_page_width[i] = bw_int_to_fixed(32);
1006 data->scatter_gather_page_height[i] = bw_int_to_fixed(32);
1007 break;
1008 case 2:
1009 data->scatter_gather_page_width[i] = bw_int_to_fixed(64);
1010 data->scatter_gather_page_height[i] = bw_int_to_fixed(32);
1011 break;
1012 default:
1013 data->scatter_gather_page_width[i] = bw_int_to_fixed(64);
1014 data->scatter_gather_page_height[i] = bw_int_to_fixed(64);
1015 break;
1016 }
1017 data->scatter_gather_pte_request_rows = bw_int_to_fixed(dceip->scatter_gather_pte_request_rows_in_tiling_mode);
1018 data->scatter_gather_row_height = data->scatter_gather_page_height[i];
1019 }
1020 else {
1021 data->useful_pte_per_pte_request = bw_int_to_fixed(1);
1022 switch (data->bytes_per_pixel[i]) {
1023 case 4:
1024 data->scatter_gather_page_width[i] = bw_int_to_fixed(32);
1025 data->scatter_gather_page_height[i] = bw_int_to_fixed(32);
1026 break;
1027 case 2:
1028 data->scatter_gather_page_width[i] = bw_int_to_fixed(32);
1029 data->scatter_gather_page_height[i] = bw_int_to_fixed(64);
1030 break;
1031 default:
1032 data->scatter_gather_page_width[i] = bw_int_to_fixed(64);
1033 data->scatter_gather_page_height[i] = bw_int_to_fixed(64);
1034 break;
1035 }
1036 data->scatter_gather_pte_request_rows = bw_int_to_fixed(dceip->scatter_gather_pte_request_rows_in_tiling_mode);
1037 data->scatter_gather_row_height = data->scatter_gather_page_height[i];
1038 }
1039 data->pte_request_per_chunk[i] = bw_div(bw_div(bw_int_to_fixed(dceip->chunk_width), data->scatter_gather_page_width[i]), data->useful_pte_per_pte_request);
1040 data->scatter_gather_pte_requests_in_row[i] = bw_div(bw_mul(bw_ceil2(bw_mul(bw_div(data->source_width_rounded_up_to_chunks[i], bw_int_to_fixed(dceip->chunk_width)), data->pte_request_per_chunk[i]), bw_int_to_fixed(1)), data->scatter_gather_row_height), data->scatter_gather_page_height[i]);
1041 data->scatter_gather_pte_requests_in_vblank = bw_mul(data->scatter_gather_pte_request_rows, data->scatter_gather_pte_requests_in_row[i]);
1042 if (bw_equ(data->peak_pte_request_to_eviction_ratio_limiting, bw_int_to_fixed(0))) {
1043 data->scatter_gather_pte_request_limit[i] = data->scatter_gather_pte_requests_in_vblank;
1044 }
1045 else {
1046 data->scatter_gather_pte_request_limit[i] = bw_max2(dceip->minimum_outstanding_pte_request_limit, bw_min2(data->scatter_gather_pte_requests_in_vblank, bw_ceil2(bw_mul(bw_mul(bw_div(bw_ceil2(data->adjusted_data_buffer_size[i], data->memory_chunk_size_in_bytes[i]), data->memory_chunk_size_in_bytes[i]), data->pte_request_per_chunk[i]), data->peak_pte_request_to_eviction_ratio_limiting), bw_int_to_fixed(1))));
1047 }
1048 }
1049 }
1050 /*pitch padding recommended for efficiency in linear mode*/
1051 /*in linear mode graphics or underlay with scatter gather, a pitch that is a multiple of the channel interleave (256 bytes) times the channel-bank rotation is not efficient*/
1052 /*if that is the case it is recommended to pad the pitch by at least 256 pixels*/
1053 data->inefficient_linear_pitch_in_bytes = bw_mul(bw_mul(bw_int_to_fixed(256), bw_int_to_fixed(vbios->number_of_dram_banks)), bw_int_to_fixed(data->number_of_dram_channels));
1054
1055 /*pixel transfer time*/
1056 /*the dmif and mcifwr yclk(pclk) required is the one that allows the transfer of all pipe's data buffer size in memory in the time for data transfer*/
1057 /*for dmif, pte and cursor requests have to be included.*/
1058 /*the dram data requirement is doubled when the data request size in bytes is less than the dram channel width times the burst size (8)*/
1059 /*the dram data requirement is also multiplied by the number of channels in the case of low power tiling*/
1060 /*the page close-open time is determined by trc and the number of page close-opens*/
1061 /*in tiled mode graphics or underlay with scatter-gather enabled the bytes per page close-open is the product of the memory line interleave times the maximum of the scatter-gather page width and the product of the tile width (8 pixels) times the number of channels times the number of banks.*/
1062 /*in linear mode graphics or underlay with scatter-gather enabled and inefficient pitch, the bytes per page close-open is the line request alternation slice, because different lines are in completely different 4k address bases.*/
1063 /*otherwise, the bytes page close-open is the chunk size because that is the arbitration slice.*/
1064 /*pte requests are grouped by pte requests per chunk if that is more than 1. each group costs a page close-open time for dmif reads*/
1065 /*cursor requests outstanding are limited to a group of two source lines. each group costs a page close-open time for dmif reads*/
1066 /*the display reads and writes time for data transfer is the minimum data or cursor buffer size in time minus the mc urgent latency*/
1067 /*the mc urgent latency is experienced more than one time if the number of dmif requests in the data buffer exceeds the request buffer size plus the request slots reserved for dmif in the dram channel arbiter queues*/
1068 /*the dispclk required is the maximum for all surfaces of the maximum of the source pixels for first output pixel times the throughput factor, divided by the pixels per dispclk, and divided by the minimum latency hiding minus the dram speed/p-state change latency minus the burst time, and the source pixels for last output pixel, times the throughput factor, divided by the pixels per dispclk, and divided by the minimum latency hiding minus the dram speed/p-state change latency minus the burst time, plus the active time.*/
1069 /*the data burst time is the maximum of the total page close-open time, total dmif/mcifwr buffer size in memory divided by the dram bandwidth, and the total dmif/mcifwr buffer size in memory divided by the 32 byte sclk data bus bandwidth, each multiplied by its efficiency.*/
1070 /*the source line transfer time is the maximum for all surfaces of the maximum of the burst time plus the urgent latency times the floor of the data required divided by the buffer size for the fist pixel, and the burst time plus the urgent latency times the floor of the data required divided by the buffer size for the last pixel plus the active time.*/
1071 /*the source pixels for the first output pixel is 512 if the scaler vertical filter initialization value is greater than 2, and it is 4 times the source width if it is greater than 4.*/
1072 /*the source pixels for the last output pixel is the source width times the scaler vertical filter initialization value rounded up to even*/
1073 /*the source data for these pixels is the number of pixels times the bytes per pixel times the bytes per request divided by the useful bytes per request.*/
1074 data->cursor_total_data = bw_int_to_fixed(0);
1075 data->cursor_total_request_groups = bw_int_to_fixed(0);
1076 data->scatter_gather_total_pte_requests = bw_int_to_fixed(0);
1077 data->scatter_gather_total_pte_request_groups = bw_int_to_fixed(0);
1078 for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
1079 if (data->enable[i]) {
1080 data->cursor_total_data = bw_add(data->cursor_total_data, bw_mul(bw_mul(bw_int_to_fixed(2), data->cursor_width_pixels[i]), bw_int_to_fixed(4)));
1081 if (dceip->large_cursor == 1) {
1082 data->cursor_total_request_groups = bw_add(data->cursor_total_request_groups, bw_int_to_fixed((dceip->cursor_max_outstanding_group_num + 1)));
1083 }
1084 else {
1085 data->cursor_total_request_groups = bw_add(data->cursor_total_request_groups, bw_ceil2(bw_div(data->cursor_width_pixels[i], dceip->cursor_chunk_width), bw_int_to_fixed(1)));
1086 }
1087 if (data->scatter_gather_enable_for_pipe[i]) {
1088 data->scatter_gather_total_pte_requests = bw_add(data->scatter_gather_total_pte_requests, data->scatter_gather_pte_request_limit[i]);
1089 data->scatter_gather_total_pte_request_groups = bw_add(data->scatter_gather_total_pte_request_groups, bw_ceil2(bw_div(data->scatter_gather_pte_request_limit[i], bw_ceil2(data->pte_request_per_chunk[i], bw_int_to_fixed(1))), bw_int_to_fixed(1)));
1090 }
1091 }
1092 }
1093 data->tile_width_in_pixels = bw_int_to_fixed(8);
1094 data->dmif_total_number_of_data_request_page_close_open = bw_int_to_fixed(0);
1095 data->mcifwr_total_number_of_data_request_page_close_open = bw_int_to_fixed(0);
1096 for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
1097 if (data->enable[i]) {
1098 if (data->scatter_gather_enable_for_pipe[i] == 1 && tiling_mode[i] != bw_def_linear) {
1099 data->bytes_per_page_close_open = bw_mul(data->lines_interleaved_in_mem_access[i], bw_max2(bw_mul(bw_mul(bw_mul(bw_int_to_fixed(data->bytes_per_pixel[i]), data->tile_width_in_pixels), bw_int_to_fixed(vbios->number_of_dram_banks)), bw_int_to_fixed(data->number_of_dram_channels)), bw_mul(bw_int_to_fixed(data->bytes_per_pixel[i]), data->scatter_gather_page_width[i])));
1100 }
1101 else if (data->scatter_gather_enable_for_pipe[i] == 1 && tiling_mode[i] == bw_def_linear && bw_equ(bw_mod((bw_mul(data->pitch_in_pixels_after_surface_type[i], bw_int_to_fixed(data->bytes_per_pixel[i]))), data->inefficient_linear_pitch_in_bytes), bw_int_to_fixed(0))) {
1102 data->bytes_per_page_close_open = dceip->linear_mode_line_request_alternation_slice;
1103 }
1104 else {
1105 data->bytes_per_page_close_open = data->memory_chunk_size_in_bytes[i];
1106 }
1107 if (surface_type[i] != bw_def_display_write_back420_luma && surface_type[i] != bw_def_display_write_back420_chroma) {
1108 data->dmif_total_number_of_data_request_page_close_open = bw_add(data->dmif_total_number_of_data_request_page_close_open, bw_div(bw_ceil2(data->adjusted_data_buffer_size[i], data->memory_chunk_size_in_bytes[i]), data->bytes_per_page_close_open));
1109 }
1110 else {
1111 data->mcifwr_total_number_of_data_request_page_close_open = bw_add(data->mcifwr_total_number_of_data_request_page_close_open, bw_div(bw_ceil2(data->adjusted_data_buffer_size[i], data->memory_chunk_size_in_bytes[i]), data->bytes_per_page_close_open));
1112 }
1113 }
1114 }
1115 data->dmif_total_page_close_open_time = bw_div(bw_mul((bw_add(bw_add(data->dmif_total_number_of_data_request_page_close_open, data->scatter_gather_total_pte_request_groups), data->cursor_total_request_groups)), vbios->trc), bw_int_to_fixed(1000));
1116 data->mcifwr_total_page_close_open_time = bw_div(bw_mul(data->mcifwr_total_number_of_data_request_page_close_open, vbios->trc), bw_int_to_fixed(1000));
1117 for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
1118 if (data->enable[i]) {
1119 data->adjusted_data_buffer_size_in_memory[i] = bw_div(bw_mul(data->adjusted_data_buffer_size[i], data->bytes_per_request[i]), data->useful_bytes_per_request[i]);
1120 }
1121 }
1122 data->total_requests_for_adjusted_dmif_size = bw_int_to_fixed(0);
1123 for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
1124 if (data->enable[i]) {
1125 if (surface_type[i] != bw_def_display_write_back420_luma && surface_type[i] != bw_def_display_write_back420_chroma) {
1126 data->total_requests_for_adjusted_dmif_size = bw_add(data->total_requests_for_adjusted_dmif_size, bw_div(data->adjusted_data_buffer_size[i], data->useful_bytes_per_request[i]));
1127 }
1128 }
1129 }
1130 data->total_dmifmc_urgent_trips = bw_ceil2(bw_div(data->total_requests_for_adjusted_dmif_size, (bw_add(dceip->dmif_request_buffer_size, bw_int_to_fixed(vbios->number_of_request_slots_gmc_reserves_for_dmif_per_channel * data->number_of_dram_channels)))), bw_int_to_fixed(1));
1131 data->total_dmifmc_urgent_latency = bw_mul(vbios->dmifmc_urgent_latency, data->total_dmifmc_urgent_trips);
1132 data->total_display_reads_required_data = bw_int_to_fixed(0);
1133 data->total_display_reads_required_dram_access_data = bw_int_to_fixed(0);
1134 data->total_display_writes_required_data = bw_int_to_fixed(0);
1135 data->total_display_writes_required_dram_access_data = bw_int_to_fixed(0);
1136 for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
1137 if (data->enable[i]) {
1138 if (surface_type[i] != bw_def_display_write_back420_luma && surface_type[i] != bw_def_display_write_back420_chroma) {
1139 data->display_reads_required_data = data->adjusted_data_buffer_size_in_memory[i];
1140 /*for hbm memories, each channel is split into 2 pseudo-channels that are each 64 bits in width. each*/
1141 /*pseudo-channel may be read independently of one another.*/
1142 /*the read burst length (bl) for hbm memories is 4, so each read command will access 32 bytes of data.*/
1143 /*the 64 or 32 byte sized data is stored in one pseudo-channel.*/
1144 /*it will take 4 memclk cycles or 8 yclk cycles to fetch 64 bytes of data from the hbm memory (2 read commands).*/
1145 /*it will take 2 memclk cycles or 4 yclk cycles to fetch 32 bytes of data from the hbm memory (1 read command).*/
1146 /*for gddr5/ddr4 memories, there is additional overhead if the size of the request is smaller than 64 bytes.*/
1147 /*the read burst length (bl) for gddr5/ddr4 memories is 8, regardless of the size of the data request.*/
1148 /*therefore it will require 8 cycles to fetch 64 or 32 bytes of data from the memory.*/
1149 /*the memory efficiency will be 50% for the 32 byte sized data.*/
1150 if (vbios->memory_type == bw_def_hbm) {
1151 data->display_reads_required_dram_access_data = data->adjusted_data_buffer_size_in_memory[i];
1152 }
1153 else {
1154 data->display_reads_required_dram_access_data = bw_mul(data->adjusted_data_buffer_size_in_memory[i], bw_ceil2(bw_div(bw_int_to_fixed((8 * vbios->dram_channel_width_in_bits / 8)), data->bytes_per_request[i]), bw_int_to_fixed(1)));
1155 }
1156 data->total_display_reads_required_data = bw_add(data->total_display_reads_required_data, data->display_reads_required_data);
1157 data->total_display_reads_required_dram_access_data = bw_add(data->total_display_reads_required_dram_access_data, data->display_reads_required_dram_access_data);
1158 }
1159 else {
1160 data->total_display_writes_required_data = bw_add(data->total_display_writes_required_data, data->adjusted_data_buffer_size_in_memory[i]);
1161 data->total_display_writes_required_dram_access_data = bw_add(data->total_display_writes_required_dram_access_data, bw_mul(data->adjusted_data_buffer_size_in_memory[i], bw_ceil2(bw_div(bw_int_to_fixed(vbios->dram_channel_width_in_bits), data->bytes_per_request[i]), bw_int_to_fixed(1))));
1162 }
1163 }
1164 }
1165 data->total_display_reads_required_data = bw_add(bw_add(data->total_display_reads_required_data, data->cursor_total_data), bw_mul(data->scatter_gather_total_pte_requests, bw_int_to_fixed(64)));
1166 data->total_display_reads_required_dram_access_data = bw_add(bw_add(data->total_display_reads_required_dram_access_data, data->cursor_total_data), bw_mul(data->scatter_gather_total_pte_requests, bw_int_to_fixed(64)));
1167 for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
1168 if (data->enable[i]) {
1169 if (bw_mtn(data->v_filter_init[i], bw_int_to_fixed(4))) {
1170 data->src_pixels_for_first_output_pixel[i] = bw_mul(bw_int_to_fixed(4), data->source_width_rounded_up_to_chunks[i]);
1171 }
1172 else {
1173 if (bw_mtn(data->v_filter_init[i], bw_int_to_fixed(2))) {
1174 data->src_pixels_for_first_output_pixel[i] = bw_int_to_fixed(512);
1175 }
1176 else {
1177 data->src_pixels_for_first_output_pixel[i] = bw_int_to_fixed(0);
1178 }
1179 }
1180 data->src_data_for_first_output_pixel[i] = bw_div(bw_mul(bw_mul(data->src_pixels_for_first_output_pixel[i], bw_int_to_fixed(data->bytes_per_pixel[i])), data->bytes_per_request[i]), data->useful_bytes_per_request[i]);
1181 data->src_pixels_for_last_output_pixel[i] = bw_mul(data->source_width_rounded_up_to_chunks[i], bw_max2(bw_ceil2(data->v_filter_init[i], bw_int_to_fixed(dceip->lines_interleaved_into_lb)), bw_mul(bw_ceil2(data->vsr[i], bw_int_to_fixed(dceip->lines_interleaved_into_lb)), data->horizontal_blank_and_chunk_granularity_factor[i])));
1182 data->src_data_for_last_output_pixel[i] = bw_div(bw_mul(bw_mul(bw_mul(data->source_width_rounded_up_to_chunks[i], bw_max2(bw_ceil2(data->v_filter_init[i], bw_int_to_fixed(dceip->lines_interleaved_into_lb)), data->lines_interleaved_in_mem_access[i])), bw_int_to_fixed(data->bytes_per_pixel[i])), data->bytes_per_request[i]), data->useful_bytes_per_request[i]);
1183 data->active_time[i] = bw_div(bw_div(data->source_width_rounded_up_to_chunks[i], data->hsr[i]), data->pixel_rate[i]);
1184 }
1185 }
1186 for (i = 0; i <= 2; i++) {
1187 for (j = 0; j <= 7; j++) {
1188 data->dmif_burst_time[i][j] = bw_max3(data->dmif_total_page_close_open_time, bw_div(data->total_display_reads_required_dram_access_data, (bw_mul(bw_div(bw_mul(bw_mul(data->dram_efficiency, yclk[i]), bw_int_to_fixed(vbios->dram_channel_width_in_bits)), bw_int_to_fixed(8)), bw_int_to_fixed(data->number_of_dram_channels)))), bw_div(data->total_display_reads_required_data, (bw_mul(bw_mul(sclk[j], vbios->data_return_bus_width), bw_frc_to_fixed(dceip->percent_of_ideal_port_bw_received_after_urgent_latency, 100)))));
1189 if (data->d1_display_write_back_dwb_enable == 1) {
1190 data->mcifwr_burst_time[i][j] = bw_max3(data->mcifwr_total_page_close_open_time, bw_div(data->total_display_writes_required_dram_access_data, (bw_mul(bw_div(bw_mul(bw_mul(data->dram_efficiency, yclk[i]), bw_int_to_fixed(vbios->dram_channel_width_in_bits)), bw_int_to_fixed(8)), bw_int_to_fixed(data->number_of_dram_wrchannels)))), bw_div(data->total_display_writes_required_data, (bw_mul(sclk[j], vbios->data_return_bus_width))));
1191 }
1192 }
1193 }
1194 for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
1195 for (j = 0; j <= 2; j++) {
1196 for (k = 0; k <= 7; k++) {
1197 if (data->enable[i]) {
1198 if (surface_type[i] != bw_def_display_write_back420_luma && surface_type[i] != bw_def_display_write_back420_chroma) {
1199 /*time to transfer data from the dmif buffer to the lb. since the mc to dmif transfer time overlaps*/
1200 /*with the dmif to lb transfer time, only time to transfer the last chunk is considered.*/
1201 data->dmif_buffer_transfer_time[i] = bw_mul(data->source_width_rounded_up_to_chunks[i], (bw_div(dceip->lb_write_pixels_per_dispclk, (bw_div(vbios->low_voltage_max_dispclk, dceip->display_pipe_throughput_factor)))));
1202 data->line_source_transfer_time[i][j][k] = bw_max2(bw_mul((bw_add(data->total_dmifmc_urgent_latency, data->dmif_burst_time[j][k])), bw_floor2(bw_div(data->src_data_for_first_output_pixel[i], data->adjusted_data_buffer_size_in_memory[i]), bw_int_to_fixed(1))), bw_sub(bw_add(bw_mul((bw_add(data->total_dmifmc_urgent_latency, data->dmif_burst_time[j][k])), bw_floor2(bw_div(data->src_data_for_last_output_pixel[i], data->adjusted_data_buffer_size_in_memory[i]), bw_int_to_fixed(1))), data->dmif_buffer_transfer_time[i]), data->active_time[i]));
1203 /*during an mclk switch the requests from the dce ip are stored in the gmc/arb. these requests should be serviced immediately*/
1204 /*after the mclk switch sequence and not incur an urgent latency penalty. it is assumed that the gmc/arb can hold up to 256 requests*/
1205 /*per memory channel. if the dce ip is urgent after the mclk switch sequence, all pending requests and subsequent requests should be*/
1206 /*immediately serviced without a gap in the urgent requests.*/
1207 /*the latency incurred would be the time to issue the requests and return the data for the first or last output pixel.*/
1208 if (surface_type[i] == bw_def_graphics) {
1209 switch (data->lb_bpc[i]) {
1210 case 6:
1211 data->v_scaler_efficiency = dceip->graphics_vscaler_efficiency6_bit_per_component;
1212 break;
1213 case 8:
1214 data->v_scaler_efficiency = dceip->graphics_vscaler_efficiency8_bit_per_component;
1215 break;
1216 case 10:
1217 data->v_scaler_efficiency = dceip->graphics_vscaler_efficiency10_bit_per_component;
1218 break;
1219 default:
1220 data->v_scaler_efficiency = dceip->graphics_vscaler_efficiency12_bit_per_component;
1221 break;
1222 }
1223 if (data->use_alpha[i] == 1) {
1224 data->v_scaler_efficiency = bw_min2(data->v_scaler_efficiency, dceip->alpha_vscaler_efficiency);
1225 }
1226 }
1227 else {
1228 switch (data->lb_bpc[i]) {
1229 case 6:
1230 data->v_scaler_efficiency = dceip->underlay_vscaler_efficiency6_bit_per_component;
1231 break;
1232 case 8:
1233 data->v_scaler_efficiency = dceip->underlay_vscaler_efficiency8_bit_per_component;
1234 break;
1235 case 10:
1236 data->v_scaler_efficiency = dceip->underlay_vscaler_efficiency10_bit_per_component;
1237 break;
1238 default:
1239 data->v_scaler_efficiency = bw_int_to_fixed(3);
1240 break;
1241 }
1242 }
1243 if (dceip->pre_downscaler_enabled && bw_mtn(data->hsr[i], bw_int_to_fixed(1))) {
1244 data->scaler_limits_factor = bw_max2(bw_div(data->v_taps[i], data->v_scaler_efficiency), bw_div(data->source_width_rounded_up_to_chunks[i], data->h_total[i]));
1245 }
1246 else {
1247 data->scaler_limits_factor = bw_max3(bw_int_to_fixed(1), bw_ceil2(bw_div(data->h_taps[i], bw_int_to_fixed(4)), bw_int_to_fixed(1)), bw_mul(data->hsr[i], bw_max2(bw_div(data->v_taps[i], data->v_scaler_efficiency), bw_int_to_fixed(1))));
1248 }
1249 data->dram_speed_change_line_source_transfer_time[i][j][k] = bw_mul(bw_int_to_fixed(2), bw_max2((bw_add((bw_div(data->src_data_for_first_output_pixel[i], bw_min2(bw_mul(data->bytes_per_request[i], sclk[k]), bw_div(bw_mul(bw_mul(data->bytes_per_request[i], data->pixel_rate[i]), data->scaler_limits_factor), bw_int_to_fixed(2))))), (bw_mul(data->dmif_burst_time[j][k], bw_floor2(bw_div(data->src_data_for_first_output_pixel[i], data->adjusted_data_buffer_size_in_memory[i]), bw_int_to_fixed(1)))))), (bw_add((bw_div(data->src_data_for_last_output_pixel[i], bw_min2(bw_mul(data->bytes_per_request[i], sclk[k]), bw_div(bw_mul(bw_mul(data->bytes_per_request[i], data->pixel_rate[i]), data->scaler_limits_factor), bw_int_to_fixed(2))))), (bw_sub(bw_mul(data->dmif_burst_time[j][k], bw_floor2(bw_div(data->src_data_for_last_output_pixel[i], data->adjusted_data_buffer_size_in_memory[i]), bw_int_to_fixed(1))), data->active_time[i]))))));
1250 }
1251 else {
1252 data->line_source_transfer_time[i][j][k] = bw_max2(bw_mul((bw_add(vbios->mcifwrmc_urgent_latency, data->mcifwr_burst_time[j][k])), bw_floor2(bw_div(data->src_data_for_first_output_pixel[i], data->adjusted_data_buffer_size_in_memory[i]), bw_int_to_fixed(1))), bw_sub(bw_mul((bw_add(vbios->mcifwrmc_urgent_latency, data->mcifwr_burst_time[j][k])), bw_floor2(bw_div(data->src_data_for_last_output_pixel[i], data->adjusted_data_buffer_size_in_memory[i]), bw_int_to_fixed(1))), data->active_time[i]));
1253 /*during an mclk switch the requests from the dce ip are stored in the gmc/arb. these requests should be serviced immediately*/
1254 /*after the mclk switch sequence and not incur an urgent latency penalty. it is assumed that the gmc/arb can hold up to 256 requests*/
1255 /*per memory channel. if the dce ip is urgent after the mclk switch sequence, all pending requests and subsequent requests should be*/
1256 /*immediately serviced without a gap in the urgent requests.*/
1257 /*the latency incurred would be the time to issue the requests and return the data for the first or last output pixel.*/
1258 data->dram_speed_change_line_source_transfer_time[i][j][k] = bw_max2((bw_add((bw_div(data->src_data_for_first_output_pixel[i], bw_min2(bw_mul(data->bytes_per_request[i], sclk[k]), bw_div(bw_mul(data->bytes_per_request[i], vbios->low_voltage_max_dispclk), bw_int_to_fixed(2))))), (bw_mul(data->mcifwr_burst_time[j][k], bw_floor2(bw_div(data->src_data_for_first_output_pixel[i], data->adjusted_data_buffer_size_in_memory[i]), bw_int_to_fixed(1)))))), (bw_add((bw_div(data->src_data_for_last_output_pixel[i], bw_min2(bw_mul(data->bytes_per_request[i], sclk[k]), bw_div(bw_mul(data->bytes_per_request[i], vbios->low_voltage_max_dispclk), bw_int_to_fixed(2))))), (bw_sub(bw_mul(data->mcifwr_burst_time[j][k], bw_floor2(bw_div(data->src_data_for_last_output_pixel[i], data->adjusted_data_buffer_size_in_memory[i]), bw_int_to_fixed(1))), data->active_time[i])))));
1259 }
1260 }
1261 }
1262 }
1263 }
1264 /*cpu c-state and p-state change enable*/
1265 /*for cpu p-state change to be possible for a yclk(pclk) and sclk level the dispclk required has to be enough for the blackout duration*/
1266 /*for cpu c-state change to be possible for a yclk(pclk) and sclk level the dispclk required has to be enough for the blackout duration and recovery*/
1267 /*condition for the blackout duration:*/
1268 /* minimum latency hiding > blackout duration + dmif burst time + line source transfer time*/
1269 /*condition for the blackout recovery:*/
1270 /* recovery time > dmif burst time + 2 * urgent latency*/
1271 /* recovery time > (display bw * blackout duration + (2 * urgent latency + dmif burst time)*dispclk - dmif size )*/
1272 /* / (dispclk - display bw)*/
1273 /*the minimum latency hiding is the minimum for all pipes of one screen line time, plus one more line time if doing lb prefetch, plus the dmif data buffer size equivalent in time, minus the urgent latency.*/
1274 /*the minimum latency hiding is further limited by the cursor. the cursor latency hiding is the number of lines of the cursor buffer, minus one if the downscaling is less than two, or minus three if it is more*/
1275
1276 /*initialize variables*/
1277 number_of_displays_enabled = 0;
1278 number_of_displays_enabled_with_margin = 0;
1279 for (k = 0; k <= maximum_number_of_surfaces - 1; k++) {
1280 if (data->enable[k]) {
1281 number_of_displays_enabled = number_of_displays_enabled + 1;
1282 }
1283 data->display_pstate_change_enable[k] = 0;
1284 }
1285 for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
1286 if (data->enable[i]) {
1287 if ((bw_equ(dceip->stutter_and_dram_clock_state_change_gated_before_cursor, bw_int_to_fixed(0)) && bw_mtn(data->cursor_width_pixels[i], bw_int_to_fixed(0)))) {
1288 if (bw_ltn(data->vsr[i], bw_int_to_fixed(2))) {
1289 data->cursor_latency_hiding[i] = bw_div(bw_div(bw_mul((bw_sub(dceip->cursor_dcp_buffer_lines, bw_int_to_fixed(1))), data->h_total[i]), data->vsr[i]), data->pixel_rate[i]);
1290 }
1291 else {
1292 data->cursor_latency_hiding[i] = bw_div(bw_div(bw_mul((bw_sub(dceip->cursor_dcp_buffer_lines, bw_int_to_fixed(3))), data->h_total[i]), data->vsr[i]), data->pixel_rate[i]);
1293 }
1294 }
1295 else {
1296 data->cursor_latency_hiding[i] = bw_int_to_fixed(9999);
1297 }
1298 }
1299 }
1300 for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
1301 if (data->enable[i]) {
1302 if (dceip->graphics_lb_nodownscaling_multi_line_prefetching == 1 && (bw_equ(data->vsr[i], bw_int_to_fixed(1)) || (bw_leq(data->vsr[i], bw_frc_to_fixed(8, 10)) && bw_leq(data->v_taps[i], bw_int_to_fixed(2)) && data->lb_bpc[i] == 8)) && surface_type[i] == bw_def_graphics) {
1303 if (number_of_displays_enabled > 2)
1304 data->minimum_latency_hiding[i] = bw_sub(bw_div(bw_mul((bw_div((bw_add(bw_sub(data->lb_partitions[i], bw_int_to_fixed(2)), bw_div(bw_div(data->data_buffer_size[i], bw_int_to_fixed(data->bytes_per_pixel[i])), data->source_width_pixels[i]))), data->vsr[i])), data->h_total[i]), data->pixel_rate[i]), data->total_dmifmc_urgent_latency);
1305 else
1306 data->minimum_latency_hiding[i] = bw_sub(bw_div(bw_mul((bw_div((bw_add(bw_sub(data->lb_partitions[i], bw_int_to_fixed(1)), bw_div(bw_div(data->data_buffer_size[i], bw_int_to_fixed(data->bytes_per_pixel[i])), data->source_width_pixels[i]))), data->vsr[i])), data->h_total[i]), data->pixel_rate[i]), data->total_dmifmc_urgent_latency);
1307 }
1308 else {
1309 data->minimum_latency_hiding[i] = bw_sub(bw_div(bw_mul((bw_div((bw_add(bw_int_to_fixed(1 + data->line_buffer_prefetch[i]), bw_div(bw_div(data->data_buffer_size[i], bw_int_to_fixed(data->bytes_per_pixel[i])), data->source_width_pixels[i]))), data->vsr[i])), data->h_total[i]), data->pixel_rate[i]), data->total_dmifmc_urgent_latency);
1310 }
1311 data->minimum_latency_hiding_with_cursor[i] = bw_min2(data->minimum_latency_hiding[i], data->cursor_latency_hiding[i]);
1312 }
1313 }
1314 for (i = 0; i <= 2; i++) {
1315 for (j = 0; j <= 7; j++) {
1316 data->blackout_duration_margin[i][j] = bw_int_to_fixed(9999);
1317 data->dispclk_required_for_blackout_duration[i][j] = bw_int_to_fixed(0);
1318 data->dispclk_required_for_blackout_recovery[i][j] = bw_int_to_fixed(0);
1319 for (k = 0; k <= maximum_number_of_surfaces - 1; k++) {
1320 if (data->enable[k] && bw_mtn(vbios->blackout_duration, bw_int_to_fixed(0))) {
1321 if (surface_type[k] != bw_def_display_write_back420_luma && surface_type[k] != bw_def_display_write_back420_chroma) {
1322 data->blackout_duration_margin[i][j] = bw_min2(data->blackout_duration_margin[i][j], bw_sub(bw_sub(bw_sub(data->minimum_latency_hiding_with_cursor[k], vbios->blackout_duration), data->dmif_burst_time[i][j]), data->line_source_transfer_time[k][i][j]));
1323 data->dispclk_required_for_blackout_duration[i][j] = bw_max3(data->dispclk_required_for_blackout_duration[i][j], bw_div(bw_div(bw_mul(data->src_pixels_for_first_output_pixel[k], dceip->display_pipe_throughput_factor), dceip->lb_write_pixels_per_dispclk), (bw_sub(bw_sub(data->minimum_latency_hiding_with_cursor[k], vbios->blackout_duration), data->dmif_burst_time[i][j]))), bw_div(bw_div(bw_mul(data->src_pixels_for_last_output_pixel[k], dceip->display_pipe_throughput_factor), dceip->lb_write_pixels_per_dispclk), (bw_add(bw_sub(bw_sub(data->minimum_latency_hiding_with_cursor[k], vbios->blackout_duration), data->dmif_burst_time[i][j]), data->active_time[k]))));
1324 if (bw_leq(vbios->maximum_blackout_recovery_time, bw_add(bw_mul(bw_int_to_fixed(2), data->total_dmifmc_urgent_latency), data->dmif_burst_time[i][j]))) {
1325 data->dispclk_required_for_blackout_recovery[i][j] = bw_int_to_fixed(9999);
1326 }
1327 else if (bw_ltn(data->adjusted_data_buffer_size[k], bw_mul(bw_div(bw_mul(data->display_bandwidth[k], data->useful_bytes_per_request[k]), data->bytes_per_request[k]), (bw_add(vbios->blackout_duration, bw_add(bw_mul(bw_int_to_fixed(2), data->total_dmifmc_urgent_latency), data->dmif_burst_time[i][j])))))) {
1328 data->dispclk_required_for_blackout_recovery[i][j] = bw_max2(data->dispclk_required_for_blackout_recovery[i][j], bw_div(bw_mul(bw_div(bw_div((bw_sub(bw_mul(bw_div(bw_mul(data->display_bandwidth[k], data->useful_bytes_per_request[k]), data->bytes_per_request[k]), (bw_add(vbios->blackout_duration, vbios->maximum_blackout_recovery_time))), data->adjusted_data_buffer_size[k])), bw_int_to_fixed(data->bytes_per_pixel[k])), (bw_sub(vbios->maximum_blackout_recovery_time, bw_sub(bw_mul(bw_int_to_fixed(2), data->total_dmifmc_urgent_latency), data->dmif_burst_time[i][j])))), data->latency_hiding_lines[k]), data->lines_interleaved_in_mem_access[k]));
1329 }
1330 }
1331 else {
1332 data->blackout_duration_margin[i][j] = bw_min2(data->blackout_duration_margin[i][j], bw_sub(bw_sub(bw_sub(bw_sub(data->minimum_latency_hiding_with_cursor[k], vbios->blackout_duration), data->dmif_burst_time[i][j]), data->mcifwr_burst_time[i][j]), data->line_source_transfer_time[k][i][j]));
1333 data->dispclk_required_for_blackout_duration[i][j] = bw_max3(data->dispclk_required_for_blackout_duration[i][j], bw_div(bw_div(bw_mul(data->src_pixels_for_first_output_pixel[k], dceip->display_pipe_throughput_factor), dceip->lb_write_pixels_per_dispclk), (bw_sub(bw_sub(bw_sub(data->minimum_latency_hiding_with_cursor[k], vbios->blackout_duration), data->dmif_burst_time[i][j]), data->mcifwr_burst_time[i][j]))), bw_div(bw_div(bw_mul(data->src_pixels_for_last_output_pixel[k], dceip->display_pipe_throughput_factor), dceip->lb_write_pixels_per_dispclk), (bw_add(bw_sub(bw_sub(bw_sub(data->minimum_latency_hiding_with_cursor[k], vbios->blackout_duration), data->dmif_burst_time[i][j]), data->mcifwr_burst_time[i][j]), data->active_time[k]))));
1334 if (bw_ltn(vbios->maximum_blackout_recovery_time, bw_add(bw_add(bw_mul(bw_int_to_fixed(2), vbios->mcifwrmc_urgent_latency), data->dmif_burst_time[i][j]), data->mcifwr_burst_time[i][j]))) {
1335 data->dispclk_required_for_blackout_recovery[i][j] = bw_int_to_fixed(9999);
1336 }
1337 else if (bw_ltn(data->adjusted_data_buffer_size[k], bw_mul(bw_div(bw_mul(data->display_bandwidth[k], data->useful_bytes_per_request[k]), data->bytes_per_request[k]), (bw_add(vbios->blackout_duration, bw_add(bw_mul(bw_int_to_fixed(2), data->total_dmifmc_urgent_latency), data->dmif_burst_time[i][j])))))) {
1338 data->dispclk_required_for_blackout_recovery[i][j] = bw_max2(data->dispclk_required_for_blackout_recovery[i][j], bw_div(bw_mul(bw_div(bw_div((bw_sub(bw_mul(bw_div(bw_mul(data->display_bandwidth[k], data->useful_bytes_per_request[k]), data->bytes_per_request[k]), (bw_add(vbios->blackout_duration, vbios->maximum_blackout_recovery_time))), data->adjusted_data_buffer_size[k])), bw_int_to_fixed(data->bytes_per_pixel[k])), (bw_sub(vbios->maximum_blackout_recovery_time, (bw_add(bw_mul(bw_int_to_fixed(2), data->total_dmifmc_urgent_latency), data->dmif_burst_time[i][j]))))), data->latency_hiding_lines[k]), data->lines_interleaved_in_mem_access[k]));
1339 }
1340 }
1341 }
1342 }
1343 }
1344 }
1345 if (bw_mtn(data->blackout_duration_margin[high][s_high], bw_int_to_fixed(0)) && bw_ltn(data->dispclk_required_for_blackout_duration[high][s_high], vbios->high_voltage_max_dispclk)) {
1346 data->cpup_state_change_enable = bw_def_yes;
1347 if (bw_ltn(data->dispclk_required_for_blackout_recovery[high][s_high], vbios->high_voltage_max_dispclk)) {
1348 data->cpuc_state_change_enable = bw_def_yes;
1349 }
1350 else {
1351 data->cpuc_state_change_enable = bw_def_no;
1352 }
1353 }
1354 else {
1355 data->cpup_state_change_enable = bw_def_no;
1356 data->cpuc_state_change_enable = bw_def_no;
1357 }
1358 /*nb p-state change enable*/
1359 /*for dram speed/p-state change to be possible for a yclk(pclk) and sclk level there has to be positive margin and the dispclk required has to be*/
1360 /*below the maximum.*/
1361 /*the dram speed/p-state change margin is the minimum for all surfaces of the maximum latency hiding minus the dram speed/p-state change latency,*/
1362 /*minus the dmif burst time, minus the source line transfer time*/
1363 /*the maximum latency hiding is the minimum latency hiding plus one source line used for de-tiling in the line buffer, plus half the urgent latency*/
1364 /*if stutter and dram clock state change are gated before cursor then the cursor latency hiding does not limit stutter or dram clock state change*/
1365 for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
1366 if (data->enable[i]) {
1367 if (dceip->graphics_lb_nodownscaling_multi_line_prefetching == 1) {
1368 data->maximum_latency_hiding[i] = bw_add(data->minimum_latency_hiding[i], bw_mul(bw_frc_to_fixed(5, 10), data->total_dmifmc_urgent_latency));
1369 }
1370 else {
1371 /*maximum_latency_hiding(i) = minimum_latency_hiding(i) + 1 / vsr(i) * h_total(i) / pixel_rate(i) + 0.5 * total_dmifmc_urgent_latency*/
1372 data->maximum_latency_hiding[i] = bw_add(data->minimum_latency_hiding[i], bw_mul(bw_frc_to_fixed(5, 10), data->total_dmifmc_urgent_latency));
1373 }
1374 data->maximum_latency_hiding_with_cursor[i] = bw_min2(data->maximum_latency_hiding[i], data->cursor_latency_hiding[i]);
1375 }
1376 }
1377 for (i = 0; i <= 2; i++) {
1378 for (j = 0; j <= 7; j++) {
1379 data->min_dram_speed_change_margin[i][j] = bw_int_to_fixed(9999);
1380 data->dram_speed_change_margin = bw_int_to_fixed(9999);
1381 data->dispclk_required_for_dram_speed_change[i][j] = bw_int_to_fixed(0);
1382 data->num_displays_with_margin[i][j] = 0;
1383 for (k = 0; k <= maximum_number_of_surfaces - 1; k++) {
1384 if (data->enable[k]) {
1385 if (surface_type[k] != bw_def_display_write_back420_luma && surface_type[k] != bw_def_display_write_back420_chroma) {
1386 data->dram_speed_change_margin = bw_sub(bw_sub(bw_sub(data->maximum_latency_hiding_with_cursor[k], vbios->nbp_state_change_latency), data->dmif_burst_time[i][j]), data->dram_speed_change_line_source_transfer_time[k][i][j]);
1387 if ((bw_mtn(data->dram_speed_change_margin, bw_int_to_fixed(0)) && bw_ltn(data->dram_speed_change_margin, bw_int_to_fixed(9999)))) {
1388 /*determine the minimum dram clock change margin for each set of clock frequencies*/
1389 data->min_dram_speed_change_margin[i][j] = bw_min2(data->min_dram_speed_change_margin[i][j], data->dram_speed_change_margin);
1390 /*compute the maximum clock frequuency required for the dram clock change at each set of clock frequencies*/
1391 data->dispclk_required_for_dram_speed_change_pipe[i][j] = bw_max2(bw_div(bw_div(bw_mul(data->src_pixels_for_first_output_pixel[k], dceip->display_pipe_throughput_factor), dceip->lb_write_pixels_per_dispclk), (bw_sub(bw_sub(bw_sub(data->maximum_latency_hiding_with_cursor[k], vbios->nbp_state_change_latency), data->dmif_burst_time[i][j]), data->dram_speed_change_line_source_transfer_time[k][i][j]))), bw_div(bw_div(bw_mul(data->src_pixels_for_last_output_pixel[k], dceip->display_pipe_throughput_factor), dceip->lb_write_pixels_per_dispclk), (bw_add(bw_sub(bw_sub(bw_sub(data->maximum_latency_hiding_with_cursor[k], vbios->nbp_state_change_latency), data->dmif_burst_time[i][j]), data->dram_speed_change_line_source_transfer_time[k][i][j]), data->active_time[k]))));
1392 if ((bw_ltn(data->dispclk_required_for_dram_speed_change_pipe[i][j], vbios->high_voltage_max_dispclk))) {
1393 data->display_pstate_change_enable[k] = 1;
1394 data->num_displays_with_margin[i][j] = data->num_displays_with_margin[i][j] + 1;
1395 data->dispclk_required_for_dram_speed_change[i][j] = bw_max2(data->dispclk_required_for_dram_speed_change[i][j], data->dispclk_required_for_dram_speed_change_pipe[i][j]);
1396 }
1397 }
1398 }
1399 else {
1400 data->dram_speed_change_margin = bw_sub(bw_sub(bw_sub(bw_sub(data->maximum_latency_hiding_with_cursor[k], vbios->nbp_state_change_latency), data->dmif_burst_time[i][j]), data->mcifwr_burst_time[i][j]), data->dram_speed_change_line_source_transfer_time[k][i][j]);
1401 if ((bw_mtn(data->dram_speed_change_margin, bw_int_to_fixed(0)) && bw_ltn(data->dram_speed_change_margin, bw_int_to_fixed(9999)))) {
1402 /*determine the minimum dram clock change margin for each display pipe*/
1403 data->min_dram_speed_change_margin[i][j] = bw_min2(data->min_dram_speed_change_margin[i][j], data->dram_speed_change_margin);
1404 /*compute the maximum clock frequuency required for the dram clock change at each set of clock frequencies*/
1405 data->dispclk_required_for_dram_speed_change_pipe[i][j] = bw_max2(bw_div(bw_div(bw_mul(data->src_pixels_for_first_output_pixel[k], dceip->display_pipe_throughput_factor), dceip->lb_write_pixels_per_dispclk), (bw_sub(bw_sub(bw_sub(bw_sub(data->maximum_latency_hiding_with_cursor[k], vbios->nbp_state_change_latency), data->dmif_burst_time[i][j]), data->dram_speed_change_line_source_transfer_time[k][i][j]), data->mcifwr_burst_time[i][j]))), bw_div(bw_div(bw_mul(data->src_pixels_for_last_output_pixel[k], dceip->display_pipe_throughput_factor), dceip->lb_write_pixels_per_dispclk), (bw_add(bw_sub(bw_sub(bw_sub(bw_sub(data->maximum_latency_hiding_with_cursor[k], vbios->nbp_state_change_latency), data->dmif_burst_time[i][j]), data->dram_speed_change_line_source_transfer_time[k][i][j]), data->mcifwr_burst_time[i][j]), data->active_time[k]))));
1406 if ((bw_ltn(data->dispclk_required_for_dram_speed_change_pipe[i][j], vbios->high_voltage_max_dispclk))) {
1407 data->display_pstate_change_enable[k] = 1;
1408 data->num_displays_with_margin[i][j] = data->num_displays_with_margin[i][j] + 1;
1409 data->dispclk_required_for_dram_speed_change[i][j] = bw_max2(data->dispclk_required_for_dram_speed_change[i][j], data->dispclk_required_for_dram_speed_change_pipe[i][j]);
1410 }
1411 }
1412 }
1413 }
1414 }
1415 }
1416 }
1417 /*determine the number of displays with margin to switch in the v_active region*/
1418 for (k = 0; k <= maximum_number_of_surfaces - 1; k++) {
1419 if (data->enable[k] == 1 && data->display_pstate_change_enable[k] == 1) {
1420 number_of_displays_enabled_with_margin = number_of_displays_enabled_with_margin + 1;
1421 }
1422 }
1423 /*determine the number of displays that don't have any dram clock change margin, but*/
1424 /*have the same resolution. these displays can switch in a common vblank region if*/
1425 /*their frames are aligned.*/
1426 data->min_vblank_dram_speed_change_margin = bw_int_to_fixed(9999);
1427 for (k = 0; k <= maximum_number_of_surfaces - 1; k++) {
1428 if (data->enable[k]) {
1429 if (surface_type[k] != bw_def_display_write_back420_luma && surface_type[k] != bw_def_display_write_back420_chroma) {
1430 data->v_blank_dram_speed_change_margin[k] = bw_sub(bw_sub(bw_sub(bw_div(bw_mul((bw_sub(data->v_total[k], bw_sub(bw_div(data->src_height[k], data->v_scale_ratio[k]), bw_int_to_fixed(4)))), data->h_total[k]), data->pixel_rate[k]), vbios->nbp_state_change_latency), data->dmif_burst_time[low][s_low]), data->dram_speed_change_line_source_transfer_time[k][low][s_low]);
1431 data->min_vblank_dram_speed_change_margin = bw_min2(data->min_vblank_dram_speed_change_margin, data->v_blank_dram_speed_change_margin[k]);
1432 }
1433 else {
1434 data->v_blank_dram_speed_change_margin[k] = bw_sub(bw_sub(bw_sub(bw_sub(bw_div(bw_mul((bw_sub(data->v_total[k], bw_sub(bw_div(data->src_height[k], data->v_scale_ratio[k]), bw_int_to_fixed(4)))), data->h_total[k]), data->pixel_rate[k]), vbios->nbp_state_change_latency), data->dmif_burst_time[low][s_low]), data->mcifwr_burst_time[low][s_low]), data->dram_speed_change_line_source_transfer_time[k][low][s_low]);
1435 data->min_vblank_dram_speed_change_margin = bw_min2(data->min_vblank_dram_speed_change_margin, data->v_blank_dram_speed_change_margin[k]);
1436 }
1437 }
1438 }
1439 for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
1440 data->displays_with_same_mode[i] = bw_int_to_fixed(0);
1441 if (data->enable[i] == 1 && data->display_pstate_change_enable[i] == 0 && bw_mtn(data->v_blank_dram_speed_change_margin[i], bw_int_to_fixed(0))) {
1442 for (j = 0; j <= maximum_number_of_surfaces - 1; j++) {
1443 if ((i == j || data->display_synchronization_enabled) && (data->enable[j] == 1 && bw_equ(data->source_width_rounded_up_to_chunks[i], data->source_width_rounded_up_to_chunks[j]) && bw_equ(data->source_height_rounded_up_to_chunks[i], data->source_height_rounded_up_to_chunks[j]) && bw_equ(data->vsr[i], data->vsr[j]) && bw_equ(data->hsr[i], data->hsr[j]) && bw_equ(data->pixel_rate[i], data->pixel_rate[j]))) {
1444 data->displays_with_same_mode[i] = bw_add(data->displays_with_same_mode[i], bw_int_to_fixed(1));
1445 }
1446 }
1447 }
1448 }
1449 /*compute the maximum number of aligned displays with no margin*/
1450 number_of_aligned_displays_with_no_margin = 0;
1451 for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
1452 number_of_aligned_displays_with_no_margin = bw_fixed_to_int(bw_max2(bw_int_to_fixed(number_of_aligned_displays_with_no_margin), data->displays_with_same_mode[i]));
1453 }
1454 /*dram clock change is possible, if all displays have positive margin except for one display or a group of*/
1455 /*aligned displays with the same timing.*/
1456 /*the display(s) with the negative margin can be switched in the v_blank region while the other*/
1457 /*displays are in v_blank or v_active.*/
1458 if (number_of_displays_enabled_with_margin > 0 && (number_of_displays_enabled_with_margin + number_of_aligned_displays_with_no_margin) == number_of_displays_enabled && bw_mtn(data->min_dram_speed_change_margin[high][s_high], bw_int_to_fixed(0)) && bw_ltn(data->min_dram_speed_change_margin[high][s_high], bw_int_to_fixed(9999)) && bw_ltn(data->dispclk_required_for_dram_speed_change[high][s_high], vbios->high_voltage_max_dispclk)) {
1459 data->nbp_state_change_enable = bw_def_yes;
1460 }
1461 else {
1462 data->nbp_state_change_enable = bw_def_no;
1463 }
1464 /*dram clock change is possible only in vblank if all displays are aligned and have no margin*/
1465 if (number_of_aligned_displays_with_no_margin == number_of_displays_enabled) {
1466 nbp_state_change_enable_blank = bw_def_yes;
1467 }
1468 else {
1469 nbp_state_change_enable_blank = bw_def_no;
1470 }
1471
1472 /*average bandwidth*/
1473 /*the average bandwidth with no compression is the vertical active time is the source width times the bytes per pixel divided by the line time, multiplied by the vertical scale ratio and the ratio of bytes per request divided by the useful bytes per request.*/
1474 /*the average bandwidth with compression is the same, divided by the compression ratio*/
1475 for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
1476 if (data->enable[i]) {
1477 data->average_bandwidth_no_compression[i] = bw_div(bw_mul(bw_mul(bw_div(bw_mul(data->source_width_rounded_up_to_chunks[i], bw_int_to_fixed(data->bytes_per_pixel[i])), (bw_div(data->h_total[i], data->pixel_rate[i]))), data->vsr[i]), data->bytes_per_request[i]), data->useful_bytes_per_request[i]);
1478 data->average_bandwidth[i] = bw_div(data->average_bandwidth_no_compression[i], data->compression_rate[i]);
1479 }
1480 }
1481 data->total_average_bandwidth_no_compression = bw_int_to_fixed(0);
1482 data->total_average_bandwidth = bw_int_to_fixed(0);
1483 for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
1484 if (data->enable[i]) {
1485 data->total_average_bandwidth_no_compression = bw_add(data->total_average_bandwidth_no_compression, data->average_bandwidth_no_compression[i]);
1486 data->total_average_bandwidth = bw_add(data->total_average_bandwidth, data->average_bandwidth[i]);
1487 }
1488 }
1489
1490 /*required yclk(pclk)*/
1491 /*yclk requirement only makes sense if the dmif and mcifwr data total page close-open time is less than the time for data transfer and the total pte requests fit in the scatter-gather saw queque size*/
1492 /*if that is the case, the yclk requirement is the maximum of the ones required by dmif and mcifwr, and the high/low yclk(pclk) is chosen accordingly*/
1493 /*high yclk(pclk) has to be selected when dram speed/p-state change is not possible.*/
1494 data->min_cursor_memory_interface_buffer_size_in_time = bw_int_to_fixed(9999);
1495 /* number of cursor lines stored in the cursor data return buffer*/
1496 num_cursor_lines = 0;
1497 for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
1498 if (data->enable[i]) {
1499 if (bw_mtn(data->cursor_width_pixels[i], bw_int_to_fixed(0))) {
1500 /*compute number of cursor lines stored in data return buffer*/
1501 if (bw_leq(data->cursor_width_pixels[i], bw_int_to_fixed(64)) && dceip->large_cursor == 1) {
1502 num_cursor_lines = 4;
1503 }
1504 else {
1505 num_cursor_lines = 2;
1506 }
1507 data->min_cursor_memory_interface_buffer_size_in_time = bw_min2(data->min_cursor_memory_interface_buffer_size_in_time, bw_div(bw_mul(bw_div(bw_int_to_fixed(num_cursor_lines), data->vsr[i]), data->h_total[i]), data->pixel_rate[i]));
1508 }
1509 }
1510 }
1511 /*compute minimum time to read one chunk from the dmif buffer*/
1512 if (number_of_displays_enabled > 2) {
1513 data->chunk_request_delay = 0;
1514 }
1515 else {
1516 data->chunk_request_delay = bw_fixed_to_int(bw_div(bw_int_to_fixed(512), vbios->high_voltage_max_dispclk));
1517 }
1518 data->min_read_buffer_size_in_time = bw_min2(data->min_cursor_memory_interface_buffer_size_in_time, data->min_dmif_size_in_time);
1519 data->display_reads_time_for_data_transfer = bw_sub(bw_sub(data->min_read_buffer_size_in_time, data->total_dmifmc_urgent_latency), bw_int_to_fixed(data->chunk_request_delay));
1520 data->display_writes_time_for_data_transfer = bw_sub(data->min_mcifwr_size_in_time, vbios->mcifwrmc_urgent_latency);
1521 data->dmif_required_dram_bandwidth = bw_div(data->total_display_reads_required_dram_access_data, data->display_reads_time_for_data_transfer);
1522 data->mcifwr_required_dram_bandwidth = bw_div(data->total_display_writes_required_dram_access_data, data->display_writes_time_for_data_transfer);
1523 data->required_dmifmc_urgent_latency_for_page_close_open = bw_div((bw_sub(data->min_read_buffer_size_in_time, data->dmif_total_page_close_open_time)), data->total_dmifmc_urgent_trips);
1524 data->required_mcifmcwr_urgent_latency = bw_sub(data->min_mcifwr_size_in_time, data->mcifwr_total_page_close_open_time);
1525 if (bw_mtn(data->scatter_gather_total_pte_requests, dceip->maximum_total_outstanding_pte_requests_allowed_by_saw)) {
1526 data->required_dram_bandwidth_gbyte_per_second = bw_int_to_fixed(9999);
1527 yclk_message = bw_def_exceeded_allowed_outstanding_pte_req_queue_size;
1528 data->y_clk_level = high;
1529 data->dram_bandwidth = bw_mul(bw_div(bw_mul(bw_mul(data->dram_efficiency, yclk[high]), bw_int_to_fixed(vbios->dram_channel_width_in_bits)), bw_int_to_fixed(8)), bw_int_to_fixed(data->number_of_dram_channels));
1530 }
1531 else if (bw_mtn(vbios->dmifmc_urgent_latency, data->required_dmifmc_urgent_latency_for_page_close_open) || bw_mtn(vbios->mcifwrmc_urgent_latency, data->required_mcifmcwr_urgent_latency)) {
1532 data->required_dram_bandwidth_gbyte_per_second = bw_int_to_fixed(9999);
1533 yclk_message = bw_def_exceeded_allowed_page_close_open;
1534 data->y_clk_level = high;
1535 data->dram_bandwidth = bw_mul(bw_div(bw_mul(bw_mul(data->dram_efficiency, yclk[high]), bw_int_to_fixed(vbios->dram_channel_width_in_bits)), bw_int_to_fixed(8)), bw_int_to_fixed(data->number_of_dram_channels));
1536 }
1537 else {
1538 data->required_dram_bandwidth_gbyte_per_second = bw_div(bw_max2(data->dmif_required_dram_bandwidth, data->mcifwr_required_dram_bandwidth), bw_int_to_fixed(1000));
1539 if (bw_ltn(data->total_average_bandwidth_no_compression, bw_mul(bw_mul(bw_mul(bw_frc_to_fixed(dceip->max_average_percent_of_ideal_drambw_display_can_use_in_normal_system_operation, 100),yclk[low]),bw_div(bw_int_to_fixed(vbios->dram_channel_width_in_bits),bw_int_to_fixed(8))),bw_int_to_fixed(vbios->number_of_dram_channels)))
1540 && bw_ltn(bw_mul(data->required_dram_bandwidth_gbyte_per_second, bw_int_to_fixed(1000)), bw_mul(bw_div(bw_mul(bw_mul(data->dram_efficiency, yclk[low]), bw_int_to_fixed(vbios->dram_channel_width_in_bits)), bw_int_to_fixed(8)), bw_int_to_fixed(data->number_of_dram_channels))) && (data->cpup_state_change_enable == bw_def_no || (bw_mtn(data->blackout_duration_margin[low][s_high], bw_int_to_fixed(0)) && bw_ltn(data->dispclk_required_for_blackout_duration[low][s_high], vbios->high_voltage_max_dispclk))) && (data->cpuc_state_change_enable == bw_def_no || (bw_mtn(data->blackout_duration_margin[low][s_high], bw_int_to_fixed(0)) && bw_ltn(data->dispclk_required_for_blackout_duration[low][s_high], vbios->high_voltage_max_dispclk) && bw_ltn(data->dispclk_required_for_blackout_recovery[low][s_high], vbios->high_voltage_max_dispclk))) && (!data->increase_voltage_to_support_mclk_switch || data->nbp_state_change_enable == bw_def_no || (bw_mtn(data->min_dram_speed_change_margin[low][s_high], bw_int_to_fixed(0)) && bw_ltn(data->min_dram_speed_change_margin[low][s_high], bw_int_to_fixed(9999)) && bw_leq(data->dispclk_required_for_dram_speed_change[low][s_high], vbios->high_voltage_max_dispclk) && data->num_displays_with_margin[low][s_high] == number_of_displays_enabled_with_margin))) {
1541 yclk_message = bw_fixed_to_int(vbios->low_yclk);
1542 data->y_clk_level = low;
1543 data->dram_bandwidth = bw_mul(bw_div(bw_mul(bw_mul(data->dram_efficiency, yclk[low]), bw_int_to_fixed(vbios->dram_channel_width_in_bits)), bw_int_to_fixed(8)), bw_int_to_fixed(data->number_of_dram_channels));
1544 }
1545 else if (bw_ltn(data->total_average_bandwidth_no_compression, bw_mul(bw_mul(bw_mul(bw_frc_to_fixed(dceip->max_average_percent_of_ideal_drambw_display_can_use_in_normal_system_operation, 100),yclk[mid]),bw_div(bw_int_to_fixed(vbios->dram_channel_width_in_bits),bw_int_to_fixed(8))),bw_int_to_fixed(vbios->number_of_dram_channels)))
1546 && bw_ltn(bw_mul(data->required_dram_bandwidth_gbyte_per_second, bw_int_to_fixed(1000)), bw_mul(bw_div(bw_mul(bw_mul(data->dram_efficiency, yclk[mid]), bw_int_to_fixed(vbios->dram_channel_width_in_bits)), bw_int_to_fixed(8)), bw_int_to_fixed(data->number_of_dram_channels))) && (data->cpup_state_change_enable == bw_def_no || (bw_mtn(data->blackout_duration_margin[mid][s_high], bw_int_to_fixed(0)) && bw_ltn(data->dispclk_required_for_blackout_duration[mid][s_high], vbios->high_voltage_max_dispclk))) && (data->cpuc_state_change_enable == bw_def_no || (bw_mtn(data->blackout_duration_margin[mid][s_high], bw_int_to_fixed(0)) && bw_ltn(data->dispclk_required_for_blackout_duration[mid][s_high], vbios->high_voltage_max_dispclk) && bw_ltn(data->dispclk_required_for_blackout_recovery[mid][s_high], vbios->high_voltage_max_dispclk))) && (!data->increase_voltage_to_support_mclk_switch || data->nbp_state_change_enable == bw_def_no || (bw_mtn(data->min_dram_speed_change_margin[mid][s_high], bw_int_to_fixed(0)) && bw_ltn(data->min_dram_speed_change_margin[mid][s_high], bw_int_to_fixed(9999)) && bw_leq(data->dispclk_required_for_dram_speed_change[mid][s_high], vbios->high_voltage_max_dispclk) && data->num_displays_with_margin[mid][s_high] == number_of_displays_enabled_with_margin))) {
1547 yclk_message = bw_fixed_to_int(vbios->mid_yclk);
1548 data->y_clk_level = mid;
1549 data->dram_bandwidth = bw_mul(bw_div(bw_mul(bw_mul(data->dram_efficiency, yclk[mid]), bw_int_to_fixed(vbios->dram_channel_width_in_bits)), bw_int_to_fixed(8)), bw_int_to_fixed(data->number_of_dram_channels));
1550 }
1551 else if (bw_ltn(data->total_average_bandwidth_no_compression, bw_mul(bw_mul(bw_mul(bw_frc_to_fixed(dceip->max_average_percent_of_ideal_drambw_display_can_use_in_normal_system_operation, 100),yclk[high]),bw_div(bw_int_to_fixed(vbios->dram_channel_width_in_bits),bw_int_to_fixed(8))),bw_int_to_fixed(vbios->number_of_dram_channels)))
1552 && bw_ltn(bw_mul(data->required_dram_bandwidth_gbyte_per_second, bw_int_to_fixed(1000)), bw_mul(bw_div(bw_mul(bw_mul(data->dram_efficiency, yclk[high]), bw_int_to_fixed(vbios->dram_channel_width_in_bits)), bw_int_to_fixed(8)), bw_int_to_fixed(data->number_of_dram_channels)))) {
1553 yclk_message = bw_fixed_to_int(vbios->high_yclk);
1554 data->y_clk_level = high;
1555 data->dram_bandwidth = bw_mul(bw_div(bw_mul(bw_mul(data->dram_efficiency, yclk[high]), bw_int_to_fixed(vbios->dram_channel_width_in_bits)), bw_int_to_fixed(8)), bw_int_to_fixed(data->number_of_dram_channels));
1556 }
1557 else {
1558 yclk_message = bw_def_exceeded_allowed_maximum_bw;
1559 data->y_clk_level = high;
1560 data->dram_bandwidth = bw_mul(bw_div(bw_mul(bw_mul(data->dram_efficiency, yclk[high]), bw_int_to_fixed(vbios->dram_channel_width_in_bits)), bw_int_to_fixed(8)), bw_int_to_fixed(data->number_of_dram_channels));
1561 }
1562 }
1563 /*required sclk*/
1564 /*sclk requirement only makes sense if the total pte requests fit in the scatter-gather saw queque size*/
1565 /*if that is the case, the sclk requirement is the maximum of the ones required by dmif and mcifwr, and the high/mid/low sclk is chosen accordingly, unless that choice results in foresaking dram speed/nb p-state change.*/
1566 /*the dmif and mcifwr sclk required is the one that allows the transfer of all pipe's data buffer size through the sclk bus in the time for data transfer*/
1567 /*for dmif, pte and cursor requests have to be included.*/
1568 data->dmif_required_sclk = bw_div(bw_div(data->total_display_reads_required_data, data->display_reads_time_for_data_transfer), (bw_mul(vbios->data_return_bus_width, bw_frc_to_fixed(dceip->percent_of_ideal_port_bw_received_after_urgent_latency, 100))));
1569 data->mcifwr_required_sclk = bw_div(bw_div(data->total_display_writes_required_data, data->display_writes_time_for_data_transfer), vbios->data_return_bus_width);
1570 if (bw_mtn(data->scatter_gather_total_pte_requests, dceip->maximum_total_outstanding_pte_requests_allowed_by_saw)) {
1571 data->required_sclk = bw_int_to_fixed(9999);
1572 sclk_message = bw_def_exceeded_allowed_outstanding_pte_req_queue_size;
1573 data->sclk_level = s_high;
1574 }
1575 else if (bw_mtn(vbios->dmifmc_urgent_latency, data->required_dmifmc_urgent_latency_for_page_close_open) || bw_mtn(vbios->mcifwrmc_urgent_latency, data->required_mcifmcwr_urgent_latency)) {
1576 data->required_sclk = bw_int_to_fixed(9999);
1577 sclk_message = bw_def_exceeded_allowed_page_close_open;
1578 data->sclk_level = s_high;
1579 }
1580 else {
1581 data->required_sclk = bw_max2(data->dmif_required_sclk, data->mcifwr_required_sclk);
1582 if (bw_ltn(data->total_average_bandwidth_no_compression, bw_mul(bw_mul(bw_frc_to_fixed(dceip->max_average_percent_of_ideal_port_bw_display_can_use_in_normal_system_operation, 100),sclk[low]),vbios->data_return_bus_width))
1583 && bw_ltn(data->required_sclk, sclk[s_low]) && (data->cpup_state_change_enable == bw_def_no || (bw_mtn(data->blackout_duration_margin[data->y_clk_level][s_low], bw_int_to_fixed(0)) && bw_ltn(data->dispclk_required_for_blackout_duration[data->y_clk_level][s_low], vbios->high_voltage_max_dispclk))) && (data->cpuc_state_change_enable == bw_def_no || (bw_mtn(data->blackout_duration_margin[data->y_clk_level][s_low], bw_int_to_fixed(0)) && bw_ltn(data->dispclk_required_for_blackout_duration[data->y_clk_level][s_low], vbios->high_voltage_max_dispclk) && bw_ltn(data->dispclk_required_for_blackout_recovery[data->y_clk_level][s_low], vbios->high_voltage_max_dispclk))) && (!data->increase_voltage_to_support_mclk_switch || data->nbp_state_change_enable == bw_def_no || (bw_mtn(data->min_dram_speed_change_margin[data->y_clk_level][s_low], bw_int_to_fixed(0)) && bw_ltn(data->min_dram_speed_change_margin[data->y_clk_level][s_low], bw_int_to_fixed(9999)) && bw_leq(data->dispclk_required_for_dram_speed_change[data->y_clk_level][s_low], vbios->low_voltage_max_dispclk) && data->num_displays_with_margin[data->y_clk_level][s_low] == number_of_displays_enabled_with_margin))) {
1584 sclk_message = bw_def_low;
1585 data->sclk_level = s_low;
1586 data->required_sclk = vbios->low_sclk;
1587 }
1588 else if (bw_ltn(data->total_average_bandwidth_no_compression, bw_mul(bw_mul(bw_frc_to_fixed(dceip->max_average_percent_of_ideal_port_bw_display_can_use_in_normal_system_operation, 100),sclk[mid]),vbios->data_return_bus_width))
1589 && bw_ltn(data->required_sclk, sclk[s_mid1]) && (data->cpup_state_change_enable == bw_def_no || (bw_mtn(data->blackout_duration_margin[data->y_clk_level][s_mid1], bw_int_to_fixed(0)) && bw_ltn(data->dispclk_required_for_blackout_duration[data->y_clk_level][s_mid1], vbios->high_voltage_max_dispclk))) && (data->cpuc_state_change_enable == bw_def_no || (bw_mtn(data->blackout_duration_margin[data->y_clk_level][s_mid1], bw_int_to_fixed(0)) && bw_ltn(data->dispclk_required_for_blackout_duration[data->y_clk_level][s_mid1], vbios->high_voltage_max_dispclk) && bw_ltn(data->dispclk_required_for_blackout_recovery[data->y_clk_level][s_mid1], vbios->high_voltage_max_dispclk))) && (!data->increase_voltage_to_support_mclk_switch || data->nbp_state_change_enable == bw_def_no || (bw_mtn(data->min_dram_speed_change_margin[data->y_clk_level][s_mid1], bw_int_to_fixed(0)) && bw_ltn(data->min_dram_speed_change_margin[data->y_clk_level][s_mid1], bw_int_to_fixed(9999)) && bw_leq(data->dispclk_required_for_dram_speed_change[data->y_clk_level][s_mid1], vbios->mid_voltage_max_dispclk) && data->num_displays_with_margin[data->y_clk_level][s_mid1] == number_of_displays_enabled_with_margin))) {
1590 sclk_message = bw_def_mid;
1591 data->sclk_level = s_mid1;
1592 data->required_sclk = vbios->mid1_sclk;
1593 }
1594 else if (bw_ltn(data->total_average_bandwidth_no_compression, bw_mul(bw_mul(bw_frc_to_fixed(dceip->max_average_percent_of_ideal_port_bw_display_can_use_in_normal_system_operation, 100),sclk[s_mid2]),vbios->data_return_bus_width))
1595 && bw_ltn(data->required_sclk, sclk[s_mid2]) && (data->cpup_state_change_enable == bw_def_no || (bw_mtn(data->blackout_duration_margin[data->y_clk_level][s_mid2], bw_int_to_fixed(0)) && bw_ltn(data->dispclk_required_for_blackout_duration[data->y_clk_level][s_mid2], vbios->high_voltage_max_dispclk))) && (data->cpuc_state_change_enable == bw_def_no || (bw_mtn(data->blackout_duration_margin[data->y_clk_level][s_mid2], bw_int_to_fixed(0)) && bw_ltn(data->dispclk_required_for_blackout_duration[data->y_clk_level][s_mid2], vbios->high_voltage_max_dispclk) && bw_ltn(data->dispclk_required_for_blackout_recovery[data->y_clk_level][s_mid2], vbios->high_voltage_max_dispclk))) && (!data->increase_voltage_to_support_mclk_switch || data->nbp_state_change_enable == bw_def_no || (bw_mtn(data->min_dram_speed_change_margin[data->y_clk_level][s_mid2], bw_int_to_fixed(0)) && bw_ltn(data->min_dram_speed_change_margin[data->y_clk_level][s_mid2], bw_int_to_fixed(9999)) && bw_leq(data->dispclk_required_for_dram_speed_change[data->y_clk_level][s_mid2], vbios->mid_voltage_max_dispclk) && data->num_displays_with_margin[data->y_clk_level][s_mid2] == number_of_displays_enabled_with_margin))) {
1596 sclk_message = bw_def_mid;
1597 data->sclk_level = s_mid2;
1598 data->required_sclk = vbios->mid2_sclk;
1599 }
1600 else if (bw_ltn(data->total_average_bandwidth_no_compression, bw_mul(bw_mul(bw_frc_to_fixed(dceip->max_average_percent_of_ideal_port_bw_display_can_use_in_normal_system_operation, 100),sclk[s_mid3]),vbios->data_return_bus_width))
1601 && bw_ltn(data->required_sclk, sclk[s_mid3]) && (data->cpup_state_change_enable == bw_def_no || (bw_mtn(data->blackout_duration_margin[data->y_clk_level][s_mid3], bw_int_to_fixed(0)) && bw_ltn(data->dispclk_required_for_blackout_duration[data->y_clk_level][s_mid3], vbios->high_voltage_max_dispclk))) && (data->cpuc_state_change_enable == bw_def_no || (bw_mtn(data->blackout_duration_margin[data->y_clk_level][s_mid3], bw_int_to_fixed(0)) && bw_ltn(data->dispclk_required_for_blackout_duration[data->y_clk_level][s_mid3], vbios->high_voltage_max_dispclk) && bw_ltn(data->dispclk_required_for_blackout_recovery[data->y_clk_level][s_mid3], vbios->high_voltage_max_dispclk))) && (!data->increase_voltage_to_support_mclk_switch || data->nbp_state_change_enable == bw_def_no || (bw_mtn(data->min_dram_speed_change_margin[data->y_clk_level][s_mid3], bw_int_to_fixed(0)) && bw_ltn(data->min_dram_speed_change_margin[data->y_clk_level][s_mid3], bw_int_to_fixed(9999)) && bw_leq(data->dispclk_required_for_dram_speed_change[data->y_clk_level][s_mid3], vbios->mid_voltage_max_dispclk) && data->num_displays_with_margin[data->y_clk_level][s_mid3] == number_of_displays_enabled_with_margin))) {
1602 sclk_message = bw_def_mid;
1603 data->sclk_level = s_mid3;
1604 data->required_sclk = vbios->mid3_sclk;
1605 }
1606 else if (bw_ltn(data->total_average_bandwidth_no_compression, bw_mul(bw_mul(bw_frc_to_fixed(dceip->max_average_percent_of_ideal_port_bw_display_can_use_in_normal_system_operation, 100),sclk[s_mid4]),vbios->data_return_bus_width))
1607 && bw_ltn(data->required_sclk, sclk[s_mid4]) && (data->cpup_state_change_enable == bw_def_no || (bw_mtn(data->blackout_duration_margin[data->y_clk_level][s_mid4], bw_int_to_fixed(0)) && bw_ltn(data->dispclk_required_for_blackout_duration[data->y_clk_level][s_mid4], vbios->high_voltage_max_dispclk))) && (data->cpuc_state_change_enable == bw_def_no || (bw_mtn(data->blackout_duration_margin[data->y_clk_level][s_mid4], bw_int_to_fixed(0)) && bw_ltn(data->dispclk_required_for_blackout_duration[data->y_clk_level][s_mid4], vbios->high_voltage_max_dispclk) && bw_ltn(data->dispclk_required_for_blackout_recovery[data->y_clk_level][s_mid4], vbios->high_voltage_max_dispclk))) && (!data->increase_voltage_to_support_mclk_switch || data->nbp_state_change_enable == bw_def_no || (bw_mtn(data->min_dram_speed_change_margin[data->y_clk_level][s_mid4], bw_int_to_fixed(0)) && bw_ltn(data->min_dram_speed_change_margin[data->y_clk_level][s_mid4], bw_int_to_fixed(9999)) && bw_leq(data->dispclk_required_for_dram_speed_change[data->y_clk_level][s_mid4], vbios->mid_voltage_max_dispclk) && data->num_displays_with_margin[data->y_clk_level][s_mid4] == number_of_displays_enabled_with_margin))) {
1608 sclk_message = bw_def_mid;
1609 data->sclk_level = s_mid4;
1610 data->required_sclk = vbios->mid4_sclk;
1611 }
1612 else if (bw_ltn(data->total_average_bandwidth_no_compression, bw_mul(bw_mul(bw_frc_to_fixed(dceip->max_average_percent_of_ideal_port_bw_display_can_use_in_normal_system_operation, 100),sclk[s_mid5]),vbios->data_return_bus_width))
1613 && bw_ltn(data->required_sclk, sclk[s_mid5]) && (data->cpup_state_change_enable == bw_def_no || (bw_mtn(data->blackout_duration_margin[data->y_clk_level][s_mid5], bw_int_to_fixed(0)) && bw_ltn(data->dispclk_required_for_blackout_duration[data->y_clk_level][s_mid5], vbios->high_voltage_max_dispclk))) && (data->cpuc_state_change_enable == bw_def_no || (bw_mtn(data->blackout_duration_margin[data->y_clk_level][s_mid5], bw_int_to_fixed(0)) && bw_ltn(data->dispclk_required_for_blackout_duration[data->y_clk_level][s_mid5], vbios->high_voltage_max_dispclk) && bw_ltn(data->dispclk_required_for_blackout_recovery[data->y_clk_level][s_mid5], vbios->high_voltage_max_dispclk))) && (!data->increase_voltage_to_support_mclk_switch || data->nbp_state_change_enable == bw_def_no || (bw_mtn(data->min_dram_speed_change_margin[data->y_clk_level][s_mid5], bw_int_to_fixed(0)) && bw_ltn(data->min_dram_speed_change_margin[data->y_clk_level][s_mid5], bw_int_to_fixed(9999)) && bw_leq(data->dispclk_required_for_dram_speed_change[data->y_clk_level][s_mid5], vbios->mid_voltage_max_dispclk) && data->num_displays_with_margin[data->y_clk_level][s_mid5] == number_of_displays_enabled_with_margin))) {
1614 sclk_message = bw_def_mid;
1615 data->sclk_level = s_mid5;
1616 data->required_sclk = vbios->mid5_sclk;
1617 }
1618 else if (bw_ltn(data->total_average_bandwidth_no_compression, bw_mul(bw_mul(bw_frc_to_fixed(dceip->max_average_percent_of_ideal_port_bw_display_can_use_in_normal_system_operation, 100),sclk[s_mid6]),vbios->data_return_bus_width))
1619 && bw_ltn(data->required_sclk, sclk[s_mid6]) && (data->cpup_state_change_enable == bw_def_no || (bw_mtn(data->blackout_duration_margin[data->y_clk_level][s_mid6], bw_int_to_fixed(0)) && bw_ltn(data->dispclk_required_for_blackout_duration[data->y_clk_level][s_mid6], vbios->high_voltage_max_dispclk))) && (data->cpuc_state_change_enable == bw_def_no || (bw_mtn(data->blackout_duration_margin[data->y_clk_level][s_mid6], bw_int_to_fixed(0)) && bw_ltn(data->dispclk_required_for_blackout_duration[data->y_clk_level][s_mid6], vbios->high_voltage_max_dispclk) && bw_ltn(data->dispclk_required_for_blackout_recovery[data->y_clk_level][s_mid6], vbios->high_voltage_max_dispclk))) && (!data->increase_voltage_to_support_mclk_switch || data->nbp_state_change_enable == bw_def_no || (bw_mtn(data->min_dram_speed_change_margin[data->y_clk_level][s_mid6], bw_int_to_fixed(0)) && bw_ltn(data->min_dram_speed_change_margin[data->y_clk_level][s_mid6], bw_int_to_fixed(9999)) && bw_leq(data->dispclk_required_for_dram_speed_change[data->y_clk_level][s_mid6], vbios->high_voltage_max_dispclk) && data->num_displays_with_margin[data->y_clk_level][s_mid6] == number_of_displays_enabled_with_margin))) {
1620 sclk_message = bw_def_mid;
1621 data->sclk_level = s_mid6;
1622 data->required_sclk = vbios->mid6_sclk;
1623 }
1624 else if (bw_ltn(data->total_average_bandwidth_no_compression, bw_mul(bw_mul(bw_frc_to_fixed(dceip->max_average_percent_of_ideal_port_bw_display_can_use_in_normal_system_operation, 100),sclk[s_high]),vbios->data_return_bus_width))
1625 && bw_ltn(data->required_sclk, sclk[s_high])) {
1626 sclk_message = bw_def_high;
1627 data->sclk_level = s_high;
1628 data->required_sclk = vbios->high_sclk;
1629 }
1630 else if (bw_meq(data->total_average_bandwidth_no_compression, bw_mul(bw_mul(bw_frc_to_fixed(dceip->max_average_percent_of_ideal_port_bw_display_can_use_in_normal_system_operation, 100),sclk[s_high]),vbios->data_return_bus_width))
1631 && bw_ltn(data->required_sclk, sclk[s_high])) {
1632 sclk_message = bw_def_high;
1633 data->sclk_level = s_high;
1634 data->required_sclk = vbios->high_sclk;
1635 }
1636 else {
1637 sclk_message = bw_def_exceeded_allowed_maximum_sclk;
1638 data->sclk_level = s_high;
1639 /*required_sclk = high_sclk*/
1640 }
1641 }
1642 /*dispclk*/
1643 /*if dispclk is set to the maximum, ramping is not required. dispclk required without ramping is less than the dispclk required with ramping.*/
1644 /*if dispclk required without ramping is more than the maximum dispclk, that is the dispclk required, and the mode is not supported*/
1645 /*if that does not happen, but dispclk required with ramping is more than the maximum dispclk, dispclk required is just the maximum dispclk*/
1646 /*if that does not happen either, dispclk required is the dispclk required with ramping.*/
1647 /*dispclk required without ramping is the maximum of the one required for display pipe pixel throughput, for scaler throughput, for total read request thrrougput and for dram/np p-state change if enabled.*/
1648 /*the display pipe pixel throughput is the maximum of lines in per line out in the beginning of the frame and lines in per line out in the middle of the frame multiplied by the horizontal blank and chunk granularity factor, altogether multiplied by the ratio of the source width to the line time, divided by the line buffer pixels per dispclk throughput, and multiplied by the display pipe throughput factor.*/
1649 /*the horizontal blank and chunk granularity factor is the ratio of the line time divided by the line time minus half the horizontal blank and chunk time. it applies when the lines in per line out is not 2 or 4.*/
1650 /*the dispclk required for scaler throughput is the product of the pixel rate and the scaling limits factor.*/
1651 /*the dispclk required for total read request throughput is the product of the peak request-per-second bandwidth and the dispclk cycles per request, divided by the request efficiency.*/
1652 /*for the dispclk required with ramping, instead of multiplying just the pipe throughput by the display pipe throughput factor, we multiply the scaler and pipe throughput by the ramping factor.*/
1653 /*the scaling limits factor is the product of the horizontal scale ratio, and the ratio of the vertical taps divided by the scaler efficiency clamped to at least 1.*/
1654 /*the scaling limits factor itself it also clamped to at least 1*/
1655 /*if doing downscaling with the pre-downscaler enabled, the horizontal scale ratio should not be considered above (use "1")*/
1656 data->downspread_factor = bw_add(bw_int_to_fixed(1), bw_div(vbios->down_spread_percentage, bw_int_to_fixed(100)));
1657 for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
1658 if (data->enable[i]) {
1659 if (surface_type[i] == bw_def_graphics) {
1660 switch (data->lb_bpc[i]) {
1661 case 6:
1662 data->v_scaler_efficiency = dceip->graphics_vscaler_efficiency6_bit_per_component;
1663 break;
1664 case 8:
1665 data->v_scaler_efficiency = dceip->graphics_vscaler_efficiency8_bit_per_component;
1666 break;
1667 case 10:
1668 data->v_scaler_efficiency = dceip->graphics_vscaler_efficiency10_bit_per_component;
1669 break;
1670 default:
1671 data->v_scaler_efficiency = dceip->graphics_vscaler_efficiency12_bit_per_component;
1672 break;
1673 }
1674 if (data->use_alpha[i] == 1) {
1675 data->v_scaler_efficiency = bw_min2(data->v_scaler_efficiency, dceip->alpha_vscaler_efficiency);
1676 }
1677 }
1678 else {
1679 switch (data->lb_bpc[i]) {
1680 case 6:
1681 data->v_scaler_efficiency = dceip->underlay_vscaler_efficiency6_bit_per_component;
1682 break;
1683 case 8:
1684 data->v_scaler_efficiency = dceip->underlay_vscaler_efficiency8_bit_per_component;
1685 break;
1686 case 10:
1687 data->v_scaler_efficiency = dceip->underlay_vscaler_efficiency10_bit_per_component;
1688 break;
1689 default:
1690 data->v_scaler_efficiency = dceip->underlay_vscaler_efficiency12_bit_per_component;
1691 break;
1692 }
1693 }
1694 if (dceip->pre_downscaler_enabled && bw_mtn(data->hsr[i], bw_int_to_fixed(1))) {
1695 data->scaler_limits_factor = bw_max2(bw_div(data->v_taps[i], data->v_scaler_efficiency), bw_div(data->source_width_rounded_up_to_chunks[i], data->h_total[i]));
1696 }
1697 else {
1698 data->scaler_limits_factor = bw_max3(bw_int_to_fixed(1), bw_ceil2(bw_div(data->h_taps[i], bw_int_to_fixed(4)), bw_int_to_fixed(1)), bw_mul(data->hsr[i], bw_max2(bw_div(data->v_taps[i], data->v_scaler_efficiency), bw_int_to_fixed(1))));
1699 }
1700 data->display_pipe_pixel_throughput = bw_div(bw_div(bw_mul(bw_max2(data->lb_lines_in_per_line_out_in_beginning_of_frame[i], bw_mul(data->lb_lines_in_per_line_out_in_middle_of_frame[i], data->horizontal_blank_and_chunk_granularity_factor[i])), data->source_width_rounded_up_to_chunks[i]), (bw_div(data->h_total[i], data->pixel_rate[i]))), dceip->lb_write_pixels_per_dispclk);
1701 data->dispclk_required_without_ramping[i] = bw_mul(data->downspread_factor, bw_max2(bw_mul(data->pixel_rate[i], data->scaler_limits_factor), bw_mul(dceip->display_pipe_throughput_factor, data->display_pipe_pixel_throughput)));
1702 data->dispclk_required_with_ramping[i] = bw_mul(dceip->dispclk_ramping_factor, bw_max2(bw_mul(data->pixel_rate[i], data->scaler_limits_factor), data->display_pipe_pixel_throughput));
1703 }
1704 }
1705 data->total_dispclk_required_with_ramping = bw_int_to_fixed(0);
1706 data->total_dispclk_required_without_ramping = bw_int_to_fixed(0);
1707 for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
1708 if (data->enable[i]) {
1709 if (bw_ltn(data->total_dispclk_required_with_ramping, data->dispclk_required_with_ramping[i])) {
1710 data->total_dispclk_required_with_ramping = data->dispclk_required_with_ramping[i];
1711 }
1712 if (bw_ltn(data->total_dispclk_required_without_ramping, data->dispclk_required_without_ramping[i])) {
1713 data->total_dispclk_required_without_ramping = data->dispclk_required_without_ramping[i];
1714 }
1715 }
1716 }
1717 data->total_read_request_bandwidth = bw_int_to_fixed(0);
1718 data->total_write_request_bandwidth = bw_int_to_fixed(0);
1719 for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
1720 if (data->enable[i]) {
1721 if (surface_type[i] != bw_def_display_write_back420_luma && surface_type[i] != bw_def_display_write_back420_chroma) {
1722 data->total_read_request_bandwidth = bw_add(data->total_read_request_bandwidth, data->request_bandwidth[i]);
1723 }
1724 else {
1725 data->total_write_request_bandwidth = bw_add(data->total_write_request_bandwidth, data->request_bandwidth[i]);
1726 }
1727 }
1728 }
1729 data->dispclk_required_for_total_read_request_bandwidth = bw_div(bw_mul(data->total_read_request_bandwidth, dceip->dispclk_per_request), dceip->request_efficiency);
1730 data->total_dispclk_required_with_ramping_with_request_bandwidth = bw_max2(data->total_dispclk_required_with_ramping, data->dispclk_required_for_total_read_request_bandwidth);
1731 data->total_dispclk_required_without_ramping_with_request_bandwidth = bw_max2(data->total_dispclk_required_without_ramping, data->dispclk_required_for_total_read_request_bandwidth);
1732 if (data->cpuc_state_change_enable == bw_def_yes) {
1733 data->total_dispclk_required_with_ramping_with_request_bandwidth = bw_max3(data->total_dispclk_required_with_ramping_with_request_bandwidth, data->dispclk_required_for_blackout_duration[data->y_clk_level][data->sclk_level], data->dispclk_required_for_blackout_recovery[data->y_clk_level][data->sclk_level]);
1734 data->total_dispclk_required_without_ramping_with_request_bandwidth = bw_max3(data->total_dispclk_required_without_ramping_with_request_bandwidth, data->dispclk_required_for_blackout_duration[data->y_clk_level][data->sclk_level], data->dispclk_required_for_blackout_recovery[data->y_clk_level][data->sclk_level]);
1735 }
1736 if (data->cpup_state_change_enable == bw_def_yes) {
1737 data->total_dispclk_required_with_ramping_with_request_bandwidth = bw_max2(data->total_dispclk_required_with_ramping_with_request_bandwidth, data->dispclk_required_for_blackout_duration[data->y_clk_level][data->sclk_level]);
1738 data->total_dispclk_required_without_ramping_with_request_bandwidth = bw_max2(data->total_dispclk_required_without_ramping_with_request_bandwidth, data->dispclk_required_for_blackout_duration[data->y_clk_level][data->sclk_level]);
1739 }
1740 if (data->nbp_state_change_enable == bw_def_yes && data->increase_voltage_to_support_mclk_switch) {
1741 data->total_dispclk_required_with_ramping_with_request_bandwidth = bw_max2(data->total_dispclk_required_with_ramping_with_request_bandwidth, data->dispclk_required_for_dram_speed_change[data->y_clk_level][data->sclk_level]);
1742 data->total_dispclk_required_without_ramping_with_request_bandwidth = bw_max2(data->total_dispclk_required_without_ramping_with_request_bandwidth, data->dispclk_required_for_dram_speed_change[data->y_clk_level][data->sclk_level]);
1743 }
1744 if (bw_ltn(data->total_dispclk_required_with_ramping_with_request_bandwidth, vbios->high_voltage_max_dispclk)) {
1745 data->dispclk = data->total_dispclk_required_with_ramping_with_request_bandwidth;
1746 }
1747 else if (bw_ltn(data->total_dispclk_required_without_ramping_with_request_bandwidth, vbios->high_voltage_max_dispclk)) {
1748 data->dispclk = vbios->high_voltage_max_dispclk;
1749 }
1750 else {
1751 data->dispclk = data->total_dispclk_required_without_ramping_with_request_bandwidth;
1752 }
1753 /* required core voltage*/
1754 /* the core voltage required is low if sclk, yclk(pclk)and dispclk are within the low limits*/
1755 /* otherwise, the core voltage required is medium if yclk (pclk) is within the low limit and sclk and dispclk are within the medium limit*/
1756 /* otherwise, the core voltage required is high if the three clocks are within the high limits*/
1757 /* otherwise, or if the mode is not supported, core voltage requirement is not applicable*/
1758 if (pipe_check == bw_def_notok) {
1759 voltage = bw_def_na;
1760 }
1761 else if (mode_check == bw_def_notok) {
1762 voltage = bw_def_notok;
1763 }
1764 else if (bw_equ(bw_int_to_fixed(yclk_message), vbios->low_yclk) && sclk_message == bw_def_low && bw_ltn(data->dispclk, vbios->low_voltage_max_dispclk)) {
1765 voltage = bw_def_0_72;
1766 }
1767 else if ((bw_equ(bw_int_to_fixed(yclk_message), vbios->low_yclk) || bw_equ(bw_int_to_fixed(yclk_message), vbios->mid_yclk)) && (sclk_message == bw_def_low || sclk_message == bw_def_mid) && bw_ltn(data->dispclk, vbios->mid_voltage_max_dispclk)) {
1768 voltage = bw_def_0_8;
1769 }
1770 else if ((bw_equ(bw_int_to_fixed(yclk_message), vbios->low_yclk) || bw_equ(bw_int_to_fixed(yclk_message), vbios->mid_yclk) || bw_equ(bw_int_to_fixed(yclk_message), vbios->high_yclk)) && (sclk_message == bw_def_low || sclk_message == bw_def_mid || sclk_message == bw_def_high) && bw_leq(data->dispclk, vbios->high_voltage_max_dispclk)) {
1771 if ((data->nbp_state_change_enable == bw_def_no && nbp_state_change_enable_blank == bw_def_no)) {
1772 voltage = bw_def_high_no_nbp_state_change;
1773 }
1774 else {
1775 voltage = bw_def_0_9;
1776 }
1777 }
1778 else {
1779 voltage = bw_def_notok;
1780 }
1781 if (voltage == bw_def_0_72) {
1782 data->max_phyclk = vbios->low_voltage_max_phyclk;
1783 }
1784 else if (voltage == bw_def_0_8) {
1785 data->max_phyclk = vbios->mid_voltage_max_phyclk;
1786 }
1787 else {
1788 data->max_phyclk = vbios->high_voltage_max_phyclk;
1789 }
1790 /*required blackout recovery time*/
1791 data->blackout_recovery_time = bw_int_to_fixed(0);
1792 for (k = 0; k <= maximum_number_of_surfaces - 1; k++) {
1793 if (data->enable[k] && bw_mtn(vbios->blackout_duration, bw_int_to_fixed(0)) && data->cpup_state_change_enable == bw_def_yes) {
1794 if (surface_type[k] != bw_def_display_write_back420_luma && surface_type[k] != bw_def_display_write_back420_chroma) {
1795 data->blackout_recovery_time = bw_max2(data->blackout_recovery_time, bw_add(bw_mul(bw_int_to_fixed(2), data->total_dmifmc_urgent_latency), data->dmif_burst_time[data->y_clk_level][data->sclk_level]));
1796 if (bw_ltn(data->adjusted_data_buffer_size[k], bw_mul(bw_div(bw_mul(data->display_bandwidth[k], data->useful_bytes_per_request[k]), data->bytes_per_request[k]), (bw_add(vbios->blackout_duration, bw_add(bw_mul(bw_int_to_fixed(2), data->total_dmifmc_urgent_latency), data->dmif_burst_time[data->y_clk_level][data->sclk_level])))))) {
1797 data->blackout_recovery_time = bw_max2(data->blackout_recovery_time, bw_div((bw_add(bw_mul(bw_div(bw_mul(data->display_bandwidth[k], data->useful_bytes_per_request[k]), data->bytes_per_request[k]), vbios->blackout_duration), bw_sub(bw_div(bw_mul(bw_mul(bw_mul((bw_add(bw_mul(bw_int_to_fixed(2), data->total_dmifmc_urgent_latency), data->dmif_burst_time[data->y_clk_level][data->sclk_level])), data->dispclk), bw_int_to_fixed(data->bytes_per_pixel[k])), data->lines_interleaved_in_mem_access[k]), data->latency_hiding_lines[k]), data->adjusted_data_buffer_size[k]))), (bw_sub(bw_div(bw_mul(bw_mul(data->dispclk, bw_int_to_fixed(data->bytes_per_pixel[k])), data->lines_interleaved_in_mem_access[k]), data->latency_hiding_lines[k]), bw_div(bw_mul(data->display_bandwidth[k], data->useful_bytes_per_request[k]), data->bytes_per_request[k])))));
1798 }
1799 }
1800 else {
1801 data->blackout_recovery_time = bw_max2(data->blackout_recovery_time, bw_add(bw_mul(bw_int_to_fixed(2), vbios->mcifwrmc_urgent_latency), data->mcifwr_burst_time[data->y_clk_level][data->sclk_level]));
1802 if (bw_ltn(data->adjusted_data_buffer_size[k], bw_mul(bw_div(bw_mul(data->display_bandwidth[k], data->useful_bytes_per_request[k]), data->bytes_per_request[k]), (bw_add(vbios->blackout_duration, bw_add(bw_mul(bw_int_to_fixed(2), vbios->mcifwrmc_urgent_latency), data->mcifwr_burst_time[data->y_clk_level][data->sclk_level])))))) {
1803 data->blackout_recovery_time = bw_max2(data->blackout_recovery_time, bw_div((bw_add(bw_mul(bw_div(bw_mul(data->display_bandwidth[k], data->useful_bytes_per_request[k]), data->bytes_per_request[k]), vbios->blackout_duration), bw_sub(bw_div(bw_mul(bw_mul(bw_mul((bw_add(bw_add(bw_mul(bw_int_to_fixed(2), vbios->mcifwrmc_urgent_latency), data->dmif_burst_time[data->y_clk_level][data->sclk_level]), data->mcifwr_burst_time[data->y_clk_level][data->sclk_level])), data->dispclk), bw_int_to_fixed(data->bytes_per_pixel[k])), data->lines_interleaved_in_mem_access[k]), data->latency_hiding_lines[k]), data->adjusted_data_buffer_size[k]))), (bw_sub(bw_div(bw_mul(bw_mul(data->dispclk, bw_int_to_fixed(data->bytes_per_pixel[k])), data->lines_interleaved_in_mem_access[k]), data->latency_hiding_lines[k]), bw_div(bw_mul(data->display_bandwidth[k], data->useful_bytes_per_request[k]), data->bytes_per_request[k])))));
1804 }
1805 }
1806 }
1807 }
1808 /*sclk deep sleep*/
1809 /*during self-refresh, sclk can be reduced to dispclk divided by the minimum pixels in the data fifo entry, with 15% margin, but shoudl not be set to less than the request bandwidth.*/
1810 /*the data fifo entry is 16 pixels for the writeback, 64 bytes/bytes_per_pixel for the graphics, 16 pixels for the parallel rotation underlay,*/
1811 /*and 16 bytes/bytes_per_pixel for the orthogonal rotation underlay.*/
1812 /*in parallel mode (underlay pipe), the data read from the dmifv buffer is variable and based on the pixel depth (8bbp - 16 bytes, 16 bpp - 32 bytes, 32 bpp - 64 bytes)*/
1813 /*in orthogonal mode (underlay pipe), the data read from the dmifv buffer is fixed at 16 bytes.*/
1814 for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
1815 if (data->enable[i]) {
1816 if (surface_type[i] == bw_def_display_write_back420_luma || surface_type[i] == bw_def_display_write_back420_chroma) {
1817 data->pixels_per_data_fifo_entry[i] = bw_int_to_fixed(16);
1818 }
1819 else if (surface_type[i] == bw_def_graphics) {
1820 data->pixels_per_data_fifo_entry[i] = bw_div(bw_int_to_fixed(64), bw_int_to_fixed(data->bytes_per_pixel[i]));
1821 }
1822 else if (data->orthogonal_rotation[i] == 0) {
1823 data->pixels_per_data_fifo_entry[i] = bw_int_to_fixed(16);
1824 }
1825 else {
1826 data->pixels_per_data_fifo_entry[i] = bw_div(bw_int_to_fixed(16), bw_int_to_fixed(data->bytes_per_pixel[i]));
1827 }
1828 }
1829 }
1830 data->min_pixels_per_data_fifo_entry = bw_int_to_fixed(9999);
1831 for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
1832 if (data->enable[i]) {
1833 if (bw_mtn(data->min_pixels_per_data_fifo_entry, data->pixels_per_data_fifo_entry[i])) {
1834 data->min_pixels_per_data_fifo_entry = data->pixels_per_data_fifo_entry[i];
1835 }
1836 }
1837 }
1838 data->sclk_deep_sleep = bw_max2(bw_div(bw_mul(data->dispclk, bw_frc_to_fixed(115, 100)), data->min_pixels_per_data_fifo_entry), data->total_read_request_bandwidth);
1839 /*urgent, stutter and nb-p_state watermark*/
1840 /*the urgent watermark is the maximum of the urgent trip time plus the pixel transfer time, the urgent trip times to get data for the first pixel, and the urgent trip times to get data for the last pixel.*/
1841 /*the stutter exit watermark is the self refresh exit time plus the maximum of the data burst time plus the pixel transfer time, the data burst times to get data for the first pixel, and the data burst times to get data for the last pixel. it does not apply to the writeback.*/
1842 /*the nb p-state change watermark is the dram speed/p-state change time plus the maximum of the data burst time plus the pixel transfer time, the data burst times to get data for the first pixel, and the data burst times to get data for the last pixel.*/
1843 /*the pixel transfer time is the maximum of the time to transfer the source pixels required for the first output pixel, and the time to transfer the pixels for the last output pixel minus the active line time.*/
1844 /*blackout_duration is added to the urgent watermark*/
1845 data->chunk_request_time = bw_int_to_fixed(0);
1846 data->cursor_request_time = bw_int_to_fixed(0);
1847 /*compute total time to request one chunk from each active display pipe*/
1848 for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
1849 if (data->enable[i]) {
1850 data->chunk_request_time = bw_add(data->chunk_request_time, (bw_div((bw_div(bw_int_to_fixed(pixels_per_chunk * data->bytes_per_pixel[i]), data->useful_bytes_per_request[i])), bw_min2(sclk[data->sclk_level], bw_div(data->dispclk, bw_int_to_fixed(2))))));
1851 }
1852 }
1853 /*compute total time to request cursor data*/
1854 data->cursor_request_time = (bw_div(data->cursor_total_data, (bw_mul(bw_int_to_fixed(32), sclk[data->sclk_level]))));
1855 for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
1856 if (data->enable[i]) {
1857 data->line_source_pixels_transfer_time = bw_max2(bw_div(bw_div(data->src_pixels_for_first_output_pixel[i], dceip->lb_write_pixels_per_dispclk), (bw_div(data->dispclk, dceip->display_pipe_throughput_factor))), bw_sub(bw_div(bw_div(data->src_pixels_for_last_output_pixel[i], dceip->lb_write_pixels_per_dispclk), (bw_div(data->dispclk, dceip->display_pipe_throughput_factor))), data->active_time[i]));
1858 if (surface_type[i] != bw_def_display_write_back420_luma && surface_type[i] != bw_def_display_write_back420_chroma) {
1859 data->urgent_watermark[i] = bw_add(bw_add(bw_add(bw_add(bw_add(data->total_dmifmc_urgent_latency, data->dmif_burst_time[data->y_clk_level][data->sclk_level]), bw_max2(data->line_source_pixels_transfer_time, data->line_source_transfer_time[i][data->y_clk_level][data->sclk_level])), vbios->blackout_duration), data->chunk_request_time), data->cursor_request_time);
1860 data->stutter_exit_watermark[i] = bw_add(bw_sub(vbios->stutter_self_refresh_exit_latency, data->total_dmifmc_urgent_latency), data->urgent_watermark[i]);
1861 data->stutter_entry_watermark[i] = bw_add(bw_sub(bw_add(vbios->stutter_self_refresh_exit_latency, vbios->stutter_self_refresh_entry_latency), data->total_dmifmc_urgent_latency), data->urgent_watermark[i]);
1862 /*unconditionally remove black out time from the nb p_state watermark*/
1863 if (data->display_pstate_change_enable[i] == 1) {
1864 data->nbp_state_change_watermark[i] = bw_add(bw_add(vbios->nbp_state_change_latency, data->dmif_burst_time[data->y_clk_level][data->sclk_level]), bw_max2(data->line_source_pixels_transfer_time, data->dram_speed_change_line_source_transfer_time[i][data->y_clk_level][data->sclk_level]));
1865 }
1866 else {
1867 /*maximize the watermark to force the switch in the vb_lank region of the frame*/
1868 data->nbp_state_change_watermark[i] = bw_int_to_fixed(131000);
1869 }
1870 }
1871 else {
1872 data->urgent_watermark[i] = bw_add(bw_add(bw_add(bw_add(bw_add(vbios->mcifwrmc_urgent_latency, data->mcifwr_burst_time[data->y_clk_level][data->sclk_level]), bw_max2(data->line_source_pixels_transfer_time, data->line_source_transfer_time[i][data->y_clk_level][data->sclk_level])), vbios->blackout_duration), data->chunk_request_time), data->cursor_request_time);
1873 data->stutter_exit_watermark[i] = bw_int_to_fixed(0);
1874 data->stutter_entry_watermark[i] = bw_int_to_fixed(0);
1875 if (data->display_pstate_change_enable[i] == 1) {
1876 data->nbp_state_change_watermark[i] = bw_add(bw_add(vbios->nbp_state_change_latency, data->mcifwr_burst_time[data->y_clk_level][data->sclk_level]), bw_max2(data->line_source_pixels_transfer_time, data->dram_speed_change_line_source_transfer_time[i][data->y_clk_level][data->sclk_level]));
1877 }
1878 else {
1879 /*maximize the watermark to force the switch in the vb_lank region of the frame*/
1880 data->nbp_state_change_watermark[i] = bw_int_to_fixed(131000);
1881 }
1882 }
1883 }
1884 }
1885 /*stutter mode enable*/
1886 /*in the multi-display case the stutter exit or entry watermark cannot exceed the minimum latency hiding capabilities of the*/
1887 /*display pipe.*/
1888 data->stutter_mode_enable = data->cpuc_state_change_enable;
1889 if (data->number_of_displays > 1) {
1890 for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
1891 if (data->enable[i]) {
1892 if ((bw_mtn(data->stutter_exit_watermark[i], data->minimum_latency_hiding[i]) || bw_mtn(data->stutter_entry_watermark[i], data->minimum_latency_hiding[i]))) {
1893 data->stutter_mode_enable = bw_def_no;
1894 }
1895 }
1896 }
1897 }
1898 /*performance metrics*/
1899 /* display read access efficiency (%)*/
1900 /* display write back access efficiency (%)*/
1901 /* stutter efficiency (%)*/
1902 /* extra underlay pitch recommended for efficiency (pixels)*/
1903 /* immediate flip time (us)*/
1904 /* latency for other clients due to urgent display read (us)*/
1905 /* latency for other clients due to urgent display write (us)*/
1906 /* average bandwidth consumed by display (no compression) (gb/s)*/
1907 /* required dram bandwidth (gb/s)*/
1908 /* required sclk (m_hz)*/
1909 /* required rd urgent latency (us)*/
1910 /* nb p-state change margin (us)*/
1911 /*dmif and mcifwr dram access efficiency*/
1912 /*is the ratio between the ideal dram access time (which is the data buffer size in memory divided by the dram bandwidth), and the actual time which is the total page close-open time. but it cannot exceed the dram efficiency provided by the memory subsystem*/
1913 data->dmifdram_access_efficiency = bw_min2(bw_div(bw_div(data->total_display_reads_required_dram_access_data, data->dram_bandwidth), data->dmif_total_page_close_open_time), bw_int_to_fixed(1));
1914 if (bw_mtn(data->total_display_writes_required_dram_access_data, bw_int_to_fixed(0))) {
1915 data->mcifwrdram_access_efficiency = bw_min2(bw_div(bw_div(data->total_display_writes_required_dram_access_data, data->dram_bandwidth), data->mcifwr_total_page_close_open_time), bw_int_to_fixed(1));
1916 }
1917 else {
1918 data->mcifwrdram_access_efficiency = bw_int_to_fixed(0);
1919 }
1920 /*stutter efficiency*/
1921 /*the stutter efficiency is the frame-average time in self-refresh divided by the frame-average stutter cycle duration. only applies if the display write-back is not enabled.*/
1922 /*the frame-average stutter cycle used is the minimum for all pipes of the frame-average data buffer size in time, times the compression rate*/
1923 /*the frame-average time in self-refresh is the stutter cycle minus the self refresh exit latency and the burst time*/
1924 /*the stutter cycle is the dmif buffer size reduced by the excess of the stutter exit watermark over the lb size in time.*/
1925 /*the burst time is the data needed during the stutter cycle divided by the available bandwidth*/
1926 /*compute the time read all the data from the dmif buffer to the lb (dram refresh period)*/
1927 for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
1928 if (data->enable[i]) {
1929 data->stutter_refresh_duration[i] = bw_sub(bw_mul(bw_div(bw_div(bw_mul(bw_div(bw_div(data->adjusted_data_buffer_size[i], bw_int_to_fixed(data->bytes_per_pixel[i])), data->source_width_rounded_up_to_chunks[i]), data->h_total[i]), data->vsr[i]), data->pixel_rate[i]), data->compression_rate[i]), bw_max2(bw_int_to_fixed(0), bw_sub(data->stutter_exit_watermark[i], bw_div(bw_mul((bw_sub(data->lb_partitions[i], bw_int_to_fixed(1))), data->h_total[i]), data->pixel_rate[i]))));
1930 data->stutter_dmif_buffer_size[i] = bw_div(bw_mul(bw_mul(bw_div(bw_mul(bw_mul(data->stutter_refresh_duration[i], bw_int_to_fixed(data->bytes_per_pixel[i])), data->source_width_rounded_up_to_chunks[i]), data->h_total[i]), data->vsr[i]), data->pixel_rate[i]), data->compression_rate[i]);
1931 }
1932 }
1933 data->min_stutter_refresh_duration = bw_int_to_fixed(9999);
1934 data->total_stutter_dmif_buffer_size = 0;
1935 data->total_bytes_requested = 0;
1936 data->min_stutter_dmif_buffer_size = 9999;
1937 for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
1938 if (data->enable[i]) {
1939 if (bw_mtn(data->min_stutter_refresh_duration, data->stutter_refresh_duration[i])) {
1940 data->min_stutter_refresh_duration = data->stutter_refresh_duration[i];
1941 data->total_bytes_requested = bw_fixed_to_int(bw_add(bw_int_to_fixed(data->total_bytes_requested), (bw_mul(bw_mul(data->source_height_rounded_up_to_chunks[i], data->source_width_rounded_up_to_chunks[i]), bw_int_to_fixed(data->bytes_per_pixel[i])))));
1942 data->min_stutter_dmif_buffer_size = bw_fixed_to_int(data->stutter_dmif_buffer_size[i]);
1943 }
1944 data->total_stutter_dmif_buffer_size = bw_fixed_to_int(bw_add(data->stutter_dmif_buffer_size[i], bw_int_to_fixed(data->total_stutter_dmif_buffer_size)));
1945 }
1946 }
1947 data->stutter_burst_time = bw_div(bw_int_to_fixed(data->total_stutter_dmif_buffer_size), bw_mul(sclk[data->sclk_level], vbios->data_return_bus_width));
1948 data->num_stutter_bursts = data->total_bytes_requested / data->min_stutter_dmif_buffer_size;
1949 data->total_stutter_cycle_duration = bw_add(bw_add(data->min_stutter_refresh_duration, vbios->stutter_self_refresh_exit_latency), data->stutter_burst_time);
1950 data->time_in_self_refresh = data->min_stutter_refresh_duration;
1951 if (data->d1_display_write_back_dwb_enable == 1) {
1952 data->stutter_efficiency = bw_int_to_fixed(0);
1953 }
1954 else if (bw_ltn(data->time_in_self_refresh, bw_int_to_fixed(0))) {
1955 data->stutter_efficiency = bw_int_to_fixed(0);
1956 }
1957 else {
1958 /*compute stutter efficiency assuming 60 hz refresh rate*/
1959 data->stutter_efficiency = bw_max2(bw_int_to_fixed(0), bw_mul((bw_sub(bw_int_to_fixed(1), (bw_div(bw_mul((bw_add(vbios->stutter_self_refresh_exit_latency, data->stutter_burst_time)), bw_int_to_fixed(data->num_stutter_bursts)), bw_frc_to_fixed(166666667, 10000))))), bw_int_to_fixed(100)));
1960 }
1961 /*immediate flip time*/
1962 /*if scatter gather is enabled, the immediate flip takes a number of urgent memory trips equivalent to the pte requests in a row divided by the pte request limit.*/
1963 /*otherwise, it may take just one urgenr memory trip*/
1964 data->worst_number_of_trips_to_memory = bw_int_to_fixed(1);
1965 for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
1966 if (data->enable[i] && data->scatter_gather_enable_for_pipe[i] == 1) {
1967 data->number_of_trips_to_memory_for_getting_apte_row[i] = bw_ceil2(bw_div(data->scatter_gather_pte_requests_in_row[i], data->scatter_gather_pte_request_limit[i]), bw_int_to_fixed(1));
1968 if (bw_ltn(data->worst_number_of_trips_to_memory, data->number_of_trips_to_memory_for_getting_apte_row[i])) {
1969 data->worst_number_of_trips_to_memory = data->number_of_trips_to_memory_for_getting_apte_row[i];
1970 }
1971 }
1972 }
1973 data->immediate_flip_time = bw_mul(data->worst_number_of_trips_to_memory, data->total_dmifmc_urgent_latency);
1974 /*worst latency for other clients*/
1975 /*it is the urgent latency plus the urgent burst time*/
1976 data->latency_for_non_dmif_clients = bw_add(data->total_dmifmc_urgent_latency, data->dmif_burst_time[data->y_clk_level][data->sclk_level]);
1977 if (data->d1_display_write_back_dwb_enable == 1) {
1978 data->latency_for_non_mcifwr_clients = bw_add(vbios->mcifwrmc_urgent_latency, dceip->mcifwr_all_surfaces_burst_time);
1979 }
1980 else {
1981 data->latency_for_non_mcifwr_clients = bw_int_to_fixed(0);
1982 }
1983 /*dmif mc urgent latency suppported in high sclk and yclk*/
1984 data->dmifmc_urgent_latency_supported_in_high_sclk_and_yclk = bw_div((bw_sub(data->min_read_buffer_size_in_time, data->dmif_burst_time[high][s_high])), data->total_dmifmc_urgent_trips);
1985 /*dram speed/p-state change margin*/
1986 /*in the multi-display case the nb p-state change watermark cannot exceed the average lb size plus the dmif size or the cursor dcp buffer size*/
1987 data->v_blank_nbp_state_dram_speed_change_latency_supported = bw_int_to_fixed(99999);
1988 data->nbp_state_dram_speed_change_latency_supported = bw_int_to_fixed(99999);
1989 for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
1990 if (data->enable[i]) {
1991 data->nbp_state_dram_speed_change_latency_supported = bw_min2(data->nbp_state_dram_speed_change_latency_supported, bw_add(bw_sub(data->maximum_latency_hiding_with_cursor[i], data->nbp_state_change_watermark[i]), vbios->nbp_state_change_latency));
1992 data->v_blank_nbp_state_dram_speed_change_latency_supported = bw_min2(data->v_blank_nbp_state_dram_speed_change_latency_supported, bw_add(bw_sub(bw_div(bw_mul((bw_sub(data->v_total[i], bw_sub(bw_div(data->src_height[i], data->v_scale_ratio[i]), bw_int_to_fixed(4)))), data->h_total[i]), data->pixel_rate[i]), data->nbp_state_change_watermark[i]), vbios->nbp_state_change_latency));
1993 }
1994 }
1995 /*sclk required vs urgent latency*/
1996 for (i = 1; i <= 5; i++) {
1997 data->display_reads_time_for_data_transfer_and_urgent_latency = bw_sub(data->min_read_buffer_size_in_time, bw_mul(data->total_dmifmc_urgent_trips, bw_int_to_fixed(i)));
1998 if (pipe_check == bw_def_ok && (bw_mtn(data->display_reads_time_for_data_transfer_and_urgent_latency, data->dmif_total_page_close_open_time))) {
1999 data->dmif_required_sclk_for_urgent_latency[i] = bw_div(bw_div(data->total_display_reads_required_data, data->display_reads_time_for_data_transfer_and_urgent_latency), (bw_mul(vbios->data_return_bus_width, bw_frc_to_fixed(dceip->percent_of_ideal_port_bw_received_after_urgent_latency, 100))));
2000 }
2001 else {
2002 data->dmif_required_sclk_for_urgent_latency[i] = bw_int_to_fixed(bw_def_na);
2003 }
2004 }
2005 /*output link bit per pixel supported*/
2006 for (k = 0; k <= maximum_number_of_surfaces - 1; k++) {
2007 data->output_bpphdmi[k] = bw_def_na;
2008 data->output_bppdp4_lane_hbr[k] = bw_def_na;
2009 data->output_bppdp4_lane_hbr2[k] = bw_def_na;
2010 data->output_bppdp4_lane_hbr3[k] = bw_def_na;
2011 if (data->enable[k]) {
2012 data->output_bpphdmi[k] = bw_fixed_to_int(bw_mul(bw_div(bw_min2(bw_int_to_fixed(600), data->max_phyclk), data->pixel_rate[k]), bw_int_to_fixed(24)));
2013 if (bw_meq(data->max_phyclk, bw_int_to_fixed(270))) {
2014 data->output_bppdp4_lane_hbr[k] = bw_fixed_to_int(bw_mul(bw_div(bw_mul(bw_int_to_fixed(270), bw_int_to_fixed(4)), data->pixel_rate[k]), bw_int_to_fixed(8)));
2015 }
2016 if (bw_meq(data->max_phyclk, bw_int_to_fixed(540))) {
2017 data->output_bppdp4_lane_hbr2[k] = bw_fixed_to_int(bw_mul(bw_div(bw_mul(bw_int_to_fixed(540), bw_int_to_fixed(4)), data->pixel_rate[k]), bw_int_to_fixed(8)));
2018 }
2019 if (bw_meq(data->max_phyclk, bw_int_to_fixed(810))) {
2020 data->output_bppdp4_lane_hbr3[k] = bw_fixed_to_int(bw_mul(bw_div(bw_mul(bw_int_to_fixed(810), bw_int_to_fixed(4)), data->pixel_rate[k]), bw_int_to_fixed(8)));
2021 }
2022 }
2023 }
2024 }
2025
2026 /*******************************************************************************
2027 * Public functions
2028 ******************************************************************************/
bw_calcs_init(struct bw_calcs_dceip * bw_dceip,struct bw_calcs_vbios * bw_vbios,struct hw_asic_id asic_id)2029 void bw_calcs_init(struct bw_calcs_dceip *bw_dceip,
2030 struct bw_calcs_vbios *bw_vbios,
2031 struct hw_asic_id asic_id)
2032 {
2033 struct bw_calcs_dceip dceip = { 0 };
2034 struct bw_calcs_vbios vbios = { 0 };
2035
2036 enum bw_calcs_version version = bw_calcs_version_from_asic_id(asic_id);
2037
2038 dceip.version = version;
2039
2040 switch (version) {
2041 case BW_CALCS_VERSION_CARRIZO:
2042 vbios.memory_type = bw_def_gddr5;
2043 vbios.dram_channel_width_in_bits = 64;
2044 vbios.number_of_dram_channels = asic_id.vram_width / vbios.dram_channel_width_in_bits;
2045 vbios.number_of_dram_banks = 8;
2046 vbios.high_yclk = bw_int_to_fixed(1600);
2047 vbios.mid_yclk = bw_int_to_fixed(1600);
2048 vbios.low_yclk = bw_frc_to_fixed(66666, 100);
2049 vbios.low_sclk = bw_int_to_fixed(200);
2050 vbios.mid1_sclk = bw_int_to_fixed(300);
2051 vbios.mid2_sclk = bw_int_to_fixed(300);
2052 vbios.mid3_sclk = bw_int_to_fixed(300);
2053 vbios.mid4_sclk = bw_int_to_fixed(300);
2054 vbios.mid5_sclk = bw_int_to_fixed(300);
2055 vbios.mid6_sclk = bw_int_to_fixed(300);
2056 vbios.high_sclk = bw_frc_to_fixed(62609, 100);
2057 vbios.low_voltage_max_dispclk = bw_int_to_fixed(352);
2058 vbios.mid_voltage_max_dispclk = bw_int_to_fixed(467);
2059 vbios.high_voltage_max_dispclk = bw_int_to_fixed(643);
2060 vbios.low_voltage_max_phyclk = bw_int_to_fixed(540);
2061 vbios.mid_voltage_max_phyclk = bw_int_to_fixed(810);
2062 vbios.high_voltage_max_phyclk = bw_int_to_fixed(810);
2063 vbios.data_return_bus_width = bw_int_to_fixed(32);
2064 vbios.trc = bw_int_to_fixed(50);
2065 vbios.dmifmc_urgent_latency = bw_int_to_fixed(4);
2066 vbios.stutter_self_refresh_exit_latency = bw_frc_to_fixed(153, 10);
2067 vbios.stutter_self_refresh_entry_latency = bw_int_to_fixed(0);
2068 vbios.nbp_state_change_latency = bw_frc_to_fixed(19649, 1000);
2069 vbios.mcifwrmc_urgent_latency = bw_int_to_fixed(10);
2070 vbios.scatter_gather_enable = true;
2071 vbios.down_spread_percentage = bw_frc_to_fixed(5, 10);
2072 vbios.cursor_width = 32;
2073 vbios.average_compression_rate = 4;
2074 vbios.number_of_request_slots_gmc_reserves_for_dmif_per_channel = 256;
2075 vbios.blackout_duration = bw_int_to_fixed(0); /* us */
2076 vbios.maximum_blackout_recovery_time = bw_int_to_fixed(0);
2077
2078 dceip.max_average_percent_of_ideal_port_bw_display_can_use_in_normal_system_operation = 100;
2079 dceip.max_average_percent_of_ideal_drambw_display_can_use_in_normal_system_operation = 100;
2080 dceip.percent_of_ideal_port_bw_received_after_urgent_latency = 100;
2081 dceip.large_cursor = false;
2082 dceip.dmif_request_buffer_size = bw_int_to_fixed(768);
2083 dceip.dmif_pipe_en_fbc_chunk_tracker = false;
2084 dceip.cursor_max_outstanding_group_num = 1;
2085 dceip.lines_interleaved_into_lb = 2;
2086 dceip.chunk_width = 256;
2087 dceip.number_of_graphics_pipes = 3;
2088 dceip.number_of_underlay_pipes = 1;
2089 dceip.low_power_tiling_mode = 0;
2090 dceip.display_write_back_supported = false;
2091 dceip.argb_compression_support = false;
2092 dceip.underlay_vscaler_efficiency6_bit_per_component =
2093 bw_frc_to_fixed(35556, 10000);
2094 dceip.underlay_vscaler_efficiency8_bit_per_component =
2095 bw_frc_to_fixed(34286, 10000);
2096 dceip.underlay_vscaler_efficiency10_bit_per_component =
2097 bw_frc_to_fixed(32, 10);
2098 dceip.underlay_vscaler_efficiency12_bit_per_component =
2099 bw_int_to_fixed(3);
2100 dceip.graphics_vscaler_efficiency6_bit_per_component =
2101 bw_frc_to_fixed(35, 10);
2102 dceip.graphics_vscaler_efficiency8_bit_per_component =
2103 bw_frc_to_fixed(34286, 10000);
2104 dceip.graphics_vscaler_efficiency10_bit_per_component =
2105 bw_frc_to_fixed(32, 10);
2106 dceip.graphics_vscaler_efficiency12_bit_per_component =
2107 bw_int_to_fixed(3);
2108 dceip.alpha_vscaler_efficiency = bw_int_to_fixed(3);
2109 dceip.max_dmif_buffer_allocated = 2;
2110 dceip.graphics_dmif_size = 12288;
2111 dceip.underlay_luma_dmif_size = 19456;
2112 dceip.underlay_chroma_dmif_size = 23552;
2113 dceip.pre_downscaler_enabled = true;
2114 dceip.underlay_downscale_prefetch_enabled = true;
2115 dceip.lb_write_pixels_per_dispclk = bw_int_to_fixed(1);
2116 dceip.lb_size_per_component444 = bw_int_to_fixed(82176);
2117 dceip.graphics_lb_nodownscaling_multi_line_prefetching = false;
2118 dceip.stutter_and_dram_clock_state_change_gated_before_cursor =
2119 bw_int_to_fixed(0);
2120 dceip.underlay420_luma_lb_size_per_component = bw_int_to_fixed(
2121 82176);
2122 dceip.underlay420_chroma_lb_size_per_component =
2123 bw_int_to_fixed(164352);
2124 dceip.underlay422_lb_size_per_component = bw_int_to_fixed(
2125 82176);
2126 dceip.cursor_chunk_width = bw_int_to_fixed(64);
2127 dceip.cursor_dcp_buffer_lines = bw_int_to_fixed(4);
2128 dceip.underlay_maximum_width_efficient_for_tiling =
2129 bw_int_to_fixed(1920);
2130 dceip.underlay_maximum_height_efficient_for_tiling =
2131 bw_int_to_fixed(1080);
2132 dceip.peak_pte_request_to_eviction_ratio_limiting_multiple_displays_or_single_rotated_display =
2133 bw_frc_to_fixed(3, 10);
2134 dceip.peak_pte_request_to_eviction_ratio_limiting_single_display_no_rotation =
2135 bw_int_to_fixed(25);
2136 dceip.minimum_outstanding_pte_request_limit = bw_int_to_fixed(
2137 2);
2138 dceip.maximum_total_outstanding_pte_requests_allowed_by_saw =
2139 bw_int_to_fixed(128);
2140 dceip.limit_excessive_outstanding_dmif_requests = true;
2141 dceip.linear_mode_line_request_alternation_slice =
2142 bw_int_to_fixed(64);
2143 dceip.scatter_gather_lines_of_pte_prefetching_in_linear_mode =
2144 32;
2145 dceip.display_write_back420_luma_mcifwr_buffer_size = 12288;
2146 dceip.display_write_back420_chroma_mcifwr_buffer_size = 8192;
2147 dceip.request_efficiency = bw_frc_to_fixed(8, 10);
2148 dceip.dispclk_per_request = bw_int_to_fixed(2);
2149 dceip.dispclk_ramping_factor = bw_frc_to_fixed(105, 100);
2150 dceip.display_pipe_throughput_factor = bw_frc_to_fixed(105, 100);
2151 dceip.scatter_gather_pte_request_rows_in_tiling_mode = 2;
2152 dceip.mcifwr_all_surfaces_burst_time = bw_int_to_fixed(0); /* todo: this is a bug*/
2153 break;
2154 case BW_CALCS_VERSION_POLARIS10:
2155 /* TODO: Treat VEGAM the same as P10 for now
2156 * Need to tune the para for VEGAM if needed */
2157 case BW_CALCS_VERSION_VEGAM:
2158 vbios.memory_type = bw_def_gddr5;
2159 vbios.dram_channel_width_in_bits = 32;
2160 vbios.number_of_dram_channels = asic_id.vram_width / vbios.dram_channel_width_in_bits;
2161 vbios.number_of_dram_banks = 8;
2162 vbios.high_yclk = bw_int_to_fixed(6000);
2163 vbios.mid_yclk = bw_int_to_fixed(3200);
2164 vbios.low_yclk = bw_int_to_fixed(1000);
2165 vbios.low_sclk = bw_int_to_fixed(300);
2166 vbios.mid1_sclk = bw_int_to_fixed(400);
2167 vbios.mid2_sclk = bw_int_to_fixed(500);
2168 vbios.mid3_sclk = bw_int_to_fixed(600);
2169 vbios.mid4_sclk = bw_int_to_fixed(700);
2170 vbios.mid5_sclk = bw_int_to_fixed(800);
2171 vbios.mid6_sclk = bw_int_to_fixed(974);
2172 vbios.high_sclk = bw_int_to_fixed(1154);
2173 vbios.low_voltage_max_dispclk = bw_int_to_fixed(459);
2174 vbios.mid_voltage_max_dispclk = bw_int_to_fixed(654);
2175 vbios.high_voltage_max_dispclk = bw_int_to_fixed(1108);
2176 vbios.low_voltage_max_phyclk = bw_int_to_fixed(540);
2177 vbios.mid_voltage_max_phyclk = bw_int_to_fixed(810);
2178 vbios.high_voltage_max_phyclk = bw_int_to_fixed(810);
2179 vbios.data_return_bus_width = bw_int_to_fixed(32);
2180 vbios.trc = bw_int_to_fixed(48);
2181 vbios.dmifmc_urgent_latency = bw_int_to_fixed(3);
2182 vbios.stutter_self_refresh_exit_latency = bw_int_to_fixed(5);
2183 vbios.stutter_self_refresh_entry_latency = bw_int_to_fixed(0);
2184 vbios.nbp_state_change_latency = bw_int_to_fixed(45);
2185 vbios.mcifwrmc_urgent_latency = bw_int_to_fixed(10);
2186 vbios.scatter_gather_enable = true;
2187 vbios.down_spread_percentage = bw_frc_to_fixed(5, 10);
2188 vbios.cursor_width = 32;
2189 vbios.average_compression_rate = 4;
2190 vbios.number_of_request_slots_gmc_reserves_for_dmif_per_channel = 256;
2191 vbios.blackout_duration = bw_int_to_fixed(0); /* us */
2192 vbios.maximum_blackout_recovery_time = bw_int_to_fixed(0);
2193
2194 dceip.max_average_percent_of_ideal_port_bw_display_can_use_in_normal_system_operation = 100;
2195 dceip.max_average_percent_of_ideal_drambw_display_can_use_in_normal_system_operation = 100;
2196 dceip.percent_of_ideal_port_bw_received_after_urgent_latency = 100;
2197 dceip.large_cursor = false;
2198 dceip.dmif_request_buffer_size = bw_int_to_fixed(768);
2199 dceip.dmif_pipe_en_fbc_chunk_tracker = false;
2200 dceip.cursor_max_outstanding_group_num = 1;
2201 dceip.lines_interleaved_into_lb = 2;
2202 dceip.chunk_width = 256;
2203 dceip.number_of_graphics_pipes = 6;
2204 dceip.number_of_underlay_pipes = 0;
2205 dceip.low_power_tiling_mode = 0;
2206 dceip.display_write_back_supported = false;
2207 dceip.argb_compression_support = true;
2208 dceip.underlay_vscaler_efficiency6_bit_per_component =
2209 bw_frc_to_fixed(35556, 10000);
2210 dceip.underlay_vscaler_efficiency8_bit_per_component =
2211 bw_frc_to_fixed(34286, 10000);
2212 dceip.underlay_vscaler_efficiency10_bit_per_component =
2213 bw_frc_to_fixed(32, 10);
2214 dceip.underlay_vscaler_efficiency12_bit_per_component =
2215 bw_int_to_fixed(3);
2216 dceip.graphics_vscaler_efficiency6_bit_per_component =
2217 bw_frc_to_fixed(35, 10);
2218 dceip.graphics_vscaler_efficiency8_bit_per_component =
2219 bw_frc_to_fixed(34286, 10000);
2220 dceip.graphics_vscaler_efficiency10_bit_per_component =
2221 bw_frc_to_fixed(32, 10);
2222 dceip.graphics_vscaler_efficiency12_bit_per_component =
2223 bw_int_to_fixed(3);
2224 dceip.alpha_vscaler_efficiency = bw_int_to_fixed(3);
2225 dceip.max_dmif_buffer_allocated = 4;
2226 dceip.graphics_dmif_size = 12288;
2227 dceip.underlay_luma_dmif_size = 19456;
2228 dceip.underlay_chroma_dmif_size = 23552;
2229 dceip.pre_downscaler_enabled = true;
2230 dceip.underlay_downscale_prefetch_enabled = true;
2231 dceip.lb_write_pixels_per_dispclk = bw_int_to_fixed(1);
2232 dceip.lb_size_per_component444 = bw_int_to_fixed(245952);
2233 dceip.graphics_lb_nodownscaling_multi_line_prefetching = true;
2234 dceip.stutter_and_dram_clock_state_change_gated_before_cursor =
2235 bw_int_to_fixed(1);
2236 dceip.underlay420_luma_lb_size_per_component = bw_int_to_fixed(
2237 82176);
2238 dceip.underlay420_chroma_lb_size_per_component =
2239 bw_int_to_fixed(164352);
2240 dceip.underlay422_lb_size_per_component = bw_int_to_fixed(
2241 82176);
2242 dceip.cursor_chunk_width = bw_int_to_fixed(64);
2243 dceip.cursor_dcp_buffer_lines = bw_int_to_fixed(4);
2244 dceip.underlay_maximum_width_efficient_for_tiling =
2245 bw_int_to_fixed(1920);
2246 dceip.underlay_maximum_height_efficient_for_tiling =
2247 bw_int_to_fixed(1080);
2248 dceip.peak_pte_request_to_eviction_ratio_limiting_multiple_displays_or_single_rotated_display =
2249 bw_frc_to_fixed(3, 10);
2250 dceip.peak_pte_request_to_eviction_ratio_limiting_single_display_no_rotation =
2251 bw_int_to_fixed(25);
2252 dceip.minimum_outstanding_pte_request_limit = bw_int_to_fixed(
2253 2);
2254 dceip.maximum_total_outstanding_pte_requests_allowed_by_saw =
2255 bw_int_to_fixed(128);
2256 dceip.limit_excessive_outstanding_dmif_requests = true;
2257 dceip.linear_mode_line_request_alternation_slice =
2258 bw_int_to_fixed(64);
2259 dceip.scatter_gather_lines_of_pte_prefetching_in_linear_mode =
2260 32;
2261 dceip.display_write_back420_luma_mcifwr_buffer_size = 12288;
2262 dceip.display_write_back420_chroma_mcifwr_buffer_size = 8192;
2263 dceip.request_efficiency = bw_frc_to_fixed(8, 10);
2264 dceip.dispclk_per_request = bw_int_to_fixed(2);
2265 dceip.dispclk_ramping_factor = bw_frc_to_fixed(105, 100);
2266 dceip.display_pipe_throughput_factor = bw_frc_to_fixed(105, 100);
2267 dceip.scatter_gather_pte_request_rows_in_tiling_mode = 2;
2268 dceip.mcifwr_all_surfaces_burst_time = bw_int_to_fixed(0);
2269 break;
2270 case BW_CALCS_VERSION_POLARIS11:
2271 vbios.memory_type = bw_def_gddr5;
2272 vbios.dram_channel_width_in_bits = 32;
2273 vbios.number_of_dram_channels = asic_id.vram_width / vbios.dram_channel_width_in_bits;
2274 vbios.number_of_dram_banks = 8;
2275 vbios.high_yclk = bw_int_to_fixed(6000);
2276 vbios.mid_yclk = bw_int_to_fixed(3200);
2277 vbios.low_yclk = bw_int_to_fixed(1000);
2278 vbios.low_sclk = bw_int_to_fixed(300);
2279 vbios.mid1_sclk = bw_int_to_fixed(400);
2280 vbios.mid2_sclk = bw_int_to_fixed(500);
2281 vbios.mid3_sclk = bw_int_to_fixed(600);
2282 vbios.mid4_sclk = bw_int_to_fixed(700);
2283 vbios.mid5_sclk = bw_int_to_fixed(800);
2284 vbios.mid6_sclk = bw_int_to_fixed(974);
2285 vbios.high_sclk = bw_int_to_fixed(1154);
2286 vbios.low_voltage_max_dispclk = bw_int_to_fixed(459);
2287 vbios.mid_voltage_max_dispclk = bw_int_to_fixed(654);
2288 vbios.high_voltage_max_dispclk = bw_int_to_fixed(1108);
2289 vbios.low_voltage_max_phyclk = bw_int_to_fixed(540);
2290 vbios.mid_voltage_max_phyclk = bw_int_to_fixed(810);
2291 vbios.high_voltage_max_phyclk = bw_int_to_fixed(810);
2292 vbios.data_return_bus_width = bw_int_to_fixed(32);
2293 vbios.trc = bw_int_to_fixed(48);
2294 if (vbios.number_of_dram_channels == 2) // 64-bit
2295 vbios.dmifmc_urgent_latency = bw_int_to_fixed(4);
2296 else
2297 vbios.dmifmc_urgent_latency = bw_int_to_fixed(3);
2298 vbios.stutter_self_refresh_exit_latency = bw_int_to_fixed(5);
2299 vbios.stutter_self_refresh_entry_latency = bw_int_to_fixed(0);
2300 vbios.nbp_state_change_latency = bw_int_to_fixed(45);
2301 vbios.mcifwrmc_urgent_latency = bw_int_to_fixed(10);
2302 vbios.scatter_gather_enable = true;
2303 vbios.down_spread_percentage = bw_frc_to_fixed(5, 10);
2304 vbios.cursor_width = 32;
2305 vbios.average_compression_rate = 4;
2306 vbios.number_of_request_slots_gmc_reserves_for_dmif_per_channel = 256;
2307 vbios.blackout_duration = bw_int_to_fixed(0); /* us */
2308 vbios.maximum_blackout_recovery_time = bw_int_to_fixed(0);
2309
2310 dceip.max_average_percent_of_ideal_port_bw_display_can_use_in_normal_system_operation = 100;
2311 dceip.max_average_percent_of_ideal_drambw_display_can_use_in_normal_system_operation = 100;
2312 dceip.percent_of_ideal_port_bw_received_after_urgent_latency = 100;
2313 dceip.large_cursor = false;
2314 dceip.dmif_request_buffer_size = bw_int_to_fixed(768);
2315 dceip.dmif_pipe_en_fbc_chunk_tracker = false;
2316 dceip.cursor_max_outstanding_group_num = 1;
2317 dceip.lines_interleaved_into_lb = 2;
2318 dceip.chunk_width = 256;
2319 dceip.number_of_graphics_pipes = 5;
2320 dceip.number_of_underlay_pipes = 0;
2321 dceip.low_power_tiling_mode = 0;
2322 dceip.display_write_back_supported = false;
2323 dceip.argb_compression_support = true;
2324 dceip.underlay_vscaler_efficiency6_bit_per_component =
2325 bw_frc_to_fixed(35556, 10000);
2326 dceip.underlay_vscaler_efficiency8_bit_per_component =
2327 bw_frc_to_fixed(34286, 10000);
2328 dceip.underlay_vscaler_efficiency10_bit_per_component =
2329 bw_frc_to_fixed(32, 10);
2330 dceip.underlay_vscaler_efficiency12_bit_per_component =
2331 bw_int_to_fixed(3);
2332 dceip.graphics_vscaler_efficiency6_bit_per_component =
2333 bw_frc_to_fixed(35, 10);
2334 dceip.graphics_vscaler_efficiency8_bit_per_component =
2335 bw_frc_to_fixed(34286, 10000);
2336 dceip.graphics_vscaler_efficiency10_bit_per_component =
2337 bw_frc_to_fixed(32, 10);
2338 dceip.graphics_vscaler_efficiency12_bit_per_component =
2339 bw_int_to_fixed(3);
2340 dceip.alpha_vscaler_efficiency = bw_int_to_fixed(3);
2341 dceip.max_dmif_buffer_allocated = 4;
2342 dceip.graphics_dmif_size = 12288;
2343 dceip.underlay_luma_dmif_size = 19456;
2344 dceip.underlay_chroma_dmif_size = 23552;
2345 dceip.pre_downscaler_enabled = true;
2346 dceip.underlay_downscale_prefetch_enabled = true;
2347 dceip.lb_write_pixels_per_dispclk = bw_int_to_fixed(1);
2348 dceip.lb_size_per_component444 = bw_int_to_fixed(245952);
2349 dceip.graphics_lb_nodownscaling_multi_line_prefetching = true;
2350 dceip.stutter_and_dram_clock_state_change_gated_before_cursor =
2351 bw_int_to_fixed(1);
2352 dceip.underlay420_luma_lb_size_per_component = bw_int_to_fixed(
2353 82176);
2354 dceip.underlay420_chroma_lb_size_per_component =
2355 bw_int_to_fixed(164352);
2356 dceip.underlay422_lb_size_per_component = bw_int_to_fixed(
2357 82176);
2358 dceip.cursor_chunk_width = bw_int_to_fixed(64);
2359 dceip.cursor_dcp_buffer_lines = bw_int_to_fixed(4);
2360 dceip.underlay_maximum_width_efficient_for_tiling =
2361 bw_int_to_fixed(1920);
2362 dceip.underlay_maximum_height_efficient_for_tiling =
2363 bw_int_to_fixed(1080);
2364 dceip.peak_pte_request_to_eviction_ratio_limiting_multiple_displays_or_single_rotated_display =
2365 bw_frc_to_fixed(3, 10);
2366 dceip.peak_pte_request_to_eviction_ratio_limiting_single_display_no_rotation =
2367 bw_int_to_fixed(25);
2368 dceip.minimum_outstanding_pte_request_limit = bw_int_to_fixed(
2369 2);
2370 dceip.maximum_total_outstanding_pte_requests_allowed_by_saw =
2371 bw_int_to_fixed(128);
2372 dceip.limit_excessive_outstanding_dmif_requests = true;
2373 dceip.linear_mode_line_request_alternation_slice =
2374 bw_int_to_fixed(64);
2375 dceip.scatter_gather_lines_of_pte_prefetching_in_linear_mode =
2376 32;
2377 dceip.display_write_back420_luma_mcifwr_buffer_size = 12288;
2378 dceip.display_write_back420_chroma_mcifwr_buffer_size = 8192;
2379 dceip.request_efficiency = bw_frc_to_fixed(8, 10);
2380 dceip.dispclk_per_request = bw_int_to_fixed(2);
2381 dceip.dispclk_ramping_factor = bw_frc_to_fixed(105, 100);
2382 dceip.display_pipe_throughput_factor = bw_frc_to_fixed(105, 100);
2383 dceip.scatter_gather_pte_request_rows_in_tiling_mode = 2;
2384 dceip.mcifwr_all_surfaces_burst_time = bw_int_to_fixed(0);
2385 break;
2386 case BW_CALCS_VERSION_POLARIS12:
2387 vbios.memory_type = bw_def_gddr5;
2388 vbios.dram_channel_width_in_bits = 32;
2389 vbios.number_of_dram_channels = asic_id.vram_width / vbios.dram_channel_width_in_bits;
2390 vbios.number_of_dram_banks = 8;
2391 vbios.high_yclk = bw_int_to_fixed(6000);
2392 vbios.mid_yclk = bw_int_to_fixed(3200);
2393 vbios.low_yclk = bw_int_to_fixed(1000);
2394 vbios.low_sclk = bw_int_to_fixed(678);
2395 vbios.mid1_sclk = bw_int_to_fixed(864);
2396 vbios.mid2_sclk = bw_int_to_fixed(900);
2397 vbios.mid3_sclk = bw_int_to_fixed(920);
2398 vbios.mid4_sclk = bw_int_to_fixed(940);
2399 vbios.mid5_sclk = bw_int_to_fixed(960);
2400 vbios.mid6_sclk = bw_int_to_fixed(980);
2401 vbios.high_sclk = bw_int_to_fixed(1049);
2402 vbios.low_voltage_max_dispclk = bw_int_to_fixed(459);
2403 vbios.mid_voltage_max_dispclk = bw_int_to_fixed(654);
2404 vbios.high_voltage_max_dispclk = bw_int_to_fixed(1108);
2405 vbios.low_voltage_max_phyclk = bw_int_to_fixed(540);
2406 vbios.mid_voltage_max_phyclk = bw_int_to_fixed(810);
2407 vbios.high_voltage_max_phyclk = bw_int_to_fixed(810);
2408 vbios.data_return_bus_width = bw_int_to_fixed(32);
2409 vbios.trc = bw_int_to_fixed(48);
2410 if (vbios.number_of_dram_channels == 2) // 64-bit
2411 vbios.dmifmc_urgent_latency = bw_int_to_fixed(4);
2412 else
2413 vbios.dmifmc_urgent_latency = bw_int_to_fixed(3);
2414 vbios.stutter_self_refresh_exit_latency = bw_int_to_fixed(5);
2415 vbios.stutter_self_refresh_entry_latency = bw_int_to_fixed(0);
2416 vbios.nbp_state_change_latency = bw_int_to_fixed(250);
2417 vbios.mcifwrmc_urgent_latency = bw_int_to_fixed(10);
2418 vbios.scatter_gather_enable = false;
2419 vbios.down_spread_percentage = bw_frc_to_fixed(5, 10);
2420 vbios.cursor_width = 32;
2421 vbios.average_compression_rate = 4;
2422 vbios.number_of_request_slots_gmc_reserves_for_dmif_per_channel = 256;
2423 vbios.blackout_duration = bw_int_to_fixed(0); /* us */
2424 vbios.maximum_blackout_recovery_time = bw_int_to_fixed(0);
2425
2426 dceip.max_average_percent_of_ideal_port_bw_display_can_use_in_normal_system_operation = 100;
2427 dceip.max_average_percent_of_ideal_drambw_display_can_use_in_normal_system_operation = 100;
2428 dceip.percent_of_ideal_port_bw_received_after_urgent_latency = 100;
2429 dceip.large_cursor = false;
2430 dceip.dmif_request_buffer_size = bw_int_to_fixed(768);
2431 dceip.dmif_pipe_en_fbc_chunk_tracker = false;
2432 dceip.cursor_max_outstanding_group_num = 1;
2433 dceip.lines_interleaved_into_lb = 2;
2434 dceip.chunk_width = 256;
2435 dceip.number_of_graphics_pipes = 5;
2436 dceip.number_of_underlay_pipes = 0;
2437 dceip.low_power_tiling_mode = 0;
2438 dceip.display_write_back_supported = true;
2439 dceip.argb_compression_support = true;
2440 dceip.underlay_vscaler_efficiency6_bit_per_component =
2441 bw_frc_to_fixed(35556, 10000);
2442 dceip.underlay_vscaler_efficiency8_bit_per_component =
2443 bw_frc_to_fixed(34286, 10000);
2444 dceip.underlay_vscaler_efficiency10_bit_per_component =
2445 bw_frc_to_fixed(32, 10);
2446 dceip.underlay_vscaler_efficiency12_bit_per_component =
2447 bw_int_to_fixed(3);
2448 dceip.graphics_vscaler_efficiency6_bit_per_component =
2449 bw_frc_to_fixed(35, 10);
2450 dceip.graphics_vscaler_efficiency8_bit_per_component =
2451 bw_frc_to_fixed(34286, 10000);
2452 dceip.graphics_vscaler_efficiency10_bit_per_component =
2453 bw_frc_to_fixed(32, 10);
2454 dceip.graphics_vscaler_efficiency12_bit_per_component =
2455 bw_int_to_fixed(3);
2456 dceip.alpha_vscaler_efficiency = bw_int_to_fixed(3);
2457 dceip.max_dmif_buffer_allocated = 4;
2458 dceip.graphics_dmif_size = 12288;
2459 dceip.underlay_luma_dmif_size = 19456;
2460 dceip.underlay_chroma_dmif_size = 23552;
2461 dceip.pre_downscaler_enabled = true;
2462 dceip.underlay_downscale_prefetch_enabled = true;
2463 dceip.lb_write_pixels_per_dispclk = bw_int_to_fixed(1);
2464 dceip.lb_size_per_component444 = bw_int_to_fixed(245952);
2465 dceip.graphics_lb_nodownscaling_multi_line_prefetching = true;
2466 dceip.stutter_and_dram_clock_state_change_gated_before_cursor =
2467 bw_int_to_fixed(1);
2468 dceip.underlay420_luma_lb_size_per_component = bw_int_to_fixed(
2469 82176);
2470 dceip.underlay420_chroma_lb_size_per_component =
2471 bw_int_to_fixed(164352);
2472 dceip.underlay422_lb_size_per_component = bw_int_to_fixed(
2473 82176);
2474 dceip.cursor_chunk_width = bw_int_to_fixed(64);
2475 dceip.cursor_dcp_buffer_lines = bw_int_to_fixed(4);
2476 dceip.underlay_maximum_width_efficient_for_tiling =
2477 bw_int_to_fixed(1920);
2478 dceip.underlay_maximum_height_efficient_for_tiling =
2479 bw_int_to_fixed(1080);
2480 dceip.peak_pte_request_to_eviction_ratio_limiting_multiple_displays_or_single_rotated_display =
2481 bw_frc_to_fixed(3, 10);
2482 dceip.peak_pte_request_to_eviction_ratio_limiting_single_display_no_rotation =
2483 bw_int_to_fixed(25);
2484 dceip.minimum_outstanding_pte_request_limit = bw_int_to_fixed(
2485 2);
2486 dceip.maximum_total_outstanding_pte_requests_allowed_by_saw =
2487 bw_int_to_fixed(128);
2488 dceip.limit_excessive_outstanding_dmif_requests = true;
2489 dceip.linear_mode_line_request_alternation_slice =
2490 bw_int_to_fixed(64);
2491 dceip.scatter_gather_lines_of_pte_prefetching_in_linear_mode =
2492 32;
2493 dceip.display_write_back420_luma_mcifwr_buffer_size = 12288;
2494 dceip.display_write_back420_chroma_mcifwr_buffer_size = 8192;
2495 dceip.request_efficiency = bw_frc_to_fixed(8, 10);
2496 dceip.dispclk_per_request = bw_int_to_fixed(2);
2497 dceip.dispclk_ramping_factor = bw_frc_to_fixed(105, 100);
2498 dceip.display_pipe_throughput_factor = bw_frc_to_fixed(105, 100);
2499 dceip.scatter_gather_pte_request_rows_in_tiling_mode = 2;
2500 dceip.mcifwr_all_surfaces_burst_time = bw_int_to_fixed(0);
2501 break;
2502 case BW_CALCS_VERSION_STONEY:
2503 vbios.memory_type = bw_def_gddr5;
2504 vbios.dram_channel_width_in_bits = 64;
2505 vbios.number_of_dram_channels = asic_id.vram_width / vbios.dram_channel_width_in_bits;
2506 vbios.number_of_dram_banks = 8;
2507 vbios.high_yclk = bw_int_to_fixed(1866);
2508 vbios.mid_yclk = bw_int_to_fixed(1866);
2509 vbios.low_yclk = bw_int_to_fixed(1333);
2510 vbios.low_sclk = bw_int_to_fixed(200);
2511 vbios.mid1_sclk = bw_int_to_fixed(600);
2512 vbios.mid2_sclk = bw_int_to_fixed(600);
2513 vbios.mid3_sclk = bw_int_to_fixed(600);
2514 vbios.mid4_sclk = bw_int_to_fixed(600);
2515 vbios.mid5_sclk = bw_int_to_fixed(600);
2516 vbios.mid6_sclk = bw_int_to_fixed(600);
2517 vbios.high_sclk = bw_int_to_fixed(800);
2518 vbios.low_voltage_max_dispclk = bw_int_to_fixed(352);
2519 vbios.mid_voltage_max_dispclk = bw_int_to_fixed(467);
2520 vbios.high_voltage_max_dispclk = bw_int_to_fixed(643);
2521 vbios.low_voltage_max_phyclk = bw_int_to_fixed(540);
2522 vbios.mid_voltage_max_phyclk = bw_int_to_fixed(810);
2523 vbios.high_voltage_max_phyclk = bw_int_to_fixed(810);
2524 vbios.data_return_bus_width = bw_int_to_fixed(32);
2525 vbios.trc = bw_int_to_fixed(50);
2526 vbios.dmifmc_urgent_latency = bw_int_to_fixed(4);
2527 vbios.stutter_self_refresh_exit_latency = bw_frc_to_fixed(158, 10);
2528 vbios.stutter_self_refresh_entry_latency = bw_int_to_fixed(0);
2529 vbios.nbp_state_change_latency = bw_frc_to_fixed(2008, 100);
2530 vbios.mcifwrmc_urgent_latency = bw_int_to_fixed(10);
2531 vbios.scatter_gather_enable = true;
2532 vbios.down_spread_percentage = bw_frc_to_fixed(5, 10);
2533 vbios.cursor_width = 32;
2534 vbios.average_compression_rate = 4;
2535 vbios.number_of_request_slots_gmc_reserves_for_dmif_per_channel = 256;
2536 vbios.blackout_duration = bw_int_to_fixed(0); /* us */
2537 vbios.maximum_blackout_recovery_time = bw_int_to_fixed(0);
2538
2539 dceip.max_average_percent_of_ideal_port_bw_display_can_use_in_normal_system_operation = 100;
2540 dceip.max_average_percent_of_ideal_drambw_display_can_use_in_normal_system_operation = 100;
2541 dceip.percent_of_ideal_port_bw_received_after_urgent_latency = 100;
2542 dceip.large_cursor = false;
2543 dceip.dmif_request_buffer_size = bw_int_to_fixed(768);
2544 dceip.dmif_pipe_en_fbc_chunk_tracker = false;
2545 dceip.cursor_max_outstanding_group_num = 1;
2546 dceip.lines_interleaved_into_lb = 2;
2547 dceip.chunk_width = 256;
2548 dceip.number_of_graphics_pipes = 2;
2549 dceip.number_of_underlay_pipes = 1;
2550 dceip.low_power_tiling_mode = 0;
2551 dceip.display_write_back_supported = false;
2552 dceip.argb_compression_support = true;
2553 dceip.underlay_vscaler_efficiency6_bit_per_component =
2554 bw_frc_to_fixed(35556, 10000);
2555 dceip.underlay_vscaler_efficiency8_bit_per_component =
2556 bw_frc_to_fixed(34286, 10000);
2557 dceip.underlay_vscaler_efficiency10_bit_per_component =
2558 bw_frc_to_fixed(32, 10);
2559 dceip.underlay_vscaler_efficiency12_bit_per_component =
2560 bw_int_to_fixed(3);
2561 dceip.graphics_vscaler_efficiency6_bit_per_component =
2562 bw_frc_to_fixed(35, 10);
2563 dceip.graphics_vscaler_efficiency8_bit_per_component =
2564 bw_frc_to_fixed(34286, 10000);
2565 dceip.graphics_vscaler_efficiency10_bit_per_component =
2566 bw_frc_to_fixed(32, 10);
2567 dceip.graphics_vscaler_efficiency12_bit_per_component =
2568 bw_int_to_fixed(3);
2569 dceip.alpha_vscaler_efficiency = bw_int_to_fixed(3);
2570 dceip.max_dmif_buffer_allocated = 2;
2571 dceip.graphics_dmif_size = 12288;
2572 dceip.underlay_luma_dmif_size = 19456;
2573 dceip.underlay_chroma_dmif_size = 23552;
2574 dceip.pre_downscaler_enabled = true;
2575 dceip.underlay_downscale_prefetch_enabled = true;
2576 dceip.lb_write_pixels_per_dispclk = bw_int_to_fixed(1);
2577 dceip.lb_size_per_component444 = bw_int_to_fixed(82176);
2578 dceip.graphics_lb_nodownscaling_multi_line_prefetching = false;
2579 dceip.stutter_and_dram_clock_state_change_gated_before_cursor =
2580 bw_int_to_fixed(0);
2581 dceip.underlay420_luma_lb_size_per_component = bw_int_to_fixed(
2582 82176);
2583 dceip.underlay420_chroma_lb_size_per_component =
2584 bw_int_to_fixed(164352);
2585 dceip.underlay422_lb_size_per_component = bw_int_to_fixed(
2586 82176);
2587 dceip.cursor_chunk_width = bw_int_to_fixed(64);
2588 dceip.cursor_dcp_buffer_lines = bw_int_to_fixed(4);
2589 dceip.underlay_maximum_width_efficient_for_tiling =
2590 bw_int_to_fixed(1920);
2591 dceip.underlay_maximum_height_efficient_for_tiling =
2592 bw_int_to_fixed(1080);
2593 dceip.peak_pte_request_to_eviction_ratio_limiting_multiple_displays_or_single_rotated_display =
2594 bw_frc_to_fixed(3, 10);
2595 dceip.peak_pte_request_to_eviction_ratio_limiting_single_display_no_rotation =
2596 bw_int_to_fixed(25);
2597 dceip.minimum_outstanding_pte_request_limit = bw_int_to_fixed(
2598 2);
2599 dceip.maximum_total_outstanding_pte_requests_allowed_by_saw =
2600 bw_int_to_fixed(128);
2601 dceip.limit_excessive_outstanding_dmif_requests = true;
2602 dceip.linear_mode_line_request_alternation_slice =
2603 bw_int_to_fixed(64);
2604 dceip.scatter_gather_lines_of_pte_prefetching_in_linear_mode =
2605 32;
2606 dceip.display_write_back420_luma_mcifwr_buffer_size = 12288;
2607 dceip.display_write_back420_chroma_mcifwr_buffer_size = 8192;
2608 dceip.request_efficiency = bw_frc_to_fixed(8, 10);
2609 dceip.dispclk_per_request = bw_int_to_fixed(2);
2610 dceip.dispclk_ramping_factor = bw_frc_to_fixed(105, 100);
2611 dceip.display_pipe_throughput_factor = bw_frc_to_fixed(105, 100);
2612 dceip.scatter_gather_pte_request_rows_in_tiling_mode = 2;
2613 dceip.mcifwr_all_surfaces_burst_time = bw_int_to_fixed(0);
2614 break;
2615 case BW_CALCS_VERSION_VEGA10:
2616 vbios.memory_type = bw_def_hbm;
2617 vbios.dram_channel_width_in_bits = 128;
2618 vbios.number_of_dram_channels = asic_id.vram_width / vbios.dram_channel_width_in_bits;
2619 vbios.number_of_dram_banks = 16;
2620 vbios.high_yclk = bw_int_to_fixed(2400);
2621 vbios.mid_yclk = bw_int_to_fixed(1700);
2622 vbios.low_yclk = bw_int_to_fixed(1000);
2623 vbios.low_sclk = bw_int_to_fixed(300);
2624 vbios.mid1_sclk = bw_int_to_fixed(350);
2625 vbios.mid2_sclk = bw_int_to_fixed(400);
2626 vbios.mid3_sclk = bw_int_to_fixed(500);
2627 vbios.mid4_sclk = bw_int_to_fixed(600);
2628 vbios.mid5_sclk = bw_int_to_fixed(700);
2629 vbios.mid6_sclk = bw_int_to_fixed(760);
2630 vbios.high_sclk = bw_int_to_fixed(776);
2631 vbios.low_voltage_max_dispclk = bw_int_to_fixed(460);
2632 vbios.mid_voltage_max_dispclk = bw_int_to_fixed(670);
2633 vbios.high_voltage_max_dispclk = bw_int_to_fixed(1133);
2634 vbios.low_voltage_max_phyclk = bw_int_to_fixed(540);
2635 vbios.mid_voltage_max_phyclk = bw_int_to_fixed(810);
2636 vbios.high_voltage_max_phyclk = bw_int_to_fixed(810);
2637 vbios.data_return_bus_width = bw_int_to_fixed(32);
2638 vbios.trc = bw_int_to_fixed(48);
2639 vbios.dmifmc_urgent_latency = bw_int_to_fixed(3);
2640 vbios.stutter_self_refresh_exit_latency = bw_frc_to_fixed(75, 10);
2641 vbios.stutter_self_refresh_entry_latency = bw_frc_to_fixed(19, 10);
2642 vbios.nbp_state_change_latency = bw_int_to_fixed(39);
2643 vbios.mcifwrmc_urgent_latency = bw_int_to_fixed(10);
2644 vbios.scatter_gather_enable = false;
2645 vbios.down_spread_percentage = bw_frc_to_fixed(5, 10);
2646 vbios.cursor_width = 32;
2647 vbios.average_compression_rate = 4;
2648 vbios.number_of_request_slots_gmc_reserves_for_dmif_per_channel = 8;
2649 vbios.blackout_duration = bw_int_to_fixed(0); /* us */
2650 vbios.maximum_blackout_recovery_time = bw_int_to_fixed(0);
2651
2652 dceip.max_average_percent_of_ideal_port_bw_display_can_use_in_normal_system_operation = 100;
2653 dceip.max_average_percent_of_ideal_drambw_display_can_use_in_normal_system_operation = 100;
2654 dceip.percent_of_ideal_port_bw_received_after_urgent_latency = 100;
2655 dceip.large_cursor = false;
2656 dceip.dmif_request_buffer_size = bw_int_to_fixed(2304);
2657 dceip.dmif_pipe_en_fbc_chunk_tracker = true;
2658 dceip.cursor_max_outstanding_group_num = 1;
2659 dceip.lines_interleaved_into_lb = 2;
2660 dceip.chunk_width = 256;
2661 dceip.number_of_graphics_pipes = 6;
2662 dceip.number_of_underlay_pipes = 0;
2663 dceip.low_power_tiling_mode = 0;
2664 dceip.display_write_back_supported = true;
2665 dceip.argb_compression_support = true;
2666 dceip.underlay_vscaler_efficiency6_bit_per_component =
2667 bw_frc_to_fixed(35556, 10000);
2668 dceip.underlay_vscaler_efficiency8_bit_per_component =
2669 bw_frc_to_fixed(34286, 10000);
2670 dceip.underlay_vscaler_efficiency10_bit_per_component =
2671 bw_frc_to_fixed(32, 10);
2672 dceip.underlay_vscaler_efficiency12_bit_per_component =
2673 bw_int_to_fixed(3);
2674 dceip.graphics_vscaler_efficiency6_bit_per_component =
2675 bw_frc_to_fixed(35, 10);
2676 dceip.graphics_vscaler_efficiency8_bit_per_component =
2677 bw_frc_to_fixed(34286, 10000);
2678 dceip.graphics_vscaler_efficiency10_bit_per_component =
2679 bw_frc_to_fixed(32, 10);
2680 dceip.graphics_vscaler_efficiency12_bit_per_component =
2681 bw_int_to_fixed(3);
2682 dceip.alpha_vscaler_efficiency = bw_int_to_fixed(3);
2683 dceip.max_dmif_buffer_allocated = 4;
2684 dceip.graphics_dmif_size = 24576;
2685 dceip.underlay_luma_dmif_size = 19456;
2686 dceip.underlay_chroma_dmif_size = 23552;
2687 dceip.pre_downscaler_enabled = true;
2688 dceip.underlay_downscale_prefetch_enabled = false;
2689 dceip.lb_write_pixels_per_dispclk = bw_int_to_fixed(1);
2690 dceip.lb_size_per_component444 = bw_int_to_fixed(245952);
2691 dceip.graphics_lb_nodownscaling_multi_line_prefetching = true;
2692 dceip.stutter_and_dram_clock_state_change_gated_before_cursor =
2693 bw_int_to_fixed(1);
2694 dceip.underlay420_luma_lb_size_per_component = bw_int_to_fixed(
2695 82176);
2696 dceip.underlay420_chroma_lb_size_per_component =
2697 bw_int_to_fixed(164352);
2698 dceip.underlay422_lb_size_per_component = bw_int_to_fixed(
2699 82176);
2700 dceip.cursor_chunk_width = bw_int_to_fixed(64);
2701 dceip.cursor_dcp_buffer_lines = bw_int_to_fixed(4);
2702 dceip.underlay_maximum_width_efficient_for_tiling =
2703 bw_int_to_fixed(1920);
2704 dceip.underlay_maximum_height_efficient_for_tiling =
2705 bw_int_to_fixed(1080);
2706 dceip.peak_pte_request_to_eviction_ratio_limiting_multiple_displays_or_single_rotated_display =
2707 bw_frc_to_fixed(3, 10);
2708 dceip.peak_pte_request_to_eviction_ratio_limiting_single_display_no_rotation =
2709 bw_int_to_fixed(25);
2710 dceip.minimum_outstanding_pte_request_limit = bw_int_to_fixed(
2711 2);
2712 dceip.maximum_total_outstanding_pte_requests_allowed_by_saw =
2713 bw_int_to_fixed(128);
2714 dceip.limit_excessive_outstanding_dmif_requests = true;
2715 dceip.linear_mode_line_request_alternation_slice =
2716 bw_int_to_fixed(64);
2717 dceip.scatter_gather_lines_of_pte_prefetching_in_linear_mode =
2718 32;
2719 dceip.display_write_back420_luma_mcifwr_buffer_size = 12288;
2720 dceip.display_write_back420_chroma_mcifwr_buffer_size = 8192;
2721 dceip.request_efficiency = bw_frc_to_fixed(8, 10);
2722 dceip.dispclk_per_request = bw_int_to_fixed(2);
2723 dceip.dispclk_ramping_factor = bw_frc_to_fixed(105, 100);
2724 dceip.display_pipe_throughput_factor = bw_frc_to_fixed(105, 100);
2725 dceip.scatter_gather_pte_request_rows_in_tiling_mode = 2;
2726 dceip.mcifwr_all_surfaces_burst_time = bw_int_to_fixed(0);
2727 break;
2728 default:
2729 break;
2730 }
2731 *bw_dceip = dceip;
2732 *bw_vbios = vbios;
2733
2734 }
2735
2736 /**
2737 * Compare calculated (required) clocks against the clocks available at
2738 * maximum voltage (max Performance Level).
2739 */
is_display_configuration_supported(const struct bw_calcs_vbios * vbios,const struct dce_bw_output * calcs_output)2740 static bool is_display_configuration_supported(
2741 const struct bw_calcs_vbios *vbios,
2742 const struct dce_bw_output *calcs_output)
2743 {
2744 uint32_t int_max_clk;
2745
2746 int_max_clk = bw_fixed_to_int(vbios->high_voltage_max_dispclk);
2747 int_max_clk *= 1000; /* MHz to kHz */
2748 if (calcs_output->dispclk_khz > int_max_clk)
2749 return false;
2750
2751 int_max_clk = bw_fixed_to_int(vbios->high_sclk);
2752 int_max_clk *= 1000; /* MHz to kHz */
2753 if (calcs_output->sclk_khz > int_max_clk)
2754 return false;
2755
2756 return true;
2757 }
2758
populate_initial_data(const struct pipe_ctx pipe[],int pipe_count,struct bw_calcs_data * data)2759 static void populate_initial_data(
2760 const struct pipe_ctx pipe[], int pipe_count, struct bw_calcs_data *data)
2761 {
2762 int i, j;
2763 int num_displays = 0;
2764
2765 data->underlay_surface_type = bw_def_420;
2766 data->panning_and_bezel_adjustment = bw_def_none;
2767 data->graphics_lb_bpc = 10;
2768 data->underlay_lb_bpc = 8;
2769 data->underlay_tiling_mode = bw_def_tiled;
2770 data->graphics_tiling_mode = bw_def_tiled;
2771 data->underlay_micro_tile_mode = bw_def_display_micro_tiling;
2772 data->graphics_micro_tile_mode = bw_def_display_micro_tiling;
2773 data->increase_voltage_to_support_mclk_switch = true;
2774
2775 /* Pipes with underlay first */
2776 for (i = 0; i < pipe_count; i++) {
2777 if (!pipe[i].stream || !pipe[i].bottom_pipe)
2778 continue;
2779
2780 ASSERT(pipe[i].plane_state);
2781
2782 if (num_displays == 0) {
2783 if (!pipe[i].plane_state->visible)
2784 data->d0_underlay_mode = bw_def_underlay_only;
2785 else
2786 data->d0_underlay_mode = bw_def_blend;
2787 } else {
2788 if (!pipe[i].plane_state->visible)
2789 data->d1_underlay_mode = bw_def_underlay_only;
2790 else
2791 data->d1_underlay_mode = bw_def_blend;
2792 }
2793
2794 data->fbc_en[num_displays + 4] = false;
2795 data->lpt_en[num_displays + 4] = false;
2796 data->h_total[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->timing.h_total);
2797 data->v_total[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->timing.v_total);
2798 data->pixel_rate[num_displays + 4] = bw_frc_to_fixed(pipe[i].stream->timing.pix_clk_100hz, 10000);
2799 data->src_width[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.viewport.width);
2800 data->pitch_in_pixels[num_displays + 4] = data->src_width[num_displays + 4];
2801 data->src_height[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.viewport.height);
2802 data->h_taps[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.taps.h_taps);
2803 data->v_taps[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.taps.v_taps);
2804 data->h_scale_ratio[num_displays + 4] = fixed31_32_to_bw_fixed(pipe[i].plane_res.scl_data.ratios.horz.value);
2805 data->v_scale_ratio[num_displays + 4] = fixed31_32_to_bw_fixed(pipe[i].plane_res.scl_data.ratios.vert.value);
2806 switch (pipe[i].plane_state->rotation) {
2807 case ROTATION_ANGLE_0:
2808 data->rotation_angle[num_displays + 4] = bw_int_to_fixed(0);
2809 break;
2810 case ROTATION_ANGLE_90:
2811 data->rotation_angle[num_displays + 4] = bw_int_to_fixed(90);
2812 break;
2813 case ROTATION_ANGLE_180:
2814 data->rotation_angle[num_displays + 4] = bw_int_to_fixed(180);
2815 break;
2816 case ROTATION_ANGLE_270:
2817 data->rotation_angle[num_displays + 4] = bw_int_to_fixed(270);
2818 break;
2819 default:
2820 break;
2821 }
2822 switch (pipe[i].plane_state->format) {
2823 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
2824 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
2825 case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
2826 data->bytes_per_pixel[num_displays + 4] = 2;
2827 break;
2828 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
2829 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
2830 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
2831 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
2832 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS:
2833 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
2834 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
2835 data->bytes_per_pixel[num_displays + 4] = 4;
2836 break;
2837 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
2838 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
2839 data->bytes_per_pixel[num_displays + 4] = 8;
2840 break;
2841 default:
2842 data->bytes_per_pixel[num_displays + 4] = 4;
2843 break;
2844 }
2845 data->interlace_mode[num_displays + 4] = false;
2846 data->stereo_mode[num_displays + 4] = bw_def_mono;
2847
2848
2849 for (j = 0; j < 2; j++) {
2850 data->fbc_en[num_displays * 2 + j] = false;
2851 data->lpt_en[num_displays * 2 + j] = false;
2852
2853 data->src_height[num_displays * 2 + j] = bw_int_to_fixed(pipe[i].bottom_pipe->plane_res.scl_data.viewport.height);
2854 data->src_width[num_displays * 2 + j] = bw_int_to_fixed(pipe[i].bottom_pipe->plane_res.scl_data.viewport.width);
2855 data->pitch_in_pixels[num_displays * 2 + j] = bw_int_to_fixed(
2856 pipe[i].bottom_pipe->plane_state->plane_size.surface_pitch);
2857 data->h_taps[num_displays * 2 + j] = bw_int_to_fixed(pipe[i].bottom_pipe->plane_res.scl_data.taps.h_taps);
2858 data->v_taps[num_displays * 2 + j] = bw_int_to_fixed(pipe[i].bottom_pipe->plane_res.scl_data.taps.v_taps);
2859 data->h_scale_ratio[num_displays * 2 + j] = fixed31_32_to_bw_fixed(
2860 pipe[i].bottom_pipe->plane_res.scl_data.ratios.horz.value);
2861 data->v_scale_ratio[num_displays * 2 + j] = fixed31_32_to_bw_fixed(
2862 pipe[i].bottom_pipe->plane_res.scl_data.ratios.vert.value);
2863 switch (pipe[i].bottom_pipe->plane_state->rotation) {
2864 case ROTATION_ANGLE_0:
2865 data->rotation_angle[num_displays * 2 + j] = bw_int_to_fixed(0);
2866 break;
2867 case ROTATION_ANGLE_90:
2868 data->rotation_angle[num_displays * 2 + j] = bw_int_to_fixed(90);
2869 break;
2870 case ROTATION_ANGLE_180:
2871 data->rotation_angle[num_displays * 2 + j] = bw_int_to_fixed(180);
2872 break;
2873 case ROTATION_ANGLE_270:
2874 data->rotation_angle[num_displays * 2 + j] = bw_int_to_fixed(270);
2875 break;
2876 default:
2877 break;
2878 }
2879 data->stereo_mode[num_displays * 2 + j] = bw_def_mono;
2880 }
2881
2882 num_displays++;
2883 }
2884
2885 /* Pipes without underlay after */
2886 for (i = 0; i < pipe_count; i++) {
2887 unsigned int pixel_clock_100hz;
2888 if (!pipe[i].stream || pipe[i].bottom_pipe)
2889 continue;
2890
2891
2892 data->fbc_en[num_displays + 4] = false;
2893 data->lpt_en[num_displays + 4] = false;
2894 data->h_total[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->timing.h_total);
2895 data->v_total[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->timing.v_total);
2896 pixel_clock_100hz = pipe[i].stream->timing.pix_clk_100hz;
2897 if (pipe[i].stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
2898 pixel_clock_100hz *= 2;
2899 data->pixel_rate[num_displays + 4] = bw_frc_to_fixed(pixel_clock_100hz, 10000);
2900 if (pipe[i].plane_state) {
2901 data->src_width[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.viewport.width);
2902 data->pitch_in_pixels[num_displays + 4] = data->src_width[num_displays + 4];
2903 data->src_height[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.viewport.height);
2904 data->h_taps[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.taps.h_taps);
2905 data->v_taps[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.taps.v_taps);
2906 data->h_scale_ratio[num_displays + 4] = fixed31_32_to_bw_fixed(pipe[i].plane_res.scl_data.ratios.horz.value);
2907 data->v_scale_ratio[num_displays + 4] = fixed31_32_to_bw_fixed(pipe[i].plane_res.scl_data.ratios.vert.value);
2908 switch (pipe[i].plane_state->rotation) {
2909 case ROTATION_ANGLE_0:
2910 data->rotation_angle[num_displays + 4] = bw_int_to_fixed(0);
2911 break;
2912 case ROTATION_ANGLE_90:
2913 data->rotation_angle[num_displays + 4] = bw_int_to_fixed(90);
2914 break;
2915 case ROTATION_ANGLE_180:
2916 data->rotation_angle[num_displays + 4] = bw_int_to_fixed(180);
2917 break;
2918 case ROTATION_ANGLE_270:
2919 data->rotation_angle[num_displays + 4] = bw_int_to_fixed(270);
2920 break;
2921 default:
2922 break;
2923 }
2924 switch (pipe[i].plane_state->format) {
2925 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
2926 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
2927 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
2928 case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
2929 data->bytes_per_pixel[num_displays + 4] = 2;
2930 break;
2931 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
2932 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
2933 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
2934 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
2935 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS:
2936 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
2937 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
2938 data->bytes_per_pixel[num_displays + 4] = 4;
2939 break;
2940 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
2941 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
2942 data->bytes_per_pixel[num_displays + 4] = 8;
2943 break;
2944 default:
2945 data->bytes_per_pixel[num_displays + 4] = 4;
2946 break;
2947 }
2948 } else if (pipe[i].stream->dst.width != 0 &&
2949 pipe[i].stream->dst.height != 0 &&
2950 pipe[i].stream->src.width != 0 &&
2951 pipe[i].stream->src.height != 0) {
2952 data->src_width[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->src.width);
2953 data->pitch_in_pixels[num_displays + 4] = data->src_width[num_displays + 4];
2954 data->src_height[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->src.height);
2955 data->h_taps[num_displays + 4] = pipe[i].stream->src.width == pipe[i].stream->dst.width ? bw_int_to_fixed(1) : bw_int_to_fixed(2);
2956 data->v_taps[num_displays + 4] = pipe[i].stream->src.height == pipe[i].stream->dst.height ? bw_int_to_fixed(1) : bw_int_to_fixed(2);
2957 data->h_scale_ratio[num_displays + 4] = bw_frc_to_fixed(pipe[i].stream->src.width, pipe[i].stream->dst.width);
2958 data->v_scale_ratio[num_displays + 4] = bw_frc_to_fixed(pipe[i].stream->src.height, pipe[i].stream->dst.height);
2959 data->rotation_angle[num_displays + 4] = bw_int_to_fixed(0);
2960 data->bytes_per_pixel[num_displays + 4] = 4;
2961 } else {
2962 data->src_width[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->timing.h_addressable);
2963 data->pitch_in_pixels[num_displays + 4] = data->src_width[num_displays + 4];
2964 data->src_height[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->timing.v_addressable);
2965 data->h_taps[num_displays + 4] = bw_int_to_fixed(1);
2966 data->v_taps[num_displays + 4] = bw_int_to_fixed(1);
2967 data->h_scale_ratio[num_displays + 4] = bw_int_to_fixed(1);
2968 data->v_scale_ratio[num_displays + 4] = bw_int_to_fixed(1);
2969 data->rotation_angle[num_displays + 4] = bw_int_to_fixed(0);
2970 data->bytes_per_pixel[num_displays + 4] = 4;
2971 }
2972
2973 data->interlace_mode[num_displays + 4] = false;
2974 data->stereo_mode[num_displays + 4] = bw_def_mono;
2975 num_displays++;
2976 }
2977
2978 data->number_of_displays = num_displays;
2979 }
2980
all_displays_in_sync(const struct pipe_ctx pipe[],int pipe_count)2981 static bool all_displays_in_sync(const struct pipe_ctx pipe[],
2982 int pipe_count)
2983 {
2984 const struct pipe_ctx *active_pipes[MAX_PIPES];
2985 int i, num_active_pipes = 0;
2986
2987 for (i = 0; i < pipe_count; i++) {
2988 if (!pipe[i].stream || pipe[i].top_pipe)
2989 continue;
2990
2991 active_pipes[num_active_pipes++] = &pipe[i];
2992 }
2993
2994 if (!num_active_pipes)
2995 return false;
2996
2997 for (i = 1; i < num_active_pipes; ++i) {
2998 if (!resource_are_streams_timing_synchronizable(
2999 active_pipes[0]->stream, active_pipes[i]->stream)) {
3000 return false;
3001 }
3002 }
3003
3004 return true;
3005 }
3006
3007 /**
3008 * Return:
3009 * true - Display(s) configuration supported.
3010 * In this case 'calcs_output' contains data for HW programming
3011 * false - Display(s) configuration not supported (not enough bandwidth).
3012 */
3013
bw_calcs(struct dc_context * ctx,const struct bw_calcs_dceip * dceip,const struct bw_calcs_vbios * vbios,const struct pipe_ctx pipe[],int pipe_count,struct dce_bw_output * calcs_output)3014 bool bw_calcs(struct dc_context *ctx,
3015 const struct bw_calcs_dceip *dceip,
3016 const struct bw_calcs_vbios *vbios,
3017 const struct pipe_ctx pipe[],
3018 int pipe_count,
3019 struct dce_bw_output *calcs_output)
3020 {
3021 struct bw_calcs_data *data = kzalloc(sizeof(struct bw_calcs_data),
3022 GFP_KERNEL);
3023 if (!data)
3024 return false;
3025
3026 populate_initial_data(pipe, pipe_count, data);
3027
3028 if (ctx->dc->config.multi_mon_pp_mclk_switch)
3029 calcs_output->all_displays_in_sync = all_displays_in_sync(pipe, pipe_count);
3030 else
3031 calcs_output->all_displays_in_sync = false;
3032
3033 if (data->number_of_displays != 0) {
3034 uint8_t yclk_lvl, sclk_lvl;
3035 struct bw_fixed high_sclk = vbios->high_sclk;
3036 struct bw_fixed mid1_sclk = vbios->mid1_sclk;
3037 struct bw_fixed mid2_sclk = vbios->mid2_sclk;
3038 struct bw_fixed mid3_sclk = vbios->mid3_sclk;
3039 struct bw_fixed mid4_sclk = vbios->mid4_sclk;
3040 struct bw_fixed mid5_sclk = vbios->mid5_sclk;
3041 struct bw_fixed mid6_sclk = vbios->mid6_sclk;
3042 struct bw_fixed low_sclk = vbios->low_sclk;
3043 struct bw_fixed high_yclk = vbios->high_yclk;
3044 struct bw_fixed mid_yclk = vbios->mid_yclk;
3045 struct bw_fixed low_yclk = vbios->low_yclk;
3046
3047 if (ctx->dc->debug.bandwidth_calcs_trace) {
3048 print_bw_calcs_dceip(ctx, dceip);
3049 print_bw_calcs_vbios(ctx, vbios);
3050 print_bw_calcs_data(ctx, data);
3051 }
3052 calculate_bandwidth(dceip, vbios, data);
3053
3054 yclk_lvl = data->y_clk_level;
3055 sclk_lvl = data->sclk_level;
3056
3057 calcs_output->nbp_state_change_enable =
3058 data->nbp_state_change_enable;
3059 calcs_output->cpuc_state_change_enable =
3060 data->cpuc_state_change_enable;
3061 calcs_output->cpup_state_change_enable =
3062 data->cpup_state_change_enable;
3063 calcs_output->stutter_mode_enable =
3064 data->stutter_mode_enable;
3065 calcs_output->dispclk_khz =
3066 bw_fixed_to_int(bw_mul(data->dispclk,
3067 bw_int_to_fixed(1000)));
3068 calcs_output->blackout_recovery_time_us =
3069 bw_fixed_to_int(data->blackout_recovery_time);
3070 calcs_output->sclk_khz =
3071 bw_fixed_to_int(bw_mul(data->required_sclk,
3072 bw_int_to_fixed(1000)));
3073 calcs_output->sclk_deep_sleep_khz =
3074 bw_fixed_to_int(bw_mul(data->sclk_deep_sleep,
3075 bw_int_to_fixed(1000)));
3076 if (yclk_lvl == 0)
3077 calcs_output->yclk_khz = bw_fixed_to_int(
3078 bw_mul(low_yclk, bw_int_to_fixed(1000)));
3079 else if (yclk_lvl == 1)
3080 calcs_output->yclk_khz = bw_fixed_to_int(
3081 bw_mul(mid_yclk, bw_int_to_fixed(1000)));
3082 else
3083 calcs_output->yclk_khz = bw_fixed_to_int(
3084 bw_mul(high_yclk, bw_int_to_fixed(1000)));
3085
3086 /* units: nanosecond, 16bit storage. */
3087
3088 calcs_output->nbp_state_change_wm_ns[0].a_mark =
3089 bw_fixed_to_int(bw_mul(data->
3090 nbp_state_change_watermark[4], bw_int_to_fixed(1000)));
3091 calcs_output->nbp_state_change_wm_ns[1].a_mark =
3092 bw_fixed_to_int(bw_mul(data->
3093 nbp_state_change_watermark[5], bw_int_to_fixed(1000)));
3094 calcs_output->nbp_state_change_wm_ns[2].a_mark =
3095 bw_fixed_to_int(bw_mul(data->
3096 nbp_state_change_watermark[6], bw_int_to_fixed(1000)));
3097
3098 if (ctx->dc->caps.max_slave_planes) {
3099 calcs_output->nbp_state_change_wm_ns[3].a_mark =
3100 bw_fixed_to_int(bw_mul(data->
3101 nbp_state_change_watermark[0], bw_int_to_fixed(1000)));
3102 calcs_output->nbp_state_change_wm_ns[4].a_mark =
3103 bw_fixed_to_int(bw_mul(data->
3104 nbp_state_change_watermark[1], bw_int_to_fixed(1000)));
3105 } else {
3106 calcs_output->nbp_state_change_wm_ns[3].a_mark =
3107 bw_fixed_to_int(bw_mul(data->
3108 nbp_state_change_watermark[7], bw_int_to_fixed(1000)));
3109 calcs_output->nbp_state_change_wm_ns[4].a_mark =
3110 bw_fixed_to_int(bw_mul(data->
3111 nbp_state_change_watermark[8], bw_int_to_fixed(1000)));
3112 }
3113 calcs_output->nbp_state_change_wm_ns[5].a_mark =
3114 bw_fixed_to_int(bw_mul(data->
3115 nbp_state_change_watermark[9], bw_int_to_fixed(1000)));
3116
3117
3118
3119 calcs_output->stutter_exit_wm_ns[0].a_mark =
3120 bw_fixed_to_int(bw_mul(data->
3121 stutter_exit_watermark[4], bw_int_to_fixed(1000)));
3122 calcs_output->stutter_exit_wm_ns[1].a_mark =
3123 bw_fixed_to_int(bw_mul(data->
3124 stutter_exit_watermark[5], bw_int_to_fixed(1000)));
3125 calcs_output->stutter_exit_wm_ns[2].a_mark =
3126 bw_fixed_to_int(bw_mul(data->
3127 stutter_exit_watermark[6], bw_int_to_fixed(1000)));
3128 if (ctx->dc->caps.max_slave_planes) {
3129 calcs_output->stutter_exit_wm_ns[3].a_mark =
3130 bw_fixed_to_int(bw_mul(data->
3131 stutter_exit_watermark[0], bw_int_to_fixed(1000)));
3132 calcs_output->stutter_exit_wm_ns[4].a_mark =
3133 bw_fixed_to_int(bw_mul(data->
3134 stutter_exit_watermark[1], bw_int_to_fixed(1000)));
3135 } else {
3136 calcs_output->stutter_exit_wm_ns[3].a_mark =
3137 bw_fixed_to_int(bw_mul(data->
3138 stutter_exit_watermark[7], bw_int_to_fixed(1000)));
3139 calcs_output->stutter_exit_wm_ns[4].a_mark =
3140 bw_fixed_to_int(bw_mul(data->
3141 stutter_exit_watermark[8], bw_int_to_fixed(1000)));
3142 }
3143 calcs_output->stutter_exit_wm_ns[5].a_mark =
3144 bw_fixed_to_int(bw_mul(data->
3145 stutter_exit_watermark[9], bw_int_to_fixed(1000)));
3146
3147 calcs_output->stutter_entry_wm_ns[0].a_mark =
3148 bw_fixed_to_int(bw_mul(data->
3149 stutter_entry_watermark[4], bw_int_to_fixed(1000)));
3150 calcs_output->stutter_entry_wm_ns[1].a_mark =
3151 bw_fixed_to_int(bw_mul(data->
3152 stutter_entry_watermark[5], bw_int_to_fixed(1000)));
3153 calcs_output->stutter_entry_wm_ns[2].a_mark =
3154 bw_fixed_to_int(bw_mul(data->
3155 stutter_entry_watermark[6], bw_int_to_fixed(1000)));
3156 if (ctx->dc->caps.max_slave_planes) {
3157 calcs_output->stutter_entry_wm_ns[3].a_mark =
3158 bw_fixed_to_int(bw_mul(data->
3159 stutter_entry_watermark[0], bw_int_to_fixed(1000)));
3160 calcs_output->stutter_entry_wm_ns[4].a_mark =
3161 bw_fixed_to_int(bw_mul(data->
3162 stutter_entry_watermark[1], bw_int_to_fixed(1000)));
3163 } else {
3164 calcs_output->stutter_entry_wm_ns[3].a_mark =
3165 bw_fixed_to_int(bw_mul(data->
3166 stutter_entry_watermark[7], bw_int_to_fixed(1000)));
3167 calcs_output->stutter_entry_wm_ns[4].a_mark =
3168 bw_fixed_to_int(bw_mul(data->
3169 stutter_entry_watermark[8], bw_int_to_fixed(1000)));
3170 }
3171 calcs_output->stutter_entry_wm_ns[5].a_mark =
3172 bw_fixed_to_int(bw_mul(data->
3173 stutter_entry_watermark[9], bw_int_to_fixed(1000)));
3174
3175 calcs_output->urgent_wm_ns[0].a_mark =
3176 bw_fixed_to_int(bw_mul(data->
3177 urgent_watermark[4], bw_int_to_fixed(1000)));
3178 calcs_output->urgent_wm_ns[1].a_mark =
3179 bw_fixed_to_int(bw_mul(data->
3180 urgent_watermark[5], bw_int_to_fixed(1000)));
3181 calcs_output->urgent_wm_ns[2].a_mark =
3182 bw_fixed_to_int(bw_mul(data->
3183 urgent_watermark[6], bw_int_to_fixed(1000)));
3184 if (ctx->dc->caps.max_slave_planes) {
3185 calcs_output->urgent_wm_ns[3].a_mark =
3186 bw_fixed_to_int(bw_mul(data->
3187 urgent_watermark[0], bw_int_to_fixed(1000)));
3188 calcs_output->urgent_wm_ns[4].a_mark =
3189 bw_fixed_to_int(bw_mul(data->
3190 urgent_watermark[1], bw_int_to_fixed(1000)));
3191 } else {
3192 calcs_output->urgent_wm_ns[3].a_mark =
3193 bw_fixed_to_int(bw_mul(data->
3194 urgent_watermark[7], bw_int_to_fixed(1000)));
3195 calcs_output->urgent_wm_ns[4].a_mark =
3196 bw_fixed_to_int(bw_mul(data->
3197 urgent_watermark[8], bw_int_to_fixed(1000)));
3198 }
3199 calcs_output->urgent_wm_ns[5].a_mark =
3200 bw_fixed_to_int(bw_mul(data->
3201 urgent_watermark[9], bw_int_to_fixed(1000)));
3202
3203 if (dceip->version != BW_CALCS_VERSION_CARRIZO) {
3204 ((struct bw_calcs_vbios *)vbios)->low_sclk = mid3_sclk;
3205 ((struct bw_calcs_vbios *)vbios)->mid1_sclk = mid3_sclk;
3206 ((struct bw_calcs_vbios *)vbios)->mid2_sclk = mid3_sclk;
3207 calculate_bandwidth(dceip, vbios, data);
3208
3209 calcs_output->nbp_state_change_wm_ns[0].b_mark =
3210 bw_fixed_to_int(bw_mul(data->
3211 nbp_state_change_watermark[4],bw_int_to_fixed(1000)));
3212 calcs_output->nbp_state_change_wm_ns[1].b_mark =
3213 bw_fixed_to_int(bw_mul(data->
3214 nbp_state_change_watermark[5], bw_int_to_fixed(1000)));
3215 calcs_output->nbp_state_change_wm_ns[2].b_mark =
3216 bw_fixed_to_int(bw_mul(data->
3217 nbp_state_change_watermark[6], bw_int_to_fixed(1000)));
3218
3219 if (ctx->dc->caps.max_slave_planes) {
3220 calcs_output->nbp_state_change_wm_ns[3].b_mark =
3221 bw_fixed_to_int(bw_mul(data->
3222 nbp_state_change_watermark[0], bw_int_to_fixed(1000)));
3223 calcs_output->nbp_state_change_wm_ns[4].b_mark =
3224 bw_fixed_to_int(bw_mul(data->
3225 nbp_state_change_watermark[1], bw_int_to_fixed(1000)));
3226 } else {
3227 calcs_output->nbp_state_change_wm_ns[3].b_mark =
3228 bw_fixed_to_int(bw_mul(data->
3229 nbp_state_change_watermark[7], bw_int_to_fixed(1000)));
3230 calcs_output->nbp_state_change_wm_ns[4].b_mark =
3231 bw_fixed_to_int(bw_mul(data->
3232 nbp_state_change_watermark[8], bw_int_to_fixed(1000)));
3233 }
3234 calcs_output->nbp_state_change_wm_ns[5].b_mark =
3235 bw_fixed_to_int(bw_mul(data->
3236 nbp_state_change_watermark[9], bw_int_to_fixed(1000)));
3237
3238
3239
3240 calcs_output->stutter_exit_wm_ns[0].b_mark =
3241 bw_fixed_to_int(bw_mul(data->
3242 stutter_exit_watermark[4], bw_int_to_fixed(1000)));
3243 calcs_output->stutter_exit_wm_ns[1].b_mark =
3244 bw_fixed_to_int(bw_mul(data->
3245 stutter_exit_watermark[5], bw_int_to_fixed(1000)));
3246 calcs_output->stutter_exit_wm_ns[2].b_mark =
3247 bw_fixed_to_int(bw_mul(data->
3248 stutter_exit_watermark[6], bw_int_to_fixed(1000)));
3249 if (ctx->dc->caps.max_slave_planes) {
3250 calcs_output->stutter_exit_wm_ns[3].b_mark =
3251 bw_fixed_to_int(bw_mul(data->
3252 stutter_exit_watermark[0], bw_int_to_fixed(1000)));
3253 calcs_output->stutter_exit_wm_ns[4].b_mark =
3254 bw_fixed_to_int(bw_mul(data->
3255 stutter_exit_watermark[1], bw_int_to_fixed(1000)));
3256 } else {
3257 calcs_output->stutter_exit_wm_ns[3].b_mark =
3258 bw_fixed_to_int(bw_mul(data->
3259 stutter_exit_watermark[7], bw_int_to_fixed(1000)));
3260 calcs_output->stutter_exit_wm_ns[4].b_mark =
3261 bw_fixed_to_int(bw_mul(data->
3262 stutter_exit_watermark[8], bw_int_to_fixed(1000)));
3263 }
3264 calcs_output->stutter_exit_wm_ns[5].b_mark =
3265 bw_fixed_to_int(bw_mul(data->
3266 stutter_exit_watermark[9], bw_int_to_fixed(1000)));
3267
3268 calcs_output->stutter_entry_wm_ns[0].b_mark =
3269 bw_fixed_to_int(bw_mul(data->
3270 stutter_entry_watermark[4], bw_int_to_fixed(1000)));
3271 calcs_output->stutter_entry_wm_ns[1].b_mark =
3272 bw_fixed_to_int(bw_mul(data->
3273 stutter_entry_watermark[5], bw_int_to_fixed(1000)));
3274 calcs_output->stutter_entry_wm_ns[2].b_mark =
3275 bw_fixed_to_int(bw_mul(data->
3276 stutter_entry_watermark[6], bw_int_to_fixed(1000)));
3277 if (ctx->dc->caps.max_slave_planes) {
3278 calcs_output->stutter_entry_wm_ns[3].b_mark =
3279 bw_fixed_to_int(bw_mul(data->
3280 stutter_entry_watermark[0], bw_int_to_fixed(1000)));
3281 calcs_output->stutter_entry_wm_ns[4].b_mark =
3282 bw_fixed_to_int(bw_mul(data->
3283 stutter_entry_watermark[1], bw_int_to_fixed(1000)));
3284 } else {
3285 calcs_output->stutter_entry_wm_ns[3].b_mark =
3286 bw_fixed_to_int(bw_mul(data->
3287 stutter_entry_watermark[7], bw_int_to_fixed(1000)));
3288 calcs_output->stutter_entry_wm_ns[4].b_mark =
3289 bw_fixed_to_int(bw_mul(data->
3290 stutter_entry_watermark[8], bw_int_to_fixed(1000)));
3291 }
3292 calcs_output->stutter_entry_wm_ns[5].b_mark =
3293 bw_fixed_to_int(bw_mul(data->
3294 stutter_entry_watermark[9], bw_int_to_fixed(1000)));
3295
3296 calcs_output->urgent_wm_ns[0].b_mark =
3297 bw_fixed_to_int(bw_mul(data->
3298 urgent_watermark[4], bw_int_to_fixed(1000)));
3299 calcs_output->urgent_wm_ns[1].b_mark =
3300 bw_fixed_to_int(bw_mul(data->
3301 urgent_watermark[5], bw_int_to_fixed(1000)));
3302 calcs_output->urgent_wm_ns[2].b_mark =
3303 bw_fixed_to_int(bw_mul(data->
3304 urgent_watermark[6], bw_int_to_fixed(1000)));
3305 if (ctx->dc->caps.max_slave_planes) {
3306 calcs_output->urgent_wm_ns[3].b_mark =
3307 bw_fixed_to_int(bw_mul(data->
3308 urgent_watermark[0], bw_int_to_fixed(1000)));
3309 calcs_output->urgent_wm_ns[4].b_mark =
3310 bw_fixed_to_int(bw_mul(data->
3311 urgent_watermark[1], bw_int_to_fixed(1000)));
3312 } else {
3313 calcs_output->urgent_wm_ns[3].b_mark =
3314 bw_fixed_to_int(bw_mul(data->
3315 urgent_watermark[7], bw_int_to_fixed(1000)));
3316 calcs_output->urgent_wm_ns[4].b_mark =
3317 bw_fixed_to_int(bw_mul(data->
3318 urgent_watermark[8], bw_int_to_fixed(1000)));
3319 }
3320 calcs_output->urgent_wm_ns[5].b_mark =
3321 bw_fixed_to_int(bw_mul(data->
3322 urgent_watermark[9], bw_int_to_fixed(1000)));
3323
3324 ((struct bw_calcs_vbios *)vbios)->low_sclk = low_sclk;
3325 ((struct bw_calcs_vbios *)vbios)->mid1_sclk = mid1_sclk;
3326 ((struct bw_calcs_vbios *)vbios)->mid2_sclk = mid2_sclk;
3327 ((struct bw_calcs_vbios *)vbios)->low_yclk = mid_yclk;
3328 calculate_bandwidth(dceip, vbios, data);
3329
3330 calcs_output->nbp_state_change_wm_ns[0].c_mark =
3331 bw_fixed_to_int(bw_mul(data->
3332 nbp_state_change_watermark[4], bw_int_to_fixed(1000)));
3333 calcs_output->nbp_state_change_wm_ns[1].c_mark =
3334 bw_fixed_to_int(bw_mul(data->
3335 nbp_state_change_watermark[5], bw_int_to_fixed(1000)));
3336 calcs_output->nbp_state_change_wm_ns[2].c_mark =
3337 bw_fixed_to_int(bw_mul(data->
3338 nbp_state_change_watermark[6], bw_int_to_fixed(1000)));
3339 if (ctx->dc->caps.max_slave_planes) {
3340 calcs_output->nbp_state_change_wm_ns[3].c_mark =
3341 bw_fixed_to_int(bw_mul(data->
3342 nbp_state_change_watermark[0], bw_int_to_fixed(1000)));
3343 calcs_output->nbp_state_change_wm_ns[4].c_mark =
3344 bw_fixed_to_int(bw_mul(data->
3345 nbp_state_change_watermark[1], bw_int_to_fixed(1000)));
3346 } else {
3347 calcs_output->nbp_state_change_wm_ns[3].c_mark =
3348 bw_fixed_to_int(bw_mul(data->
3349 nbp_state_change_watermark[7], bw_int_to_fixed(1000)));
3350 calcs_output->nbp_state_change_wm_ns[4].c_mark =
3351 bw_fixed_to_int(bw_mul(data->
3352 nbp_state_change_watermark[8], bw_int_to_fixed(1000)));
3353 }
3354 calcs_output->nbp_state_change_wm_ns[5].c_mark =
3355 bw_fixed_to_int(bw_mul(data->
3356 nbp_state_change_watermark[9], bw_int_to_fixed(1000)));
3357
3358
3359 calcs_output->stutter_exit_wm_ns[0].c_mark =
3360 bw_fixed_to_int(bw_mul(data->
3361 stutter_exit_watermark[4], bw_int_to_fixed(1000)));
3362 calcs_output->stutter_exit_wm_ns[1].c_mark =
3363 bw_fixed_to_int(bw_mul(data->
3364 stutter_exit_watermark[5], bw_int_to_fixed(1000)));
3365 calcs_output->stutter_exit_wm_ns[2].c_mark =
3366 bw_fixed_to_int(bw_mul(data->
3367 stutter_exit_watermark[6], bw_int_to_fixed(1000)));
3368 if (ctx->dc->caps.max_slave_planes) {
3369 calcs_output->stutter_exit_wm_ns[3].c_mark =
3370 bw_fixed_to_int(bw_mul(data->
3371 stutter_exit_watermark[0], bw_int_to_fixed(1000)));
3372 calcs_output->stutter_exit_wm_ns[4].c_mark =
3373 bw_fixed_to_int(bw_mul(data->
3374 stutter_exit_watermark[1], bw_int_to_fixed(1000)));
3375 } else {
3376 calcs_output->stutter_exit_wm_ns[3].c_mark =
3377 bw_fixed_to_int(bw_mul(data->
3378 stutter_exit_watermark[7], bw_int_to_fixed(1000)));
3379 calcs_output->stutter_exit_wm_ns[4].c_mark =
3380 bw_fixed_to_int(bw_mul(data->
3381 stutter_exit_watermark[8], bw_int_to_fixed(1000)));
3382 }
3383 calcs_output->stutter_exit_wm_ns[5].c_mark =
3384 bw_fixed_to_int(bw_mul(data->
3385 stutter_exit_watermark[9], bw_int_to_fixed(1000)));
3386
3387 calcs_output->stutter_entry_wm_ns[0].c_mark =
3388 bw_fixed_to_int(bw_mul(data->
3389 stutter_entry_watermark[4], bw_int_to_fixed(1000)));
3390 calcs_output->stutter_entry_wm_ns[1].c_mark =
3391 bw_fixed_to_int(bw_mul(data->
3392 stutter_entry_watermark[5], bw_int_to_fixed(1000)));
3393 calcs_output->stutter_entry_wm_ns[2].c_mark =
3394 bw_fixed_to_int(bw_mul(data->
3395 stutter_entry_watermark[6], bw_int_to_fixed(1000)));
3396 if (ctx->dc->caps.max_slave_planes) {
3397 calcs_output->stutter_entry_wm_ns[3].c_mark =
3398 bw_fixed_to_int(bw_mul(data->
3399 stutter_entry_watermark[0], bw_int_to_fixed(1000)));
3400 calcs_output->stutter_entry_wm_ns[4].c_mark =
3401 bw_fixed_to_int(bw_mul(data->
3402 stutter_entry_watermark[1], bw_int_to_fixed(1000)));
3403 } else {
3404 calcs_output->stutter_entry_wm_ns[3].c_mark =
3405 bw_fixed_to_int(bw_mul(data->
3406 stutter_entry_watermark[7], bw_int_to_fixed(1000)));
3407 calcs_output->stutter_entry_wm_ns[4].c_mark =
3408 bw_fixed_to_int(bw_mul(data->
3409 stutter_entry_watermark[8], bw_int_to_fixed(1000)));
3410 }
3411 calcs_output->stutter_entry_wm_ns[5].c_mark =
3412 bw_fixed_to_int(bw_mul(data->
3413 stutter_entry_watermark[9], bw_int_to_fixed(1000)));
3414
3415 calcs_output->urgent_wm_ns[0].c_mark =
3416 bw_fixed_to_int(bw_mul(data->
3417 urgent_watermark[4], bw_int_to_fixed(1000)));
3418 calcs_output->urgent_wm_ns[1].c_mark =
3419 bw_fixed_to_int(bw_mul(data->
3420 urgent_watermark[5], bw_int_to_fixed(1000)));
3421 calcs_output->urgent_wm_ns[2].c_mark =
3422 bw_fixed_to_int(bw_mul(data->
3423 urgent_watermark[6], bw_int_to_fixed(1000)));
3424 if (ctx->dc->caps.max_slave_planes) {
3425 calcs_output->urgent_wm_ns[3].c_mark =
3426 bw_fixed_to_int(bw_mul(data->
3427 urgent_watermark[0], bw_int_to_fixed(1000)));
3428 calcs_output->urgent_wm_ns[4].c_mark =
3429 bw_fixed_to_int(bw_mul(data->
3430 urgent_watermark[1], bw_int_to_fixed(1000)));
3431 } else {
3432 calcs_output->urgent_wm_ns[3].c_mark =
3433 bw_fixed_to_int(bw_mul(data->
3434 urgent_watermark[7], bw_int_to_fixed(1000)));
3435 calcs_output->urgent_wm_ns[4].c_mark =
3436 bw_fixed_to_int(bw_mul(data->
3437 urgent_watermark[8], bw_int_to_fixed(1000)));
3438 }
3439 calcs_output->urgent_wm_ns[5].c_mark =
3440 bw_fixed_to_int(bw_mul(data->
3441 urgent_watermark[9], bw_int_to_fixed(1000)));
3442 }
3443
3444 if (dceip->version == BW_CALCS_VERSION_CARRIZO) {
3445 ((struct bw_calcs_vbios *)vbios)->low_yclk = high_yclk;
3446 ((struct bw_calcs_vbios *)vbios)->mid_yclk = high_yclk;
3447 ((struct bw_calcs_vbios *)vbios)->low_sclk = high_sclk;
3448 ((struct bw_calcs_vbios *)vbios)->mid1_sclk = high_sclk;
3449 ((struct bw_calcs_vbios *)vbios)->mid2_sclk = high_sclk;
3450 ((struct bw_calcs_vbios *)vbios)->mid3_sclk = high_sclk;
3451 ((struct bw_calcs_vbios *)vbios)->mid4_sclk = high_sclk;
3452 ((struct bw_calcs_vbios *)vbios)->mid5_sclk = high_sclk;
3453 ((struct bw_calcs_vbios *)vbios)->mid6_sclk = high_sclk;
3454 } else {
3455 ((struct bw_calcs_vbios *)vbios)->low_yclk = mid_yclk;
3456 ((struct bw_calcs_vbios *)vbios)->low_sclk = mid3_sclk;
3457 ((struct bw_calcs_vbios *)vbios)->mid1_sclk = mid3_sclk;
3458 ((struct bw_calcs_vbios *)vbios)->mid2_sclk = mid3_sclk;
3459 }
3460
3461 calculate_bandwidth(dceip, vbios, data);
3462
3463 calcs_output->nbp_state_change_wm_ns[0].d_mark =
3464 bw_fixed_to_int(bw_mul(data->
3465 nbp_state_change_watermark[4], bw_int_to_fixed(1000)));
3466 calcs_output->nbp_state_change_wm_ns[1].d_mark =
3467 bw_fixed_to_int(bw_mul(data->
3468 nbp_state_change_watermark[5], bw_int_to_fixed(1000)));
3469 calcs_output->nbp_state_change_wm_ns[2].d_mark =
3470 bw_fixed_to_int(bw_mul(data->
3471 nbp_state_change_watermark[6], bw_int_to_fixed(1000)));
3472 if (ctx->dc->caps.max_slave_planes) {
3473 calcs_output->nbp_state_change_wm_ns[3].d_mark =
3474 bw_fixed_to_int(bw_mul(data->
3475 nbp_state_change_watermark[0], bw_int_to_fixed(1000)));
3476 calcs_output->nbp_state_change_wm_ns[4].d_mark =
3477 bw_fixed_to_int(bw_mul(data->
3478 nbp_state_change_watermark[1], bw_int_to_fixed(1000)));
3479 } else {
3480 calcs_output->nbp_state_change_wm_ns[3].d_mark =
3481 bw_fixed_to_int(bw_mul(data->
3482 nbp_state_change_watermark[7], bw_int_to_fixed(1000)));
3483 calcs_output->nbp_state_change_wm_ns[4].d_mark =
3484 bw_fixed_to_int(bw_mul(data->
3485 nbp_state_change_watermark[8], bw_int_to_fixed(1000)));
3486 }
3487 calcs_output->nbp_state_change_wm_ns[5].d_mark =
3488 bw_fixed_to_int(bw_mul(data->
3489 nbp_state_change_watermark[9], bw_int_to_fixed(1000)));
3490
3491 calcs_output->stutter_exit_wm_ns[0].d_mark =
3492 bw_fixed_to_int(bw_mul(data->
3493 stutter_exit_watermark[4], bw_int_to_fixed(1000)));
3494 calcs_output->stutter_exit_wm_ns[1].d_mark =
3495 bw_fixed_to_int(bw_mul(data->
3496 stutter_exit_watermark[5], bw_int_to_fixed(1000)));
3497 calcs_output->stutter_exit_wm_ns[2].d_mark =
3498 bw_fixed_to_int(bw_mul(data->
3499 stutter_exit_watermark[6], bw_int_to_fixed(1000)));
3500 if (ctx->dc->caps.max_slave_planes) {
3501 calcs_output->stutter_exit_wm_ns[3].d_mark =
3502 bw_fixed_to_int(bw_mul(data->
3503 stutter_exit_watermark[0], bw_int_to_fixed(1000)));
3504 calcs_output->stutter_exit_wm_ns[4].d_mark =
3505 bw_fixed_to_int(bw_mul(data->
3506 stutter_exit_watermark[1], bw_int_to_fixed(1000)));
3507 } else {
3508 calcs_output->stutter_exit_wm_ns[3].d_mark =
3509 bw_fixed_to_int(bw_mul(data->
3510 stutter_exit_watermark[7], bw_int_to_fixed(1000)));
3511 calcs_output->stutter_exit_wm_ns[4].d_mark =
3512 bw_fixed_to_int(bw_mul(data->
3513 stutter_exit_watermark[8], bw_int_to_fixed(1000)));
3514 }
3515 calcs_output->stutter_exit_wm_ns[5].d_mark =
3516 bw_fixed_to_int(bw_mul(data->
3517 stutter_exit_watermark[9], bw_int_to_fixed(1000)));
3518
3519 calcs_output->stutter_entry_wm_ns[0].d_mark =
3520 bw_fixed_to_int(bw_mul(data->
3521 stutter_entry_watermark[4], bw_int_to_fixed(1000)));
3522 calcs_output->stutter_entry_wm_ns[1].d_mark =
3523 bw_fixed_to_int(bw_mul(data->
3524 stutter_entry_watermark[5], bw_int_to_fixed(1000)));
3525 calcs_output->stutter_entry_wm_ns[2].d_mark =
3526 bw_fixed_to_int(bw_mul(data->
3527 stutter_entry_watermark[6], bw_int_to_fixed(1000)));
3528 if (ctx->dc->caps.max_slave_planes) {
3529 calcs_output->stutter_entry_wm_ns[3].d_mark =
3530 bw_fixed_to_int(bw_mul(data->
3531 stutter_entry_watermark[0], bw_int_to_fixed(1000)));
3532 calcs_output->stutter_entry_wm_ns[4].d_mark =
3533 bw_fixed_to_int(bw_mul(data->
3534 stutter_entry_watermark[1], bw_int_to_fixed(1000)));
3535 } else {
3536 calcs_output->stutter_entry_wm_ns[3].d_mark =
3537 bw_fixed_to_int(bw_mul(data->
3538 stutter_entry_watermark[7], bw_int_to_fixed(1000)));
3539 calcs_output->stutter_entry_wm_ns[4].d_mark =
3540 bw_fixed_to_int(bw_mul(data->
3541 stutter_entry_watermark[8], bw_int_to_fixed(1000)));
3542 }
3543 calcs_output->stutter_entry_wm_ns[5].d_mark =
3544 bw_fixed_to_int(bw_mul(data->
3545 stutter_entry_watermark[9], bw_int_to_fixed(1000)));
3546
3547 calcs_output->urgent_wm_ns[0].d_mark =
3548 bw_fixed_to_int(bw_mul(data->
3549 urgent_watermark[4], bw_int_to_fixed(1000)));
3550 calcs_output->urgent_wm_ns[1].d_mark =
3551 bw_fixed_to_int(bw_mul(data->
3552 urgent_watermark[5], bw_int_to_fixed(1000)));
3553 calcs_output->urgent_wm_ns[2].d_mark =
3554 bw_fixed_to_int(bw_mul(data->
3555 urgent_watermark[6], bw_int_to_fixed(1000)));
3556 if (ctx->dc->caps.max_slave_planes) {
3557 calcs_output->urgent_wm_ns[3].d_mark =
3558 bw_fixed_to_int(bw_mul(data->
3559 urgent_watermark[0], bw_int_to_fixed(1000)));
3560 calcs_output->urgent_wm_ns[4].d_mark =
3561 bw_fixed_to_int(bw_mul(data->
3562 urgent_watermark[1], bw_int_to_fixed(1000)));
3563 } else {
3564 calcs_output->urgent_wm_ns[3].d_mark =
3565 bw_fixed_to_int(bw_mul(data->
3566 urgent_watermark[7], bw_int_to_fixed(1000)));
3567 calcs_output->urgent_wm_ns[4].d_mark =
3568 bw_fixed_to_int(bw_mul(data->
3569 urgent_watermark[8], bw_int_to_fixed(1000)));
3570 }
3571 calcs_output->urgent_wm_ns[5].d_mark =
3572 bw_fixed_to_int(bw_mul(data->
3573 urgent_watermark[9], bw_int_to_fixed(1000)));
3574
3575 ((struct bw_calcs_vbios *)vbios)->low_yclk = low_yclk;
3576 ((struct bw_calcs_vbios *)vbios)->mid_yclk = mid_yclk;
3577 ((struct bw_calcs_vbios *)vbios)->low_sclk = low_sclk;
3578 ((struct bw_calcs_vbios *)vbios)->mid1_sclk = mid1_sclk;
3579 ((struct bw_calcs_vbios *)vbios)->mid2_sclk = mid2_sclk;
3580 ((struct bw_calcs_vbios *)vbios)->mid3_sclk = mid3_sclk;
3581 ((struct bw_calcs_vbios *)vbios)->mid4_sclk = mid4_sclk;
3582 ((struct bw_calcs_vbios *)vbios)->mid5_sclk = mid5_sclk;
3583 ((struct bw_calcs_vbios *)vbios)->mid6_sclk = mid6_sclk;
3584 ((struct bw_calcs_vbios *)vbios)->high_sclk = high_sclk;
3585 } else {
3586 calcs_output->nbp_state_change_enable = true;
3587 calcs_output->cpuc_state_change_enable = true;
3588 calcs_output->cpup_state_change_enable = true;
3589 calcs_output->stutter_mode_enable = true;
3590 calcs_output->dispclk_khz = 0;
3591 calcs_output->sclk_khz = 0;
3592 }
3593
3594 kfree(data);
3595
3596 return is_display_configuration_supported(vbios, calcs_output);
3597 }
3598
