1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #ifndef __AMDGPU_SDMA_H__ 25 #define __AMDGPU_SDMA_H__ 26 27 /* max number of IP instances */ 28 #define AMDGPU_MAX_SDMA_INSTANCES 8 29 30 enum amdgpu_sdma_irq { 31 AMDGPU_SDMA_IRQ_INSTANCE0 = 0, 32 AMDGPU_SDMA_IRQ_INSTANCE1, 33 AMDGPU_SDMA_IRQ_INSTANCE2, 34 AMDGPU_SDMA_IRQ_INSTANCE3, 35 AMDGPU_SDMA_IRQ_INSTANCE4, 36 AMDGPU_SDMA_IRQ_INSTANCE5, 37 AMDGPU_SDMA_IRQ_INSTANCE6, 38 AMDGPU_SDMA_IRQ_INSTANCE7, 39 AMDGPU_SDMA_IRQ_LAST 40 }; 41 42 struct amdgpu_sdma_instance { 43 /* SDMA firmware */ 44 const struct firmware *fw; 45 uint32_t fw_version; 46 uint32_t feature_version; 47 48 struct amdgpu_ring ring; 49 struct amdgpu_ring page; 50 bool burst_nop; 51 }; 52 53 struct amdgpu_sdma { 54 struct amdgpu_sdma_instance instance[AMDGPU_MAX_SDMA_INSTANCES]; 55 struct amdgpu_irq_src trap_irq; 56 struct amdgpu_irq_src illegal_inst_irq; 57 struct amdgpu_irq_src ecc_irq; 58 int num_instances; 59 uint32_t srbm_soft_reset; 60 bool has_page_queue; 61 struct ras_common_if *ras_if; 62 }; 63 64 /* 65 * Provided by hw blocks that can move/clear data. e.g., gfx or sdma 66 * But currently, we use sdma to move data. 67 */ 68 struct amdgpu_buffer_funcs { 69 /* maximum bytes in a single operation */ 70 uint32_t copy_max_bytes; 71 72 /* number of dw to reserve per operation */ 73 unsigned copy_num_dw; 74 75 /* used for buffer migration */ 76 void (*emit_copy_buffer)(struct amdgpu_ib *ib, 77 /* src addr in bytes */ 78 uint64_t src_offset, 79 /* dst addr in bytes */ 80 uint64_t dst_offset, 81 /* number of byte to transfer */ 82 uint32_t byte_count); 83 84 /* maximum bytes in a single operation */ 85 uint32_t fill_max_bytes; 86 87 /* number of dw to reserve per operation */ 88 unsigned fill_num_dw; 89 90 /* used for buffer clearing */ 91 void (*emit_fill_buffer)(struct amdgpu_ib *ib, 92 /* value to write to memory */ 93 uint32_t src_data, 94 /* dst addr in bytes */ 95 uint64_t dst_offset, 96 /* number of byte to fill */ 97 uint32_t byte_count); 98 }; 99 100 #define amdgpu_emit_copy_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_copy_buffer((ib), (s), (d), (b)) 101 #define amdgpu_emit_fill_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_fill_buffer((ib), (s), (d), (b)) 102 103 struct amdgpu_sdma_instance * 104 amdgpu_sdma_get_instance_from_ring(struct amdgpu_ring *ring); 105 int amdgpu_sdma_get_index_from_ring(struct amdgpu_ring *ring, uint32_t *index); 106 uint64_t amdgpu_sdma_get_csa_mc_addr(struct amdgpu_ring *ring, unsigned vmid); 107 #endif 108
