1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (c) 2000-2007 Silicon Graphics, Inc. All Rights Reserved. 7 */ 8 9 10 #ifndef _ASM_IA64_SN_BTE_H 11 #define _ASM_IA64_SN_BTE_H 12 13 #include <linux/timer.h> 14 #include <linux/spinlock.h> 15 #include <linux/cache.h> 16 #include <asm/sn/pda.h> 17 #include <asm/sn/types.h> 18 #include <asm/sn/shub_mmr.h> 19 20 struct nodepda_s; 21 22 #define IBCT_NOTIFY (0x1UL << 4) 23 #define IBCT_ZFIL_MODE (0x1UL << 0) 24 25 /* #define BTE_DEBUG */ 26 /* #define BTE_DEBUG_VERBOSE */ 27 28 #ifdef BTE_DEBUG 29 # define BTE_PRINTK(x) printk x /* Terse */ 30 # ifdef BTE_DEBUG_VERBOSE 31 # define BTE_PRINTKV(x) printk x /* Verbose */ 32 # else 33 # define BTE_PRINTKV(x) 34 # endif /* BTE_DEBUG_VERBOSE */ 35 #else 36 # define BTE_PRINTK(x) 37 # define BTE_PRINTKV(x) 38 #endif /* BTE_DEBUG */ 39 40 41 /* BTE status register only supports 16 bits for length field */ 42 #define BTE_LEN_BITS (16) 43 #define BTE_LEN_MASK ((1 << BTE_LEN_BITS) - 1) 44 #define BTE_MAX_XFER (BTE_LEN_MASK << L1_CACHE_SHIFT) 45 46 47 /* Define hardware */ 48 #define BTES_PER_NODE (is_shub2() ? 4 : 2) 49 #define MAX_BTES_PER_NODE 4 50 51 #define BTE2OFF_CTRL 0 52 #define BTE2OFF_SRC (SH2_BT_ENG_SRC_ADDR_0 - SH2_BT_ENG_CSR_0) 53 #define BTE2OFF_DEST (SH2_BT_ENG_DEST_ADDR_0 - SH2_BT_ENG_CSR_0) 54 #define BTE2OFF_NOTIFY (SH2_BT_ENG_NOTIF_ADDR_0 - SH2_BT_ENG_CSR_0) 55 56 #define BTE_BASE_ADDR(interface) \ 57 (is_shub2() ? (interface == 0) ? SH2_BT_ENG_CSR_0 : \ 58 (interface == 1) ? SH2_BT_ENG_CSR_1 : \ 59 (interface == 2) ? SH2_BT_ENG_CSR_2 : \ 60 SH2_BT_ENG_CSR_3 \ 61 : (interface == 0) ? IIO_IBLS0 : IIO_IBLS1) 62 63 #define BTE_SOURCE_ADDR(base) \ 64 (is_shub2() ? base + (BTE2OFF_SRC/8) \ 65 : base + (BTEOFF_SRC/8)) 66 67 #define BTE_DEST_ADDR(base) \ 68 (is_shub2() ? base + (BTE2OFF_DEST/8) \ 69 : base + (BTEOFF_DEST/8)) 70 71 #define BTE_CTRL_ADDR(base) \ 72 (is_shub2() ? base + (BTE2OFF_CTRL/8) \ 73 : base + (BTEOFF_CTRL/8)) 74 75 #define BTE_NOTIF_ADDR(base) \ 76 (is_shub2() ? base + (BTE2OFF_NOTIFY/8) \ 77 : base + (BTEOFF_NOTIFY/8)) 78 79 /* Define hardware modes */ 80 #define BTE_NOTIFY IBCT_NOTIFY 81 #define BTE_NORMAL BTE_NOTIFY 82 #define BTE_ZERO_FILL (BTE_NOTIFY | IBCT_ZFIL_MODE) 83 /* Use a reserved bit to let the caller specify a wait for any BTE */ 84 #define BTE_WACQUIRE 0x4000 85 /* Use the BTE on the node with the destination memory */ 86 #define BTE_USE_DEST (BTE_WACQUIRE << 1) 87 /* Use any available BTE interface on any node for the transfer */ 88 #define BTE_USE_ANY (BTE_USE_DEST << 1) 89 /* macro to force the IBCT0 value valid */ 90 #define BTE_VALID_MODE(x) ((x) & (IBCT_NOTIFY | IBCT_ZFIL_MODE)) 91 92 #define BTE_ACTIVE (IBLS_BUSY | IBLS_ERROR) 93 #define BTE_WORD_AVAILABLE (IBLS_BUSY << 1) 94 #define BTE_WORD_BUSY (~BTE_WORD_AVAILABLE) 95 96 /* 97 * Some macros to simplify reading. 98 * Start with macros to locate the BTE control registers. 99 */ 100 #define BTE_LNSTAT_LOAD(_bte) \ 101 HUB_L(_bte->bte_base_addr) 102 #define BTE_LNSTAT_STORE(_bte, _x) \ 103 HUB_S(_bte->bte_base_addr, (_x)) 104 #define BTE_SRC_STORE(_bte, _x) \ 105 ({ \ 106 u64 __addr = ((_x) & ~AS_MASK); \ 107 if (is_shub2()) \ 108 __addr = SH2_TIO_PHYS_TO_DMA(__addr); \ 109 HUB_S(_bte->bte_source_addr, __addr); \ 110 }) 111 #define BTE_DEST_STORE(_bte, _x) \ 112 ({ \ 113 u64 __addr = ((_x) & ~AS_MASK); \ 114 if (is_shub2()) \ 115 __addr = SH2_TIO_PHYS_TO_DMA(__addr); \ 116 HUB_S(_bte->bte_destination_addr, __addr); \ 117 }) 118 #define BTE_CTRL_STORE(_bte, _x) \ 119 HUB_S(_bte->bte_control_addr, (_x)) 120 #define BTE_NOTIF_STORE(_bte, _x) \ 121 ({ \ 122 u64 __addr = ia64_tpa((_x) & ~AS_MASK); \ 123 if (is_shub2()) \ 124 __addr = SH2_TIO_PHYS_TO_DMA(__addr); \ 125 HUB_S(_bte->bte_notify_addr, __addr); \ 126 }) 127 128 #define BTE_START_TRANSFER(_bte, _len, _mode) \ 129 is_shub2() ? BTE_CTRL_STORE(_bte, IBLS_BUSY | (_mode << 24) | _len) \ 130 : BTE_LNSTAT_STORE(_bte, _len); \ 131 BTE_CTRL_STORE(_bte, _mode) 132 133 /* Possible results from bte_copy and bte_unaligned_copy */ 134 /* The following error codes map into the BTE hardware codes 135 * IIO_ICRB_ECODE_* (in shubio.h). The hardware uses 136 * an error code of 0 (IIO_ICRB_ECODE_DERR), but we want zero 137 * to mean BTE_SUCCESS, so add one (BTEFAIL_OFFSET) to the error 138 * codes to give the following error codes. 139 */ 140 #define BTEFAIL_OFFSET 1 141 142 typedef enum { 143 BTE_SUCCESS, /* 0 is success */ 144 BTEFAIL_DIR, /* Directory error due to IIO access*/ 145 BTEFAIL_POISON, /* poison error on IO access (write to poison page) */ 146 BTEFAIL_WERR, /* Write error (ie WINV to a Read only line) */ 147 BTEFAIL_ACCESS, /* access error (protection violation) */ 148 BTEFAIL_PWERR, /* Partial Write Error */ 149 BTEFAIL_PRERR, /* Partial Read Error */ 150 BTEFAIL_TOUT, /* CRB Time out */ 151 BTEFAIL_XTERR, /* Incoming xtalk pkt had error bit */ 152 BTEFAIL_NOTAVAIL, /* BTE not available */ 153 } bte_result_t; 154 155 #define BTEFAIL_SH2_RESP_SHORT 0x1 /* bit 000001 */ 156 #define BTEFAIL_SH2_RESP_LONG 0x2 /* bit 000010 */ 157 #define BTEFAIL_SH2_RESP_DSP 0x4 /* bit 000100 */ 158 #define BTEFAIL_SH2_RESP_ACCESS 0x8 /* bit 001000 */ 159 #define BTEFAIL_SH2_CRB_TO 0x10 /* bit 010000 */ 160 #define BTEFAIL_SH2_NACK_LIMIT 0x20 /* bit 100000 */ 161 #define BTEFAIL_SH2_ALL 0x3F /* bit 111111 */ 162 163 #define BTE_ERR_BITS 0x3FUL 164 #define BTE_ERR_SHIFT 36 165 #define BTE_ERR_MASK (BTE_ERR_BITS << BTE_ERR_SHIFT) 166 167 #define BTE_ERROR_RETRY(value) \ 168 (is_shub2() ? (value != BTEFAIL_SH2_CRB_TO) \ 169 : (value != BTEFAIL_TOUT)) 170 171 /* 172 * On shub1 BTE_ERR_MASK will always be false, so no need for is_shub2() 173 */ 174 #define BTE_SHUB2_ERROR(_status) \ 175 ((_status & BTE_ERR_MASK) \ 176 ? (((_status >> BTE_ERR_SHIFT) & BTE_ERR_BITS) | IBLS_ERROR) \ 177 : _status) 178 179 #define BTE_GET_ERROR_STATUS(_status) \ 180 (BTE_SHUB2_ERROR(_status) & ~IBLS_ERROR) 181 182 #define BTE_VALID_SH2_ERROR(value) \ 183 ((value >= BTEFAIL_SH2_RESP_SHORT) && (value <= BTEFAIL_SH2_ALL)) 184 185 /* 186 * Structure defining a bte. An instance of this 187 * structure is created in the nodepda for each 188 * bte on that node (as defined by BTES_PER_NODE) 189 * This structure contains everything necessary 190 * to work with a BTE. 191 */ 192 struct bteinfo_s { 193 volatile u64 notify ____cacheline_aligned; 194 u64 *bte_base_addr ____cacheline_aligned; 195 u64 *bte_source_addr; 196 u64 *bte_destination_addr; 197 u64 *bte_control_addr; 198 u64 *bte_notify_addr; 199 spinlock_t spinlock; 200 cnodeid_t bte_cnode; /* cnode */ 201 int bte_error_count; /* Number of errors encountered */ 202 int bte_num; /* 0 --> BTE0, 1 --> BTE1 */ 203 int cleanup_active; /* Interface is locked for cleanup */ 204 volatile bte_result_t bh_error; /* error while processing */ 205 volatile u64 *most_rcnt_na; 206 struct bteinfo_s *btes_to_try[MAX_BTES_PER_NODE]; 207 }; 208 209 210 /* 211 * Function prototypes (functions defined in bte.c, used elsewhere) 212 */ 213 extern bte_result_t bte_copy(u64, u64, u64, u64, void *); 214 extern bte_result_t bte_unaligned_copy(u64, u64, u64, u64); 215 extern void bte_error_handler(struct nodepda_s *); 216 217 #define bte_zero(dest, len, mode, notification) \ 218 bte_copy(0, dest, len, ((mode) | BTE_ZERO_FILL), notification) 219 220 /* 221 * The following is the preferred way of calling bte_unaligned_copy 222 * If the copy is fully cache line aligned, then bte_copy is 223 * used instead. Since bte_copy is inlined, this saves a call 224 * stack. NOTE: bte_copy is called synchronously and does block 225 * until the transfer is complete. In order to get the asynch 226 * version of bte_copy, you must perform this check yourself. 227 */ 228 #define BTE_UNALIGNED_COPY(src, dest, len, mode) \ 229 (((len & (L1_CACHE_BYTES - 1)) || \ 230 (src & (L1_CACHE_BYTES - 1)) || \ 231 (dest & (L1_CACHE_BYTES - 1))) ? \ 232 bte_unaligned_copy(src, dest, len, mode) : \ 233 bte_copy(src, dest, len, mode, NULL)) 234 235 236 #endif /* _ASM_IA64_SN_BTE_H */ 237
