1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1994 - 1999, 2000, 01, 06 Ralf Baechle
7 * Copyright (C) 1995, 1996 Paul M. Antoine
8 * Copyright (C) 1998 Ulf Carlsson
9 * Copyright (C) 1999 Silicon Graphics, Inc.
10 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
11 * Copyright (C) 2002, 2003, 2004, 2005, 2007 Maciej W. Rozycki
12 * Copyright (C) 2000, 2001, 2012 MIPS Technologies, Inc. All rights reserved.
13 * Copyright (C) 2014, Imagination Technologies Ltd.
14 */
15 #include <linux/bitops.h>
16 #include <linux/bug.h>
17 #include <linux/compiler.h>
18 #include <linux/context_tracking.h>
19 #include <linux/cpu_pm.h>
20 #include <linux/kexec.h>
21 #include <linux/init.h>
22 #include <linux/kernel.h>
23 #include <linux/module.h>
24 #include <linux/extable.h>
25 #include <linux/mm.h>
26 #include <linux/sched/mm.h>
27 #include <linux/sched/debug.h>
28 #include <linux/smp.h>
29 #include <linux/spinlock.h>
30 #include <linux/kallsyms.h>
31 #include <linux/bootmem.h>
32 #include <linux/interrupt.h>
33 #include <linux/ptrace.h>
34 #include <linux/kgdb.h>
35 #include <linux/kdebug.h>
36 #include <linux/kprobes.h>
37 #include <linux/notifier.h>
38 #include <linux/kdb.h>
39 #include <linux/irq.h>
40 #include <linux/perf_event.h>
41
42 #include <asm/addrspace.h>
43 #include <asm/bootinfo.h>
44 #include <asm/branch.h>
45 #include <asm/break.h>
46 #include <asm/cop2.h>
47 #include <asm/cpu.h>
48 #include <asm/cpu-type.h>
49 #include <asm/dsp.h>
50 #include <asm/fpu.h>
51 #include <asm/fpu_emulator.h>
52 #include <asm/idle.h>
53 #include <asm/mips-cps.h>
54 #include <asm/mips-r2-to-r6-emul.h>
55 #include <asm/mipsregs.h>
56 #include <asm/mipsmtregs.h>
57 #include <asm/module.h>
58 #include <asm/msa.h>
59 #include <asm/pgtable.h>
60 #include <asm/ptrace.h>
61 #include <asm/sections.h>
62 #include <asm/siginfo.h>
63 #include <asm/tlbdebug.h>
64 #include <asm/traps.h>
65 #include <linux/uaccess.h>
66 #include <asm/watch.h>
67 #include <asm/mmu_context.h>
68 #include <asm/types.h>
69 #include <asm/stacktrace.h>
70 #include <asm/tlbex.h>
71 #include <asm/uasm.h>
72
73 extern void check_wait(void);
74 extern asmlinkage void rollback_handle_int(void);
75 extern asmlinkage void handle_int(void);
76 extern asmlinkage void handle_adel(void);
77 extern asmlinkage void handle_ades(void);
78 extern asmlinkage void handle_ibe(void);
79 extern asmlinkage void handle_dbe(void);
80 extern asmlinkage void handle_sys(void);
81 extern asmlinkage void handle_bp(void);
82 extern asmlinkage void handle_ri(void);
83 extern asmlinkage void handle_ri_rdhwr_tlbp(void);
84 extern asmlinkage void handle_ri_rdhwr(void);
85 extern asmlinkage void handle_cpu(void);
86 extern asmlinkage void handle_ov(void);
87 extern asmlinkage void handle_tr(void);
88 extern asmlinkage void handle_msa_fpe(void);
89 extern asmlinkage void handle_fpe(void);
90 extern asmlinkage void handle_ftlb(void);
91 extern asmlinkage void handle_msa(void);
92 extern asmlinkage void handle_mdmx(void);
93 extern asmlinkage void handle_watch(void);
94 extern asmlinkage void handle_mt(void);
95 extern asmlinkage void handle_dsp(void);
96 extern asmlinkage void handle_mcheck(void);
97 extern asmlinkage void handle_reserved(void);
98 extern void tlb_do_page_fault_0(void);
99
100 void (*board_be_init)(void);
101 int (*board_be_handler)(struct pt_regs *regs, int is_fixup);
102 void (*board_nmi_handler_setup)(void);
103 void (*board_ejtag_handler_setup)(void);
104 void (*board_bind_eic_interrupt)(int irq, int regset);
105 void (*board_ebase_setup)(void);
106 void(*board_cache_error_setup)(void);
107
show_raw_backtrace(unsigned long reg29)108 static void show_raw_backtrace(unsigned long reg29)
109 {
110 unsigned long *sp = (unsigned long *)(reg29 & ~3);
111 unsigned long addr;
112
113 printk("Call Trace:");
114 #ifdef CONFIG_KALLSYMS
115 printk("\n");
116 #endif
117 while (!kstack_end(sp)) {
118 unsigned long __user *p =
119 (unsigned long __user *)(unsigned long)sp++;
120 if (__get_user(addr, p)) {
121 printk(" (Bad stack address)");
122 break;
123 }
124 if (__kernel_text_address(addr))
125 print_ip_sym(addr);
126 }
127 printk("\n");
128 }
129
130 #ifdef CONFIG_KALLSYMS
131 int raw_show_trace;
set_raw_show_trace(char * str)132 static int __init set_raw_show_trace(char *str)
133 {
134 raw_show_trace = 1;
135 return 1;
136 }
137 __setup("raw_show_trace", set_raw_show_trace);
138 #endif
139
show_backtrace(struct task_struct * task,const struct pt_regs * regs)140 static void show_backtrace(struct task_struct *task, const struct pt_regs *regs)
141 {
142 unsigned long sp = regs->regs[29];
143 unsigned long ra = regs->regs[31];
144 unsigned long pc = regs->cp0_epc;
145
146 if (!task)
147 task = current;
148
149 if (raw_show_trace || user_mode(regs) || !__kernel_text_address(pc)) {
150 show_raw_backtrace(sp);
151 return;
152 }
153 printk("Call Trace:\n");
154 do {
155 print_ip_sym(pc);
156 pc = unwind_stack(task, &sp, pc, &ra);
157 } while (pc);
158 pr_cont("\n");
159 }
160
161 /*
162 * This routine abuses get_user()/put_user() to reference pointers
163 * with at least a bit of error checking ...
164 */
show_stacktrace(struct task_struct * task,const struct pt_regs * regs)165 static void show_stacktrace(struct task_struct *task,
166 const struct pt_regs *regs)
167 {
168 const int field = 2 * sizeof(unsigned long);
169 long stackdata;
170 int i;
171 unsigned long __user *sp = (unsigned long __user *)regs->regs[29];
172
173 printk("Stack :");
174 i = 0;
175 while ((unsigned long) sp & (PAGE_SIZE - 1)) {
176 if (i && ((i % (64 / field)) == 0)) {
177 pr_cont("\n");
178 printk(" ");
179 }
180 if (i > 39) {
181 pr_cont(" ...");
182 break;
183 }
184
185 if (__get_user(stackdata, sp++)) {
186 pr_cont(" (Bad stack address)");
187 break;
188 }
189
190 pr_cont(" %0*lx", field, stackdata);
191 i++;
192 }
193 pr_cont("\n");
194 show_backtrace(task, regs);
195 }
196
show_stack(struct task_struct * task,unsigned long * sp)197 void show_stack(struct task_struct *task, unsigned long *sp)
198 {
199 struct pt_regs regs;
200 mm_segment_t old_fs = get_fs();
201
202 regs.cp0_status = KSU_KERNEL;
203 if (sp) {
204 regs.regs[29] = (unsigned long)sp;
205 regs.regs[31] = 0;
206 regs.cp0_epc = 0;
207 } else {
208 if (task && task != current) {
209 regs.regs[29] = task->thread.reg29;
210 regs.regs[31] = 0;
211 regs.cp0_epc = task->thread.reg31;
212 #ifdef CONFIG_KGDB_KDB
213 } else if (atomic_read(&kgdb_active) != -1 &&
214 kdb_current_regs) {
215 memcpy(®s, kdb_current_regs, sizeof(regs));
216 #endif /* CONFIG_KGDB_KDB */
217 } else {
218 prepare_frametrace(®s);
219 }
220 }
221 /*
222 * show_stack() deals exclusively with kernel mode, so be sure to access
223 * the stack in the kernel (not user) address space.
224 */
225 set_fs(KERNEL_DS);
226 show_stacktrace(task, ®s);
227 set_fs(old_fs);
228 }
229
show_code(unsigned int __user * pc)230 static void show_code(unsigned int __user *pc)
231 {
232 long i;
233 unsigned short __user *pc16 = NULL;
234
235 printk("Code:");
236
237 if ((unsigned long)pc & 1)
238 pc16 = (unsigned short __user *)((unsigned long)pc & ~1);
239 for(i = -3 ; i < 6 ; i++) {
240 unsigned int insn;
241 if (pc16 ? __get_user(insn, pc16 + i) : __get_user(insn, pc + i)) {
242 pr_cont(" (Bad address in epc)\n");
243 break;
244 }
245 pr_cont("%c%0*x%c", (i?' ':'<'), pc16 ? 4 : 8, insn, (i?' ':'>'));
246 }
247 pr_cont("\n");
248 }
249
__show_regs(const struct pt_regs * regs)250 static void __show_regs(const struct pt_regs *regs)
251 {
252 const int field = 2 * sizeof(unsigned long);
253 unsigned int cause = regs->cp0_cause;
254 unsigned int exccode;
255 int i;
256
257 show_regs_print_info(KERN_DEFAULT);
258
259 /*
260 * Saved main processor registers
261 */
262 for (i = 0; i < 32; ) {
263 if ((i % 4) == 0)
264 printk("$%2d :", i);
265 if (i == 0)
266 pr_cont(" %0*lx", field, 0UL);
267 else if (i == 26 || i == 27)
268 pr_cont(" %*s", field, "");
269 else
270 pr_cont(" %0*lx", field, regs->regs[i]);
271
272 i++;
273 if ((i % 4) == 0)
274 pr_cont("\n");
275 }
276
277 #ifdef CONFIG_CPU_HAS_SMARTMIPS
278 printk("Acx : %0*lx\n", field, regs->acx);
279 #endif
280 printk("Hi : %0*lx\n", field, regs->hi);
281 printk("Lo : %0*lx\n", field, regs->lo);
282
283 /*
284 * Saved cp0 registers
285 */
286 printk("epc : %0*lx %pS\n", field, regs->cp0_epc,
287 (void *) regs->cp0_epc);
288 printk("ra : %0*lx %pS\n", field, regs->regs[31],
289 (void *) regs->regs[31]);
290
291 printk("Status: %08x ", (uint32_t) regs->cp0_status);
292
293 if (cpu_has_3kex) {
294 if (regs->cp0_status & ST0_KUO)
295 pr_cont("KUo ");
296 if (regs->cp0_status & ST0_IEO)
297 pr_cont("IEo ");
298 if (regs->cp0_status & ST0_KUP)
299 pr_cont("KUp ");
300 if (regs->cp0_status & ST0_IEP)
301 pr_cont("IEp ");
302 if (regs->cp0_status & ST0_KUC)
303 pr_cont("KUc ");
304 if (regs->cp0_status & ST0_IEC)
305 pr_cont("IEc ");
306 } else if (cpu_has_4kex) {
307 if (regs->cp0_status & ST0_KX)
308 pr_cont("KX ");
309 if (regs->cp0_status & ST0_SX)
310 pr_cont("SX ");
311 if (regs->cp0_status & ST0_UX)
312 pr_cont("UX ");
313 switch (regs->cp0_status & ST0_KSU) {
314 case KSU_USER:
315 pr_cont("USER ");
316 break;
317 case KSU_SUPERVISOR:
318 pr_cont("SUPERVISOR ");
319 break;
320 case KSU_KERNEL:
321 pr_cont("KERNEL ");
322 break;
323 default:
324 pr_cont("BAD_MODE ");
325 break;
326 }
327 if (regs->cp0_status & ST0_ERL)
328 pr_cont("ERL ");
329 if (regs->cp0_status & ST0_EXL)
330 pr_cont("EXL ");
331 if (regs->cp0_status & ST0_IE)
332 pr_cont("IE ");
333 }
334 pr_cont("\n");
335
336 exccode = (cause & CAUSEF_EXCCODE) >> CAUSEB_EXCCODE;
337 printk("Cause : %08x (ExcCode %02x)\n", cause, exccode);
338
339 if (1 <= exccode && exccode <= 5)
340 printk("BadVA : %0*lx\n", field, regs->cp0_badvaddr);
341
342 printk("PrId : %08x (%s)\n", read_c0_prid(),
343 cpu_name_string());
344 }
345
346 /*
347 * FIXME: really the generic show_regs should take a const pointer argument.
348 */
show_regs(struct pt_regs * regs)349 void show_regs(struct pt_regs *regs)
350 {
351 __show_regs((struct pt_regs *)regs);
352 dump_stack();
353 }
354
show_registers(struct pt_regs * regs)355 void show_registers(struct pt_regs *regs)
356 {
357 const int field = 2 * sizeof(unsigned long);
358 mm_segment_t old_fs = get_fs();
359
360 __show_regs(regs);
361 print_modules();
362 printk("Process %s (pid: %d, threadinfo=%p, task=%p, tls=%0*lx)\n",
363 current->comm, current->pid, current_thread_info(), current,
364 field, current_thread_info()->tp_value);
365 if (cpu_has_userlocal) {
366 unsigned long tls;
367
368 tls = read_c0_userlocal();
369 if (tls != current_thread_info()->tp_value)
370 printk("*HwTLS: %0*lx\n", field, tls);
371 }
372
373 if (!user_mode(regs))
374 /* Necessary for getting the correct stack content */
375 set_fs(KERNEL_DS);
376 show_stacktrace(current, regs);
377 show_code((unsigned int __user *) regs->cp0_epc);
378 printk("\n");
379 set_fs(old_fs);
380 }
381
382 static DEFINE_RAW_SPINLOCK(die_lock);
383
die(const char * str,struct pt_regs * regs)384 void __noreturn die(const char *str, struct pt_regs *regs)
385 {
386 static int die_counter;
387 int sig = SIGSEGV;
388
389 oops_enter();
390
391 if (notify_die(DIE_OOPS, str, regs, 0, current->thread.trap_nr,
392 SIGSEGV) == NOTIFY_STOP)
393 sig = 0;
394
395 console_verbose();
396 raw_spin_lock_irq(&die_lock);
397 bust_spinlocks(1);
398
399 printk("%s[#%d]:\n", str, ++die_counter);
400 show_registers(regs);
401 add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE);
402 raw_spin_unlock_irq(&die_lock);
403
404 oops_exit();
405
406 if (in_interrupt())
407 panic("Fatal exception in interrupt");
408
409 if (panic_on_oops)
410 panic("Fatal exception");
411
412 if (regs && kexec_should_crash(current))
413 crash_kexec(regs);
414
415 do_exit(sig);
416 }
417
418 extern struct exception_table_entry __start___dbe_table[];
419 extern struct exception_table_entry __stop___dbe_table[];
420
421 __asm__(
422 " .section __dbe_table, \"a\"\n"
423 " .previous \n");
424
425 /* Given an address, look for it in the exception tables. */
search_dbe_tables(unsigned long addr)426 static const struct exception_table_entry *search_dbe_tables(unsigned long addr)
427 {
428 const struct exception_table_entry *e;
429
430 e = search_extable(__start___dbe_table,
431 __stop___dbe_table - __start___dbe_table, addr);
432 if (!e)
433 e = search_module_dbetables(addr);
434 return e;
435 }
436
do_be(struct pt_regs * regs)437 asmlinkage void do_be(struct pt_regs *regs)
438 {
439 const int field = 2 * sizeof(unsigned long);
440 const struct exception_table_entry *fixup = NULL;
441 int data = regs->cp0_cause & 4;
442 int action = MIPS_BE_FATAL;
443 enum ctx_state prev_state;
444
445 prev_state = exception_enter();
446 /* XXX For now. Fixme, this searches the wrong table ... */
447 if (data && !user_mode(regs))
448 fixup = search_dbe_tables(exception_epc(regs));
449
450 if (fixup)
451 action = MIPS_BE_FIXUP;
452
453 if (board_be_handler)
454 action = board_be_handler(regs, fixup != NULL);
455 else
456 mips_cm_error_report();
457
458 switch (action) {
459 case MIPS_BE_DISCARD:
460 goto out;
461 case MIPS_BE_FIXUP:
462 if (fixup) {
463 regs->cp0_epc = fixup->nextinsn;
464 goto out;
465 }
466 break;
467 default:
468 break;
469 }
470
471 /*
472 * Assume it would be too dangerous to continue ...
473 */
474 printk(KERN_ALERT "%s bus error, epc == %0*lx, ra == %0*lx\n",
475 data ? "Data" : "Instruction",
476 field, regs->cp0_epc, field, regs->regs[31]);
477 if (notify_die(DIE_OOPS, "bus error", regs, 0, current->thread.trap_nr,
478 SIGBUS) == NOTIFY_STOP)
479 goto out;
480
481 die_if_kernel("Oops", regs);
482 force_sig(SIGBUS, current);
483
484 out:
485 exception_exit(prev_state);
486 }
487
488 /*
489 * ll/sc, rdhwr, sync emulation
490 */
491
492 #define OPCODE 0xfc000000
493 #define BASE 0x03e00000
494 #define RT 0x001f0000
495 #define OFFSET 0x0000ffff
496 #define LL 0xc0000000
497 #define SC 0xe0000000
498 #define SPEC0 0x00000000
499 #define SPEC3 0x7c000000
500 #define RD 0x0000f800
501 #define FUNC 0x0000003f
502 #define SYNC 0x0000000f
503 #define RDHWR 0x0000003b
504
505 /* microMIPS definitions */
506 #define MM_POOL32A_FUNC 0xfc00ffff
507 #define MM_RDHWR 0x00006b3c
508 #define MM_RS 0x001f0000
509 #define MM_RT 0x03e00000
510
511 /*
512 * The ll_bit is cleared by r*_switch.S
513 */
514
515 unsigned int ll_bit;
516 struct task_struct *ll_task;
517
simulate_ll(struct pt_regs * regs,unsigned int opcode)518 static inline int simulate_ll(struct pt_regs *regs, unsigned int opcode)
519 {
520 unsigned long value, __user *vaddr;
521 long offset;
522
523 /*
524 * analyse the ll instruction that just caused a ri exception
525 * and put the referenced address to addr.
526 */
527
528 /* sign extend offset */
529 offset = opcode & OFFSET;
530 offset <<= 16;
531 offset >>= 16;
532
533 vaddr = (unsigned long __user *)
534 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);
535
536 if ((unsigned long)vaddr & 3)
537 return SIGBUS;
538 if (get_user(value, vaddr))
539 return SIGSEGV;
540
541 preempt_disable();
542
543 if (ll_task == NULL || ll_task == current) {
544 ll_bit = 1;
545 } else {
546 ll_bit = 0;
547 }
548 ll_task = current;
549
550 preempt_enable();
551
552 regs->regs[(opcode & RT) >> 16] = value;
553
554 return 0;
555 }
556
simulate_sc(struct pt_regs * regs,unsigned int opcode)557 static inline int simulate_sc(struct pt_regs *regs, unsigned int opcode)
558 {
559 unsigned long __user *vaddr;
560 unsigned long reg;
561 long offset;
562
563 /*
564 * analyse the sc instruction that just caused a ri exception
565 * and put the referenced address to addr.
566 */
567
568 /* sign extend offset */
569 offset = opcode & OFFSET;
570 offset <<= 16;
571 offset >>= 16;
572
573 vaddr = (unsigned long __user *)
574 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);
575 reg = (opcode & RT) >> 16;
576
577 if ((unsigned long)vaddr & 3)
578 return SIGBUS;
579
580 preempt_disable();
581
582 if (ll_bit == 0 || ll_task != current) {
583 regs->regs[reg] = 0;
584 preempt_enable();
585 return 0;
586 }
587
588 preempt_enable();
589
590 if (put_user(regs->regs[reg], vaddr))
591 return SIGSEGV;
592
593 regs->regs[reg] = 1;
594
595 return 0;
596 }
597
598 /*
599 * ll uses the opcode of lwc0 and sc uses the opcode of swc0. That is both
600 * opcodes are supposed to result in coprocessor unusable exceptions if
601 * executed on ll/sc-less processors. That's the theory. In practice a
602 * few processors such as NEC's VR4100 throw reserved instruction exceptions
603 * instead, so we're doing the emulation thing in both exception handlers.
604 */
simulate_llsc(struct pt_regs * regs,unsigned int opcode)605 static int simulate_llsc(struct pt_regs *regs, unsigned int opcode)
606 {
607 if ((opcode & OPCODE) == LL) {
608 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
609 1, regs, 0);
610 return simulate_ll(regs, opcode);
611 }
612 if ((opcode & OPCODE) == SC) {
613 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
614 1, regs, 0);
615 return simulate_sc(regs, opcode);
616 }
617
618 return -1; /* Must be something else ... */
619 }
620
621 /*
622 * Simulate trapping 'rdhwr' instructions to provide user accessible
623 * registers not implemented in hardware.
624 */
simulate_rdhwr(struct pt_regs * regs,int rd,int rt)625 static int simulate_rdhwr(struct pt_regs *regs, int rd, int rt)
626 {
627 struct thread_info *ti = task_thread_info(current);
628
629 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
630 1, regs, 0);
631 switch (rd) {
632 case MIPS_HWR_CPUNUM: /* CPU number */
633 regs->regs[rt] = smp_processor_id();
634 return 0;
635 case MIPS_HWR_SYNCISTEP: /* SYNCI length */
636 regs->regs[rt] = min(current_cpu_data.dcache.linesz,
637 current_cpu_data.icache.linesz);
638 return 0;
639 case MIPS_HWR_CC: /* Read count register */
640 regs->regs[rt] = read_c0_count();
641 return 0;
642 case MIPS_HWR_CCRES: /* Count register resolution */
643 switch (current_cpu_type()) {
644 case CPU_20KC:
645 case CPU_25KF:
646 regs->regs[rt] = 1;
647 break;
648 default:
649 regs->regs[rt] = 2;
650 }
651 return 0;
652 case MIPS_HWR_ULR: /* Read UserLocal register */
653 regs->regs[rt] = ti->tp_value;
654 return 0;
655 default:
656 return -1;
657 }
658 }
659
simulate_rdhwr_normal(struct pt_regs * regs,unsigned int opcode)660 static int simulate_rdhwr_normal(struct pt_regs *regs, unsigned int opcode)
661 {
662 if ((opcode & OPCODE) == SPEC3 && (opcode & FUNC) == RDHWR) {
663 int rd = (opcode & RD) >> 11;
664 int rt = (opcode & RT) >> 16;
665
666 simulate_rdhwr(regs, rd, rt);
667 return 0;
668 }
669
670 /* Not ours. */
671 return -1;
672 }
673
simulate_rdhwr_mm(struct pt_regs * regs,unsigned int opcode)674 static int simulate_rdhwr_mm(struct pt_regs *regs, unsigned int opcode)
675 {
676 if ((opcode & MM_POOL32A_FUNC) == MM_RDHWR) {
677 int rd = (opcode & MM_RS) >> 16;
678 int rt = (opcode & MM_RT) >> 21;
679 simulate_rdhwr(regs, rd, rt);
680 return 0;
681 }
682
683 /* Not ours. */
684 return -1;
685 }
686
simulate_sync(struct pt_regs * regs,unsigned int opcode)687 static int simulate_sync(struct pt_regs *regs, unsigned int opcode)
688 {
689 if ((opcode & OPCODE) == SPEC0 && (opcode & FUNC) == SYNC) {
690 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
691 1, regs, 0);
692 return 0;
693 }
694
695 return -1; /* Must be something else ... */
696 }
697
do_ov(struct pt_regs * regs)698 asmlinkage void do_ov(struct pt_regs *regs)
699 {
700 enum ctx_state prev_state;
701
702 prev_state = exception_enter();
703 die_if_kernel("Integer overflow", regs);
704
705 force_sig_fault(SIGFPE, FPE_INTOVF, (void __user *)regs->cp0_epc, current);
706 exception_exit(prev_state);
707 }
708
709 /*
710 * Send SIGFPE according to FCSR Cause bits, which must have already
711 * been masked against Enable bits. This is impotant as Inexact can
712 * happen together with Overflow or Underflow, and `ptrace' can set
713 * any bits.
714 */
force_fcr31_sig(unsigned long fcr31,void __user * fault_addr,struct task_struct * tsk)715 void force_fcr31_sig(unsigned long fcr31, void __user *fault_addr,
716 struct task_struct *tsk)
717 {
718 int si_code = FPE_FLTUNK;
719
720 if (fcr31 & FPU_CSR_INV_X)
721 si_code = FPE_FLTINV;
722 else if (fcr31 & FPU_CSR_DIV_X)
723 si_code = FPE_FLTDIV;
724 else if (fcr31 & FPU_CSR_OVF_X)
725 si_code = FPE_FLTOVF;
726 else if (fcr31 & FPU_CSR_UDF_X)
727 si_code = FPE_FLTUND;
728 else if (fcr31 & FPU_CSR_INE_X)
729 si_code = FPE_FLTRES;
730
731 force_sig_fault(SIGFPE, si_code, fault_addr, tsk);
732 }
733
process_fpemu_return(int sig,void __user * fault_addr,unsigned long fcr31)734 int process_fpemu_return(int sig, void __user *fault_addr, unsigned long fcr31)
735 {
736 int si_code;
737 struct vm_area_struct *vma;
738
739 switch (sig) {
740 case 0:
741 return 0;
742
743 case SIGFPE:
744 force_fcr31_sig(fcr31, fault_addr, current);
745 return 1;
746
747 case SIGBUS:
748 force_sig_fault(SIGBUS, BUS_ADRERR, fault_addr, current);
749 return 1;
750
751 case SIGSEGV:
752 down_read(¤t->mm->mmap_sem);
753 vma = find_vma(current->mm, (unsigned long)fault_addr);
754 if (vma && (vma->vm_start <= (unsigned long)fault_addr))
755 si_code = SEGV_ACCERR;
756 else
757 si_code = SEGV_MAPERR;
758 up_read(¤t->mm->mmap_sem);
759 force_sig_fault(SIGSEGV, si_code, fault_addr, current);
760 return 1;
761
762 default:
763 force_sig(sig, current);
764 return 1;
765 }
766 }
767
simulate_fp(struct pt_regs * regs,unsigned int opcode,unsigned long old_epc,unsigned long old_ra)768 static int simulate_fp(struct pt_regs *regs, unsigned int opcode,
769 unsigned long old_epc, unsigned long old_ra)
770 {
771 union mips_instruction inst = { .word = opcode };
772 void __user *fault_addr;
773 unsigned long fcr31;
774 int sig;
775
776 /* If it's obviously not an FP instruction, skip it */
777 switch (inst.i_format.opcode) {
778 case cop1_op:
779 case cop1x_op:
780 case lwc1_op:
781 case ldc1_op:
782 case swc1_op:
783 case sdc1_op:
784 break;
785
786 default:
787 return -1;
788 }
789
790 /*
791 * do_ri skipped over the instruction via compute_return_epc, undo
792 * that for the FPU emulator.
793 */
794 regs->cp0_epc = old_epc;
795 regs->regs[31] = old_ra;
796
797 /* Save the FP context to struct thread_struct */
798 lose_fpu(1);
799
800 /* Run the emulator */
801 sig = fpu_emulator_cop1Handler(regs, ¤t->thread.fpu, 1,
802 &fault_addr);
803
804 /*
805 * We can't allow the emulated instruction to leave any
806 * enabled Cause bits set in $fcr31.
807 */
808 fcr31 = mask_fcr31_x(current->thread.fpu.fcr31);
809 current->thread.fpu.fcr31 &= ~fcr31;
810
811 /* Restore the hardware register state */
812 own_fpu(1);
813
814 /* Send a signal if required. */
815 process_fpemu_return(sig, fault_addr, fcr31);
816
817 return 0;
818 }
819
820 /*
821 * XXX Delayed fp exceptions when doing a lazy ctx switch XXX
822 */
do_fpe(struct pt_regs * regs,unsigned long fcr31)823 asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31)
824 {
825 enum ctx_state prev_state;
826 void __user *fault_addr;
827 int sig;
828
829 prev_state = exception_enter();
830 if (notify_die(DIE_FP, "FP exception", regs, 0, current->thread.trap_nr,
831 SIGFPE) == NOTIFY_STOP)
832 goto out;
833
834 /* Clear FCSR.Cause before enabling interrupts */
835 write_32bit_cp1_register(CP1_STATUS, fcr31 & ~mask_fcr31_x(fcr31));
836 local_irq_enable();
837
838 die_if_kernel("FP exception in kernel code", regs);
839
840 if (fcr31 & FPU_CSR_UNI_X) {
841 /*
842 * Unimplemented operation exception. If we've got the full
843 * software emulator on-board, let's use it...
844 *
845 * Force FPU to dump state into task/thread context. We're
846 * moving a lot of data here for what is probably a single
847 * instruction, but the alternative is to pre-decode the FP
848 * register operands before invoking the emulator, which seems
849 * a bit extreme for what should be an infrequent event.
850 */
851 /* Ensure 'resume' not overwrite saved fp context again. */
852 lose_fpu(1);
853
854 /* Run the emulator */
855 sig = fpu_emulator_cop1Handler(regs, ¤t->thread.fpu, 1,
856 &fault_addr);
857
858 /*
859 * We can't allow the emulated instruction to leave any
860 * enabled Cause bits set in $fcr31.
861 */
862 fcr31 = mask_fcr31_x(current->thread.fpu.fcr31);
863 current->thread.fpu.fcr31 &= ~fcr31;
864
865 /* Restore the hardware register state */
866 own_fpu(1); /* Using the FPU again. */
867 } else {
868 sig = SIGFPE;
869 fault_addr = (void __user *) regs->cp0_epc;
870 }
871
872 /* Send a signal if required. */
873 process_fpemu_return(sig, fault_addr, fcr31);
874
875 out:
876 exception_exit(prev_state);
877 }
878
do_trap_or_bp(struct pt_regs * regs,unsigned int code,int si_code,const char * str)879 void do_trap_or_bp(struct pt_regs *regs, unsigned int code, int si_code,
880 const char *str)
881 {
882 char b[40];
883
884 #ifdef CONFIG_KGDB_LOW_LEVEL_TRAP
885 if (kgdb_ll_trap(DIE_TRAP, str, regs, code, current->thread.trap_nr,
886 SIGTRAP) == NOTIFY_STOP)
887 return;
888 #endif /* CONFIG_KGDB_LOW_LEVEL_TRAP */
889
890 if (notify_die(DIE_TRAP, str, regs, code, current->thread.trap_nr,
891 SIGTRAP) == NOTIFY_STOP)
892 return;
893
894 /*
895 * A short test says that IRIX 5.3 sends SIGTRAP for all trap
896 * insns, even for trap and break codes that indicate arithmetic
897 * failures. Weird ...
898 * But should we continue the brokenness??? --macro
899 */
900 switch (code) {
901 case BRK_OVERFLOW:
902 case BRK_DIVZERO:
903 scnprintf(b, sizeof(b), "%s instruction in kernel code", str);
904 die_if_kernel(b, regs);
905 force_sig_fault(SIGFPE,
906 code == BRK_DIVZERO ? FPE_INTDIV : FPE_INTOVF,
907 (void __user *) regs->cp0_epc, current);
908 break;
909 case BRK_BUG:
910 die_if_kernel("Kernel bug detected", regs);
911 force_sig(SIGTRAP, current);
912 break;
913 case BRK_MEMU:
914 /*
915 * This breakpoint code is used by the FPU emulator to retake
916 * control of the CPU after executing the instruction from the
917 * delay slot of an emulated branch.
918 *
919 * Terminate if exception was recognized as a delay slot return
920 * otherwise handle as normal.
921 */
922 if (do_dsemulret(regs))
923 return;
924
925 die_if_kernel("Math emu break/trap", regs);
926 force_sig(SIGTRAP, current);
927 break;
928 default:
929 scnprintf(b, sizeof(b), "%s instruction in kernel code", str);
930 die_if_kernel(b, regs);
931 if (si_code) {
932 force_sig_fault(SIGTRAP, si_code, NULL, current);
933 } else {
934 force_sig(SIGTRAP, current);
935 }
936 }
937 }
938
do_bp(struct pt_regs * regs)939 asmlinkage void do_bp(struct pt_regs *regs)
940 {
941 unsigned long epc = msk_isa16_mode(exception_epc(regs));
942 unsigned int opcode, bcode;
943 enum ctx_state prev_state;
944 mm_segment_t seg;
945
946 seg = get_fs();
947 if (!user_mode(regs))
948 set_fs(KERNEL_DS);
949
950 prev_state = exception_enter();
951 current->thread.trap_nr = (regs->cp0_cause >> 2) & 0x1f;
952 if (get_isa16_mode(regs->cp0_epc)) {
953 u16 instr[2];
954
955 if (__get_user(instr[0], (u16 __user *)epc))
956 goto out_sigsegv;
957
958 if (!cpu_has_mmips) {
959 /* MIPS16e mode */
960 bcode = (instr[0] >> 5) & 0x3f;
961 } else if (mm_insn_16bit(instr[0])) {
962 /* 16-bit microMIPS BREAK */
963 bcode = instr[0] & 0xf;
964 } else {
965 /* 32-bit microMIPS BREAK */
966 if (__get_user(instr[1], (u16 __user *)(epc + 2)))
967 goto out_sigsegv;
968 opcode = (instr[0] << 16) | instr[1];
969 bcode = (opcode >> 6) & ((1 << 20) - 1);
970 }
971 } else {
972 if (__get_user(opcode, (unsigned int __user *)epc))
973 goto out_sigsegv;
974 bcode = (opcode >> 6) & ((1 << 20) - 1);
975 }
976
977 /*
978 * There is the ancient bug in the MIPS assemblers that the break
979 * code starts left to bit 16 instead to bit 6 in the opcode.
980 * Gas is bug-compatible, but not always, grrr...
981 * We handle both cases with a simple heuristics. --macro
982 */
983 if (bcode >= (1 << 10))
984 bcode = ((bcode & ((1 << 10) - 1)) << 10) | (bcode >> 10);
985
986 /*
987 * notify the kprobe handlers, if instruction is likely to
988 * pertain to them.
989 */
990 switch (bcode) {
991 case BRK_UPROBE:
992 if (notify_die(DIE_UPROBE, "uprobe", regs, bcode,
993 current->thread.trap_nr, SIGTRAP) == NOTIFY_STOP)
994 goto out;
995 else
996 break;
997 case BRK_UPROBE_XOL:
998 if (notify_die(DIE_UPROBE_XOL, "uprobe_xol", regs, bcode,
999 current->thread.trap_nr, SIGTRAP) == NOTIFY_STOP)
1000 goto out;
1001 else
1002 break;
1003 case BRK_KPROBE_BP:
1004 if (notify_die(DIE_BREAK, "debug", regs, bcode,
1005 current->thread.trap_nr, SIGTRAP) == NOTIFY_STOP)
1006 goto out;
1007 else
1008 break;
1009 case BRK_KPROBE_SSTEPBP:
1010 if (notify_die(DIE_SSTEPBP, "single_step", regs, bcode,
1011 current->thread.trap_nr, SIGTRAP) == NOTIFY_STOP)
1012 goto out;
1013 else
1014 break;
1015 default:
1016 break;
1017 }
1018
1019 do_trap_or_bp(regs, bcode, TRAP_BRKPT, "Break");
1020
1021 out:
1022 set_fs(seg);
1023 exception_exit(prev_state);
1024 return;
1025
1026 out_sigsegv:
1027 force_sig(SIGSEGV, current);
1028 goto out;
1029 }
1030
do_tr(struct pt_regs * regs)1031 asmlinkage void do_tr(struct pt_regs *regs)
1032 {
1033 u32 opcode, tcode = 0;
1034 enum ctx_state prev_state;
1035 u16 instr[2];
1036 mm_segment_t seg;
1037 unsigned long epc = msk_isa16_mode(exception_epc(regs));
1038
1039 seg = get_fs();
1040 if (!user_mode(regs))
1041 set_fs(get_ds());
1042
1043 prev_state = exception_enter();
1044 current->thread.trap_nr = (regs->cp0_cause >> 2) & 0x1f;
1045 if (get_isa16_mode(regs->cp0_epc)) {
1046 if (__get_user(instr[0], (u16 __user *)(epc + 0)) ||
1047 __get_user(instr[1], (u16 __user *)(epc + 2)))
1048 goto out_sigsegv;
1049 opcode = (instr[0] << 16) | instr[1];
1050 /* Immediate versions don't provide a code. */
1051 if (!(opcode & OPCODE))
1052 tcode = (opcode >> 12) & ((1 << 4) - 1);
1053 } else {
1054 if (__get_user(opcode, (u32 __user *)epc))
1055 goto out_sigsegv;
1056 /* Immediate versions don't provide a code. */
1057 if (!(opcode & OPCODE))
1058 tcode = (opcode >> 6) & ((1 << 10) - 1);
1059 }
1060
1061 do_trap_or_bp(regs, tcode, 0, "Trap");
1062
1063 out:
1064 set_fs(seg);
1065 exception_exit(prev_state);
1066 return;
1067
1068 out_sigsegv:
1069 force_sig(SIGSEGV, current);
1070 goto out;
1071 }
1072
do_ri(struct pt_regs * regs)1073 asmlinkage void do_ri(struct pt_regs *regs)
1074 {
1075 unsigned int __user *epc = (unsigned int __user *)exception_epc(regs);
1076 unsigned long old_epc = regs->cp0_epc;
1077 unsigned long old31 = regs->regs[31];
1078 enum ctx_state prev_state;
1079 unsigned int opcode = 0;
1080 int status = -1;
1081
1082 /*
1083 * Avoid any kernel code. Just emulate the R2 instruction
1084 * as quickly as possible.
1085 */
1086 if (mipsr2_emulation && cpu_has_mips_r6 &&
1087 likely(user_mode(regs)) &&
1088 likely(get_user(opcode, epc) >= 0)) {
1089 unsigned long fcr31 = 0;
1090
1091 status = mipsr2_decoder(regs, opcode, &fcr31);
1092 switch (status) {
1093 case 0:
1094 case SIGEMT:
1095 return;
1096 case SIGILL:
1097 goto no_r2_instr;
1098 default:
1099 process_fpemu_return(status,
1100 ¤t->thread.cp0_baduaddr,
1101 fcr31);
1102 return;
1103 }
1104 }
1105
1106 no_r2_instr:
1107
1108 prev_state = exception_enter();
1109 current->thread.trap_nr = (regs->cp0_cause >> 2) & 0x1f;
1110
1111 if (notify_die(DIE_RI, "RI Fault", regs, 0, current->thread.trap_nr,
1112 SIGILL) == NOTIFY_STOP)
1113 goto out;
1114
1115 die_if_kernel("Reserved instruction in kernel code", regs);
1116
1117 if (unlikely(compute_return_epc(regs) < 0))
1118 goto out;
1119
1120 if (!get_isa16_mode(regs->cp0_epc)) {
1121 if (unlikely(get_user(opcode, epc) < 0))
1122 status = SIGSEGV;
1123
1124 if (!cpu_has_llsc && status < 0)
1125 status = simulate_llsc(regs, opcode);
1126
1127 if (status < 0)
1128 status = simulate_rdhwr_normal(regs, opcode);
1129
1130 if (status < 0)
1131 status = simulate_sync(regs, opcode);
1132
1133 if (status < 0)
1134 status = simulate_fp(regs, opcode, old_epc, old31);
1135 } else if (cpu_has_mmips) {
1136 unsigned short mmop[2] = { 0 };
1137
1138 if (unlikely(get_user(mmop[0], (u16 __user *)epc + 0) < 0))
1139 status = SIGSEGV;
1140 if (unlikely(get_user(mmop[1], (u16 __user *)epc + 1) < 0))
1141 status = SIGSEGV;
1142 opcode = mmop[0];
1143 opcode = (opcode << 16) | mmop[1];
1144
1145 if (status < 0)
1146 status = simulate_rdhwr_mm(regs, opcode);
1147 }
1148
1149 if (status < 0)
1150 status = SIGILL;
1151
1152 if (unlikely(status > 0)) {
1153 regs->cp0_epc = old_epc; /* Undo skip-over. */
1154 regs->regs[31] = old31;
1155 force_sig(status, current);
1156 }
1157
1158 out:
1159 exception_exit(prev_state);
1160 }
1161
1162 /*
1163 * MIPS MT processors may have fewer FPU contexts than CPU threads. If we've
1164 * emulated more than some threshold number of instructions, force migration to
1165 * a "CPU" that has FP support.
1166 */
mt_ase_fp_affinity(void)1167 static void mt_ase_fp_affinity(void)
1168 {
1169 #ifdef CONFIG_MIPS_MT_FPAFF
1170 if (mt_fpemul_threshold > 0 &&
1171 ((current->thread.emulated_fp++ > mt_fpemul_threshold))) {
1172 /*
1173 * If there's no FPU present, or if the application has already
1174 * restricted the allowed set to exclude any CPUs with FPUs,
1175 * we'll skip the procedure.
1176 */
1177 if (cpumask_intersects(¤t->cpus_allowed, &mt_fpu_cpumask)) {
1178 cpumask_t tmask;
1179
1180 current->thread.user_cpus_allowed
1181 = current->cpus_allowed;
1182 cpumask_and(&tmask, ¤t->cpus_allowed,
1183 &mt_fpu_cpumask);
1184 set_cpus_allowed_ptr(current, &tmask);
1185 set_thread_flag(TIF_FPUBOUND);
1186 }
1187 }
1188 #endif /* CONFIG_MIPS_MT_FPAFF */
1189 }
1190
1191 /*
1192 * No lock; only written during early bootup by CPU 0.
1193 */
1194 static RAW_NOTIFIER_HEAD(cu2_chain);
1195
register_cu2_notifier(struct notifier_block * nb)1196 int __ref register_cu2_notifier(struct notifier_block *nb)
1197 {
1198 return raw_notifier_chain_register(&cu2_chain, nb);
1199 }
1200
cu2_notifier_call_chain(unsigned long val,void * v)1201 int cu2_notifier_call_chain(unsigned long val, void *v)
1202 {
1203 return raw_notifier_call_chain(&cu2_chain, val, v);
1204 }
1205
default_cu2_call(struct notifier_block * nfb,unsigned long action,void * data)1206 static int default_cu2_call(struct notifier_block *nfb, unsigned long action,
1207 void *data)
1208 {
1209 struct pt_regs *regs = data;
1210
1211 die_if_kernel("COP2: Unhandled kernel unaligned access or invalid "
1212 "instruction", regs);
1213 force_sig(SIGILL, current);
1214
1215 return NOTIFY_OK;
1216 }
1217
enable_restore_fp_context(int msa)1218 static int enable_restore_fp_context(int msa)
1219 {
1220 int err, was_fpu_owner, prior_msa;
1221
1222 if (!used_math()) {
1223 /* First time FP context user. */
1224 preempt_disable();
1225 err = init_fpu();
1226 if (msa && !err) {
1227 enable_msa();
1228 init_msa_upper();
1229 set_thread_flag(TIF_USEDMSA);
1230 set_thread_flag(TIF_MSA_CTX_LIVE);
1231 }
1232 preempt_enable();
1233 if (!err)
1234 set_used_math();
1235 return err;
1236 }
1237
1238 /*
1239 * This task has formerly used the FP context.
1240 *
1241 * If this thread has no live MSA vector context then we can simply
1242 * restore the scalar FP context. If it has live MSA vector context
1243 * (that is, it has or may have used MSA since last performing a
1244 * function call) then we'll need to restore the vector context. This
1245 * applies even if we're currently only executing a scalar FP
1246 * instruction. This is because if we were to later execute an MSA
1247 * instruction then we'd either have to:
1248 *
1249 * - Restore the vector context & clobber any registers modified by
1250 * scalar FP instructions between now & then.
1251 *
1252 * or
1253 *
1254 * - Not restore the vector context & lose the most significant bits
1255 * of all vector registers.
1256 *
1257 * Neither of those options is acceptable. We cannot restore the least
1258 * significant bits of the registers now & only restore the most
1259 * significant bits later because the most significant bits of any
1260 * vector registers whose aliased FP register is modified now will have
1261 * been zeroed. We'd have no way to know that when restoring the vector
1262 * context & thus may load an outdated value for the most significant
1263 * bits of a vector register.
1264 */
1265 if (!msa && !thread_msa_context_live())
1266 return own_fpu(1);
1267
1268 /*
1269 * This task is using or has previously used MSA. Thus we require
1270 * that Status.FR == 1.
1271 */
1272 preempt_disable();
1273 was_fpu_owner = is_fpu_owner();
1274 err = own_fpu_inatomic(0);
1275 if (err)
1276 goto out;
1277
1278 enable_msa();
1279 write_msa_csr(current->thread.fpu.msacsr);
1280 set_thread_flag(TIF_USEDMSA);
1281
1282 /*
1283 * If this is the first time that the task is using MSA and it has
1284 * previously used scalar FP in this time slice then we already nave
1285 * FP context which we shouldn't clobber. We do however need to clear
1286 * the upper 64b of each vector register so that this task has no
1287 * opportunity to see data left behind by another.
1288 */
1289 prior_msa = test_and_set_thread_flag(TIF_MSA_CTX_LIVE);
1290 if (!prior_msa && was_fpu_owner) {
1291 init_msa_upper();
1292
1293 goto out;
1294 }
1295
1296 if (!prior_msa) {
1297 /*
1298 * Restore the least significant 64b of each vector register
1299 * from the existing scalar FP context.
1300 */
1301 _restore_fp(current);
1302
1303 /*
1304 * The task has not formerly used MSA, so clear the upper 64b
1305 * of each vector register such that it cannot see data left
1306 * behind by another task.
1307 */
1308 init_msa_upper();
1309 } else {
1310 /* We need to restore the vector context. */
1311 restore_msa(current);
1312
1313 /* Restore the scalar FP control & status register */
1314 if (!was_fpu_owner)
1315 write_32bit_cp1_register(CP1_STATUS,
1316 current->thread.fpu.fcr31);
1317 }
1318
1319 out:
1320 preempt_enable();
1321
1322 return 0;
1323 }
1324
do_cpu(struct pt_regs * regs)1325 asmlinkage void do_cpu(struct pt_regs *regs)
1326 {
1327 enum ctx_state prev_state;
1328 unsigned int __user *epc;
1329 unsigned long old_epc, old31;
1330 void __user *fault_addr;
1331 unsigned int opcode;
1332 unsigned long fcr31;
1333 unsigned int cpid;
1334 int status, err;
1335 int sig;
1336
1337 prev_state = exception_enter();
1338 cpid = (regs->cp0_cause >> CAUSEB_CE) & 3;
1339
1340 if (cpid != 2)
1341 die_if_kernel("do_cpu invoked from kernel context!", regs);
1342
1343 switch (cpid) {
1344 case 0:
1345 epc = (unsigned int __user *)exception_epc(regs);
1346 old_epc = regs->cp0_epc;
1347 old31 = regs->regs[31];
1348 opcode = 0;
1349 status = -1;
1350
1351 if (unlikely(compute_return_epc(regs) < 0))
1352 break;
1353
1354 if (!get_isa16_mode(regs->cp0_epc)) {
1355 if (unlikely(get_user(opcode, epc) < 0))
1356 status = SIGSEGV;
1357
1358 if (!cpu_has_llsc && status < 0)
1359 status = simulate_llsc(regs, opcode);
1360 }
1361
1362 if (status < 0)
1363 status = SIGILL;
1364
1365 if (unlikely(status > 0)) {
1366 regs->cp0_epc = old_epc; /* Undo skip-over. */
1367 regs->regs[31] = old31;
1368 force_sig(status, current);
1369 }
1370
1371 break;
1372
1373 case 3:
1374 /*
1375 * The COP3 opcode space and consequently the CP0.Status.CU3
1376 * bit and the CP0.Cause.CE=3 encoding have been removed as
1377 * of the MIPS III ISA. From the MIPS IV and MIPS32r2 ISAs
1378 * up the space has been reused for COP1X instructions, that
1379 * are enabled by the CP0.Status.CU1 bit and consequently
1380 * use the CP0.Cause.CE=1 encoding for Coprocessor Unusable
1381 * exceptions. Some FPU-less processors that implement one
1382 * of these ISAs however use this code erroneously for COP1X
1383 * instructions. Therefore we redirect this trap to the FP
1384 * emulator too.
1385 */
1386 if (raw_cpu_has_fpu || !cpu_has_mips_4_5_64_r2_r6) {
1387 force_sig(SIGILL, current);
1388 break;
1389 }
1390 /* Fall through. */
1391
1392 case 1:
1393 err = enable_restore_fp_context(0);
1394
1395 if (raw_cpu_has_fpu && !err)
1396 break;
1397
1398 sig = fpu_emulator_cop1Handler(regs, ¤t->thread.fpu, 0,
1399 &fault_addr);
1400
1401 /*
1402 * We can't allow the emulated instruction to leave
1403 * any enabled Cause bits set in $fcr31.
1404 */
1405 fcr31 = mask_fcr31_x(current->thread.fpu.fcr31);
1406 current->thread.fpu.fcr31 &= ~fcr31;
1407
1408 /* Send a signal if required. */
1409 if (!process_fpemu_return(sig, fault_addr, fcr31) && !err)
1410 mt_ase_fp_affinity();
1411
1412 break;
1413
1414 case 2:
1415 raw_notifier_call_chain(&cu2_chain, CU2_EXCEPTION, regs);
1416 break;
1417 }
1418
1419 exception_exit(prev_state);
1420 }
1421
do_msa_fpe(struct pt_regs * regs,unsigned int msacsr)1422 asmlinkage void do_msa_fpe(struct pt_regs *regs, unsigned int msacsr)
1423 {
1424 enum ctx_state prev_state;
1425
1426 prev_state = exception_enter();
1427 current->thread.trap_nr = (regs->cp0_cause >> 2) & 0x1f;
1428 if (notify_die(DIE_MSAFP, "MSA FP exception", regs, 0,
1429 current->thread.trap_nr, SIGFPE) == NOTIFY_STOP)
1430 goto out;
1431
1432 /* Clear MSACSR.Cause before enabling interrupts */
1433 write_msa_csr(msacsr & ~MSA_CSR_CAUSEF);
1434 local_irq_enable();
1435
1436 die_if_kernel("do_msa_fpe invoked from kernel context!", regs);
1437 force_sig(SIGFPE, current);
1438 out:
1439 exception_exit(prev_state);
1440 }
1441
do_msa(struct pt_regs * regs)1442 asmlinkage void do_msa(struct pt_regs *regs)
1443 {
1444 enum ctx_state prev_state;
1445 int err;
1446
1447 prev_state = exception_enter();
1448
1449 if (!cpu_has_msa || test_thread_flag(TIF_32BIT_FPREGS)) {
1450 force_sig(SIGILL, current);
1451 goto out;
1452 }
1453
1454 die_if_kernel("do_msa invoked from kernel context!", regs);
1455
1456 err = enable_restore_fp_context(1);
1457 if (err)
1458 force_sig(SIGILL, current);
1459 out:
1460 exception_exit(prev_state);
1461 }
1462
do_mdmx(struct pt_regs * regs)1463 asmlinkage void do_mdmx(struct pt_regs *regs)
1464 {
1465 enum ctx_state prev_state;
1466
1467 prev_state = exception_enter();
1468 force_sig(SIGILL, current);
1469 exception_exit(prev_state);
1470 }
1471
1472 /*
1473 * Called with interrupts disabled.
1474 */
do_watch(struct pt_regs * regs)1475 asmlinkage void do_watch(struct pt_regs *regs)
1476 {
1477 enum ctx_state prev_state;
1478
1479 prev_state = exception_enter();
1480 /*
1481 * Clear WP (bit 22) bit of cause register so we don't loop
1482 * forever.
1483 */
1484 clear_c0_cause(CAUSEF_WP);
1485
1486 /*
1487 * If the current thread has the watch registers loaded, save
1488 * their values and send SIGTRAP. Otherwise another thread
1489 * left the registers set, clear them and continue.
1490 */
1491 if (test_tsk_thread_flag(current, TIF_LOAD_WATCH)) {
1492 mips_read_watch_registers();
1493 local_irq_enable();
1494 force_sig_fault(SIGTRAP, TRAP_HWBKPT, NULL, current);
1495 } else {
1496 mips_clear_watch_registers();
1497 local_irq_enable();
1498 }
1499 exception_exit(prev_state);
1500 }
1501
do_mcheck(struct pt_regs * regs)1502 asmlinkage void do_mcheck(struct pt_regs *regs)
1503 {
1504 int multi_match = regs->cp0_status & ST0_TS;
1505 enum ctx_state prev_state;
1506 mm_segment_t old_fs = get_fs();
1507
1508 prev_state = exception_enter();
1509 show_regs(regs);
1510
1511 if (multi_match) {
1512 dump_tlb_regs();
1513 pr_info("\n");
1514 dump_tlb_all();
1515 }
1516
1517 if (!user_mode(regs))
1518 set_fs(KERNEL_DS);
1519
1520 show_code((unsigned int __user *) regs->cp0_epc);
1521
1522 set_fs(old_fs);
1523
1524 /*
1525 * Some chips may have other causes of machine check (e.g. SB1
1526 * graduation timer)
1527 */
1528 panic("Caught Machine Check exception - %scaused by multiple "
1529 "matching entries in the TLB.",
1530 (multi_match) ? "" : "not ");
1531 }
1532
do_mt(struct pt_regs * regs)1533 asmlinkage void do_mt(struct pt_regs *regs)
1534 {
1535 int subcode;
1536
1537 subcode = (read_vpe_c0_vpecontrol() & VPECONTROL_EXCPT)
1538 >> VPECONTROL_EXCPT_SHIFT;
1539 switch (subcode) {
1540 case 0:
1541 printk(KERN_DEBUG "Thread Underflow\n");
1542 break;
1543 case 1:
1544 printk(KERN_DEBUG "Thread Overflow\n");
1545 break;
1546 case 2:
1547 printk(KERN_DEBUG "Invalid YIELD Qualifier\n");
1548 break;
1549 case 3:
1550 printk(KERN_DEBUG "Gating Storage Exception\n");
1551 break;
1552 case 4:
1553 printk(KERN_DEBUG "YIELD Scheduler Exception\n");
1554 break;
1555 case 5:
1556 printk(KERN_DEBUG "Gating Storage Scheduler Exception\n");
1557 break;
1558 default:
1559 printk(KERN_DEBUG "*** UNKNOWN THREAD EXCEPTION %d ***\n",
1560 subcode);
1561 break;
1562 }
1563 die_if_kernel("MIPS MT Thread exception in kernel", regs);
1564
1565 force_sig(SIGILL, current);
1566 }
1567
1568
do_dsp(struct pt_regs * regs)1569 asmlinkage void do_dsp(struct pt_regs *regs)
1570 {
1571 if (cpu_has_dsp)
1572 panic("Unexpected DSP exception");
1573
1574 force_sig(SIGILL, current);
1575 }
1576
do_reserved(struct pt_regs * regs)1577 asmlinkage void do_reserved(struct pt_regs *regs)
1578 {
1579 /*
1580 * Game over - no way to handle this if it ever occurs. Most probably
1581 * caused by a new unknown cpu type or after another deadly
1582 * hard/software error.
1583 */
1584 show_regs(regs);
1585 panic("Caught reserved exception %ld - should not happen.",
1586 (regs->cp0_cause & 0x7f) >> 2);
1587 }
1588
1589 static int __initdata l1parity = 1;
nol1parity(char * s)1590 static int __init nol1parity(char *s)
1591 {
1592 l1parity = 0;
1593 return 1;
1594 }
1595 __setup("nol1par", nol1parity);
1596 static int __initdata l2parity = 1;
nol2parity(char * s)1597 static int __init nol2parity(char *s)
1598 {
1599 l2parity = 0;
1600 return 1;
1601 }
1602 __setup("nol2par", nol2parity);
1603
1604 /*
1605 * Some MIPS CPUs can enable/disable for cache parity detection, but do
1606 * it different ways.
1607 */
parity_protection_init(void)1608 static inline void parity_protection_init(void)
1609 {
1610 #define ERRCTL_PE 0x80000000
1611 #define ERRCTL_L2P 0x00800000
1612
1613 if (mips_cm_revision() >= CM_REV_CM3) {
1614 ulong gcr_ectl, cp0_ectl;
1615
1616 /*
1617 * With CM3 systems we need to ensure that the L1 & L2
1618 * parity enables are set to the same value, since this
1619 * is presumed by the hardware engineers.
1620 *
1621 * If the user disabled either of L1 or L2 ECC checking,
1622 * disable both.
1623 */
1624 l1parity &= l2parity;
1625 l2parity &= l1parity;
1626
1627 /* Probe L1 ECC support */
1628 cp0_ectl = read_c0_ecc();
1629 write_c0_ecc(cp0_ectl | ERRCTL_PE);
1630 back_to_back_c0_hazard();
1631 cp0_ectl = read_c0_ecc();
1632
1633 /* Probe L2 ECC support */
1634 gcr_ectl = read_gcr_err_control();
1635
1636 if (!(gcr_ectl & CM_GCR_ERR_CONTROL_L2_ECC_SUPPORT) ||
1637 !(cp0_ectl & ERRCTL_PE)) {
1638 /*
1639 * One of L1 or L2 ECC checking isn't supported,
1640 * so we cannot enable either.
1641 */
1642 l1parity = l2parity = 0;
1643 }
1644
1645 /* Configure L1 ECC checking */
1646 if (l1parity)
1647 cp0_ectl |= ERRCTL_PE;
1648 else
1649 cp0_ectl &= ~ERRCTL_PE;
1650 write_c0_ecc(cp0_ectl);
1651 back_to_back_c0_hazard();
1652 WARN_ON(!!(read_c0_ecc() & ERRCTL_PE) != l1parity);
1653
1654 /* Configure L2 ECC checking */
1655 if (l2parity)
1656 gcr_ectl |= CM_GCR_ERR_CONTROL_L2_ECC_EN;
1657 else
1658 gcr_ectl &= ~CM_GCR_ERR_CONTROL_L2_ECC_EN;
1659 write_gcr_err_control(gcr_ectl);
1660 gcr_ectl = read_gcr_err_control();
1661 gcr_ectl &= CM_GCR_ERR_CONTROL_L2_ECC_EN;
1662 WARN_ON(!!gcr_ectl != l2parity);
1663
1664 pr_info("Cache parity protection %sabled\n",
1665 l1parity ? "en" : "dis");
1666 return;
1667 }
1668
1669 switch (current_cpu_type()) {
1670 case CPU_24K:
1671 case CPU_34K:
1672 case CPU_74K:
1673 case CPU_1004K:
1674 case CPU_1074K:
1675 case CPU_INTERAPTIV:
1676 case CPU_PROAPTIV:
1677 case CPU_P5600:
1678 case CPU_QEMU_GENERIC:
1679 case CPU_P6600:
1680 {
1681 unsigned long errctl;
1682 unsigned int l1parity_present, l2parity_present;
1683
1684 errctl = read_c0_ecc();
1685 errctl &= ~(ERRCTL_PE|ERRCTL_L2P);
1686
1687 /* probe L1 parity support */
1688 write_c0_ecc(errctl | ERRCTL_PE);
1689 back_to_back_c0_hazard();
1690 l1parity_present = (read_c0_ecc() & ERRCTL_PE);
1691
1692 /* probe L2 parity support */
1693 write_c0_ecc(errctl|ERRCTL_L2P);
1694 back_to_back_c0_hazard();
1695 l2parity_present = (read_c0_ecc() & ERRCTL_L2P);
1696
1697 if (l1parity_present && l2parity_present) {
1698 if (l1parity)
1699 errctl |= ERRCTL_PE;
1700 if (l1parity ^ l2parity)
1701 errctl |= ERRCTL_L2P;
1702 } else if (l1parity_present) {
1703 if (l1parity)
1704 errctl |= ERRCTL_PE;
1705 } else if (l2parity_present) {
1706 if (l2parity)
1707 errctl |= ERRCTL_L2P;
1708 } else {
1709 /* No parity available */
1710 }
1711
1712 printk(KERN_INFO "Writing ErrCtl register=%08lx\n", errctl);
1713
1714 write_c0_ecc(errctl);
1715 back_to_back_c0_hazard();
1716 errctl = read_c0_ecc();
1717 printk(KERN_INFO "Readback ErrCtl register=%08lx\n", errctl);
1718
1719 if (l1parity_present)
1720 printk(KERN_INFO "Cache parity protection %sabled\n",
1721 (errctl & ERRCTL_PE) ? "en" : "dis");
1722
1723 if (l2parity_present) {
1724 if (l1parity_present && l1parity)
1725 errctl ^= ERRCTL_L2P;
1726 printk(KERN_INFO "L2 cache parity protection %sabled\n",
1727 (errctl & ERRCTL_L2P) ? "en" : "dis");
1728 }
1729 }
1730 break;
1731
1732 case CPU_5KC:
1733 case CPU_5KE:
1734 case CPU_LOONGSON1:
1735 write_c0_ecc(0x80000000);
1736 back_to_back_c0_hazard();
1737 /* Set the PE bit (bit 31) in the c0_errctl register. */
1738 printk(KERN_INFO "Cache parity protection %sabled\n",
1739 (read_c0_ecc() & 0x80000000) ? "en" : "dis");
1740 break;
1741 case CPU_20KC:
1742 case CPU_25KF:
1743 /* Clear the DE bit (bit 16) in the c0_status register. */
1744 printk(KERN_INFO "Enable cache parity protection for "
1745 "MIPS 20KC/25KF CPUs.\n");
1746 clear_c0_status(ST0_DE);
1747 break;
1748 default:
1749 break;
1750 }
1751 }
1752
cache_parity_error(void)1753 asmlinkage void cache_parity_error(void)
1754 {
1755 const int field = 2 * sizeof(unsigned long);
1756 unsigned int reg_val;
1757
1758 /* For the moment, report the problem and hang. */
1759 printk("Cache error exception:\n");
1760 printk("cp0_errorepc == %0*lx\n", field, read_c0_errorepc());
1761 reg_val = read_c0_cacheerr();
1762 printk("c0_cacheerr == %08x\n", reg_val);
1763
1764 printk("Decoded c0_cacheerr: %s cache fault in %s reference.\n",
1765 reg_val & (1<<30) ? "secondary" : "primary",
1766 reg_val & (1<<31) ? "data" : "insn");
1767 if ((cpu_has_mips_r2_r6) &&
1768 ((current_cpu_data.processor_id & 0xff0000) == PRID_COMP_MIPS)) {
1769 pr_err("Error bits: %s%s%s%s%s%s%s%s\n",
1770 reg_val & (1<<29) ? "ED " : "",
1771 reg_val & (1<<28) ? "ET " : "",
1772 reg_val & (1<<27) ? "ES " : "",
1773 reg_val & (1<<26) ? "EE " : "",
1774 reg_val & (1<<25) ? "EB " : "",
1775 reg_val & (1<<24) ? "EI " : "",
1776 reg_val & (1<<23) ? "E1 " : "",
1777 reg_val & (1<<22) ? "E0 " : "");
1778 } else {
1779 pr_err("Error bits: %s%s%s%s%s%s%s\n",
1780 reg_val & (1<<29) ? "ED " : "",
1781 reg_val & (1<<28) ? "ET " : "",
1782 reg_val & (1<<26) ? "EE " : "",
1783 reg_val & (1<<25) ? "EB " : "",
1784 reg_val & (1<<24) ? "EI " : "",
1785 reg_val & (1<<23) ? "E1 " : "",
1786 reg_val & (1<<22) ? "E0 " : "");
1787 }
1788 printk("IDX: 0x%08x\n", reg_val & ((1<<22)-1));
1789
1790 #if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
1791 if (reg_val & (1<<22))
1792 printk("DErrAddr0: 0x%0*lx\n", field, read_c0_derraddr0());
1793
1794 if (reg_val & (1<<23))
1795 printk("DErrAddr1: 0x%0*lx\n", field, read_c0_derraddr1());
1796 #endif
1797
1798 panic("Can't handle the cache error!");
1799 }
1800
do_ftlb(void)1801 asmlinkage void do_ftlb(void)
1802 {
1803 const int field = 2 * sizeof(unsigned long);
1804 unsigned int reg_val;
1805
1806 /* For the moment, report the problem and hang. */
1807 if ((cpu_has_mips_r2_r6) &&
1808 (((current_cpu_data.processor_id & 0xff0000) == PRID_COMP_MIPS) ||
1809 ((current_cpu_data.processor_id & 0xff0000) == PRID_COMP_LOONGSON))) {
1810 pr_err("FTLB error exception, cp0_ecc=0x%08x:\n",
1811 read_c0_ecc());
1812 pr_err("cp0_errorepc == %0*lx\n", field, read_c0_errorepc());
1813 reg_val = read_c0_cacheerr();
1814 pr_err("c0_cacheerr == %08x\n", reg_val);
1815
1816 if ((reg_val & 0xc0000000) == 0xc0000000) {
1817 pr_err("Decoded c0_cacheerr: FTLB parity error\n");
1818 } else {
1819 pr_err("Decoded c0_cacheerr: %s cache fault in %s reference.\n",
1820 reg_val & (1<<30) ? "secondary" : "primary",
1821 reg_val & (1<<31) ? "data" : "insn");
1822 }
1823 } else {
1824 pr_err("FTLB error exception\n");
1825 }
1826 /* Just print the cacheerr bits for now */
1827 cache_parity_error();
1828 }
1829
1830 /*
1831 * SDBBP EJTAG debug exception handler.
1832 * We skip the instruction and return to the next instruction.
1833 */
ejtag_exception_handler(struct pt_regs * regs)1834 void ejtag_exception_handler(struct pt_regs *regs)
1835 {
1836 const int field = 2 * sizeof(unsigned long);
1837 unsigned long depc, old_epc, old_ra;
1838 unsigned int debug;
1839
1840 printk(KERN_DEBUG "SDBBP EJTAG debug exception - not handled yet, just ignored!\n");
1841 depc = read_c0_depc();
1842 debug = read_c0_debug();
1843 printk(KERN_DEBUG "c0_depc = %0*lx, DEBUG = %08x\n", field, depc, debug);
1844 if (debug & 0x80000000) {
1845 /*
1846 * In branch delay slot.
1847 * We cheat a little bit here and use EPC to calculate the
1848 * debug return address (DEPC). EPC is restored after the
1849 * calculation.
1850 */
1851 old_epc = regs->cp0_epc;
1852 old_ra = regs->regs[31];
1853 regs->cp0_epc = depc;
1854 compute_return_epc(regs);
1855 depc = regs->cp0_epc;
1856 regs->cp0_epc = old_epc;
1857 regs->regs[31] = old_ra;
1858 } else
1859 depc += 4;
1860 write_c0_depc(depc);
1861
1862 #if 0
1863 printk(KERN_DEBUG "\n\n----- Enable EJTAG single stepping ----\n\n");
1864 write_c0_debug(debug | 0x100);
1865 #endif
1866 }
1867
1868 /*
1869 * NMI exception handler.
1870 * No lock; only written during early bootup by CPU 0.
1871 */
1872 static RAW_NOTIFIER_HEAD(nmi_chain);
1873
register_nmi_notifier(struct notifier_block * nb)1874 int register_nmi_notifier(struct notifier_block *nb)
1875 {
1876 return raw_notifier_chain_register(&nmi_chain, nb);
1877 }
1878
nmi_exception_handler(struct pt_regs * regs)1879 void __noreturn nmi_exception_handler(struct pt_regs *regs)
1880 {
1881 char str[100];
1882
1883 nmi_enter();
1884 raw_notifier_call_chain(&nmi_chain, 0, regs);
1885 bust_spinlocks(1);
1886 snprintf(str, 100, "CPU%d NMI taken, CP0_EPC=%lx\n",
1887 smp_processor_id(), regs->cp0_epc);
1888 regs->cp0_epc = read_c0_errorepc();
1889 die(str, regs);
1890 nmi_exit();
1891 }
1892
1893 #define VECTORSPACING 0x100 /* for EI/VI mode */
1894
1895 unsigned long ebase;
1896 EXPORT_SYMBOL_GPL(ebase);
1897 unsigned long exception_handlers[32];
1898 unsigned long vi_handlers[64];
1899
set_except_vector(int n,void * addr)1900 void __init *set_except_vector(int n, void *addr)
1901 {
1902 unsigned long handler = (unsigned long) addr;
1903 unsigned long old_handler;
1904
1905 #ifdef CONFIG_CPU_MICROMIPS
1906 /*
1907 * Only the TLB handlers are cache aligned with an even
1908 * address. All other handlers are on an odd address and
1909 * require no modification. Otherwise, MIPS32 mode will
1910 * be entered when handling any TLB exceptions. That
1911 * would be bad...since we must stay in microMIPS mode.
1912 */
1913 if (!(handler & 0x1))
1914 handler |= 1;
1915 #endif
1916 old_handler = xchg(&exception_handlers[n], handler);
1917
1918 if (n == 0 && cpu_has_divec) {
1919 #ifdef CONFIG_CPU_MICROMIPS
1920 unsigned long jump_mask = ~((1 << 27) - 1);
1921 #else
1922 unsigned long jump_mask = ~((1 << 28) - 1);
1923 #endif
1924 u32 *buf = (u32 *)(ebase + 0x200);
1925 unsigned int k0 = 26;
1926 if ((handler & jump_mask) == ((ebase + 0x200) & jump_mask)) {
1927 uasm_i_j(&buf, handler & ~jump_mask);
1928 uasm_i_nop(&buf);
1929 } else {
1930 UASM_i_LA(&buf, k0, handler);
1931 uasm_i_jr(&buf, k0);
1932 uasm_i_nop(&buf);
1933 }
1934 local_flush_icache_range(ebase + 0x200, (unsigned long)buf);
1935 }
1936 return (void *)old_handler;
1937 }
1938
do_default_vi(void)1939 static void do_default_vi(void)
1940 {
1941 show_regs(get_irq_regs());
1942 panic("Caught unexpected vectored interrupt.");
1943 }
1944
set_vi_srs_handler(int n,vi_handler_t addr,int srs)1945 static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs)
1946 {
1947 unsigned long handler;
1948 unsigned long old_handler = vi_handlers[n];
1949 int srssets = current_cpu_data.srsets;
1950 u16 *h;
1951 unsigned char *b;
1952
1953 BUG_ON(!cpu_has_veic && !cpu_has_vint);
1954
1955 if (addr == NULL) {
1956 handler = (unsigned long) do_default_vi;
1957 srs = 0;
1958 } else
1959 handler = (unsigned long) addr;
1960 vi_handlers[n] = handler;
1961
1962 b = (unsigned char *)(ebase + 0x200 + n*VECTORSPACING);
1963
1964 if (srs >= srssets)
1965 panic("Shadow register set %d not supported", srs);
1966
1967 if (cpu_has_veic) {
1968 if (board_bind_eic_interrupt)
1969 board_bind_eic_interrupt(n, srs);
1970 } else if (cpu_has_vint) {
1971 /* SRSMap is only defined if shadow sets are implemented */
1972 if (srssets > 1)
1973 change_c0_srsmap(0xf << n*4, srs << n*4);
1974 }
1975
1976 if (srs == 0) {
1977 /*
1978 * If no shadow set is selected then use the default handler
1979 * that does normal register saving and standard interrupt exit
1980 */
1981 extern char except_vec_vi, except_vec_vi_lui;
1982 extern char except_vec_vi_ori, except_vec_vi_end;
1983 extern char rollback_except_vec_vi;
1984 char *vec_start = using_rollback_handler() ?
1985 &rollback_except_vec_vi : &except_vec_vi;
1986 #if defined(CONFIG_CPU_MICROMIPS) || defined(CONFIG_CPU_BIG_ENDIAN)
1987 const int lui_offset = &except_vec_vi_lui - vec_start + 2;
1988 const int ori_offset = &except_vec_vi_ori - vec_start + 2;
1989 #else
1990 const int lui_offset = &except_vec_vi_lui - vec_start;
1991 const int ori_offset = &except_vec_vi_ori - vec_start;
1992 #endif
1993 const int handler_len = &except_vec_vi_end - vec_start;
1994
1995 if (handler_len > VECTORSPACING) {
1996 /*
1997 * Sigh... panicing won't help as the console
1998 * is probably not configured :(
1999 */
2000 panic("VECTORSPACING too small");
2001 }
2002
2003 set_handler(((unsigned long)b - ebase), vec_start,
2004 #ifdef CONFIG_CPU_MICROMIPS
2005 (handler_len - 1));
2006 #else
2007 handler_len);
2008 #endif
2009 h = (u16 *)(b + lui_offset);
2010 *h = (handler >> 16) & 0xffff;
2011 h = (u16 *)(b + ori_offset);
2012 *h = (handler & 0xffff);
2013 local_flush_icache_range((unsigned long)b,
2014 (unsigned long)(b+handler_len));
2015 }
2016 else {
2017 /*
2018 * In other cases jump directly to the interrupt handler. It
2019 * is the handler's responsibility to save registers if required
2020 * (eg hi/lo) and return from the exception using "eret".
2021 */
2022 u32 insn;
2023
2024 h = (u16 *)b;
2025 /* j handler */
2026 #ifdef CONFIG_CPU_MICROMIPS
2027 insn = 0xd4000000 | (((u32)handler & 0x07ffffff) >> 1);
2028 #else
2029 insn = 0x08000000 | (((u32)handler & 0x0fffffff) >> 2);
2030 #endif
2031 h[0] = (insn >> 16) & 0xffff;
2032 h[1] = insn & 0xffff;
2033 h[2] = 0;
2034 h[3] = 0;
2035 local_flush_icache_range((unsigned long)b,
2036 (unsigned long)(b+8));
2037 }
2038
2039 return (void *)old_handler;
2040 }
2041
set_vi_handler(int n,vi_handler_t addr)2042 void *set_vi_handler(int n, vi_handler_t addr)
2043 {
2044 return set_vi_srs_handler(n, addr, 0);
2045 }
2046
2047 extern void tlb_init(void);
2048
2049 /*
2050 * Timer interrupt
2051 */
2052 int cp0_compare_irq;
2053 EXPORT_SYMBOL_GPL(cp0_compare_irq);
2054 int cp0_compare_irq_shift;
2055
2056 /*
2057 * Performance counter IRQ or -1 if shared with timer
2058 */
2059 int cp0_perfcount_irq;
2060 EXPORT_SYMBOL_GPL(cp0_perfcount_irq);
2061
2062 /*
2063 * Fast debug channel IRQ or -1 if not present
2064 */
2065 int cp0_fdc_irq;
2066 EXPORT_SYMBOL_GPL(cp0_fdc_irq);
2067
2068 static int noulri;
2069
ulri_disable(char * s)2070 static int __init ulri_disable(char *s)
2071 {
2072 pr_info("Disabling ulri\n");
2073 noulri = 1;
2074
2075 return 1;
2076 }
2077 __setup("noulri", ulri_disable);
2078
2079 /* configure STATUS register */
configure_status(void)2080 static void configure_status(void)
2081 {
2082 /*
2083 * Disable coprocessors and select 32-bit or 64-bit addressing
2084 * and the 16/32 or 32/32 FPR register model. Reset the BEV
2085 * flag that some firmware may have left set and the TS bit (for
2086 * IP27). Set XX for ISA IV code to work.
2087 */
2088 unsigned int status_set = ST0_CU0;
2089 #ifdef CONFIG_64BIT
2090 status_set |= ST0_FR|ST0_KX|ST0_SX|ST0_UX;
2091 #endif
2092 if (current_cpu_data.isa_level & MIPS_CPU_ISA_IV)
2093 status_set |= ST0_XX;
2094 if (cpu_has_dsp)
2095 status_set |= ST0_MX;
2096
2097 change_c0_status(ST0_CU|ST0_MX|ST0_RE|ST0_FR|ST0_BEV|ST0_TS|ST0_KX|ST0_SX|ST0_UX,
2098 status_set);
2099 }
2100
2101 unsigned int hwrena;
2102 EXPORT_SYMBOL_GPL(hwrena);
2103
2104 /* configure HWRENA register */
configure_hwrena(void)2105 static void configure_hwrena(void)
2106 {
2107 hwrena = cpu_hwrena_impl_bits;
2108
2109 if (cpu_has_mips_r2_r6)
2110 hwrena |= MIPS_HWRENA_CPUNUM |
2111 MIPS_HWRENA_SYNCISTEP |
2112 MIPS_HWRENA_CC |
2113 MIPS_HWRENA_CCRES;
2114
2115 if (!noulri && cpu_has_userlocal)
2116 hwrena |= MIPS_HWRENA_ULR;
2117
2118 if (hwrena)
2119 write_c0_hwrena(hwrena);
2120 }
2121
configure_exception_vector(void)2122 static void configure_exception_vector(void)
2123 {
2124 if (cpu_has_veic || cpu_has_vint) {
2125 unsigned long sr = set_c0_status(ST0_BEV);
2126 /* If available, use WG to set top bits of EBASE */
2127 if (cpu_has_ebase_wg) {
2128 #ifdef CONFIG_64BIT
2129 write_c0_ebase_64(ebase | MIPS_EBASE_WG);
2130 #else
2131 write_c0_ebase(ebase | MIPS_EBASE_WG);
2132 #endif
2133 }
2134 write_c0_ebase(ebase);
2135 write_c0_status(sr);
2136 /* Setting vector spacing enables EI/VI mode */
2137 change_c0_intctl(0x3e0, VECTORSPACING);
2138 }
2139 if (cpu_has_divec) {
2140 if (cpu_has_mipsmt) {
2141 unsigned int vpflags = dvpe();
2142 set_c0_cause(CAUSEF_IV);
2143 evpe(vpflags);
2144 } else
2145 set_c0_cause(CAUSEF_IV);
2146 }
2147 }
2148
per_cpu_trap_init(bool is_boot_cpu)2149 void per_cpu_trap_init(bool is_boot_cpu)
2150 {
2151 unsigned int cpu = smp_processor_id();
2152
2153 configure_status();
2154 configure_hwrena();
2155
2156 configure_exception_vector();
2157
2158 /*
2159 * Before R2 both interrupt numbers were fixed to 7, so on R2 only:
2160 *
2161 * o read IntCtl.IPTI to determine the timer interrupt
2162 * o read IntCtl.IPPCI to determine the performance counter interrupt
2163 * o read IntCtl.IPFDC to determine the fast debug channel interrupt
2164 */
2165 if (cpu_has_mips_r2_r6) {
2166 /*
2167 * We shouldn't trust a secondary core has a sane EBASE register
2168 * so use the one calculated by the boot CPU.
2169 */
2170 if (!is_boot_cpu) {
2171 /* If available, use WG to set top bits of EBASE */
2172 if (cpu_has_ebase_wg) {
2173 #ifdef CONFIG_64BIT
2174 write_c0_ebase_64(ebase | MIPS_EBASE_WG);
2175 #else
2176 write_c0_ebase(ebase | MIPS_EBASE_WG);
2177 #endif
2178 }
2179 write_c0_ebase(ebase);
2180 }
2181
2182 cp0_compare_irq_shift = CAUSEB_TI - CAUSEB_IP;
2183 cp0_compare_irq = (read_c0_intctl() >> INTCTLB_IPTI) & 7;
2184 cp0_perfcount_irq = (read_c0_intctl() >> INTCTLB_IPPCI) & 7;
2185 cp0_fdc_irq = (read_c0_intctl() >> INTCTLB_IPFDC) & 7;
2186 if (!cp0_fdc_irq)
2187 cp0_fdc_irq = -1;
2188
2189 } else {
2190 cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ;
2191 cp0_compare_irq_shift = CP0_LEGACY_PERFCNT_IRQ;
2192 cp0_perfcount_irq = -1;
2193 cp0_fdc_irq = -1;
2194 }
2195
2196 if (!cpu_data[cpu].asid_cache)
2197 cpu_data[cpu].asid_cache = asid_first_version(cpu);
2198
2199 mmgrab(&init_mm);
2200 current->active_mm = &init_mm;
2201 BUG_ON(current->mm);
2202 enter_lazy_tlb(&init_mm, current);
2203
2204 /* Boot CPU's cache setup in setup_arch(). */
2205 if (!is_boot_cpu)
2206 cpu_cache_init();
2207 tlb_init();
2208 TLBMISS_HANDLER_SETUP();
2209 }
2210
2211 /* Install CPU exception handler */
set_handler(unsigned long offset,void * addr,unsigned long size)2212 void set_handler(unsigned long offset, void *addr, unsigned long size)
2213 {
2214 #ifdef CONFIG_CPU_MICROMIPS
2215 memcpy((void *)(ebase + offset), ((unsigned char *)addr - 1), size);
2216 #else
2217 memcpy((void *)(ebase + offset), addr, size);
2218 #endif
2219 local_flush_icache_range(ebase + offset, ebase + offset + size);
2220 }
2221
2222 static const char panic_null_cerr[] =
2223 "Trying to set NULL cache error exception handler\n";
2224
2225 /*
2226 * Install uncached CPU exception handler.
2227 * This is suitable only for the cache error exception which is the only
2228 * exception handler that is being run uncached.
2229 */
set_uncached_handler(unsigned long offset,void * addr,unsigned long size)2230 void set_uncached_handler(unsigned long offset, void *addr,
2231 unsigned long size)
2232 {
2233 unsigned long uncached_ebase = CKSEG1ADDR(ebase);
2234
2235 if (!addr)
2236 panic(panic_null_cerr);
2237
2238 memcpy((void *)(uncached_ebase + offset), addr, size);
2239 }
2240
2241 static int __initdata rdhwr_noopt;
set_rdhwr_noopt(char * str)2242 static int __init set_rdhwr_noopt(char *str)
2243 {
2244 rdhwr_noopt = 1;
2245 return 1;
2246 }
2247
2248 __setup("rdhwr_noopt", set_rdhwr_noopt);
2249
trap_init(void)2250 void __init trap_init(void)
2251 {
2252 extern char except_vec3_generic;
2253 extern char except_vec4;
2254 extern char except_vec3_r4000;
2255 unsigned long i;
2256
2257 check_wait();
2258
2259 if (cpu_has_veic || cpu_has_vint) {
2260 unsigned long size = 0x200 + VECTORSPACING*64;
2261 phys_addr_t ebase_pa;
2262
2263 ebase = (unsigned long)
2264 __alloc_bootmem(size, 1 << fls(size), 0);
2265
2266 /*
2267 * Try to ensure ebase resides in KSeg0 if possible.
2268 *
2269 * It shouldn't generally be in XKPhys on MIPS64 to avoid
2270 * hitting a poorly defined exception base for Cache Errors.
2271 * The allocation is likely to be in the low 512MB of physical,
2272 * in which case we should be able to convert to KSeg0.
2273 *
2274 * EVA is special though as it allows segments to be rearranged
2275 * and to become uncached during cache error handling.
2276 */
2277 ebase_pa = __pa(ebase);
2278 if (!IS_ENABLED(CONFIG_EVA) && !WARN_ON(ebase_pa >= 0x20000000))
2279 ebase = CKSEG0ADDR(ebase_pa);
2280 } else {
2281 ebase = CAC_BASE;
2282
2283 if (cpu_has_mips_r2_r6) {
2284 if (cpu_has_ebase_wg) {
2285 #ifdef CONFIG_64BIT
2286 ebase = (read_c0_ebase_64() & ~0xfff);
2287 #else
2288 ebase = (read_c0_ebase() & ~0xfff);
2289 #endif
2290 } else {
2291 ebase += (read_c0_ebase() & 0x3ffff000);
2292 }
2293 }
2294 }
2295
2296 if (cpu_has_mmips) {
2297 unsigned int config3 = read_c0_config3();
2298
2299 if (IS_ENABLED(CONFIG_CPU_MICROMIPS))
2300 write_c0_config3(config3 | MIPS_CONF3_ISA_OE);
2301 else
2302 write_c0_config3(config3 & ~MIPS_CONF3_ISA_OE);
2303 }
2304
2305 if (board_ebase_setup)
2306 board_ebase_setup();
2307 per_cpu_trap_init(true);
2308
2309 /*
2310 * Copy the generic exception handlers to their final destination.
2311 * This will be overridden later as suitable for a particular
2312 * configuration.
2313 */
2314 set_handler(0x180, &except_vec3_generic, 0x80);
2315
2316 /*
2317 * Setup default vectors
2318 */
2319 for (i = 0; i <= 31; i++)
2320 set_except_vector(i, handle_reserved);
2321
2322 /*
2323 * Copy the EJTAG debug exception vector handler code to it's final
2324 * destination.
2325 */
2326 if (cpu_has_ejtag && board_ejtag_handler_setup)
2327 board_ejtag_handler_setup();
2328
2329 /*
2330 * Only some CPUs have the watch exceptions.
2331 */
2332 if (cpu_has_watch)
2333 set_except_vector(EXCCODE_WATCH, handle_watch);
2334
2335 /*
2336 * Initialise interrupt handlers
2337 */
2338 if (cpu_has_veic || cpu_has_vint) {
2339 int nvec = cpu_has_veic ? 64 : 8;
2340 for (i = 0; i < nvec; i++)
2341 set_vi_handler(i, NULL);
2342 }
2343 else if (cpu_has_divec)
2344 set_handler(0x200, &except_vec4, 0x8);
2345
2346 /*
2347 * Some CPUs can enable/disable for cache parity detection, but does
2348 * it different ways.
2349 */
2350 parity_protection_init();
2351
2352 /*
2353 * The Data Bus Errors / Instruction Bus Errors are signaled
2354 * by external hardware. Therefore these two exceptions
2355 * may have board specific handlers.
2356 */
2357 if (board_be_init)
2358 board_be_init();
2359
2360 set_except_vector(EXCCODE_INT, using_rollback_handler() ?
2361 rollback_handle_int : handle_int);
2362 set_except_vector(EXCCODE_MOD, handle_tlbm);
2363 set_except_vector(EXCCODE_TLBL, handle_tlbl);
2364 set_except_vector(EXCCODE_TLBS, handle_tlbs);
2365
2366 set_except_vector(EXCCODE_ADEL, handle_adel);
2367 set_except_vector(EXCCODE_ADES, handle_ades);
2368
2369 set_except_vector(EXCCODE_IBE, handle_ibe);
2370 set_except_vector(EXCCODE_DBE, handle_dbe);
2371
2372 set_except_vector(EXCCODE_SYS, handle_sys);
2373 set_except_vector(EXCCODE_BP, handle_bp);
2374
2375 if (rdhwr_noopt)
2376 set_except_vector(EXCCODE_RI, handle_ri);
2377 else {
2378 if (cpu_has_vtag_icache)
2379 set_except_vector(EXCCODE_RI, handle_ri_rdhwr_tlbp);
2380 else if (current_cpu_type() == CPU_LOONGSON3)
2381 set_except_vector(EXCCODE_RI, handle_ri_rdhwr_tlbp);
2382 else
2383 set_except_vector(EXCCODE_RI, handle_ri_rdhwr);
2384 }
2385
2386 set_except_vector(EXCCODE_CPU, handle_cpu);
2387 set_except_vector(EXCCODE_OV, handle_ov);
2388 set_except_vector(EXCCODE_TR, handle_tr);
2389 set_except_vector(EXCCODE_MSAFPE, handle_msa_fpe);
2390
2391 if (board_nmi_handler_setup)
2392 board_nmi_handler_setup();
2393
2394 if (cpu_has_fpu && !cpu_has_nofpuex)
2395 set_except_vector(EXCCODE_FPE, handle_fpe);
2396
2397 set_except_vector(MIPS_EXCCODE_TLBPAR, handle_ftlb);
2398
2399 if (cpu_has_rixiex) {
2400 set_except_vector(EXCCODE_TLBRI, tlb_do_page_fault_0);
2401 set_except_vector(EXCCODE_TLBXI, tlb_do_page_fault_0);
2402 }
2403
2404 set_except_vector(EXCCODE_MSADIS, handle_msa);
2405 set_except_vector(EXCCODE_MDMX, handle_mdmx);
2406
2407 if (cpu_has_mcheck)
2408 set_except_vector(EXCCODE_MCHECK, handle_mcheck);
2409
2410 if (cpu_has_mipsmt)
2411 set_except_vector(EXCCODE_THREAD, handle_mt);
2412
2413 set_except_vector(EXCCODE_DSPDIS, handle_dsp);
2414
2415 if (board_cache_error_setup)
2416 board_cache_error_setup();
2417
2418 if (cpu_has_vce)
2419 /* Special exception: R4[04]00 uses also the divec space. */
2420 set_handler(0x180, &except_vec3_r4000, 0x100);
2421 else if (cpu_has_4kex)
2422 set_handler(0x180, &except_vec3_generic, 0x80);
2423 else
2424 set_handler(0x080, &except_vec3_generic, 0x80);
2425
2426 local_flush_icache_range(ebase, ebase + 0x400);
2427
2428 sort_extable(__start___dbe_table, __stop___dbe_table);
2429
2430 cu2_notifier(default_cu2_call, 0x80000000); /* Run last */
2431 }
2432
trap_pm_notifier(struct notifier_block * self,unsigned long cmd,void * v)2433 static int trap_pm_notifier(struct notifier_block *self, unsigned long cmd,
2434 void *v)
2435 {
2436 switch (cmd) {
2437 case CPU_PM_ENTER_FAILED:
2438 case CPU_PM_EXIT:
2439 configure_status();
2440 configure_hwrena();
2441 configure_exception_vector();
2442
2443 /* Restore register with CPU number for TLB handlers */
2444 TLBMISS_HANDLER_RESTORE();
2445
2446 break;
2447 }
2448
2449 return NOTIFY_OK;
2450 }
2451
2452 static struct notifier_block trap_pm_notifier_block = {
2453 .notifier_call = trap_pm_notifier,
2454 };
2455
trap_pm_init(void)2456 static int __init trap_pm_init(void)
2457 {
2458 return cpu_pm_register_notifier(&trap_pm_notifier_block);
2459 }
2460 arch_initcall(trap_pm_init);
2461
