1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright(c) 2013 - 2018 Intel Corporation. */ 3 4 #ifndef _FM10K_TYPE_H_ 5 #define _FM10K_TYPE_H_ 6 7 /* forward declaration */ 8 struct fm10k_hw; 9 10 #include <linux/types.h> 11 #include <asm/byteorder.h> 12 #include <linux/etherdevice.h> 13 14 #include "fm10k_mbx.h" 15 16 #define FM10K_DEV_ID_PF 0x15A4 17 #define FM10K_DEV_ID_VF 0x15A5 18 19 #define FM10K_MAX_QUEUES 256 20 #define FM10K_MAX_QUEUES_PF 128 21 #define FM10K_MAX_QUEUES_POOL 16 22 23 #define FM10K_48_BIT_MASK 0x0000FFFFFFFFFFFFull 24 #define FM10K_STAT_VALID 0x80000000 25 26 /* PCI Bus Info */ 27 #define FM10K_PCIE_LINK_CAP 0x7C 28 #define FM10K_PCIE_LINK_STATUS 0x82 29 #define FM10K_PCIE_LINK_WIDTH 0x3F0 30 #define FM10K_PCIE_LINK_WIDTH_1 0x10 31 #define FM10K_PCIE_LINK_WIDTH_2 0x20 32 #define FM10K_PCIE_LINK_WIDTH_4 0x40 33 #define FM10K_PCIE_LINK_WIDTH_8 0x80 34 #define FM10K_PCIE_LINK_SPEED 0xF 35 #define FM10K_PCIE_LINK_SPEED_2500 0x1 36 #define FM10K_PCIE_LINK_SPEED_5000 0x2 37 #define FM10K_PCIE_LINK_SPEED_8000 0x3 38 39 /* PCIe payload size */ 40 #define FM10K_PCIE_DEV_CAP 0x74 41 #define FM10K_PCIE_DEV_CAP_PAYLOAD 0x07 42 #define FM10K_PCIE_DEV_CAP_PAYLOAD_128 0x00 43 #define FM10K_PCIE_DEV_CAP_PAYLOAD_256 0x01 44 #define FM10K_PCIE_DEV_CAP_PAYLOAD_512 0x02 45 #define FM10K_PCIE_DEV_CTRL 0x78 46 #define FM10K_PCIE_DEV_CTRL_PAYLOAD 0xE0 47 #define FM10K_PCIE_DEV_CTRL_PAYLOAD_128 0x00 48 #define FM10K_PCIE_DEV_CTRL_PAYLOAD_256 0x20 49 #define FM10K_PCIE_DEV_CTRL_PAYLOAD_512 0x40 50 51 /* PCIe MSI-X Capability info */ 52 #define FM10K_PCI_MSIX_MSG_CTRL 0xB2 53 #define FM10K_PCI_MSIX_MSG_CTRL_TBL_SZ_MASK 0x7FF 54 #define FM10K_MAX_MSIX_VECTORS 256 55 #define FM10K_MAX_VECTORS_PF 256 56 #define FM10K_MAX_VECTORS_POOL 32 57 58 /* PCIe SR-IOV Info */ 59 #define FM10K_PCIE_SRIOV_CTRL 0x190 60 #define FM10K_PCIE_SRIOV_CTRL_VFARI 0x10 61 62 #define FM10K_ERR_PARAM -2 63 #define FM10K_ERR_NO_RESOURCES -3 64 #define FM10K_ERR_REQUESTS_PENDING -4 65 #define FM10K_ERR_RESET_REQUESTED -5 66 #define FM10K_ERR_DMA_PENDING -6 67 #define FM10K_ERR_RESET_FAILED -7 68 #define FM10K_ERR_INVALID_MAC_ADDR -8 69 #define FM10K_ERR_INVALID_VALUE -9 70 #define FM10K_NOT_IMPLEMENTED 0x7FFFFFFF 71 72 /* Start of PF registers */ 73 #define FM10K_CTRL 0x0000 74 #define FM10K_CTRL_BAR4_ALLOWED 0x00000004 75 76 #define FM10K_CTRL_EXT 0x0001 77 #define FM10K_GCR 0x0003 78 #define FM10K_GCR_EXT 0x0005 79 80 /* Interrupt control registers */ 81 #define FM10K_EICR 0x0006 82 #define FM10K_EICR_FAULT_MASK 0x0000003F 83 #define FM10K_EICR_MAILBOX 0x00000040 84 #define FM10K_EICR_SWITCHREADY 0x00000080 85 #define FM10K_EICR_SWITCHNOTREADY 0x00000100 86 #define FM10K_EICR_SWITCHINTERRUPT 0x00000200 87 #define FM10K_EICR_VFLR 0x00000800 88 #define FM10K_EICR_MAXHOLDTIME 0x00001000 89 #define FM10K_EIMR 0x0007 90 #define FM10K_EIMR_PCA_FAULT 0x00000001 91 #define FM10K_EIMR_THI_FAULT 0x00000010 92 #define FM10K_EIMR_FUM_FAULT 0x00000400 93 #define FM10K_EIMR_MAILBOX 0x00001000 94 #define FM10K_EIMR_SWITCHREADY 0x00004000 95 #define FM10K_EIMR_SWITCHNOTREADY 0x00010000 96 #define FM10K_EIMR_SWITCHINTERRUPT 0x00040000 97 #define FM10K_EIMR_SRAMERROR 0x00100000 98 #define FM10K_EIMR_VFLR 0x00400000 99 #define FM10K_EIMR_MAXHOLDTIME 0x01000000 100 #define FM10K_EIMR_ALL 0x55555555 101 #define FM10K_EIMR_DISABLE(NAME) ((FM10K_EIMR_ ## NAME) << 0) 102 #define FM10K_EIMR_ENABLE(NAME) ((FM10K_EIMR_ ## NAME) << 1) 103 #define FM10K_FAULT_ADDR_LO 0x0 104 #define FM10K_FAULT_ADDR_HI 0x1 105 #define FM10K_FAULT_SPECINFO 0x2 106 #define FM10K_FAULT_FUNC 0x3 107 #define FM10K_FAULT_SIZE 0x4 108 #define FM10K_FAULT_FUNC_VALID 0x00008000 109 #define FM10K_FAULT_FUNC_PF 0x00004000 110 #define FM10K_FAULT_FUNC_VF_MASK 0x00003F00 111 #define FM10K_FAULT_FUNC_VF_SHIFT 8 112 #define FM10K_FAULT_FUNC_TYPE_MASK 0x000000FF 113 114 #define FM10K_PCA_FAULT 0x0008 115 #define FM10K_THI_FAULT 0x0010 116 #define FM10K_FUM_FAULT 0x001C 117 118 /* Rx queue timeout indicator */ 119 #define FM10K_MAXHOLDQ(_n) ((_n) + 0x0020) 120 121 /* Switch Manager info */ 122 #define FM10K_SM_AREA(_n) ((_n) + 0x0028) 123 124 /* GLORT mapping registers */ 125 #define FM10K_DGLORTMAP(_n) ((_n) + 0x0030) 126 #define FM10K_DGLORT_COUNT 8 127 #define FM10K_DGLORTMAP_MASK_SHIFT 16 128 #define FM10K_DGLORTMAP_ANY 0x00000000 129 #define FM10K_DGLORTMAP_NONE 0x0000FFFF 130 #define FM10K_DGLORTMAP_ZERO 0xFFFF0000 131 #define FM10K_DGLORTDEC(_n) ((_n) + 0x0038) 132 #define FM10K_DGLORTDEC_VSILENGTH_SHIFT 4 133 #define FM10K_DGLORTDEC_VSIBASE_SHIFT 7 134 #define FM10K_DGLORTDEC_PCLENGTH_SHIFT 14 135 #define FM10K_DGLORTDEC_QBASE_SHIFT 16 136 #define FM10K_DGLORTDEC_RSSLENGTH_SHIFT 24 137 #define FM10K_DGLORTDEC_INNERRSS_ENABLE 0x08000000 138 #define FM10K_TUNNEL_CFG 0x0040 139 #define FM10K_TUNNEL_CFG_NVGRE_SHIFT 16 140 #define FM10K_TUNNEL_CFG_GENEVE 0x0041 141 #define FM10K_SWPRI_MAP(_n) ((_n) + 0x0050) 142 #define FM10K_SWPRI_MAX 16 143 #define FM10K_RSSRK(_n, _m) (((_n) * 0x10) + (_m) + 0x0800) 144 #define FM10K_RSSRK_SIZE 10 145 #define FM10K_RSSRK_ENTRIES_PER_REG 4 146 #define FM10K_RETA(_n, _m) (((_n) * 0x20) + (_m) + 0x1000) 147 #define FM10K_RETA_SIZE 32 148 #define FM10K_RETA_ENTRIES_PER_REG 4 149 #define FM10K_MAX_RSS_INDICES 128 150 151 /* Rate limiting registers */ 152 #define FM10K_TC_CREDIT(_n) ((_n) + 0x2000) 153 #define FM10K_TC_CREDIT_CREDIT_MASK 0x001FFFFF 154 #define FM10K_TC_MAXCREDIT(_n) ((_n) + 0x2040) 155 #define FM10K_TC_MAXCREDIT_64K 0x00010000 156 #define FM10K_TC_RATE(_n) ((_n) + 0x2080) 157 #define FM10K_TC_RATE_QUANTA_MASK 0x0000FFFF 158 #define FM10K_TC_RATE_INTERVAL_4US_GEN1 0x00020000 159 #define FM10K_TC_RATE_INTERVAL_4US_GEN2 0x00040000 160 #define FM10K_TC_RATE_INTERVAL_4US_GEN3 0x00080000 161 162 /* DMA control registers */ 163 #define FM10K_DMA_CTRL 0x20C3 164 #define FM10K_DMA_CTRL_TX_ENABLE 0x00000001 165 #define FM10K_DMA_CTRL_TX_ACTIVE 0x00000008 166 #define FM10K_DMA_CTRL_RX_ENABLE 0x00000010 167 #define FM10K_DMA_CTRL_RX_ACTIVE 0x00000080 168 #define FM10K_DMA_CTRL_RX_DESC_SIZE 0x00000100 169 #define FM10K_DMA_CTRL_MINMSS_64 0x00008000 170 #define FM10K_DMA_CTRL_MAX_HOLD_1US_GEN3 0x04800000 171 #define FM10K_DMA_CTRL_MAX_HOLD_1US_GEN2 0x04000000 172 #define FM10K_DMA_CTRL_MAX_HOLD_1US_GEN1 0x03800000 173 #define FM10K_DMA_CTRL_DATAPATH_RESET 0x20000000 174 #define FM10K_DMA_CTRL_32_DESC 0x00000000 175 176 #define FM10K_DMA_CTRL2 0x20C4 177 #define FM10K_DMA_CTRL2_SWITCH_READY 0x00002000 178 179 /* TSO flags configuration 180 * First packet contains all flags except for fin and psh 181 * Middle packet contains only urg and ack 182 * Last packet contains urg, ack, fin, and psh 183 */ 184 #define FM10K_TSO_FLAGS_LOW 0x00300FF6 185 #define FM10K_TSO_FLAGS_HI 0x00000039 186 #define FM10K_DTXTCPFLGL 0x20C5 187 #define FM10K_DTXTCPFLGH 0x20C6 188 189 #define FM10K_TPH_CTRL 0x20C7 190 #define FM10K_MRQC(_n) ((_n) + 0x2100) 191 #define FM10K_MRQC_TCP_IPV4 0x00000001 192 #define FM10K_MRQC_IPV4 0x00000002 193 #define FM10K_MRQC_IPV6 0x00000010 194 #define FM10K_MRQC_TCP_IPV6 0x00000020 195 #define FM10K_MRQC_UDP_IPV4 0x00000040 196 #define FM10K_MRQC_UDP_IPV6 0x00000080 197 198 #define FM10K_TQMAP(_n) ((_n) + 0x2800) 199 #define FM10K_TQMAP_TABLE_SIZE 2048 200 #define FM10K_RQMAP(_n) ((_n) + 0x3000) 201 202 /* Hardware Statistics */ 203 #define FM10K_STATS_TIMEOUT 0x3800 204 #define FM10K_STATS_UR 0x3801 205 #define FM10K_STATS_CA 0x3802 206 #define FM10K_STATS_UM 0x3803 207 #define FM10K_STATS_XEC 0x3804 208 #define FM10K_STATS_VLAN_DROP 0x3805 209 #define FM10K_STATS_LOOPBACK_DROP 0x3806 210 #define FM10K_STATS_NODESC_DROP 0x3807 211 212 /* PCIe state registers */ 213 #define FM10K_PHYADDR 0x381C 214 215 /* Rx ring registers */ 216 #define FM10K_RDBAL(_n) ((0x40 * (_n)) + 0x4000) 217 #define FM10K_RDBAH(_n) ((0x40 * (_n)) + 0x4001) 218 #define FM10K_RDLEN(_n) ((0x40 * (_n)) + 0x4002) 219 #define FM10K_TPH_RXCTRL(_n) ((0x40 * (_n)) + 0x4003) 220 #define FM10K_TPH_RXCTRL_DESC_TPHEN 0x00000020 221 #define FM10K_TPH_RXCTRL_DESC_RROEN 0x00000200 222 #define FM10K_TPH_RXCTRL_DATA_WROEN 0x00002000 223 #define FM10K_TPH_RXCTRL_HDR_WROEN 0x00008000 224 #define FM10K_RDH(_n) ((0x40 * (_n)) + 0x4004) 225 #define FM10K_RDT(_n) ((0x40 * (_n)) + 0x4005) 226 #define FM10K_RXQCTL(_n) ((0x40 * (_n)) + 0x4006) 227 #define FM10K_RXQCTL_ENABLE 0x00000001 228 #define FM10K_RXQCTL_PF 0x000000FC 229 #define FM10K_RXQCTL_VF_SHIFT 2 230 #define FM10K_RXQCTL_VF 0x00000100 231 #define FM10K_RXQCTL_ID_MASK (FM10K_RXQCTL_PF | FM10K_RXQCTL_VF) 232 #define FM10K_RXDCTL(_n) ((0x40 * (_n)) + 0x4007) 233 #define FM10K_RXDCTL_WRITE_BACK_MIN_DELAY 0x00000001 234 #define FM10K_RXDCTL_DROP_ON_EMPTY 0x00000200 235 #define FM10K_RXINT(_n) ((0x40 * (_n)) + 0x4008) 236 #define FM10K_SRRCTL(_n) ((0x40 * (_n)) + 0x4009) 237 #define FM10K_SRRCTL_BSIZEPKT_SHIFT 8 /* shift _right_ */ 238 #define FM10K_SRRCTL_LOOPBACK_SUPPRESS 0x40000000 239 #define FM10K_SRRCTL_BUFFER_CHAINING_EN 0x80000000 240 241 /* Rx Statistics */ 242 #define FM10K_QPRC(_n) ((0x40 * (_n)) + 0x400A) 243 #define FM10K_QPRDC(_n) ((0x40 * (_n)) + 0x400B) 244 #define FM10K_QBRC_L(_n) ((0x40 * (_n)) + 0x400C) 245 #define FM10K_QBRC_H(_n) ((0x40 * (_n)) + 0x400D) 246 247 /* Rx GLORT register */ 248 #define FM10K_RX_SGLORT(_n) ((0x40 * (_n)) + 0x400E) 249 250 /* Tx ring registers */ 251 #define FM10K_TDBAL(_n) ((0x40 * (_n)) + 0x8000) 252 #define FM10K_TDBAH(_n) ((0x40 * (_n)) + 0x8001) 253 #define FM10K_TDLEN(_n) ((0x40 * (_n)) + 0x8002) 254 /* When fist initialized, VFs need to know the Interrupt Throttle Rate (ITR) 255 * scale which is based on the PCIe speed but the speed information in the PCI 256 * configuration space may not be accurate. The PF already knows the ITR scale 257 * but there is no defined method to pass that information from the PF to the 258 * VF. This is accomplished during VF initialization by temporarily co-opting 259 * the yet-to-be-used TDLEN register to have the PF store the ITR shift for 260 * the VF to retrieve before the VF needs to use the TDLEN register for its 261 * intended purpose, i.e. before the Tx resources are allocated. 262 */ 263 #define FM10K_TDLEN_ITR_SCALE_SHIFT 9 264 #define FM10K_TDLEN_ITR_SCALE_MASK 0x00000E00 265 #define FM10K_TDLEN_ITR_SCALE_GEN1 2 266 #define FM10K_TDLEN_ITR_SCALE_GEN2 1 267 #define FM10K_TDLEN_ITR_SCALE_GEN3 0 268 #define FM10K_TPH_TXCTRL(_n) ((0x40 * (_n)) + 0x8003) 269 #define FM10K_TPH_TXCTRL_DESC_TPHEN 0x00000020 270 #define FM10K_TPH_TXCTRL_DESC_RROEN 0x00000200 271 #define FM10K_TPH_TXCTRL_DESC_WROEN 0x00000800 272 #define FM10K_TPH_TXCTRL_DATA_RROEN 0x00002000 273 #define FM10K_TDH(_n) ((0x40 * (_n)) + 0x8004) 274 #define FM10K_TDT(_n) ((0x40 * (_n)) + 0x8005) 275 #define FM10K_TXDCTL(_n) ((0x40 * (_n)) + 0x8006) 276 #define FM10K_TXDCTL_ENABLE 0x00004000 277 #define FM10K_TXDCTL_MAX_TIME_SHIFT 16 278 #define FM10K_TXQCTL(_n) ((0x40 * (_n)) + 0x8007) 279 #define FM10K_TXQCTL_PF 0x0000003F 280 #define FM10K_TXQCTL_VF 0x00000040 281 #define FM10K_TXQCTL_ID_MASK (FM10K_TXQCTL_PF | FM10K_TXQCTL_VF) 282 #define FM10K_TXQCTL_PC_SHIFT 7 283 #define FM10K_TXQCTL_PC_MASK 0x00000380 284 #define FM10K_TXQCTL_TC_SHIFT 10 285 #define FM10K_TXQCTL_VID_SHIFT 16 286 #define FM10K_TXQCTL_VID_MASK 0x0FFF0000 287 #define FM10K_TXQCTL_UNLIMITED_BW 0x10000000 288 #define FM10K_TXINT(_n) ((0x40 * (_n)) + 0x8008) 289 290 /* Tx Statistics */ 291 #define FM10K_QPTC(_n) ((0x40 * (_n)) + 0x8009) 292 #define FM10K_QBTC_L(_n) ((0x40 * (_n)) + 0x800A) 293 #define FM10K_QBTC_H(_n) ((0x40 * (_n)) + 0x800B) 294 295 /* Tx Push registers */ 296 #define FM10K_TQDLOC(_n) ((0x40 * (_n)) + 0x800C) 297 #define FM10K_TQDLOC_BASE_32_DESC 0x08 298 #define FM10K_TQDLOC_SIZE_32_DESC 0x00050000 299 300 /* Tx GLORT registers */ 301 #define FM10K_TX_SGLORT(_n) ((0x40 * (_n)) + 0x800D) 302 #define FM10K_PFVTCTL(_n) ((0x40 * (_n)) + 0x800E) 303 #define FM10K_PFVTCTL_FTAG_DESC_ENABLE 0x00000001 304 305 /* Interrupt moderation and control registers */ 306 #define FM10K_INT_MAP(_n) ((_n) + 0x10080) 307 #define FM10K_INT_MAP_TIMER0 0x00000000 308 #define FM10K_INT_MAP_TIMER1 0x00000100 309 #define FM10K_INT_MAP_IMMEDIATE 0x00000200 310 #define FM10K_INT_MAP_DISABLE 0x00000300 311 #define FM10K_MSIX_VECTOR_MASK(_n) ((0x4 * (_n)) + 0x11003) 312 #define FM10K_INT_CTRL 0x12000 313 #define FM10K_INT_CTRL_ENABLEMODERATOR 0x00000400 314 #define FM10K_ITR(_n) ((_n) + 0x12400) 315 #define FM10K_ITR_INTERVAL1_SHIFT 12 316 #define FM10K_ITR_PENDING2 0x10000000 317 #define FM10K_ITR_AUTOMASK 0x20000000 318 #define FM10K_ITR_MASK_SET 0x40000000 319 #define FM10K_ITR_MASK_CLEAR 0x80000000 320 #define FM10K_ITR2(_n) ((0x2 * (_n)) + 0x12800) 321 #define FM10K_ITR_REG_COUNT 768 322 #define FM10K_ITR_REG_COUNT_PF 256 323 324 /* Switch manager interrupt registers */ 325 #define FM10K_IP 0x13000 326 #define FM10K_IP_NOTINRESET 0x00000100 327 328 /* VLAN registers */ 329 #define FM10K_VLAN_TABLE(_n, _m) ((0x80 * (_n)) + (_m) + 0x14000) 330 #define FM10K_VLAN_TABLE_SIZE 128 331 332 /* VLAN specific message offsets */ 333 #define FM10K_VLAN_TABLE_VID_MAX 4096 334 #define FM10K_VLAN_TABLE_VSI_MAX 64 335 #define FM10K_VLAN_LENGTH_SHIFT 16 336 #define FM10K_VLAN_CLEAR BIT(15) 337 #define FM10K_VLAN_OVERRIDE FM10K_VLAN_CLEAR 338 #define FM10K_VLAN_ALL \ 339 ((FM10K_VLAN_TABLE_VID_MAX - 1) << FM10K_VLAN_LENGTH_SHIFT) 340 341 /* VF FLR event notification registers */ 342 #define FM10K_PFVFLRE(_n) ((0x1 * (_n)) + 0x18844) 343 #define FM10K_PFVFLREC(_n) ((0x1 * (_n)) + 0x18846) 344 345 /* Defines for size of uncacheable memories */ 346 #define FM10K_UC_ADDR_START 0x000000 /* start of standard regs */ 347 #define FM10K_UC_ADDR_END 0x100000 /* end of standard regs */ 348 #define FM10K_UC_ADDR_SIZE (FM10K_UC_ADDR_END - FM10K_UC_ADDR_START) 349 350 /* Define timeouts for resets and disables */ 351 #define FM10K_QUEUE_DISABLE_TIMEOUT 100 352 #define FM10K_RESET_TIMEOUT 150 353 354 /* Maximum supported combined inner and outer header length for encapsulation */ 355 #define FM10K_TUNNEL_HEADER_LENGTH 184 356 357 /* VF registers */ 358 #define FM10K_VFCTRL 0x00000 359 #define FM10K_VFCTRL_RST 0x00000008 360 #define FM10K_VFINT_MAP 0x00030 361 #define FM10K_VFSYSTIME 0x00040 362 #define FM10K_VFITR(_n) ((_n) + 0x00060) 363 364 enum fm10k_int_source { 365 fm10k_int_mailbox = 0, 366 fm10k_int_pcie_fault = 1, 367 fm10k_int_switch_up_down = 2, 368 fm10k_int_switch_event = 3, 369 fm10k_int_sram = 4, 370 fm10k_int_vflr = 5, 371 fm10k_int_max_hold_time = 6, 372 fm10k_int_sources_max_pf 373 }; 374 375 /* PCIe bus speeds */ 376 enum fm10k_bus_speed { 377 fm10k_bus_speed_unknown = 0, 378 fm10k_bus_speed_2500 = 2500, 379 fm10k_bus_speed_5000 = 5000, 380 fm10k_bus_speed_8000 = 8000, 381 fm10k_bus_speed_reserved 382 }; 383 384 /* PCIe bus widths */ 385 enum fm10k_bus_width { 386 fm10k_bus_width_unknown = 0, 387 fm10k_bus_width_pcie_x1 = 1, 388 fm10k_bus_width_pcie_x2 = 2, 389 fm10k_bus_width_pcie_x4 = 4, 390 fm10k_bus_width_pcie_x8 = 8, 391 fm10k_bus_width_reserved 392 }; 393 394 /* PCIe payload sizes */ 395 enum fm10k_bus_payload { 396 fm10k_bus_payload_unknown = 0, 397 fm10k_bus_payload_128 = 1, 398 fm10k_bus_payload_256 = 2, 399 fm10k_bus_payload_512 = 3, 400 fm10k_bus_payload_reserved 401 }; 402 403 /* Bus parameters */ 404 struct fm10k_bus_info { 405 enum fm10k_bus_speed speed; 406 enum fm10k_bus_width width; 407 enum fm10k_bus_payload payload; 408 }; 409 410 /* Statistics related declarations */ 411 struct fm10k_hw_stat { 412 u64 count; 413 u32 base_l; 414 u32 base_h; 415 }; 416 417 struct fm10k_hw_stats_q { 418 struct fm10k_hw_stat tx_bytes; 419 struct fm10k_hw_stat tx_packets; 420 #define tx_stats_idx tx_packets.base_h 421 struct fm10k_hw_stat rx_bytes; 422 struct fm10k_hw_stat rx_packets; 423 #define rx_stats_idx rx_packets.base_h 424 struct fm10k_hw_stat rx_drops; 425 }; 426 427 struct fm10k_hw_stats { 428 struct fm10k_hw_stat timeout; 429 #define stats_idx timeout.base_h 430 struct fm10k_hw_stat ur; 431 struct fm10k_hw_stat ca; 432 struct fm10k_hw_stat um; 433 struct fm10k_hw_stat xec; 434 struct fm10k_hw_stat vlan_drop; 435 struct fm10k_hw_stat loopback_drop; 436 struct fm10k_hw_stat nodesc_drop; 437 struct fm10k_hw_stats_q q[FM10K_MAX_QUEUES_PF]; 438 }; 439 440 /* Establish DGLORT feature priority */ 441 enum fm10k_dglortdec_idx { 442 fm10k_dglort_default = 0, 443 fm10k_dglort_vf_rsvd0 = 1, 444 fm10k_dglort_vf_rss = 2, 445 fm10k_dglort_pf_rsvd0 = 3, 446 fm10k_dglort_pf_queue = 4, 447 fm10k_dglort_pf_vsi = 5, 448 fm10k_dglort_pf_rsvd1 = 6, 449 fm10k_dglort_pf_rss = 7 450 }; 451 452 struct fm10k_dglort_cfg { 453 u16 glort; /* GLORT base */ 454 u16 queue_b; /* Base value for queue */ 455 u8 vsi_b; /* Base value for VSI */ 456 u8 idx; /* index of DGLORTDEC entry */ 457 u8 rss_l; /* RSS indices */ 458 u8 pc_l; /* Priority Class indices */ 459 u8 vsi_l; /* Number of bits from GLORT used to determine VSI */ 460 u8 queue_l; /* Number of bits from GLORT used to determine queue */ 461 u8 shared_l; /* Ignored bits from GLORT resulting in shared VSI */ 462 u8 inner_rss; /* Boolean value if inner header is used for RSS */ 463 }; 464 465 enum fm10k_pca_fault { 466 PCA_NO_FAULT, 467 PCA_UNMAPPED_ADDR, 468 PCA_BAD_QACCESS_PF, 469 PCA_BAD_QACCESS_VF, 470 PCA_MALICIOUS_REQ, 471 PCA_POISONED_TLP, 472 PCA_TLP_ABORT, 473 __PCA_MAX 474 }; 475 476 enum fm10k_thi_fault { 477 THI_NO_FAULT, 478 THI_MAL_DIS_Q_FAULT, 479 __THI_MAX 480 }; 481 482 enum fm10k_fum_fault { 483 FUM_NO_FAULT, 484 FUM_UNMAPPED_ADDR, 485 FUM_POISONED_TLP, 486 FUM_BAD_VF_QACCESS, 487 FUM_ADD_DECODE_ERR, 488 FUM_RO_ERROR, 489 FUM_QPRC_CRC_ERROR, 490 FUM_CSR_TIMEOUT, 491 FUM_INVALID_TYPE, 492 FUM_INVALID_LENGTH, 493 FUM_INVALID_BE, 494 FUM_INVALID_ALIGN, 495 __FUM_MAX 496 }; 497 498 struct fm10k_fault { 499 u64 address; /* Address at the time fault was detected */ 500 u32 specinfo; /* Extra info on this fault (fault dependent) */ 501 u8 type; /* Fault value dependent on subunit */ 502 u8 func; /* Function number of the fault */ 503 }; 504 505 struct fm10k_mac_ops { 506 /* basic bring-up and tear-down */ 507 s32 (*reset_hw)(struct fm10k_hw *); 508 s32 (*init_hw)(struct fm10k_hw *); 509 s32 (*start_hw)(struct fm10k_hw *); 510 s32 (*stop_hw)(struct fm10k_hw *); 511 s32 (*get_bus_info)(struct fm10k_hw *); 512 s32 (*get_host_state)(struct fm10k_hw *, bool *); 513 s32 (*request_lport_map)(struct fm10k_hw *); 514 s32 (*update_vlan)(struct fm10k_hw *, u32, u8, bool); 515 s32 (*read_mac_addr)(struct fm10k_hw *); 516 s32 (*update_uc_addr)(struct fm10k_hw *, u16, const u8 *, 517 u16, bool, u8); 518 s32 (*update_mc_addr)(struct fm10k_hw *, u16, const u8 *, u16, bool); 519 s32 (*update_xcast_mode)(struct fm10k_hw *, u16, u8); 520 void (*update_int_moderator)(struct fm10k_hw *); 521 s32 (*update_lport_state)(struct fm10k_hw *, u16, u16, bool); 522 void (*update_hw_stats)(struct fm10k_hw *, struct fm10k_hw_stats *); 523 void (*rebind_hw_stats)(struct fm10k_hw *, struct fm10k_hw_stats *); 524 s32 (*configure_dglort_map)(struct fm10k_hw *, 525 struct fm10k_dglort_cfg *); 526 void (*set_dma_mask)(struct fm10k_hw *, u64); 527 s32 (*get_fault)(struct fm10k_hw *, int, struct fm10k_fault *); 528 }; 529 530 enum fm10k_mac_type { 531 fm10k_mac_unknown = 0, 532 fm10k_mac_pf, 533 fm10k_mac_vf, 534 fm10k_num_macs 535 }; 536 537 struct fm10k_mac_info { 538 struct fm10k_mac_ops ops; 539 enum fm10k_mac_type type; 540 u8 addr[ETH_ALEN]; 541 u8 perm_addr[ETH_ALEN]; 542 u16 default_vid; 543 u16 max_msix_vectors; 544 u16 max_queues; 545 bool vlan_override; 546 bool get_host_state; 547 bool tx_ready; 548 u32 dglort_map; 549 u8 itr_scale; 550 u64 reset_while_pending; 551 }; 552 553 struct fm10k_swapi_table_info { 554 u32 used; 555 u32 avail; 556 }; 557 558 struct fm10k_swapi_info { 559 u32 status; 560 struct fm10k_swapi_table_info mac; 561 struct fm10k_swapi_table_info nexthop; 562 struct fm10k_swapi_table_info ffu; 563 }; 564 565 enum fm10k_xcast_modes { 566 FM10K_XCAST_MODE_ALLMULTI = 0, 567 FM10K_XCAST_MODE_MULTI = 1, 568 FM10K_XCAST_MODE_PROMISC = 2, 569 FM10K_XCAST_MODE_NONE = 3, 570 FM10K_XCAST_MODE_DISABLE = 4 571 }; 572 573 #define FM10K_VF_TC_MAX 100000 /* 100,000 Mb/s aka 100Gb/s */ 574 #define FM10K_VF_TC_MIN 1 /* 1 Mb/s is the slowest rate */ 575 576 struct fm10k_vf_info { 577 /* mbx must be first field in struct unless all default IOV message 578 * handlers are redone as the assumption is that vf_info starts 579 * at the same offset as the mailbox 580 */ 581 struct fm10k_mbx_info mbx; /* PF side of VF mailbox */ 582 int rate; /* Tx BW cap as defined by OS */ 583 u16 glort; /* resource tag for this VF */ 584 u16 sw_vid; /* Switch API assigned VLAN */ 585 u16 pf_vid; /* PF assigned Default VLAN */ 586 u8 mac[ETH_ALEN]; /* PF Default MAC address */ 587 u8 vsi; /* VSI identifier */ 588 u8 vf_idx; /* which VF this is */ 589 u8 vf_flags; /* flags indicating what modes 590 * are supported for the port 591 */ 592 }; 593 594 #define FM10K_VF_FLAG_ALLMULTI_CAPABLE (u8)(BIT(FM10K_XCAST_MODE_ALLMULTI)) 595 #define FM10K_VF_FLAG_MULTI_CAPABLE (u8)(BIT(FM10K_XCAST_MODE_MULTI)) 596 #define FM10K_VF_FLAG_PROMISC_CAPABLE (u8)(BIT(FM10K_XCAST_MODE_PROMISC)) 597 #define FM10K_VF_FLAG_NONE_CAPABLE (u8)(BIT(FM10K_XCAST_MODE_NONE)) 598 #define FM10K_VF_FLAG_CAPABLE(vf_info) ((vf_info)->vf_flags & (u8)0xF) 599 #define FM10K_VF_FLAG_ENABLED(vf_info) ((vf_info)->vf_flags >> 4) 600 #define FM10K_VF_FLAG_SET_MODE(mode) ((u8)0x10 << (mode)) 601 #define FM10K_VF_FLAG_SET_MODE_NONE \ 602 FM10K_VF_FLAG_SET_MODE(FM10K_XCAST_MODE_NONE) 603 #define FM10K_VF_FLAG_MULTI_ENABLED \ 604 (FM10K_VF_FLAG_SET_MODE(FM10K_XCAST_MODE_ALLMULTI) | \ 605 FM10K_VF_FLAG_SET_MODE(FM10K_XCAST_MODE_MULTI) | \ 606 FM10K_VF_FLAG_SET_MODE(FM10K_XCAST_MODE_PROMISC)) 607 608 struct fm10k_iov_ops { 609 /* IOV related bring-up and tear-down */ 610 s32 (*assign_resources)(struct fm10k_hw *, u16, u16); 611 s32 (*configure_tc)(struct fm10k_hw *, u16, int); 612 s32 (*assign_int_moderator)(struct fm10k_hw *, u16); 613 s32 (*assign_default_mac_vlan)(struct fm10k_hw *, 614 struct fm10k_vf_info *); 615 s32 (*reset_resources)(struct fm10k_hw *, 616 struct fm10k_vf_info *); 617 s32 (*set_lport)(struct fm10k_hw *, struct fm10k_vf_info *, u16, u8); 618 void (*reset_lport)(struct fm10k_hw *, struct fm10k_vf_info *); 619 void (*update_stats)(struct fm10k_hw *, struct fm10k_hw_stats_q *, u16); 620 }; 621 622 struct fm10k_iov_info { 623 struct fm10k_iov_ops ops; 624 u16 total_vfs; 625 u16 num_vfs; 626 u16 num_pools; 627 }; 628 629 enum fm10k_devices { 630 fm10k_device_pf, 631 fm10k_device_vf, 632 }; 633 634 struct fm10k_info { 635 enum fm10k_mac_type mac; 636 s32 (*get_invariants)(struct fm10k_hw *); 637 const struct fm10k_mac_ops *mac_ops; 638 const struct fm10k_iov_ops *iov_ops; 639 }; 640 641 struct fm10k_hw { 642 u32 __iomem *hw_addr; 643 void *back; 644 struct fm10k_mac_info mac; 645 struct fm10k_bus_info bus; 646 struct fm10k_bus_info bus_caps; 647 struct fm10k_iov_info iov; 648 struct fm10k_mbx_info mbx; 649 struct fm10k_swapi_info swapi; 650 u16 device_id; 651 u16 vendor_id; 652 u16 subsystem_device_id; 653 u16 subsystem_vendor_id; 654 u8 revision_id; 655 }; 656 657 /* Number of Transmit and Receive Descriptors must be a multiple of 8 */ 658 #define FM10K_REQ_TX_DESCRIPTOR_MULTIPLE 8 659 #define FM10K_REQ_RX_DESCRIPTOR_MULTIPLE 8 660 661 /* Transmit Descriptor */ 662 struct fm10k_tx_desc { 663 __le64 buffer_addr; /* Address of the descriptor's data buffer */ 664 __le16 buflen; /* Length of data to be DMAed */ 665 __le16 vlan; /* VLAN_ID and VPRI to be inserted in FTAG */ 666 __le16 mss; /* MSS for segmentation offload */ 667 u8 hdrlen; /* Header size for segmentation offload */ 668 u8 flags; /* Status and offload request flags */ 669 }; 670 671 /* Transmit Descriptor Cache Structure */ 672 struct fm10k_tx_desc_cache { 673 struct fm10k_tx_desc tx_desc[256]; 674 }; 675 676 #define FM10K_TXD_FLAG_INT 0x01 677 #define FM10K_TXD_FLAG_TIME 0x02 678 #define FM10K_TXD_FLAG_CSUM 0x04 679 #define FM10K_TXD_FLAG_FTAG 0x10 680 #define FM10K_TXD_FLAG_RS 0x20 681 #define FM10K_TXD_FLAG_LAST 0x40 682 #define FM10K_TXD_FLAG_DONE 0x80 683 684 /* These macros are meant to enable optimal placement of the RS and INT 685 * bits. It will point us to the last descriptor in the cache for either the 686 * start of the packet, or the end of the packet. If the index is actually 687 * at the start of the FIFO it will point to the offset for the last index 688 * in the FIFO to prevent an unnecessary write. 689 */ 690 #define FM10K_TXD_WB_FIFO_SIZE 4 691 692 /* Receive Descriptor - 32B */ 693 union fm10k_rx_desc { 694 struct { 695 __le64 pkt_addr; /* Packet buffer address */ 696 __le64 hdr_addr; /* Header buffer address */ 697 __le64 reserved; /* Empty space, RSS hash */ 698 __le64 timestamp; 699 } q; /* Read, Writeback, 64b quad-words */ 700 struct { 701 __le32 data; /* RSS and header data */ 702 __le32 rss; /* RSS Hash */ 703 __le32 staterr; 704 __le32 vlan_len; 705 __le32 glort; /* sglort/dglort */ 706 } d; /* Writeback, 32b double-words */ 707 struct { 708 __le16 pkt_info; /* RSS, Pkt type */ 709 __le16 hdr_info; /* Splithdr, hdrlen, xC */ 710 __le16 rss_lower; 711 __le16 rss_upper; 712 __le16 status; /* status/error */ 713 __le16 csum_err; /* checksum or extended error value */ 714 __le16 length; /* Packet length */ 715 __le16 vlan; /* VLAN tag */ 716 __le16 dglort; 717 __le16 sglort; 718 } w; /* Writeback, 16b words */ 719 }; 720 721 #define FM10K_RXD_RSSTYPE_MASK 0x000F 722 enum fm10k_rdesc_rss_type { 723 FM10K_RSSTYPE_NONE = 0x0, 724 FM10K_RSSTYPE_IPV4_TCP = 0x1, 725 FM10K_RSSTYPE_IPV4 = 0x2, 726 FM10K_RSSTYPE_IPV6_TCP = 0x3, 727 /* Reserved 0x4 */ 728 FM10K_RSSTYPE_IPV6 = 0x5, 729 /* Reserved 0x6 */ 730 FM10K_RSSTYPE_IPV4_UDP = 0x7, 731 FM10K_RSSTYPE_IPV6_UDP = 0x8 732 /* Reserved 0x9 - 0xF */ 733 }; 734 735 #define FM10K_RXD_HDR_INFO_XC_MASK 0x0006 736 enum fm10k_rxdesc_xc { 737 FM10K_XC_UNICAST = 0x0, 738 FM10K_XC_MULTICAST = 0x4, 739 FM10K_XC_BROADCAST = 0x6 740 }; 741 742 #define FM10K_RXD_STATUS_DD 0x0001 /* Descriptor done */ 743 #define FM10K_RXD_STATUS_EOP 0x0002 /* End of packet */ 744 #define FM10K_RXD_STATUS_L4CS 0x0010 /* Indicates an L4 csum */ 745 #define FM10K_RXD_STATUS_L4CS2 0x0040 /* Inner header L4 csum */ 746 #define FM10K_RXD_STATUS_L4E2 0x0800 /* Inner header L4 csum err */ 747 #define FM10K_RXD_STATUS_IPE2 0x1000 /* Inner header IPv4 csum err */ 748 #define FM10K_RXD_STATUS_RXE 0x2000 /* Generic Rx error */ 749 #define FM10K_RXD_STATUS_L4E 0x4000 /* L4 csum error */ 750 #define FM10K_RXD_STATUS_IPE 0x8000 /* IPv4 csum error */ 751 752 #define FM10K_RXD_ERR_SWITCH_ERROR 0x0001 /* Switch found bad packet */ 753 #define FM10K_RXD_ERR_NO_DESCRIPTOR 0x0002 /* No descriptor available */ 754 #define FM10K_RXD_ERR_PP_ERROR 0x0004 /* RAM error during processing */ 755 #define FM10K_RXD_ERR_SWITCH_READY 0x0008 /* Link transition mid-packet */ 756 #define FM10K_RXD_ERR_TOO_BIG 0x0010 /* Pkt too big for single buf */ 757 758 struct fm10k_ftag { 759 __be16 swpri_type_user; 760 __be16 vlan; 761 __be16 sglort; 762 __be16 dglort; 763 }; 764 765 #endif /* _FM10K_TYPE_H */ 766
