1 /*
2 * Copyright © 2012 Mike Dunn <mikedunn@newsguy.com>
3 *
4 * mtd nand driver for M-Systems DiskOnChip G4
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * Tested on the Palm Treo 680. The G4 is also present on Toshiba Portege, Asus
12 * P526, some HTC smartphones (Wizard, Prophet, ...), O2 XDA Zinc, maybe others.
13 * Should work on these as well. Let me know!
14 *
15 * TODO:
16 *
17 * Mechanism for management of password-protected areas
18 *
19 * Hamming ecc when reading oob only
20 *
21 * According to the M-Sys documentation, this device is also available in a
22 * "dual-die" configuration having a 256MB capacity, but no mechanism for
23 * detecting this variant is documented. Currently this driver assumes 128MB
24 * capacity.
25 *
26 * Support for multiple cascaded devices ("floors"). Not sure which gadgets
27 * contain multiple G4s in a cascaded configuration, if any.
28 *
29 */
30
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/init.h>
34 #include <linux/string.h>
35 #include <linux/sched.h>
36 #include <linux/delay.h>
37 #include <linux/module.h>
38 #include <linux/export.h>
39 #include <linux/platform_device.h>
40 #include <linux/io.h>
41 #include <linux/bitops.h>
42 #include <linux/mtd/partitions.h>
43 #include <linux/mtd/mtd.h>
44 #include <linux/mtd/rawnand.h>
45 #include <linux/bch.h>
46 #include <linux/bitrev.h>
47 #include <linux/jiffies.h>
48
49 /*
50 * In "reliable mode" consecutive 2k pages are used in parallel (in some
51 * fashion) to store the same data. The data can be read back from the
52 * even-numbered pages in the normal manner; odd-numbered pages will appear to
53 * contain junk. Systems that boot from the docg4 typically write the secondary
54 * program loader (SPL) code in this mode. The SPL is loaded by the initial
55 * program loader (IPL, stored in the docg4's 2k NOR-like region that is mapped
56 * to the reset vector address). This module parameter enables you to use this
57 * driver to write the SPL. When in this mode, no more than 2k of data can be
58 * written at a time, because the addresses do not increment in the normal
59 * manner, and the starting offset must be within an even-numbered 2k region;
60 * i.e., invalid starting offsets are 0x800, 0xa00, 0xc00, 0xe00, 0x1800,
61 * 0x1a00, ... Reliable mode is a special case and should not be used unless
62 * you know what you're doing.
63 */
64 static bool reliable_mode;
65 module_param(reliable_mode, bool, 0);
66 MODULE_PARM_DESC(reliable_mode, "pages are programmed in reliable mode");
67
68 /*
69 * You'll want to ignore badblocks if you're reading a partition that contains
70 * data written by the TrueFFS library (i.e., by PalmOS, Windows, etc), since
71 * it does not use mtd nand's method for marking bad blocks (using oob area).
72 * This will also skip the check of the "page written" flag.
73 */
74 static bool ignore_badblocks;
75 module_param(ignore_badblocks, bool, 0);
76 MODULE_PARM_DESC(ignore_badblocks, "no badblock checking performed");
77
78 struct docg4_priv {
79 struct mtd_info *mtd;
80 struct device *dev;
81 void __iomem *virtadr;
82 int status;
83 struct {
84 unsigned int command;
85 int column;
86 int page;
87 } last_command;
88 uint8_t oob_buf[16];
89 uint8_t ecc_buf[7];
90 int oob_page;
91 struct bch_control *bch;
92 };
93
94 /*
95 * Defines prefixed with DOCG4 are unique to the diskonchip G4. All others are
96 * shared with other diskonchip devices (P3, G3 at least).
97 *
98 * Functions with names prefixed with docg4_ are mtd / nand interface functions
99 * (though they may also be called internally). All others are internal.
100 */
101
102 #define DOC_IOSPACE_DATA 0x0800
103
104 /* register offsets */
105 #define DOC_CHIPID 0x1000
106 #define DOC_DEVICESELECT 0x100a
107 #define DOC_ASICMODE 0x100c
108 #define DOC_DATAEND 0x101e
109 #define DOC_NOP 0x103e
110
111 #define DOC_FLASHSEQUENCE 0x1032
112 #define DOC_FLASHCOMMAND 0x1034
113 #define DOC_FLASHADDRESS 0x1036
114 #define DOC_FLASHCONTROL 0x1038
115 #define DOC_ECCCONF0 0x1040
116 #define DOC_ECCCONF1 0x1042
117 #define DOC_HAMMINGPARITY 0x1046
118 #define DOC_BCH_SYNDROM(idx) (0x1048 + idx)
119
120 #define DOC_ASICMODECONFIRM 0x1072
121 #define DOC_CHIPID_INV 0x1074
122 #define DOC_POWERMODE 0x107c
123
124 #define DOCG4_MYSTERY_REG 0x1050
125
126 /* apparently used only to write oob bytes 6 and 7 */
127 #define DOCG4_OOB_6_7 0x1052
128
129 /* DOC_FLASHSEQUENCE register commands */
130 #define DOC_SEQ_RESET 0x00
131 #define DOCG4_SEQ_PAGE_READ 0x03
132 #define DOCG4_SEQ_FLUSH 0x29
133 #define DOCG4_SEQ_PAGEWRITE 0x16
134 #define DOCG4_SEQ_PAGEPROG 0x1e
135 #define DOCG4_SEQ_BLOCKERASE 0x24
136 #define DOCG4_SEQ_SETMODE 0x45
137
138 /* DOC_FLASHCOMMAND register commands */
139 #define DOCG4_CMD_PAGE_READ 0x00
140 #define DOC_CMD_ERASECYCLE2 0xd0
141 #define DOCG4_CMD_FLUSH 0x70
142 #define DOCG4_CMD_READ2 0x30
143 #define DOC_CMD_PROG_BLOCK_ADDR 0x60
144 #define DOCG4_CMD_PAGEWRITE 0x80
145 #define DOC_CMD_PROG_CYCLE2 0x10
146 #define DOCG4_CMD_FAST_MODE 0xa3 /* functionality guessed */
147 #define DOC_CMD_RELIABLE_MODE 0x22
148 #define DOC_CMD_RESET 0xff
149
150 /* DOC_POWERMODE register bits */
151 #define DOC_POWERDOWN_READY 0x80
152
153 /* DOC_FLASHCONTROL register bits */
154 #define DOC_CTRL_CE 0x10
155 #define DOC_CTRL_UNKNOWN 0x40
156 #define DOC_CTRL_FLASHREADY 0x01
157
158 /* DOC_ECCCONF0 register bits */
159 #define DOC_ECCCONF0_READ_MODE 0x8000
160 #define DOC_ECCCONF0_UNKNOWN 0x2000
161 #define DOC_ECCCONF0_ECC_ENABLE 0x1000
162 #define DOC_ECCCONF0_DATA_BYTES_MASK 0x07ff
163
164 /* DOC_ECCCONF1 register bits */
165 #define DOC_ECCCONF1_BCH_SYNDROM_ERR 0x80
166 #define DOC_ECCCONF1_ECC_ENABLE 0x07
167 #define DOC_ECCCONF1_PAGE_IS_WRITTEN 0x20
168
169 /* DOC_ASICMODE register bits */
170 #define DOC_ASICMODE_RESET 0x00
171 #define DOC_ASICMODE_NORMAL 0x01
172 #define DOC_ASICMODE_POWERDOWN 0x02
173 #define DOC_ASICMODE_MDWREN 0x04
174 #define DOC_ASICMODE_BDETCT_RESET 0x08
175 #define DOC_ASICMODE_RSTIN_RESET 0x10
176 #define DOC_ASICMODE_RAM_WE 0x20
177
178 /* good status values read after read/write/erase operations */
179 #define DOCG4_PROGSTATUS_GOOD 0x51
180 #define DOCG4_PROGSTATUS_GOOD_2 0xe0
181
182 /*
183 * On read operations (page and oob-only), the first byte read from I/O reg is a
184 * status. On error, it reads 0x73; otherwise, it reads either 0x71 (first read
185 * after reset only) or 0x51, so bit 1 is presumed to be an error indicator.
186 */
187 #define DOCG4_READ_ERROR 0x02 /* bit 1 indicates read error */
188
189 /* anatomy of the device */
190 #define DOCG4_CHIP_SIZE 0x8000000
191 #define DOCG4_PAGE_SIZE 0x200
192 #define DOCG4_PAGES_PER_BLOCK 0x200
193 #define DOCG4_BLOCK_SIZE (DOCG4_PAGES_PER_BLOCK * DOCG4_PAGE_SIZE)
194 #define DOCG4_NUMBLOCKS (DOCG4_CHIP_SIZE / DOCG4_BLOCK_SIZE)
195 #define DOCG4_OOB_SIZE 0x10
196 #define DOCG4_CHIP_SHIFT 27 /* log_2(DOCG4_CHIP_SIZE) */
197 #define DOCG4_PAGE_SHIFT 9 /* log_2(DOCG4_PAGE_SIZE) */
198 #define DOCG4_ERASE_SHIFT 18 /* log_2(DOCG4_BLOCK_SIZE) */
199
200 /* all but the last byte is included in ecc calculation */
201 #define DOCG4_BCH_SIZE (DOCG4_PAGE_SIZE + DOCG4_OOB_SIZE - 1)
202
203 #define DOCG4_USERDATA_LEN 520 /* 512 byte page plus 8 oob avail to user */
204
205 /* expected values from the ID registers */
206 #define DOCG4_IDREG1_VALUE 0x0400
207 #define DOCG4_IDREG2_VALUE 0xfbff
208
209 /* primitive polynomial used to build the Galois field used by hw ecc gen */
210 #define DOCG4_PRIMITIVE_POLY 0x4443
211
212 #define DOCG4_M 14 /* Galois field is of order 2^14 */
213 #define DOCG4_T 4 /* BCH alg corrects up to 4 bit errors */
214
215 #define DOCG4_FACTORY_BBT_PAGE 16 /* page where read-only factory bbt lives */
216 #define DOCG4_REDUNDANT_BBT_PAGE 24 /* page where redundant factory bbt lives */
217
218 /*
219 * Bytes 0, 1 are used as badblock marker.
220 * Bytes 2 - 6 are available to the user.
221 * Byte 7 is hamming ecc for first 7 oob bytes only.
222 * Bytes 8 - 14 are hw-generated ecc covering entire page + oob bytes 0 - 14.
223 * Byte 15 (the last) is used by the driver as a "page written" flag.
224 */
docg4_ooblayout_ecc(struct mtd_info * mtd,int section,struct mtd_oob_region * oobregion)225 static int docg4_ooblayout_ecc(struct mtd_info *mtd, int section,
226 struct mtd_oob_region *oobregion)
227 {
228 if (section)
229 return -ERANGE;
230
231 oobregion->offset = 7;
232 oobregion->length = 9;
233
234 return 0;
235 }
236
docg4_ooblayout_free(struct mtd_info * mtd,int section,struct mtd_oob_region * oobregion)237 static int docg4_ooblayout_free(struct mtd_info *mtd, int section,
238 struct mtd_oob_region *oobregion)
239 {
240 if (section)
241 return -ERANGE;
242
243 oobregion->offset = 2;
244 oobregion->length = 5;
245
246 return 0;
247 }
248
249 static const struct mtd_ooblayout_ops docg4_ooblayout_ops = {
250 .ecc = docg4_ooblayout_ecc,
251 .free = docg4_ooblayout_free,
252 };
253
254 /*
255 * The device has a nop register which M-Sys claims is for the purpose of
256 * inserting precise delays. But beware; at least some operations fail if the
257 * nop writes are replaced with a generic delay!
258 */
write_nop(void __iomem * docptr)259 static inline void write_nop(void __iomem *docptr)
260 {
261 writew(0, docptr + DOC_NOP);
262 }
263
docg4_read_buf(struct mtd_info * mtd,uint8_t * buf,int len)264 static void docg4_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
265 {
266 int i;
267 struct nand_chip *nand = mtd_to_nand(mtd);
268 uint16_t *p = (uint16_t *) buf;
269 len >>= 1;
270
271 for (i = 0; i < len; i++)
272 p[i] = readw(nand->IO_ADDR_R);
273 }
274
docg4_write_buf16(struct mtd_info * mtd,const uint8_t * buf,int len)275 static void docg4_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
276 {
277 int i;
278 struct nand_chip *nand = mtd_to_nand(mtd);
279 uint16_t *p = (uint16_t *) buf;
280 len >>= 1;
281
282 for (i = 0; i < len; i++)
283 writew(p[i], nand->IO_ADDR_W);
284 }
285
poll_status(struct docg4_priv * doc)286 static int poll_status(struct docg4_priv *doc)
287 {
288 /*
289 * Busy-wait for the FLASHREADY bit to be set in the FLASHCONTROL
290 * register. Operations known to take a long time (e.g., block erase)
291 * should sleep for a while before calling this.
292 */
293
294 uint16_t flash_status;
295 unsigned long timeo;
296 void __iomem *docptr = doc->virtadr;
297
298 dev_dbg(doc->dev, "%s...\n", __func__);
299
300 /* hardware quirk requires reading twice initially */
301 flash_status = readw(docptr + DOC_FLASHCONTROL);
302
303 timeo = jiffies + msecs_to_jiffies(200); /* generous timeout */
304 do {
305 cpu_relax();
306 flash_status = readb(docptr + DOC_FLASHCONTROL);
307 } while (!(flash_status & DOC_CTRL_FLASHREADY) &&
308 time_before(jiffies, timeo));
309
310 if (unlikely(!(flash_status & DOC_CTRL_FLASHREADY))) {
311 dev_err(doc->dev, "%s: timed out!\n", __func__);
312 return NAND_STATUS_FAIL;
313 }
314
315 return 0;
316 }
317
318
docg4_wait(struct mtd_info * mtd,struct nand_chip * nand)319 static int docg4_wait(struct mtd_info *mtd, struct nand_chip *nand)
320 {
321
322 struct docg4_priv *doc = nand_get_controller_data(nand);
323 int status = NAND_STATUS_WP; /* inverse logic?? */
324 dev_dbg(doc->dev, "%s...\n", __func__);
325
326 /* report any previously unreported error */
327 if (doc->status) {
328 status |= doc->status;
329 doc->status = 0;
330 return status;
331 }
332
333 status |= poll_status(doc);
334 return status;
335 }
336
docg4_select_chip(struct mtd_info * mtd,int chip)337 static void docg4_select_chip(struct mtd_info *mtd, int chip)
338 {
339 /*
340 * Select among multiple cascaded chips ("floors"). Multiple floors are
341 * not yet supported, so the only valid non-negative value is 0.
342 */
343 struct nand_chip *nand = mtd_to_nand(mtd);
344 struct docg4_priv *doc = nand_get_controller_data(nand);
345 void __iomem *docptr = doc->virtadr;
346
347 dev_dbg(doc->dev, "%s: chip %d\n", __func__, chip);
348
349 if (chip < 0)
350 return; /* deselected */
351
352 if (chip > 0)
353 dev_warn(doc->dev, "multiple floors currently unsupported\n");
354
355 writew(0, docptr + DOC_DEVICESELECT);
356 }
357
reset(struct mtd_info * mtd)358 static void reset(struct mtd_info *mtd)
359 {
360 /* full device reset */
361
362 struct nand_chip *nand = mtd_to_nand(mtd);
363 struct docg4_priv *doc = nand_get_controller_data(nand);
364 void __iomem *docptr = doc->virtadr;
365
366 writew(DOC_ASICMODE_RESET | DOC_ASICMODE_MDWREN,
367 docptr + DOC_ASICMODE);
368 writew(~(DOC_ASICMODE_RESET | DOC_ASICMODE_MDWREN),
369 docptr + DOC_ASICMODECONFIRM);
370 write_nop(docptr);
371
372 writew(DOC_ASICMODE_NORMAL | DOC_ASICMODE_MDWREN,
373 docptr + DOC_ASICMODE);
374 writew(~(DOC_ASICMODE_NORMAL | DOC_ASICMODE_MDWREN),
375 docptr + DOC_ASICMODECONFIRM);
376
377 writew(DOC_ECCCONF1_ECC_ENABLE, docptr + DOC_ECCCONF1);
378
379 poll_status(doc);
380 }
381
read_hw_ecc(void __iomem * docptr,uint8_t * ecc_buf)382 static void read_hw_ecc(void __iomem *docptr, uint8_t *ecc_buf)
383 {
384 /* read the 7 hw-generated ecc bytes */
385
386 int i;
387 for (i = 0; i < 7; i++) { /* hw quirk; read twice */
388 ecc_buf[i] = readb(docptr + DOC_BCH_SYNDROM(i));
389 ecc_buf[i] = readb(docptr + DOC_BCH_SYNDROM(i));
390 }
391 }
392
correct_data(struct mtd_info * mtd,uint8_t * buf,int page)393 static int correct_data(struct mtd_info *mtd, uint8_t *buf, int page)
394 {
395 /*
396 * Called after a page read when hardware reports bitflips.
397 * Up to four bitflips can be corrected.
398 */
399
400 struct nand_chip *nand = mtd_to_nand(mtd);
401 struct docg4_priv *doc = nand_get_controller_data(nand);
402 void __iomem *docptr = doc->virtadr;
403 int i, numerrs, errpos[4];
404 const uint8_t blank_read_hwecc[8] = {
405 0xcf, 0x72, 0xfc, 0x1b, 0xa9, 0xc7, 0xb9, 0 };
406
407 read_hw_ecc(docptr, doc->ecc_buf); /* read 7 hw-generated ecc bytes */
408
409 /* check if read error is due to a blank page */
410 if (!memcmp(doc->ecc_buf, blank_read_hwecc, 7))
411 return 0; /* yes */
412
413 /* skip additional check of "written flag" if ignore_badblocks */
414 if (ignore_badblocks == false) {
415
416 /*
417 * If the hw ecc bytes are not those of a blank page, there's
418 * still a chance that the page is blank, but was read with
419 * errors. Check the "written flag" in last oob byte, which
420 * is set to zero when a page is written. If more than half
421 * the bits are set, assume a blank page. Unfortunately, the
422 * bit flips(s) are not reported in stats.
423 */
424
425 if (nand->oob_poi[15]) {
426 int bit, numsetbits = 0;
427 unsigned long written_flag = nand->oob_poi[15];
428 for_each_set_bit(bit, &written_flag, 8)
429 numsetbits++;
430 if (numsetbits > 4) { /* assume blank */
431 dev_warn(doc->dev,
432 "error(s) in blank page "
433 "at offset %08x\n",
434 page * DOCG4_PAGE_SIZE);
435 return 0;
436 }
437 }
438 }
439
440 /*
441 * The hardware ecc unit produces oob_ecc ^ calc_ecc. The kernel's bch
442 * algorithm is used to decode this. However the hw operates on page
443 * data in a bit order that is the reverse of that of the bch alg,
444 * requiring that the bits be reversed on the result. Thanks to Ivan
445 * Djelic for his analysis!
446 */
447 for (i = 0; i < 7; i++)
448 doc->ecc_buf[i] = bitrev8(doc->ecc_buf[i]);
449
450 numerrs = decode_bch(doc->bch, NULL, DOCG4_USERDATA_LEN, NULL,
451 doc->ecc_buf, NULL, errpos);
452
453 if (numerrs == -EBADMSG) {
454 dev_warn(doc->dev, "uncorrectable errors at offset %08x\n",
455 page * DOCG4_PAGE_SIZE);
456 return -EBADMSG;
457 }
458
459 BUG_ON(numerrs < 0); /* -EINVAL, or anything other than -EBADMSG */
460
461 /* undo last step in BCH alg (modulo mirroring not needed) */
462 for (i = 0; i < numerrs; i++)
463 errpos[i] = (errpos[i] & ~7)|(7-(errpos[i] & 7));
464
465 /* fix the errors */
466 for (i = 0; i < numerrs; i++) {
467
468 /* ignore if error within oob ecc bytes */
469 if (errpos[i] > DOCG4_USERDATA_LEN * 8)
470 continue;
471
472 /* if error within oob area preceeding ecc bytes... */
473 if (errpos[i] > DOCG4_PAGE_SIZE * 8)
474 change_bit(errpos[i] - DOCG4_PAGE_SIZE * 8,
475 (unsigned long *)nand->oob_poi);
476
477 else /* error in page data */
478 change_bit(errpos[i], (unsigned long *)buf);
479 }
480
481 dev_notice(doc->dev, "%d error(s) corrected at offset %08x\n",
482 numerrs, page * DOCG4_PAGE_SIZE);
483
484 return numerrs;
485 }
486
docg4_read_byte(struct mtd_info * mtd)487 static uint8_t docg4_read_byte(struct mtd_info *mtd)
488 {
489 struct nand_chip *nand = mtd_to_nand(mtd);
490 struct docg4_priv *doc = nand_get_controller_data(nand);
491
492 dev_dbg(doc->dev, "%s\n", __func__);
493
494 if (doc->last_command.command == NAND_CMD_STATUS) {
495 int status;
496
497 /*
498 * Previous nand command was status request, so nand
499 * infrastructure code expects to read the status here. If an
500 * error occurred in a previous operation, report it.
501 */
502 doc->last_command.command = 0;
503
504 if (doc->status) {
505 status = doc->status;
506 doc->status = 0;
507 }
508
509 /* why is NAND_STATUS_WP inverse logic?? */
510 else
511 status = NAND_STATUS_WP | NAND_STATUS_READY;
512
513 return status;
514 }
515
516 dev_warn(doc->dev, "unexpected call to read_byte()\n");
517
518 return 0;
519 }
520
write_addr(struct docg4_priv * doc,uint32_t docg4_addr)521 static void write_addr(struct docg4_priv *doc, uint32_t docg4_addr)
522 {
523 /* write the four address bytes packed in docg4_addr to the device */
524
525 void __iomem *docptr = doc->virtadr;
526 writeb(docg4_addr & 0xff, docptr + DOC_FLASHADDRESS);
527 docg4_addr >>= 8;
528 writeb(docg4_addr & 0xff, docptr + DOC_FLASHADDRESS);
529 docg4_addr >>= 8;
530 writeb(docg4_addr & 0xff, docptr + DOC_FLASHADDRESS);
531 docg4_addr >>= 8;
532 writeb(docg4_addr & 0xff, docptr + DOC_FLASHADDRESS);
533 }
534
read_progstatus(struct docg4_priv * doc)535 static int read_progstatus(struct docg4_priv *doc)
536 {
537 /*
538 * This apparently checks the status of programming. Done after an
539 * erasure, and after page data is written. On error, the status is
540 * saved, to be later retrieved by the nand infrastructure code.
541 */
542 void __iomem *docptr = doc->virtadr;
543
544 /* status is read from the I/O reg */
545 uint16_t status1 = readw(docptr + DOC_IOSPACE_DATA);
546 uint16_t status2 = readw(docptr + DOC_IOSPACE_DATA);
547 uint16_t status3 = readw(docptr + DOCG4_MYSTERY_REG);
548
549 dev_dbg(doc->dev, "docg4: %s: %02x %02x %02x\n",
550 __func__, status1, status2, status3);
551
552 if (status1 != DOCG4_PROGSTATUS_GOOD
553 || status2 != DOCG4_PROGSTATUS_GOOD_2
554 || status3 != DOCG4_PROGSTATUS_GOOD_2) {
555 doc->status = NAND_STATUS_FAIL;
556 dev_warn(doc->dev, "read_progstatus failed: "
557 "%02x, %02x, %02x\n", status1, status2, status3);
558 return -EIO;
559 }
560 return 0;
561 }
562
pageprog(struct mtd_info * mtd)563 static int pageprog(struct mtd_info *mtd)
564 {
565 /*
566 * Final step in writing a page. Writes the contents of its
567 * internal buffer out to the flash array, or some such.
568 */
569
570 struct nand_chip *nand = mtd_to_nand(mtd);
571 struct docg4_priv *doc = nand_get_controller_data(nand);
572 void __iomem *docptr = doc->virtadr;
573 int retval = 0;
574
575 dev_dbg(doc->dev, "docg4: %s\n", __func__);
576
577 writew(DOCG4_SEQ_PAGEPROG, docptr + DOC_FLASHSEQUENCE);
578 writew(DOC_CMD_PROG_CYCLE2, docptr + DOC_FLASHCOMMAND);
579 write_nop(docptr);
580 write_nop(docptr);
581
582 /* Just busy-wait; usleep_range() slows things down noticeably. */
583 poll_status(doc);
584
585 writew(DOCG4_SEQ_FLUSH, docptr + DOC_FLASHSEQUENCE);
586 writew(DOCG4_CMD_FLUSH, docptr + DOC_FLASHCOMMAND);
587 writew(DOC_ECCCONF0_READ_MODE | 4, docptr + DOC_ECCCONF0);
588 write_nop(docptr);
589 write_nop(docptr);
590 write_nop(docptr);
591 write_nop(docptr);
592 write_nop(docptr);
593
594 retval = read_progstatus(doc);
595 writew(0, docptr + DOC_DATAEND);
596 write_nop(docptr);
597 poll_status(doc);
598 write_nop(docptr);
599
600 return retval;
601 }
602
sequence_reset(struct mtd_info * mtd)603 static void sequence_reset(struct mtd_info *mtd)
604 {
605 /* common starting sequence for all operations */
606
607 struct nand_chip *nand = mtd_to_nand(mtd);
608 struct docg4_priv *doc = nand_get_controller_data(nand);
609 void __iomem *docptr = doc->virtadr;
610
611 writew(DOC_CTRL_UNKNOWN | DOC_CTRL_CE, docptr + DOC_FLASHCONTROL);
612 writew(DOC_SEQ_RESET, docptr + DOC_FLASHSEQUENCE);
613 writew(DOC_CMD_RESET, docptr + DOC_FLASHCOMMAND);
614 write_nop(docptr);
615 write_nop(docptr);
616 poll_status(doc);
617 write_nop(docptr);
618 }
619
read_page_prologue(struct mtd_info * mtd,uint32_t docg4_addr)620 static void read_page_prologue(struct mtd_info *mtd, uint32_t docg4_addr)
621 {
622 /* first step in reading a page */
623
624 struct nand_chip *nand = mtd_to_nand(mtd);
625 struct docg4_priv *doc = nand_get_controller_data(nand);
626 void __iomem *docptr = doc->virtadr;
627
628 dev_dbg(doc->dev,
629 "docg4: %s: g4 page %08x\n", __func__, docg4_addr);
630
631 sequence_reset(mtd);
632
633 writew(DOCG4_SEQ_PAGE_READ, docptr + DOC_FLASHSEQUENCE);
634 writew(DOCG4_CMD_PAGE_READ, docptr + DOC_FLASHCOMMAND);
635 write_nop(docptr);
636
637 write_addr(doc, docg4_addr);
638
639 write_nop(docptr);
640 writew(DOCG4_CMD_READ2, docptr + DOC_FLASHCOMMAND);
641 write_nop(docptr);
642 write_nop(docptr);
643
644 poll_status(doc);
645 }
646
write_page_prologue(struct mtd_info * mtd,uint32_t docg4_addr)647 static void write_page_prologue(struct mtd_info *mtd, uint32_t docg4_addr)
648 {
649 /* first step in writing a page */
650
651 struct nand_chip *nand = mtd_to_nand(mtd);
652 struct docg4_priv *doc = nand_get_controller_data(nand);
653 void __iomem *docptr = doc->virtadr;
654
655 dev_dbg(doc->dev,
656 "docg4: %s: g4 addr: %x\n", __func__, docg4_addr);
657 sequence_reset(mtd);
658
659 if (unlikely(reliable_mode)) {
660 writew(DOCG4_SEQ_SETMODE, docptr + DOC_FLASHSEQUENCE);
661 writew(DOCG4_CMD_FAST_MODE, docptr + DOC_FLASHCOMMAND);
662 writew(DOC_CMD_RELIABLE_MODE, docptr + DOC_FLASHCOMMAND);
663 write_nop(docptr);
664 }
665
666 writew(DOCG4_SEQ_PAGEWRITE, docptr + DOC_FLASHSEQUENCE);
667 writew(DOCG4_CMD_PAGEWRITE, docptr + DOC_FLASHCOMMAND);
668 write_nop(docptr);
669 write_addr(doc, docg4_addr);
670 write_nop(docptr);
671 write_nop(docptr);
672 poll_status(doc);
673 }
674
mtd_to_docg4_address(int page,int column)675 static uint32_t mtd_to_docg4_address(int page, int column)
676 {
677 /*
678 * Convert mtd address to format used by the device, 32 bit packed.
679 *
680 * Some notes on G4 addressing... The M-Sys documentation on this device
681 * claims that pages are 2K in length, and indeed, the format of the
682 * address used by the device reflects that. But within each page are
683 * four 512 byte "sub-pages", each with its own oob data that is
684 * read/written immediately after the 512 bytes of page data. This oob
685 * data contains the ecc bytes for the preceeding 512 bytes.
686 *
687 * Rather than tell the mtd nand infrastructure that page size is 2k,
688 * with four sub-pages each, we engage in a little subterfuge and tell
689 * the infrastructure code that pages are 512 bytes in size. This is
690 * done because during the course of reverse-engineering the device, I
691 * never observed an instance where an entire 2K "page" was read or
692 * written as a unit. Each "sub-page" is always addressed individually,
693 * its data read/written, and ecc handled before the next "sub-page" is
694 * addressed.
695 *
696 * This requires us to convert addresses passed by the mtd nand
697 * infrastructure code to those used by the device.
698 *
699 * The address that is written to the device consists of four bytes: the
700 * first two are the 2k page number, and the second is the index into
701 * the page. The index is in terms of 16-bit half-words and includes
702 * the preceeding oob data, so e.g., the index into the second
703 * "sub-page" is 0x108, and the full device address of the start of mtd
704 * page 0x201 is 0x00800108.
705 */
706 int g4_page = page / 4; /* device's 2K page */
707 int g4_index = (page % 4) * 0x108 + column/2; /* offset into page */
708 return (g4_page << 16) | g4_index; /* pack */
709 }
710
docg4_command(struct mtd_info * mtd,unsigned command,int column,int page_addr)711 static void docg4_command(struct mtd_info *mtd, unsigned command, int column,
712 int page_addr)
713 {
714 /* handle standard nand commands */
715
716 struct nand_chip *nand = mtd_to_nand(mtd);
717 struct docg4_priv *doc = nand_get_controller_data(nand);
718 uint32_t g4_addr = mtd_to_docg4_address(page_addr, column);
719
720 dev_dbg(doc->dev, "%s %x, page_addr=%x, column=%x\n",
721 __func__, command, page_addr, column);
722
723 /*
724 * Save the command and its arguments. This enables emulation of
725 * standard flash devices, and also some optimizations.
726 */
727 doc->last_command.command = command;
728 doc->last_command.column = column;
729 doc->last_command.page = page_addr;
730
731 switch (command) {
732
733 case NAND_CMD_RESET:
734 reset(mtd);
735 break;
736
737 case NAND_CMD_READ0:
738 read_page_prologue(mtd, g4_addr);
739 break;
740
741 case NAND_CMD_STATUS:
742 /* next call to read_byte() will expect a status */
743 break;
744
745 case NAND_CMD_SEQIN:
746 if (unlikely(reliable_mode)) {
747 uint16_t g4_page = g4_addr >> 16;
748
749 /* writes to odd-numbered 2k pages are invalid */
750 if (g4_page & 0x01)
751 dev_warn(doc->dev,
752 "invalid reliable mode address\n");
753 }
754
755 write_page_prologue(mtd, g4_addr);
756
757 /* hack for deferred write of oob bytes */
758 if (doc->oob_page == page_addr)
759 memcpy(nand->oob_poi, doc->oob_buf, 16);
760 break;
761
762 case NAND_CMD_PAGEPROG:
763 pageprog(mtd);
764 break;
765
766 /* we don't expect these, based on review of nand_base.c */
767 case NAND_CMD_READOOB:
768 case NAND_CMD_READID:
769 case NAND_CMD_ERASE1:
770 case NAND_CMD_ERASE2:
771 dev_warn(doc->dev, "docg4_command: "
772 "unexpected nand command 0x%x\n", command);
773 break;
774
775 }
776 }
777
read_page(struct mtd_info * mtd,struct nand_chip * nand,uint8_t * buf,int page,bool use_ecc)778 static int read_page(struct mtd_info *mtd, struct nand_chip *nand,
779 uint8_t *buf, int page, bool use_ecc)
780 {
781 struct docg4_priv *doc = nand_get_controller_data(nand);
782 void __iomem *docptr = doc->virtadr;
783 uint16_t status, edc_err, *buf16;
784 int bits_corrected = 0;
785
786 dev_dbg(doc->dev, "%s: page %08x\n", __func__, page);
787
788 nand_read_page_op(nand, page, 0, NULL, 0);
789
790 writew(DOC_ECCCONF0_READ_MODE |
791 DOC_ECCCONF0_ECC_ENABLE |
792 DOC_ECCCONF0_UNKNOWN |
793 DOCG4_BCH_SIZE,
794 docptr + DOC_ECCCONF0);
795 write_nop(docptr);
796 write_nop(docptr);
797 write_nop(docptr);
798 write_nop(docptr);
799 write_nop(docptr);
800
801 /* the 1st byte from the I/O reg is a status; the rest is page data */
802 status = readw(docptr + DOC_IOSPACE_DATA);
803 if (status & DOCG4_READ_ERROR) {
804 dev_err(doc->dev,
805 "docg4_read_page: bad status: 0x%02x\n", status);
806 writew(0, docptr + DOC_DATAEND);
807 return -EIO;
808 }
809
810 dev_dbg(doc->dev, "%s: status = 0x%x\n", __func__, status);
811
812 docg4_read_buf(mtd, buf, DOCG4_PAGE_SIZE); /* read the page data */
813
814 /* this device always reads oob after page data */
815 /* first 14 oob bytes read from I/O reg */
816 docg4_read_buf(mtd, nand->oob_poi, 14);
817
818 /* last 2 read from another reg */
819 buf16 = (uint16_t *)(nand->oob_poi + 14);
820 *buf16 = readw(docptr + DOCG4_MYSTERY_REG);
821
822 write_nop(docptr);
823
824 if (likely(use_ecc == true)) {
825
826 /* read the register that tells us if bitflip(s) detected */
827 edc_err = readw(docptr + DOC_ECCCONF1);
828 edc_err = readw(docptr + DOC_ECCCONF1);
829 dev_dbg(doc->dev, "%s: edc_err = 0x%02x\n", __func__, edc_err);
830
831 /* If bitflips are reported, attempt to correct with ecc */
832 if (edc_err & DOC_ECCCONF1_BCH_SYNDROM_ERR) {
833 bits_corrected = correct_data(mtd, buf, page);
834 if (bits_corrected == -EBADMSG)
835 mtd->ecc_stats.failed++;
836 else
837 mtd->ecc_stats.corrected += bits_corrected;
838 }
839 }
840
841 writew(0, docptr + DOC_DATAEND);
842 if (bits_corrected == -EBADMSG) /* uncorrectable errors */
843 return 0;
844 return bits_corrected;
845 }
846
847
docg4_read_page_raw(struct mtd_info * mtd,struct nand_chip * nand,uint8_t * buf,int oob_required,int page)848 static int docg4_read_page_raw(struct mtd_info *mtd, struct nand_chip *nand,
849 uint8_t *buf, int oob_required, int page)
850 {
851 return read_page(mtd, nand, buf, page, false);
852 }
853
docg4_read_page(struct mtd_info * mtd,struct nand_chip * nand,uint8_t * buf,int oob_required,int page)854 static int docg4_read_page(struct mtd_info *mtd, struct nand_chip *nand,
855 uint8_t *buf, int oob_required, int page)
856 {
857 return read_page(mtd, nand, buf, page, true);
858 }
859
docg4_read_oob(struct mtd_info * mtd,struct nand_chip * nand,int page)860 static int docg4_read_oob(struct mtd_info *mtd, struct nand_chip *nand,
861 int page)
862 {
863 struct docg4_priv *doc = nand_get_controller_data(nand);
864 void __iomem *docptr = doc->virtadr;
865 uint16_t status;
866
867 dev_dbg(doc->dev, "%s: page %x\n", __func__, page);
868
869 nand_read_page_op(nand, page, nand->ecc.size, NULL, 0);
870
871 writew(DOC_ECCCONF0_READ_MODE | DOCG4_OOB_SIZE, docptr + DOC_ECCCONF0);
872 write_nop(docptr);
873 write_nop(docptr);
874 write_nop(docptr);
875 write_nop(docptr);
876 write_nop(docptr);
877
878 /* the 1st byte from the I/O reg is a status; the rest is oob data */
879 status = readw(docptr + DOC_IOSPACE_DATA);
880 if (status & DOCG4_READ_ERROR) {
881 dev_warn(doc->dev,
882 "docg4_read_oob failed: status = 0x%02x\n", status);
883 return -EIO;
884 }
885
886 dev_dbg(doc->dev, "%s: status = 0x%x\n", __func__, status);
887
888 docg4_read_buf(mtd, nand->oob_poi, 16);
889
890 write_nop(docptr);
891 write_nop(docptr);
892 write_nop(docptr);
893 writew(0, docptr + DOC_DATAEND);
894 write_nop(docptr);
895
896 return 0;
897 }
898
docg4_erase_block(struct mtd_info * mtd,int page)899 static int docg4_erase_block(struct mtd_info *mtd, int page)
900 {
901 struct nand_chip *nand = mtd_to_nand(mtd);
902 struct docg4_priv *doc = nand_get_controller_data(nand);
903 void __iomem *docptr = doc->virtadr;
904 uint16_t g4_page;
905 int status;
906
907 dev_dbg(doc->dev, "%s: page %04x\n", __func__, page);
908
909 sequence_reset(mtd);
910
911 writew(DOCG4_SEQ_BLOCKERASE, docptr + DOC_FLASHSEQUENCE);
912 writew(DOC_CMD_PROG_BLOCK_ADDR, docptr + DOC_FLASHCOMMAND);
913 write_nop(docptr);
914
915 /* only 2 bytes of address are written to specify erase block */
916 g4_page = (uint16_t)(page / 4); /* to g4's 2k page addressing */
917 writeb(g4_page & 0xff, docptr + DOC_FLASHADDRESS);
918 g4_page >>= 8;
919 writeb(g4_page & 0xff, docptr + DOC_FLASHADDRESS);
920 write_nop(docptr);
921
922 /* start the erasure */
923 writew(DOC_CMD_ERASECYCLE2, docptr + DOC_FLASHCOMMAND);
924 write_nop(docptr);
925 write_nop(docptr);
926
927 usleep_range(500, 1000); /* erasure is long; take a snooze */
928 poll_status(doc);
929 writew(DOCG4_SEQ_FLUSH, docptr + DOC_FLASHSEQUENCE);
930 writew(DOCG4_CMD_FLUSH, docptr + DOC_FLASHCOMMAND);
931 writew(DOC_ECCCONF0_READ_MODE | 4, docptr + DOC_ECCCONF0);
932 write_nop(docptr);
933 write_nop(docptr);
934 write_nop(docptr);
935 write_nop(docptr);
936 write_nop(docptr);
937
938 read_progstatus(doc);
939
940 writew(0, docptr + DOC_DATAEND);
941 write_nop(docptr);
942 poll_status(doc);
943 write_nop(docptr);
944
945 status = nand->waitfunc(mtd, nand);
946 if (status < 0)
947 return status;
948
949 return status & NAND_STATUS_FAIL ? -EIO : 0;
950 }
951
write_page(struct mtd_info * mtd,struct nand_chip * nand,const uint8_t * buf,int page,bool use_ecc)952 static int write_page(struct mtd_info *mtd, struct nand_chip *nand,
953 const uint8_t *buf, int page, bool use_ecc)
954 {
955 struct docg4_priv *doc = nand_get_controller_data(nand);
956 void __iomem *docptr = doc->virtadr;
957 uint8_t ecc_buf[8];
958
959 dev_dbg(doc->dev, "%s...\n", __func__);
960
961 nand_prog_page_begin_op(nand, page, 0, NULL, 0);
962
963 writew(DOC_ECCCONF0_ECC_ENABLE |
964 DOC_ECCCONF0_UNKNOWN |
965 DOCG4_BCH_SIZE,
966 docptr + DOC_ECCCONF0);
967 write_nop(docptr);
968
969 /* write the page data */
970 docg4_write_buf16(mtd, buf, DOCG4_PAGE_SIZE);
971
972 /* oob bytes 0 through 5 are written to I/O reg */
973 docg4_write_buf16(mtd, nand->oob_poi, 6);
974
975 /* oob byte 6 written to a separate reg */
976 writew(nand->oob_poi[6], docptr + DOCG4_OOB_6_7);
977
978 write_nop(docptr);
979 write_nop(docptr);
980
981 /* write hw-generated ecc bytes to oob */
982 if (likely(use_ecc == true)) {
983 /* oob byte 7 is hamming code */
984 uint8_t hamming = readb(docptr + DOC_HAMMINGPARITY);
985 hamming = readb(docptr + DOC_HAMMINGPARITY); /* 2nd read */
986 writew(hamming, docptr + DOCG4_OOB_6_7);
987 write_nop(docptr);
988
989 /* read the 7 bch bytes from ecc regs */
990 read_hw_ecc(docptr, ecc_buf);
991 ecc_buf[7] = 0; /* clear the "page written" flag */
992 }
993
994 /* write user-supplied bytes to oob */
995 else {
996 writew(nand->oob_poi[7], docptr + DOCG4_OOB_6_7);
997 write_nop(docptr);
998 memcpy(ecc_buf, &nand->oob_poi[8], 8);
999 }
1000
1001 docg4_write_buf16(mtd, ecc_buf, 8);
1002 write_nop(docptr);
1003 write_nop(docptr);
1004 writew(0, docptr + DOC_DATAEND);
1005 write_nop(docptr);
1006
1007 return nand_prog_page_end_op(nand);
1008 }
1009
docg4_write_page_raw(struct mtd_info * mtd,struct nand_chip * nand,const uint8_t * buf,int oob_required,int page)1010 static int docg4_write_page_raw(struct mtd_info *mtd, struct nand_chip *nand,
1011 const uint8_t *buf, int oob_required, int page)
1012 {
1013 return write_page(mtd, nand, buf, page, false);
1014 }
1015
docg4_write_page(struct mtd_info * mtd,struct nand_chip * nand,const uint8_t * buf,int oob_required,int page)1016 static int docg4_write_page(struct mtd_info *mtd, struct nand_chip *nand,
1017 const uint8_t *buf, int oob_required, int page)
1018 {
1019 return write_page(mtd, nand, buf, page, true);
1020 }
1021
docg4_write_oob(struct mtd_info * mtd,struct nand_chip * nand,int page)1022 static int docg4_write_oob(struct mtd_info *mtd, struct nand_chip *nand,
1023 int page)
1024 {
1025 /*
1026 * Writing oob-only is not really supported, because MLC nand must write
1027 * oob bytes at the same time as page data. Nonetheless, we save the
1028 * oob buffer contents here, and then write it along with the page data
1029 * if the same page is subsequently written. This allows user space
1030 * utilities that write the oob data prior to the page data to work
1031 * (e.g., nandwrite). The disdvantage is that, if the intention was to
1032 * write oob only, the operation is quietly ignored. Also, oob can get
1033 * corrupted if two concurrent processes are running nandwrite.
1034 */
1035
1036 /* note that bytes 7..14 are hw generated hamming/ecc and overwritten */
1037 struct docg4_priv *doc = nand_get_controller_data(nand);
1038 doc->oob_page = page;
1039 memcpy(doc->oob_buf, nand->oob_poi, 16);
1040 return 0;
1041 }
1042
read_factory_bbt(struct mtd_info * mtd)1043 static int __init read_factory_bbt(struct mtd_info *mtd)
1044 {
1045 /*
1046 * The device contains a read-only factory bad block table. Read it and
1047 * update the memory-based bbt accordingly.
1048 */
1049
1050 struct nand_chip *nand = mtd_to_nand(mtd);
1051 struct docg4_priv *doc = nand_get_controller_data(nand);
1052 uint32_t g4_addr = mtd_to_docg4_address(DOCG4_FACTORY_BBT_PAGE, 0);
1053 uint8_t *buf;
1054 int i, block;
1055 __u32 eccfailed_stats = mtd->ecc_stats.failed;
1056
1057 buf = kzalloc(DOCG4_PAGE_SIZE, GFP_KERNEL);
1058 if (buf == NULL)
1059 return -ENOMEM;
1060
1061 read_page_prologue(mtd, g4_addr);
1062 docg4_read_page(mtd, nand, buf, 0, DOCG4_FACTORY_BBT_PAGE);
1063
1064 /*
1065 * If no memory-based bbt was created, exit. This will happen if module
1066 * parameter ignore_badblocks is set. Then why even call this function?
1067 * For an unknown reason, block erase always fails if it's the first
1068 * operation after device power-up. The above read ensures it never is.
1069 * Ugly, I know.
1070 */
1071 if (nand->bbt == NULL) /* no memory-based bbt */
1072 goto exit;
1073
1074 if (mtd->ecc_stats.failed > eccfailed_stats) {
1075 /*
1076 * Whoops, an ecc failure ocurred reading the factory bbt.
1077 * It is stored redundantly, so we get another chance.
1078 */
1079 eccfailed_stats = mtd->ecc_stats.failed;
1080 docg4_read_page(mtd, nand, buf, 0, DOCG4_REDUNDANT_BBT_PAGE);
1081 if (mtd->ecc_stats.failed > eccfailed_stats) {
1082 dev_warn(doc->dev,
1083 "The factory bbt could not be read!\n");
1084 goto exit;
1085 }
1086 }
1087
1088 /*
1089 * Parse factory bbt and update memory-based bbt. Factory bbt format is
1090 * simple: one bit per block, block numbers increase left to right (msb
1091 * to lsb). Bit clear means bad block.
1092 */
1093 for (i = block = 0; block < DOCG4_NUMBLOCKS; block += 8, i++) {
1094 int bitnum;
1095 unsigned long bits = ~buf[i];
1096 for_each_set_bit(bitnum, &bits, 8) {
1097 int badblock = block + 7 - bitnum;
1098 nand->bbt[badblock / 4] |=
1099 0x03 << ((badblock % 4) * 2);
1100 mtd->ecc_stats.badblocks++;
1101 dev_notice(doc->dev, "factory-marked bad block: %d\n",
1102 badblock);
1103 }
1104 }
1105 exit:
1106 kfree(buf);
1107 return 0;
1108 }
1109
docg4_block_markbad(struct mtd_info * mtd,loff_t ofs)1110 static int docg4_block_markbad(struct mtd_info *mtd, loff_t ofs)
1111 {
1112 /*
1113 * Mark a block as bad. Bad blocks are marked in the oob area of the
1114 * first page of the block. The default scan_bbt() in the nand
1115 * infrastructure code works fine for building the memory-based bbt
1116 * during initialization, as does the nand infrastructure function that
1117 * checks if a block is bad by reading the bbt. This function replaces
1118 * the nand default because writes to oob-only are not supported.
1119 */
1120
1121 int ret, i;
1122 uint8_t *buf;
1123 struct nand_chip *nand = mtd_to_nand(mtd);
1124 struct docg4_priv *doc = nand_get_controller_data(nand);
1125 struct nand_bbt_descr *bbtd = nand->badblock_pattern;
1126 int page = (int)(ofs >> nand->page_shift);
1127 uint32_t g4_addr = mtd_to_docg4_address(page, 0);
1128
1129 dev_dbg(doc->dev, "%s: %08llx\n", __func__, ofs);
1130
1131 if (unlikely(ofs & (DOCG4_BLOCK_SIZE - 1)))
1132 dev_warn(doc->dev, "%s: ofs %llx not start of block!\n",
1133 __func__, ofs);
1134
1135 /* allocate blank buffer for page data */
1136 buf = kzalloc(DOCG4_PAGE_SIZE, GFP_KERNEL);
1137 if (buf == NULL)
1138 return -ENOMEM;
1139
1140 /* write bit-wise negation of pattern to oob buffer */
1141 memset(nand->oob_poi, 0xff, mtd->oobsize);
1142 for (i = 0; i < bbtd->len; i++)
1143 nand->oob_poi[bbtd->offs + i] = ~bbtd->pattern[i];
1144
1145 /* write first page of block */
1146 write_page_prologue(mtd, g4_addr);
1147 docg4_write_page(mtd, nand, buf, 1, page);
1148 ret = pageprog(mtd);
1149
1150 kfree(buf);
1151
1152 return ret;
1153 }
1154
docg4_block_neverbad(struct mtd_info * mtd,loff_t ofs)1155 static int docg4_block_neverbad(struct mtd_info *mtd, loff_t ofs)
1156 {
1157 /* only called when module_param ignore_badblocks is set */
1158 return 0;
1159 }
1160
docg4_suspend(struct platform_device * pdev,pm_message_t state)1161 static int docg4_suspend(struct platform_device *pdev, pm_message_t state)
1162 {
1163 /*
1164 * Put the device into "deep power-down" mode. Note that CE# must be
1165 * deasserted for this to take effect. The xscale, e.g., can be
1166 * configured to float this signal when the processor enters power-down,
1167 * and a suitable pull-up ensures its deassertion.
1168 */
1169
1170 int i;
1171 uint8_t pwr_down;
1172 struct docg4_priv *doc = platform_get_drvdata(pdev);
1173 void __iomem *docptr = doc->virtadr;
1174
1175 dev_dbg(doc->dev, "%s...\n", __func__);
1176
1177 /* poll the register that tells us we're ready to go to sleep */
1178 for (i = 0; i < 10; i++) {
1179 pwr_down = readb(docptr + DOC_POWERMODE);
1180 if (pwr_down & DOC_POWERDOWN_READY)
1181 break;
1182 usleep_range(1000, 4000);
1183 }
1184
1185 if (pwr_down & DOC_POWERDOWN_READY) {
1186 dev_err(doc->dev, "suspend failed; "
1187 "timeout polling DOC_POWERDOWN_READY\n");
1188 return -EIO;
1189 }
1190
1191 writew(DOC_ASICMODE_POWERDOWN | DOC_ASICMODE_MDWREN,
1192 docptr + DOC_ASICMODE);
1193 writew(~(DOC_ASICMODE_POWERDOWN | DOC_ASICMODE_MDWREN),
1194 docptr + DOC_ASICMODECONFIRM);
1195
1196 write_nop(docptr);
1197
1198 return 0;
1199 }
1200
docg4_resume(struct platform_device * pdev)1201 static int docg4_resume(struct platform_device *pdev)
1202 {
1203
1204 /*
1205 * Exit power-down. Twelve consecutive reads of the address below
1206 * accomplishes this, assuming CE# has been asserted.
1207 */
1208
1209 struct docg4_priv *doc = platform_get_drvdata(pdev);
1210 void __iomem *docptr = doc->virtadr;
1211 int i;
1212
1213 dev_dbg(doc->dev, "%s...\n", __func__);
1214
1215 for (i = 0; i < 12; i++)
1216 readb(docptr + 0x1fff);
1217
1218 return 0;
1219 }
1220
init_mtd_structs(struct mtd_info * mtd)1221 static void init_mtd_structs(struct mtd_info *mtd)
1222 {
1223 /* initialize mtd and nand data structures */
1224
1225 /*
1226 * Note that some of the following initializations are not usually
1227 * required within a nand driver because they are performed by the nand
1228 * infrastructure code as part of nand_scan(). In this case they need
1229 * to be initialized here because we skip call to nand_scan_ident() (the
1230 * first half of nand_scan()). The call to nand_scan_ident() could be
1231 * skipped because for this device the chip id is not read in the manner
1232 * of a standard nand device.
1233 */
1234
1235 struct nand_chip *nand = mtd_to_nand(mtd);
1236 struct docg4_priv *doc = nand_get_controller_data(nand);
1237
1238 mtd->size = DOCG4_CHIP_SIZE;
1239 mtd->name = "Msys_Diskonchip_G4";
1240 mtd->writesize = DOCG4_PAGE_SIZE;
1241 mtd->erasesize = DOCG4_BLOCK_SIZE;
1242 mtd->oobsize = DOCG4_OOB_SIZE;
1243 mtd_set_ooblayout(mtd, &docg4_ooblayout_ops);
1244 nand->chipsize = DOCG4_CHIP_SIZE;
1245 nand->chip_shift = DOCG4_CHIP_SHIFT;
1246 nand->bbt_erase_shift = nand->phys_erase_shift = DOCG4_ERASE_SHIFT;
1247 nand->chip_delay = 20;
1248 nand->page_shift = DOCG4_PAGE_SHIFT;
1249 nand->pagemask = 0x3ffff;
1250 nand->badblockpos = NAND_LARGE_BADBLOCK_POS;
1251 nand->badblockbits = 8;
1252 nand->ecc.mode = NAND_ECC_HW_SYNDROME;
1253 nand->ecc.size = DOCG4_PAGE_SIZE;
1254 nand->ecc.prepad = 8;
1255 nand->ecc.bytes = 8;
1256 nand->ecc.strength = DOCG4_T;
1257 nand->options = NAND_BUSWIDTH_16 | NAND_NO_SUBPAGE_WRITE;
1258 nand->IO_ADDR_R = nand->IO_ADDR_W = doc->virtadr + DOC_IOSPACE_DATA;
1259 nand->controller = &nand->dummy_controller;
1260 nand_controller_init(nand->controller);
1261
1262 /* methods */
1263 nand->cmdfunc = docg4_command;
1264 nand->waitfunc = docg4_wait;
1265 nand->select_chip = docg4_select_chip;
1266 nand->read_byte = docg4_read_byte;
1267 nand->block_markbad = docg4_block_markbad;
1268 nand->read_buf = docg4_read_buf;
1269 nand->write_buf = docg4_write_buf16;
1270 nand->erase = docg4_erase_block;
1271 nand->set_features = nand_get_set_features_notsupp;
1272 nand->get_features = nand_get_set_features_notsupp;
1273 nand->ecc.read_page = docg4_read_page;
1274 nand->ecc.write_page = docg4_write_page;
1275 nand->ecc.read_page_raw = docg4_read_page_raw;
1276 nand->ecc.write_page_raw = docg4_write_page_raw;
1277 nand->ecc.read_oob = docg4_read_oob;
1278 nand->ecc.write_oob = docg4_write_oob;
1279
1280 /*
1281 * The way the nand infrastructure code is written, a memory-based bbt
1282 * is not created if NAND_SKIP_BBTSCAN is set. With no memory bbt,
1283 * nand->block_bad() is used. So when ignoring bad blocks, we skip the
1284 * scan and define a dummy block_bad() which always returns 0.
1285 */
1286 if (ignore_badblocks) {
1287 nand->options |= NAND_SKIP_BBTSCAN;
1288 nand->block_bad = docg4_block_neverbad;
1289 }
1290
1291 }
1292
read_id_reg(struct mtd_info * mtd)1293 static int read_id_reg(struct mtd_info *mtd)
1294 {
1295 struct nand_chip *nand = mtd_to_nand(mtd);
1296 struct docg4_priv *doc = nand_get_controller_data(nand);
1297 void __iomem *docptr = doc->virtadr;
1298 uint16_t id1, id2;
1299
1300 /* check for presence of g4 chip by reading id registers */
1301 id1 = readw(docptr + DOC_CHIPID);
1302 id1 = readw(docptr + DOCG4_MYSTERY_REG);
1303 id2 = readw(docptr + DOC_CHIPID_INV);
1304 id2 = readw(docptr + DOCG4_MYSTERY_REG);
1305
1306 if (id1 == DOCG4_IDREG1_VALUE && id2 == DOCG4_IDREG2_VALUE) {
1307 dev_info(doc->dev,
1308 "NAND device: 128MiB Diskonchip G4 detected\n");
1309 return 0;
1310 }
1311
1312 return -ENODEV;
1313 }
1314
1315 static char const *part_probes[] = { "cmdlinepart", "saftlpart", NULL };
1316
docg4_attach_chip(struct nand_chip * chip)1317 static int docg4_attach_chip(struct nand_chip *chip)
1318 {
1319 struct mtd_info *mtd = nand_to_mtd(chip);
1320 struct docg4_priv *doc = (struct docg4_priv *)(chip + 1);
1321 int ret;
1322
1323 init_mtd_structs(mtd);
1324
1325 /* Initialize kernel BCH algorithm */
1326 doc->bch = init_bch(DOCG4_M, DOCG4_T, DOCG4_PRIMITIVE_POLY);
1327 if (!doc->bch)
1328 return -EINVAL;
1329
1330 reset(mtd);
1331
1332 ret = read_id_reg(mtd);
1333 if (ret)
1334 free_bch(doc->bch);
1335
1336 return ret;
1337 }
1338
docg4_detach_chip(struct nand_chip * chip)1339 static void docg4_detach_chip(struct nand_chip *chip)
1340 {
1341 struct docg4_priv *doc = (struct docg4_priv *)(chip + 1);
1342
1343 free_bch(doc->bch);
1344 }
1345
1346 static const struct nand_controller_ops docg4_controller_ops = {
1347 .attach_chip = docg4_attach_chip,
1348 .detach_chip = docg4_detach_chip,
1349 };
1350
probe_docg4(struct platform_device * pdev)1351 static int __init probe_docg4(struct platform_device *pdev)
1352 {
1353 struct mtd_info *mtd;
1354 struct nand_chip *nand;
1355 void __iomem *virtadr;
1356 struct docg4_priv *doc;
1357 int len, retval;
1358 struct resource *r;
1359 struct device *dev = &pdev->dev;
1360
1361 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1362 if (r == NULL) {
1363 dev_err(dev, "no io memory resource defined!\n");
1364 return -ENODEV;
1365 }
1366
1367 virtadr = ioremap(r->start, resource_size(r));
1368 if (!virtadr) {
1369 dev_err(dev, "Diskonchip ioremap failed: %pR\n", r);
1370 return -EIO;
1371 }
1372
1373 len = sizeof(struct nand_chip) + sizeof(struct docg4_priv);
1374 nand = kzalloc(len, GFP_KERNEL);
1375 if (nand == NULL) {
1376 retval = -ENOMEM;
1377 goto unmap;
1378 }
1379
1380 mtd = nand_to_mtd(nand);
1381 doc = (struct docg4_priv *) (nand + 1);
1382 nand_set_controller_data(nand, doc);
1383 mtd->dev.parent = &pdev->dev;
1384 doc->virtadr = virtadr;
1385 doc->dev = dev;
1386 platform_set_drvdata(pdev, doc);
1387
1388 /*
1389 * Running nand_scan() with maxchips == 0 will skip nand_scan_ident(),
1390 * which is a specific operation with this driver and done in the
1391 * ->attach_chip callback.
1392 */
1393 nand->dummy_controller.ops = &docg4_controller_ops;
1394 retval = nand_scan(mtd, 0);
1395 if (retval)
1396 goto free_nand;
1397
1398 retval = read_factory_bbt(mtd);
1399 if (retval)
1400 goto cleanup_nand;
1401
1402 retval = mtd_device_parse_register(mtd, part_probes, NULL, NULL, 0);
1403 if (retval)
1404 goto cleanup_nand;
1405
1406 doc->mtd = mtd;
1407
1408 return 0;
1409
1410 cleanup_nand:
1411 nand_cleanup(nand);
1412 free_nand:
1413 kfree(nand);
1414 unmap:
1415 iounmap(virtadr);
1416
1417 return retval;
1418 }
1419
cleanup_docg4(struct platform_device * pdev)1420 static int __exit cleanup_docg4(struct platform_device *pdev)
1421 {
1422 struct docg4_priv *doc = platform_get_drvdata(pdev);
1423 nand_release(doc->mtd);
1424 kfree(mtd_to_nand(doc->mtd));
1425 iounmap(doc->virtadr);
1426 return 0;
1427 }
1428
1429 static struct platform_driver docg4_driver = {
1430 .driver = {
1431 .name = "docg4",
1432 },
1433 .suspend = docg4_suspend,
1434 .resume = docg4_resume,
1435 .remove = __exit_p(cleanup_docg4),
1436 };
1437
1438 module_platform_driver_probe(docg4_driver, probe_docg4);
1439
1440 MODULE_LICENSE("GPL");
1441 MODULE_AUTHOR("Mike Dunn");
1442 MODULE_DESCRIPTION("M-Systems DiskOnChip G4 device driver");
1443
