1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #ifndef _HWMGR_H_ 24 #define _HWMGR_H_ 25 26 #include <linux/seq_file.h> 27 #include "amd_powerplay.h" 28 #include "hardwaremanager.h" 29 #include "hwmgr_ppt.h" 30 #include "ppatomctrl.h" 31 #include "power_state.h" 32 #include "smu_helper.h" 33 34 struct pp_hwmgr; 35 struct phm_fan_speed_info; 36 struct pp_atomctrl_voltage_table; 37 38 #define VOLTAGE_SCALE 4 39 #define VOLTAGE_VID_OFFSET_SCALE1 625 40 #define VOLTAGE_VID_OFFSET_SCALE2 100 41 42 enum DISPLAY_GAP { 43 DISPLAY_GAP_VBLANK_OR_WM = 0, /* Wait for vblank or MCHG watermark. */ 44 DISPLAY_GAP_VBLANK = 1, /* Wait for vblank. */ 45 DISPLAY_GAP_WATERMARK = 2, /* Wait for MCHG watermark. (Note that HW may deassert WM in VBI depending on DC_STUTTER_CNTL.) */ 46 DISPLAY_GAP_IGNORE = 3 /* Do not wait. */ 47 }; 48 typedef enum DISPLAY_GAP DISPLAY_GAP; 49 50 enum BACO_STATE { 51 BACO_STATE_OUT = 0, 52 BACO_STATE_IN, 53 }; 54 55 struct vi_dpm_level { 56 bool enabled; 57 uint32_t value; 58 uint32_t param1; 59 }; 60 61 struct vi_dpm_table { 62 uint32_t count; 63 struct vi_dpm_level dpm_level[1]; 64 }; 65 66 #define PCIE_PERF_REQ_REMOVE_REGISTRY 0 67 #define PCIE_PERF_REQ_FORCE_LOWPOWER 1 68 #define PCIE_PERF_REQ_GEN1 2 69 #define PCIE_PERF_REQ_GEN2 3 70 #define PCIE_PERF_REQ_GEN3 4 71 72 enum PHM_BackEnd_Magic { 73 PHM_Dummy_Magic = 0xAA5555AA, 74 PHM_RV770_Magic = 0xDCBAABCD, 75 PHM_Kong_Magic = 0x239478DF, 76 PHM_NIslands_Magic = 0x736C494E, 77 PHM_Sumo_Magic = 0x8339FA11, 78 PHM_SIslands_Magic = 0x369431AC, 79 PHM_Trinity_Magic = 0x96751873, 80 PHM_CIslands_Magic = 0x38AC78B0, 81 PHM_Kv_Magic = 0xDCBBABC0, 82 PHM_VIslands_Magic = 0x20130307, 83 PHM_Cz_Magic = 0x67DCBA25, 84 PHM_Rv_Magic = 0x20161121 85 }; 86 87 struct phm_set_power_state_input { 88 const struct pp_hw_power_state *pcurrent_state; 89 const struct pp_hw_power_state *pnew_state; 90 }; 91 92 struct phm_clock_array { 93 uint32_t count; 94 uint32_t values[1]; 95 }; 96 97 struct phm_clock_voltage_dependency_record { 98 uint32_t clk; 99 uint32_t v; 100 }; 101 102 struct phm_vceclock_voltage_dependency_record { 103 uint32_t ecclk; 104 uint32_t evclk; 105 uint32_t v; 106 }; 107 108 struct phm_uvdclock_voltage_dependency_record { 109 uint32_t vclk; 110 uint32_t dclk; 111 uint32_t v; 112 }; 113 114 struct phm_samuclock_voltage_dependency_record { 115 uint32_t samclk; 116 uint32_t v; 117 }; 118 119 struct phm_acpclock_voltage_dependency_record { 120 uint32_t acpclk; 121 uint32_t v; 122 }; 123 124 struct phm_clock_voltage_dependency_table { 125 uint32_t count; /* Number of entries. */ 126 struct phm_clock_voltage_dependency_record entries[1]; /* Dynamically allocate count entries. */ 127 }; 128 129 struct phm_phase_shedding_limits_record { 130 uint32_t Voltage; 131 uint32_t Sclk; 132 uint32_t Mclk; 133 }; 134 135 struct phm_uvd_clock_voltage_dependency_record { 136 uint32_t vclk; 137 uint32_t dclk; 138 uint32_t v; 139 }; 140 141 struct phm_uvd_clock_voltage_dependency_table { 142 uint8_t count; 143 struct phm_uvd_clock_voltage_dependency_record entries[1]; 144 }; 145 146 struct phm_acp_clock_voltage_dependency_record { 147 uint32_t acpclk; 148 uint32_t v; 149 }; 150 151 struct phm_acp_clock_voltage_dependency_table { 152 uint32_t count; 153 struct phm_acp_clock_voltage_dependency_record entries[1]; 154 }; 155 156 struct phm_vce_clock_voltage_dependency_record { 157 uint32_t ecclk; 158 uint32_t evclk; 159 uint32_t v; 160 }; 161 162 struct phm_phase_shedding_limits_table { 163 uint32_t count; 164 struct phm_phase_shedding_limits_record entries[1]; 165 }; 166 167 struct phm_vceclock_voltage_dependency_table { 168 uint8_t count; /* Number of entries. */ 169 struct phm_vceclock_voltage_dependency_record entries[1]; /* Dynamically allocate count entries. */ 170 }; 171 172 struct phm_uvdclock_voltage_dependency_table { 173 uint8_t count; /* Number of entries. */ 174 struct phm_uvdclock_voltage_dependency_record entries[1]; /* Dynamically allocate count entries. */ 175 }; 176 177 struct phm_samuclock_voltage_dependency_table { 178 uint8_t count; /* Number of entries. */ 179 struct phm_samuclock_voltage_dependency_record entries[1]; /* Dynamically allocate count entries. */ 180 }; 181 182 struct phm_acpclock_voltage_dependency_table { 183 uint32_t count; /* Number of entries. */ 184 struct phm_acpclock_voltage_dependency_record entries[1]; /* Dynamically allocate count entries. */ 185 }; 186 187 struct phm_vce_clock_voltage_dependency_table { 188 uint8_t count; 189 struct phm_vce_clock_voltage_dependency_record entries[1]; 190 }; 191 192 193 enum SMU_ASIC_RESET_MODE 194 { 195 SMU_ASIC_RESET_MODE_0, 196 SMU_ASIC_RESET_MODE_1, 197 SMU_ASIC_RESET_MODE_2, 198 }; 199 200 struct pp_smumgr_func { 201 char *name; 202 int (*smu_init)(struct pp_hwmgr *hwmgr); 203 int (*smu_fini)(struct pp_hwmgr *hwmgr); 204 int (*start_smu)(struct pp_hwmgr *hwmgr); 205 int (*check_fw_load_finish)(struct pp_hwmgr *hwmgr, 206 uint32_t firmware); 207 int (*request_smu_load_fw)(struct pp_hwmgr *hwmgr); 208 int (*request_smu_load_specific_fw)(struct pp_hwmgr *hwmgr, 209 uint32_t firmware); 210 uint32_t (*get_argument)(struct pp_hwmgr *hwmgr); 211 int (*send_msg_to_smc)(struct pp_hwmgr *hwmgr, uint16_t msg); 212 int (*send_msg_to_smc_with_parameter)(struct pp_hwmgr *hwmgr, 213 uint16_t msg, uint32_t parameter); 214 int (*download_pptable_settings)(struct pp_hwmgr *hwmgr, 215 void **table); 216 int (*upload_pptable_settings)(struct pp_hwmgr *hwmgr); 217 int (*update_smc_table)(struct pp_hwmgr *hwmgr, uint32_t type); 218 int (*process_firmware_header)(struct pp_hwmgr *hwmgr); 219 int (*update_sclk_threshold)(struct pp_hwmgr *hwmgr); 220 int (*thermal_setup_fan_table)(struct pp_hwmgr *hwmgr); 221 int (*thermal_avfs_enable)(struct pp_hwmgr *hwmgr); 222 int (*init_smc_table)(struct pp_hwmgr *hwmgr); 223 int (*populate_all_graphic_levels)(struct pp_hwmgr *hwmgr); 224 int (*populate_all_memory_levels)(struct pp_hwmgr *hwmgr); 225 int (*initialize_mc_reg_table)(struct pp_hwmgr *hwmgr); 226 uint32_t (*get_offsetof)(uint32_t type, uint32_t member); 227 uint32_t (*get_mac_definition)(uint32_t value); 228 bool (*is_dpm_running)(struct pp_hwmgr *hwmgr); 229 bool (*is_hw_avfs_present)(struct pp_hwmgr *hwmgr); 230 int (*update_dpm_settings)(struct pp_hwmgr *hwmgr, void *profile_setting); 231 int (*smc_table_manager)(struct pp_hwmgr *hwmgr, uint8_t *table, uint16_t table_id, bool rw); /*rw: true for read, false for write */ 232 }; 233 234 struct pp_hwmgr_func { 235 int (*backend_init)(struct pp_hwmgr *hw_mgr); 236 int (*backend_fini)(struct pp_hwmgr *hw_mgr); 237 int (*asic_setup)(struct pp_hwmgr *hw_mgr); 238 int (*get_power_state_size)(struct pp_hwmgr *hw_mgr); 239 240 int (*apply_state_adjust_rules)(struct pp_hwmgr *hwmgr, 241 struct pp_power_state *prequest_ps, 242 const struct pp_power_state *pcurrent_ps); 243 244 int (*apply_clocks_adjust_rules)(struct pp_hwmgr *hwmgr); 245 246 int (*force_dpm_level)(struct pp_hwmgr *hw_mgr, 247 enum amd_dpm_forced_level level); 248 249 int (*dynamic_state_management_enable)( 250 struct pp_hwmgr *hw_mgr); 251 int (*dynamic_state_management_disable)( 252 struct pp_hwmgr *hw_mgr); 253 254 int (*patch_boot_state)(struct pp_hwmgr *hwmgr, 255 struct pp_hw_power_state *hw_ps); 256 257 int (*get_pp_table_entry)(struct pp_hwmgr *hwmgr, 258 unsigned long, struct pp_power_state *); 259 int (*get_num_of_pp_table_entries)(struct pp_hwmgr *hwmgr); 260 int (*powerdown_uvd)(struct pp_hwmgr *hwmgr); 261 void (*powergate_vce)(struct pp_hwmgr *hwmgr, bool bgate); 262 void (*powergate_uvd)(struct pp_hwmgr *hwmgr, bool bgate); 263 void (*powergate_acp)(struct pp_hwmgr *hwmgr, bool bgate); 264 uint32_t (*get_mclk)(struct pp_hwmgr *hwmgr, bool low); 265 uint32_t (*get_sclk)(struct pp_hwmgr *hwmgr, bool low); 266 int (*power_state_set)(struct pp_hwmgr *hwmgr, 267 const void *state); 268 int (*notify_smc_display_config_after_ps_adjustment)(struct pp_hwmgr *hwmgr); 269 int (*pre_display_config_changed)(struct pp_hwmgr *hwmgr); 270 int (*display_config_changed)(struct pp_hwmgr *hwmgr); 271 int (*disable_clock_power_gating)(struct pp_hwmgr *hwmgr); 272 int (*update_clock_gatings)(struct pp_hwmgr *hwmgr, 273 const uint32_t *msg_id); 274 int (*set_max_fan_rpm_output)(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_pwm); 275 int (*set_max_fan_pwm_output)(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_pwm); 276 int (*stop_thermal_controller)(struct pp_hwmgr *hwmgr); 277 int (*get_fan_speed_info)(struct pp_hwmgr *hwmgr, struct phm_fan_speed_info *fan_speed_info); 278 void (*set_fan_control_mode)(struct pp_hwmgr *hwmgr, uint32_t mode); 279 uint32_t (*get_fan_control_mode)(struct pp_hwmgr *hwmgr); 280 int (*set_fan_speed_percent)(struct pp_hwmgr *hwmgr, uint32_t percent); 281 int (*get_fan_speed_percent)(struct pp_hwmgr *hwmgr, uint32_t *speed); 282 int (*set_fan_speed_rpm)(struct pp_hwmgr *hwmgr, uint32_t percent); 283 int (*get_fan_speed_rpm)(struct pp_hwmgr *hwmgr, uint32_t *speed); 284 int (*reset_fan_speed_to_default)(struct pp_hwmgr *hwmgr); 285 int (*uninitialize_thermal_controller)(struct pp_hwmgr *hwmgr); 286 int (*register_irq_handlers)(struct pp_hwmgr *hwmgr); 287 bool (*check_smc_update_required_for_display_configuration)(struct pp_hwmgr *hwmgr); 288 int (*check_states_equal)(struct pp_hwmgr *hwmgr, 289 const struct pp_hw_power_state *pstate1, 290 const struct pp_hw_power_state *pstate2, 291 bool *equal); 292 int (*set_cpu_power_state)(struct pp_hwmgr *hwmgr); 293 int (*store_cc6_data)(struct pp_hwmgr *hwmgr, uint32_t separation_time, 294 bool cc6_disable, bool pstate_disable, 295 bool pstate_switch_disable); 296 int (*get_dal_power_level)(struct pp_hwmgr *hwmgr, 297 struct amd_pp_simple_clock_info *info); 298 int (*get_performance_level)(struct pp_hwmgr *, const struct pp_hw_power_state *, 299 PHM_PerformanceLevelDesignation, uint32_t, PHM_PerformanceLevel *); 300 int (*get_current_shallow_sleep_clocks)(struct pp_hwmgr *hwmgr, 301 const struct pp_hw_power_state *state, struct pp_clock_info *clock_info); 302 int (*get_clock_by_type)(struct pp_hwmgr *hwmgr, enum amd_pp_clock_type type, struct amd_pp_clocks *clocks); 303 int (*get_clock_by_type_with_latency)(struct pp_hwmgr *hwmgr, 304 enum amd_pp_clock_type type, 305 struct pp_clock_levels_with_latency *clocks); 306 int (*get_clock_by_type_with_voltage)(struct pp_hwmgr *hwmgr, 307 enum amd_pp_clock_type type, 308 struct pp_clock_levels_with_voltage *clocks); 309 int (*set_watermarks_for_clocks_ranges)(struct pp_hwmgr *hwmgr, void *clock_ranges); 310 int (*display_clock_voltage_request)(struct pp_hwmgr *hwmgr, 311 struct pp_display_clock_request *clock); 312 int (*get_max_high_clocks)(struct pp_hwmgr *hwmgr, struct amd_pp_simple_clock_info *clocks); 313 int (*power_off_asic)(struct pp_hwmgr *hwmgr); 314 int (*force_clock_level)(struct pp_hwmgr *hwmgr, enum pp_clock_type type, uint32_t mask); 315 int (*print_clock_levels)(struct pp_hwmgr *hwmgr, enum pp_clock_type type, char *buf); 316 int (*powergate_gfx)(struct pp_hwmgr *hwmgr, bool enable); 317 int (*get_sclk_od)(struct pp_hwmgr *hwmgr); 318 int (*set_sclk_od)(struct pp_hwmgr *hwmgr, uint32_t value); 319 int (*get_mclk_od)(struct pp_hwmgr *hwmgr); 320 int (*set_mclk_od)(struct pp_hwmgr *hwmgr, uint32_t value); 321 int (*read_sensor)(struct pp_hwmgr *hwmgr, int idx, void *value, int *size); 322 int (*avfs_control)(struct pp_hwmgr *hwmgr, bool enable); 323 int (*disable_smc_firmware_ctf)(struct pp_hwmgr *hwmgr); 324 int (*set_active_display_count)(struct pp_hwmgr *hwmgr, uint32_t count); 325 int (*set_min_deep_sleep_dcefclk)(struct pp_hwmgr *hwmgr, uint32_t clock); 326 int (*start_thermal_controller)(struct pp_hwmgr *hwmgr, struct PP_TemperatureRange *range); 327 int (*notify_cac_buffer_info)(struct pp_hwmgr *hwmgr, 328 uint32_t virtual_addr_low, 329 uint32_t virtual_addr_hi, 330 uint32_t mc_addr_low, 331 uint32_t mc_addr_hi, 332 uint32_t size); 333 int (*update_nbdpm_pstate)(struct pp_hwmgr *hwmgr, 334 bool enable, 335 bool lock); 336 int (*get_thermal_temperature_range)(struct pp_hwmgr *hwmgr, 337 struct PP_TemperatureRange *range); 338 int (*get_power_profile_mode)(struct pp_hwmgr *hwmgr, char *buf); 339 int (*set_power_profile_mode)(struct pp_hwmgr *hwmgr, long *input, uint32_t size); 340 int (*odn_edit_dpm_table)(struct pp_hwmgr *hwmgr, 341 enum PP_OD_DPM_TABLE_COMMAND type, 342 long *input, uint32_t size); 343 int (*set_power_limit)(struct pp_hwmgr *hwmgr, uint32_t n); 344 int (*powergate_mmhub)(struct pp_hwmgr *hwmgr); 345 int (*smus_notify_pwe)(struct pp_hwmgr *hwmgr); 346 int (*powergate_sdma)(struct pp_hwmgr *hwmgr, bool bgate); 347 int (*enable_mgpu_fan_boost)(struct pp_hwmgr *hwmgr); 348 int (*set_hard_min_dcefclk_by_freq)(struct pp_hwmgr *hwmgr, uint32_t clock); 349 int (*set_hard_min_fclk_by_freq)(struct pp_hwmgr *hwmgr, uint32_t clock); 350 int (*get_asic_baco_capability)(struct pp_hwmgr *hwmgr, bool *cap); 351 int (*get_asic_baco_state)(struct pp_hwmgr *hwmgr, enum BACO_STATE *state); 352 int (*set_asic_baco_state)(struct pp_hwmgr *hwmgr, enum BACO_STATE state); 353 int (*get_ppfeature_status)(struct pp_hwmgr *hwmgr, char *buf); 354 int (*set_ppfeature_status)(struct pp_hwmgr *hwmgr, uint64_t ppfeature_masks); 355 int (*set_mp1_state)(struct pp_hwmgr *hwmgr, enum pp_mp1_state mp1_state); 356 int (*asic_reset)(struct pp_hwmgr *hwmgr, enum SMU_ASIC_RESET_MODE mode); 357 int (*smu_i2c_bus_access)(struct pp_hwmgr *hwmgr, bool aquire); 358 }; 359 360 struct pp_table_func { 361 int (*pptable_init)(struct pp_hwmgr *hw_mgr); 362 int (*pptable_fini)(struct pp_hwmgr *hw_mgr); 363 int (*pptable_get_number_of_vce_state_table_entries)(struct pp_hwmgr *hw_mgr); 364 int (*pptable_get_vce_state_table_entry)( 365 struct pp_hwmgr *hwmgr, 366 unsigned long i, 367 struct amd_vce_state *vce_state, 368 void **clock_info, 369 unsigned long *flag); 370 }; 371 372 union phm_cac_leakage_record { 373 struct { 374 uint16_t Vddc; /* in CI, we use it for StdVoltageHiSidd */ 375 uint32_t Leakage; /* in CI, we use it for StdVoltageLoSidd */ 376 }; 377 struct { 378 uint16_t Vddc1; 379 uint16_t Vddc2; 380 uint16_t Vddc3; 381 }; 382 }; 383 384 struct phm_cac_leakage_table { 385 uint32_t count; 386 union phm_cac_leakage_record entries[1]; 387 }; 388 389 struct phm_samu_clock_voltage_dependency_record { 390 uint32_t samclk; 391 uint32_t v; 392 }; 393 394 395 struct phm_samu_clock_voltage_dependency_table { 396 uint8_t count; 397 struct phm_samu_clock_voltage_dependency_record entries[1]; 398 }; 399 400 struct phm_cac_tdp_table { 401 uint16_t usTDP; 402 uint16_t usConfigurableTDP; 403 uint16_t usTDC; 404 uint16_t usBatteryPowerLimit; 405 uint16_t usSmallPowerLimit; 406 uint16_t usLowCACLeakage; 407 uint16_t usHighCACLeakage; 408 uint16_t usMaximumPowerDeliveryLimit; 409 uint16_t usEDCLimit; 410 uint16_t usOperatingTempMinLimit; 411 uint16_t usOperatingTempMaxLimit; 412 uint16_t usOperatingTempStep; 413 uint16_t usOperatingTempHyst; 414 uint16_t usDefaultTargetOperatingTemp; 415 uint16_t usTargetOperatingTemp; 416 uint16_t usPowerTuneDataSetID; 417 uint16_t usSoftwareShutdownTemp; 418 uint16_t usClockStretchAmount; 419 uint16_t usTemperatureLimitHotspot; 420 uint16_t usTemperatureLimitLiquid1; 421 uint16_t usTemperatureLimitLiquid2; 422 uint16_t usTemperatureLimitVrVddc; 423 uint16_t usTemperatureLimitVrMvdd; 424 uint16_t usTemperatureLimitPlx; 425 uint8_t ucLiquid1_I2C_address; 426 uint8_t ucLiquid2_I2C_address; 427 uint8_t ucLiquid_I2C_Line; 428 uint8_t ucVr_I2C_address; 429 uint8_t ucVr_I2C_Line; 430 uint8_t ucPlx_I2C_address; 431 uint8_t ucPlx_I2C_Line; 432 uint32_t usBoostPowerLimit; 433 uint8_t ucCKS_LDO_REFSEL; 434 }; 435 436 struct phm_tdp_table { 437 uint16_t usTDP; 438 uint16_t usConfigurableTDP; 439 uint16_t usTDC; 440 uint16_t usBatteryPowerLimit; 441 uint16_t usSmallPowerLimit; 442 uint16_t usLowCACLeakage; 443 uint16_t usHighCACLeakage; 444 uint16_t usMaximumPowerDeliveryLimit; 445 uint16_t usEDCLimit; 446 uint16_t usOperatingTempMinLimit; 447 uint16_t usOperatingTempMaxLimit; 448 uint16_t usOperatingTempStep; 449 uint16_t usOperatingTempHyst; 450 uint16_t usDefaultTargetOperatingTemp; 451 uint16_t usTargetOperatingTemp; 452 uint16_t usPowerTuneDataSetID; 453 uint16_t usSoftwareShutdownTemp; 454 uint16_t usClockStretchAmount; 455 uint16_t usTemperatureLimitTedge; 456 uint16_t usTemperatureLimitHotspot; 457 uint16_t usTemperatureLimitLiquid1; 458 uint16_t usTemperatureLimitLiquid2; 459 uint16_t usTemperatureLimitHBM; 460 uint16_t usTemperatureLimitVrVddc; 461 uint16_t usTemperatureLimitVrMvdd; 462 uint16_t usTemperatureLimitPlx; 463 uint8_t ucLiquid1_I2C_address; 464 uint8_t ucLiquid2_I2C_address; 465 uint8_t ucLiquid_I2C_Line; 466 uint8_t ucVr_I2C_address; 467 uint8_t ucVr_I2C_Line; 468 uint8_t ucPlx_I2C_address; 469 uint8_t ucPlx_I2C_Line; 470 uint8_t ucLiquid_I2C_LineSDA; 471 uint8_t ucVr_I2C_LineSDA; 472 uint8_t ucPlx_I2C_LineSDA; 473 uint32_t usBoostPowerLimit; 474 uint16_t usBoostStartTemperature; 475 uint16_t usBoostStopTemperature; 476 uint32_t ulBoostClock; 477 }; 478 479 struct phm_ppm_table { 480 uint8_t ppm_design; 481 uint16_t cpu_core_number; 482 uint32_t platform_tdp; 483 uint32_t small_ac_platform_tdp; 484 uint32_t platform_tdc; 485 uint32_t small_ac_platform_tdc; 486 uint32_t apu_tdp; 487 uint32_t dgpu_tdp; 488 uint32_t dgpu_ulv_power; 489 uint32_t tj_max; 490 }; 491 492 struct phm_vq_budgeting_record { 493 uint32_t ulCUs; 494 uint32_t ulSustainableSOCPowerLimitLow; 495 uint32_t ulSustainableSOCPowerLimitHigh; 496 uint32_t ulMinSclkLow; 497 uint32_t ulMinSclkHigh; 498 uint8_t ucDispConfig; 499 uint32_t ulDClk; 500 uint32_t ulEClk; 501 uint32_t ulSustainableSclk; 502 uint32_t ulSustainableCUs; 503 }; 504 505 struct phm_vq_budgeting_table { 506 uint8_t numEntries; 507 struct phm_vq_budgeting_record entries[1]; 508 }; 509 510 struct phm_clock_and_voltage_limits { 511 uint32_t sclk; 512 uint32_t mclk; 513 uint32_t gfxclk; 514 uint16_t vddc; 515 uint16_t vddci; 516 uint16_t vddgfx; 517 uint16_t vddmem; 518 }; 519 520 /* Structure to hold PPTable information */ 521 522 struct phm_ppt_v1_information { 523 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_sclk; 524 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_mclk; 525 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_socclk; 526 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_dcefclk; 527 struct phm_clock_array *valid_sclk_values; 528 struct phm_clock_array *valid_mclk_values; 529 struct phm_clock_array *valid_socclk_values; 530 struct phm_clock_array *valid_dcefclk_values; 531 struct phm_clock_and_voltage_limits max_clock_voltage_on_dc; 532 struct phm_clock_and_voltage_limits max_clock_voltage_on_ac; 533 struct phm_clock_voltage_dependency_table *vddc_dep_on_dal_pwrl; 534 struct phm_ppm_table *ppm_parameter_table; 535 struct phm_cac_tdp_table *cac_dtp_table; 536 struct phm_tdp_table *tdp_table; 537 struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_dep_table; 538 struct phm_ppt_v1_voltage_lookup_table *vddc_lookup_table; 539 struct phm_ppt_v1_voltage_lookup_table *vddgfx_lookup_table; 540 struct phm_ppt_v1_voltage_lookup_table *vddmem_lookup_table; 541 struct phm_ppt_v1_pcie_table *pcie_table; 542 struct phm_ppt_v1_gpio_table *gpio_table; 543 uint16_t us_ulv_voltage_offset; 544 uint16_t us_ulv_smnclk_did; 545 uint16_t us_ulv_mp1clk_did; 546 uint16_t us_ulv_gfxclk_bypass; 547 uint16_t us_gfxclk_slew_rate; 548 uint16_t us_min_gfxclk_freq_limit; 549 }; 550 551 struct phm_ppt_v2_information { 552 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_sclk; 553 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_mclk; 554 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_socclk; 555 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_dcefclk; 556 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_pixclk; 557 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_dispclk; 558 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_phyclk; 559 struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_dep_table; 560 561 struct phm_clock_voltage_dependency_table *vddc_dep_on_dalpwrl; 562 563 struct phm_clock_array *valid_sclk_values; 564 struct phm_clock_array *valid_mclk_values; 565 struct phm_clock_array *valid_socclk_values; 566 struct phm_clock_array *valid_dcefclk_values; 567 568 struct phm_clock_and_voltage_limits max_clock_voltage_on_dc; 569 struct phm_clock_and_voltage_limits max_clock_voltage_on_ac; 570 571 struct phm_ppm_table *ppm_parameter_table; 572 struct phm_cac_tdp_table *cac_dtp_table; 573 struct phm_tdp_table *tdp_table; 574 575 struct phm_ppt_v1_voltage_lookup_table *vddc_lookup_table; 576 struct phm_ppt_v1_voltage_lookup_table *vddgfx_lookup_table; 577 struct phm_ppt_v1_voltage_lookup_table *vddmem_lookup_table; 578 struct phm_ppt_v1_voltage_lookup_table *vddci_lookup_table; 579 580 struct phm_ppt_v1_pcie_table *pcie_table; 581 582 uint16_t us_ulv_voltage_offset; 583 uint16_t us_ulv_smnclk_did; 584 uint16_t us_ulv_mp1clk_did; 585 uint16_t us_ulv_gfxclk_bypass; 586 uint16_t us_gfxclk_slew_rate; 587 uint16_t us_min_gfxclk_freq_limit; 588 589 uint8_t uc_gfx_dpm_voltage_mode; 590 uint8_t uc_soc_dpm_voltage_mode; 591 uint8_t uc_uclk_dpm_voltage_mode; 592 uint8_t uc_uvd_dpm_voltage_mode; 593 uint8_t uc_vce_dpm_voltage_mode; 594 uint8_t uc_mp0_dpm_voltage_mode; 595 uint8_t uc_dcef_dpm_voltage_mode; 596 }; 597 598 struct phm_ppt_v3_information 599 { 600 uint8_t uc_thermal_controller_type; 601 602 uint16_t us_small_power_limit1; 603 uint16_t us_small_power_limit2; 604 uint16_t us_boost_power_limit; 605 606 uint16_t us_od_turbo_power_limit; 607 uint16_t us_od_powersave_power_limit; 608 uint16_t us_software_shutdown_temp; 609 610 uint32_t *power_saving_clock_max; 611 uint32_t *power_saving_clock_min; 612 613 uint8_t *od_feature_capabilities; 614 uint32_t *od_settings_max; 615 uint32_t *od_settings_min; 616 617 void *smc_pptable; 618 }; 619 620 struct phm_dynamic_state_info { 621 struct phm_clock_voltage_dependency_table *vddc_dependency_on_sclk; 622 struct phm_clock_voltage_dependency_table *vddci_dependency_on_mclk; 623 struct phm_clock_voltage_dependency_table *vddc_dependency_on_mclk; 624 struct phm_clock_voltage_dependency_table *mvdd_dependency_on_mclk; 625 struct phm_clock_voltage_dependency_table *vddc_dep_on_dal_pwrl; 626 struct phm_clock_array *valid_sclk_values; 627 struct phm_clock_array *valid_mclk_values; 628 struct phm_clock_and_voltage_limits max_clock_voltage_on_dc; 629 struct phm_clock_and_voltage_limits max_clock_voltage_on_ac; 630 uint32_t mclk_sclk_ratio; 631 uint32_t sclk_mclk_delta; 632 uint32_t vddc_vddci_delta; 633 uint32_t min_vddc_for_pcie_gen2; 634 struct phm_cac_leakage_table *cac_leakage_table; 635 struct phm_phase_shedding_limits_table *vddc_phase_shed_limits_table; 636 637 struct phm_vce_clock_voltage_dependency_table 638 *vce_clock_voltage_dependency_table; 639 struct phm_uvd_clock_voltage_dependency_table 640 *uvd_clock_voltage_dependency_table; 641 struct phm_acp_clock_voltage_dependency_table 642 *acp_clock_voltage_dependency_table; 643 struct phm_samu_clock_voltage_dependency_table 644 *samu_clock_voltage_dependency_table; 645 646 struct phm_ppm_table *ppm_parameter_table; 647 struct phm_cac_tdp_table *cac_dtp_table; 648 struct phm_clock_voltage_dependency_table *vdd_gfx_dependency_on_sclk; 649 }; 650 651 struct pp_fan_info { 652 bool bNoFan; 653 uint8_t ucTachometerPulsesPerRevolution; 654 uint32_t ulMinRPM; 655 uint32_t ulMaxRPM; 656 }; 657 658 struct pp_advance_fan_control_parameters { 659 uint16_t usTMin; /* The temperature, in 0.01 centigrades, below which we just run at a minimal PWM. */ 660 uint16_t usTMed; /* The middle temperature where we change slopes. */ 661 uint16_t usTHigh; /* The high temperature for setting the second slope. */ 662 uint16_t usPWMMin; /* The minimum PWM value in percent (0.01% increments). */ 663 uint16_t usPWMMed; /* The PWM value (in percent) at TMed. */ 664 uint16_t usPWMHigh; /* The PWM value at THigh. */ 665 uint8_t ucTHyst; /* Temperature hysteresis. Integer. */ 666 uint32_t ulCycleDelay; /* The time between two invocations of the fan control routine in microseconds. */ 667 uint16_t usTMax; /* The max temperature */ 668 uint8_t ucFanControlMode; 669 uint16_t usFanPWMMinLimit; 670 uint16_t usFanPWMMaxLimit; 671 uint16_t usFanPWMStep; 672 uint16_t usDefaultMaxFanPWM; 673 uint16_t usFanOutputSensitivity; 674 uint16_t usDefaultFanOutputSensitivity; 675 uint16_t usMaxFanPWM; /* The max Fan PWM value for Fuzzy Fan Control feature */ 676 uint16_t usFanRPMMinLimit; /* Minimum limit range in percentage, need to calculate based on minRPM/MaxRpm */ 677 uint16_t usFanRPMMaxLimit; /* Maximum limit range in percentage, usually set to 100% by default */ 678 uint16_t usFanRPMStep; /* Step increments/decerements, in percent */ 679 uint16_t usDefaultMaxFanRPM; /* The max Fan RPM value for Fuzzy Fan Control feature, default from PPTable */ 680 uint16_t usMaxFanRPM; /* The max Fan RPM value for Fuzzy Fan Control feature, user defined */ 681 uint16_t usFanCurrentLow; /* Low current */ 682 uint16_t usFanCurrentHigh; /* High current */ 683 uint16_t usFanRPMLow; /* Low RPM */ 684 uint16_t usFanRPMHigh; /* High RPM */ 685 uint32_t ulMinFanSCLKAcousticLimit; /* Minimum Fan Controller SCLK Frequency Acoustic Limit. */ 686 uint8_t ucTargetTemperature; /* Advanced fan controller target temperature. */ 687 uint8_t ucMinimumPWMLimit; /* The minimum PWM that the advanced fan controller can set. This should be set to the highest PWM that will run the fan at its lowest RPM. */ 688 uint16_t usFanGainEdge; /* The following is added for Fiji */ 689 uint16_t usFanGainHotspot; 690 uint16_t usFanGainLiquid; 691 uint16_t usFanGainVrVddc; 692 uint16_t usFanGainVrMvdd; 693 uint16_t usFanGainPlx; 694 uint16_t usFanGainHbm; 695 uint8_t ucEnableZeroRPM; 696 uint8_t ucFanStopTemperature; 697 uint8_t ucFanStartTemperature; 698 uint32_t ulMaxFanSCLKAcousticLimit; /* Maximum Fan Controller SCLK Frequency Acoustic Limit. */ 699 uint32_t ulTargetGfxClk; 700 uint16_t usZeroRPMStartTemperature; 701 uint16_t usZeroRPMStopTemperature; 702 uint16_t usMGpuThrottlingRPMLimit; 703 }; 704 705 struct pp_thermal_controller_info { 706 uint8_t ucType; 707 uint8_t ucI2cLine; 708 uint8_t ucI2cAddress; 709 uint8_t use_hw_fan_control; 710 struct pp_fan_info fanInfo; 711 struct pp_advance_fan_control_parameters advanceFanControlParameters; 712 }; 713 714 struct phm_microcode_version_info { 715 uint32_t SMC; 716 uint32_t DMCU; 717 uint32_t MC; 718 uint32_t NB; 719 }; 720 721 enum PP_TABLE_VERSION { 722 PP_TABLE_V0 = 0, 723 PP_TABLE_V1, 724 PP_TABLE_V2, 725 PP_TABLE_MAX 726 }; 727 728 /** 729 * The main hardware manager structure. 730 */ 731 #define Workload_Policy_Max 6 732 733 struct pp_hwmgr { 734 void *adev; 735 uint32_t chip_family; 736 uint32_t chip_id; 737 uint32_t smu_version; 738 bool not_vf; 739 bool pm_en; 740 struct mutex smu_lock; 741 742 uint32_t pp_table_version; 743 void *device; 744 struct pp_smumgr *smumgr; 745 const void *soft_pp_table; 746 uint32_t soft_pp_table_size; 747 void *hardcode_pp_table; 748 bool need_pp_table_upload; 749 750 struct amd_vce_state vce_states[AMD_MAX_VCE_LEVELS]; 751 uint32_t num_vce_state_tables; 752 753 enum amd_dpm_forced_level dpm_level; 754 enum amd_dpm_forced_level saved_dpm_level; 755 enum amd_dpm_forced_level request_dpm_level; 756 uint32_t usec_timeout; 757 void *pptable; 758 struct phm_platform_descriptor platform_descriptor; 759 void *backend; 760 761 void *smu_backend; 762 const struct pp_smumgr_func *smumgr_funcs; 763 bool is_kicker; 764 765 enum PP_DAL_POWERLEVEL dal_power_level; 766 struct phm_dynamic_state_info dyn_state; 767 const struct pp_hwmgr_func *hwmgr_func; 768 const struct pp_table_func *pptable_func; 769 770 struct pp_power_state *ps; 771 uint32_t num_ps; 772 struct pp_thermal_controller_info thermal_controller; 773 bool fan_ctrl_is_in_default_mode; 774 uint32_t fan_ctrl_default_mode; 775 bool fan_ctrl_enabled; 776 uint32_t tmin; 777 struct phm_microcode_version_info microcode_version_info; 778 uint32_t ps_size; 779 struct pp_power_state *current_ps; 780 struct pp_power_state *request_ps; 781 struct pp_power_state *boot_ps; 782 struct pp_power_state *uvd_ps; 783 const struct amd_pp_display_configuration *display_config; 784 uint32_t feature_mask; 785 bool avfs_supported; 786 /* UMD Pstate */ 787 bool en_umd_pstate; 788 uint32_t power_profile_mode; 789 uint32_t default_power_profile_mode; 790 uint32_t pstate_sclk; 791 uint32_t pstate_mclk; 792 bool od_enabled; 793 uint32_t power_limit; 794 uint32_t default_power_limit; 795 uint32_t workload_mask; 796 uint32_t workload_prority[Workload_Policy_Max]; 797 uint32_t workload_setting[Workload_Policy_Max]; 798 bool gfxoff_state_changed_by_workload; 799 }; 800 801 int hwmgr_early_init(struct pp_hwmgr *hwmgr); 802 int hwmgr_sw_init(struct pp_hwmgr *hwmgr); 803 int hwmgr_sw_fini(struct pp_hwmgr *hwmgr); 804 int hwmgr_hw_init(struct pp_hwmgr *hwmgr); 805 int hwmgr_hw_fini(struct pp_hwmgr *hwmgr); 806 int hwmgr_suspend(struct pp_hwmgr *hwmgr); 807 int hwmgr_resume(struct pp_hwmgr *hwmgr); 808 809 int hwmgr_handle_task(struct pp_hwmgr *hwmgr, 810 enum amd_pp_task task_id, 811 enum amd_pm_state_type *user_state); 812 813 814 #define PHM_ENTIRE_REGISTER_MASK 0xFFFFFFFFU 815 816 817 #endif /* _HWMGR_H_ */ 818
