1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved.
4 *
5 * Based on the r8180 driver, which is:
6 * Copyright 2004-2005 Andrea Merello <andrea.merello@gmail.com>, et al.
7 *
8 * Contact Information: wlanfae <wlanfae@realtek.com>
9 */
10 #include "rtl_core.h"
11 #include "r8192E_phy.h"
12 #include "r8192E_phyreg.h"
13 #include "r8190P_rtl8256.h"
14 #include "r8192E_cmdpkt.h"
15 #include "rtl_dm.h"
16 #include "rtl_wx.h"
17
18 static int WDCAPARA_ADD[] = {EDCAPARA_BE, EDCAPARA_BK, EDCAPARA_VI,
19 EDCAPARA_VO};
20
rtl92e_start_beacon(struct net_device * dev)21 void rtl92e_start_beacon(struct net_device *dev)
22 {
23 struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev);
24 struct rtllib_network *net = &priv->rtllib->current_network;
25 u16 BcnTimeCfg = 0;
26 u16 BcnCW = 6;
27 u16 BcnIFS = 0xf;
28
29 rtl92e_irq_disable(dev);
30
31 rtl92e_writew(dev, ATIMWND, 2);
32
33 rtl92e_writew(dev, BCN_INTERVAL, net->beacon_interval);
34 rtl92e_writew(dev, BCN_DRV_EARLY_INT, 10);
35 rtl92e_writew(dev, BCN_DMATIME, 256);
36
37 rtl92e_writeb(dev, BCN_ERR_THRESH, 100);
38
39 BcnTimeCfg |= BcnCW<<BCN_TCFG_CW_SHIFT;
40 BcnTimeCfg |= BcnIFS<<BCN_TCFG_IFS;
41 rtl92e_writew(dev, BCN_TCFG, BcnTimeCfg);
42 rtl92e_irq_enable(dev);
43 }
44
_rtl92e_update_msr(struct net_device * dev)45 static void _rtl92e_update_msr(struct net_device *dev)
46 {
47 struct r8192_priv *priv = rtllib_priv(dev);
48 u8 msr;
49 enum led_ctl_mode LedAction = LED_CTL_NO_LINK;
50
51 msr = rtl92e_readb(dev, MSR);
52 msr &= ~MSR_LINK_MASK;
53
54 switch (priv->rtllib->iw_mode) {
55 case IW_MODE_INFRA:
56 if (priv->rtllib->state == RTLLIB_LINKED)
57 msr |= (MSR_LINK_MANAGED << MSR_LINK_SHIFT);
58 else
59 msr |= (MSR_LINK_NONE << MSR_LINK_SHIFT);
60 LedAction = LED_CTL_LINK;
61 break;
62 case IW_MODE_ADHOC:
63 if (priv->rtllib->state == RTLLIB_LINKED)
64 msr |= (MSR_LINK_ADHOC << MSR_LINK_SHIFT);
65 else
66 msr |= (MSR_LINK_NONE << MSR_LINK_SHIFT);
67 break;
68 case IW_MODE_MASTER:
69 if (priv->rtllib->state == RTLLIB_LINKED)
70 msr |= (MSR_LINK_MASTER << MSR_LINK_SHIFT);
71 else
72 msr |= (MSR_LINK_NONE << MSR_LINK_SHIFT);
73 break;
74 default:
75 break;
76 }
77
78 rtl92e_writeb(dev, MSR, msr);
79 if (priv->rtllib->LedControlHandler)
80 priv->rtllib->LedControlHandler(dev, LedAction);
81 }
82
rtl92e_set_reg(struct net_device * dev,u8 variable,u8 * val)83 void rtl92e_set_reg(struct net_device *dev, u8 variable, u8 *val)
84 {
85 struct r8192_priv *priv = rtllib_priv(dev);
86
87 switch (variable) {
88 case HW_VAR_BSSID:
89 /* BSSIDR 2 byte alignment */
90 rtl92e_writew(dev, BSSIDR, *(u16 *)val);
91 rtl92e_writel(dev, BSSIDR + 2, *(u32 *)(val + 2));
92 break;
93
94 case HW_VAR_MEDIA_STATUS:
95 {
96 enum rt_op_mode OpMode = *((enum rt_op_mode *)(val));
97 u8 btMsr = rtl92e_readb(dev, MSR);
98
99 btMsr &= 0xfc;
100
101 switch (OpMode) {
102 case RT_OP_MODE_INFRASTRUCTURE:
103 btMsr |= MSR_INFRA;
104 break;
105
106 case RT_OP_MODE_IBSS:
107 btMsr |= MSR_ADHOC;
108 break;
109
110 case RT_OP_MODE_AP:
111 btMsr |= MSR_AP;
112 break;
113
114 default:
115 btMsr |= MSR_NOLINK;
116 break;
117 }
118
119 rtl92e_writeb(dev, MSR, btMsr);
120
121 }
122 break;
123
124 case HW_VAR_CECHK_BSSID:
125 {
126 u32 RegRCR, Type;
127
128 Type = val[0];
129 RegRCR = rtl92e_readl(dev, RCR);
130 priv->ReceiveConfig = RegRCR;
131
132 if (Type)
133 RegRCR |= (RCR_CBSSID);
134 else
135 RegRCR &= (~RCR_CBSSID);
136
137 rtl92e_writel(dev, RCR, RegRCR);
138 priv->ReceiveConfig = RegRCR;
139
140 }
141 break;
142
143 case HW_VAR_SLOT_TIME:
144
145 priv->slot_time = val[0];
146 rtl92e_writeb(dev, SLOT_TIME, val[0]);
147
148 break;
149
150 case HW_VAR_ACK_PREAMBLE:
151 {
152 u32 regTmp;
153
154 priv->short_preamble = (bool)*val;
155 regTmp = priv->basic_rate;
156 if (priv->short_preamble)
157 regTmp |= BRSR_AckShortPmb;
158 rtl92e_writel(dev, RRSR, regTmp);
159 break;
160 }
161
162 case HW_VAR_CPU_RST:
163 rtl92e_writel(dev, CPU_GEN, ((u32 *)(val))[0]);
164 break;
165
166 case HW_VAR_AC_PARAM:
167 {
168 u8 pAcParam = *val;
169 u32 eACI = pAcParam;
170 u8 u1bAIFS;
171 u32 u4bAcParam;
172 u8 mode = priv->rtllib->mode;
173 struct rtllib_qos_parameters *qop =
174 &priv->rtllib->current_network.qos_data.parameters;
175
176 u1bAIFS = qop->aifs[pAcParam] *
177 ((mode&(IEEE_G|IEEE_N_24G)) ? 9 : 20) + aSifsTime;
178
179 rtl92e_dm_init_edca_turbo(dev);
180
181 u4bAcParam = (le16_to_cpu(qop->tx_op_limit[pAcParam]) <<
182 AC_PARAM_TXOP_LIMIT_OFFSET) |
183 ((le16_to_cpu(qop->cw_max[pAcParam])) <<
184 AC_PARAM_ECW_MAX_OFFSET) |
185 ((le16_to_cpu(qop->cw_min[pAcParam])) <<
186 AC_PARAM_ECW_MIN_OFFSET) |
187 (((u32)u1bAIFS) << AC_PARAM_AIFS_OFFSET);
188
189 switch (eACI) {
190 case AC1_BK:
191 rtl92e_writel(dev, EDCAPARA_BK, u4bAcParam);
192 break;
193
194 case AC0_BE:
195 rtl92e_writel(dev, EDCAPARA_BE, u4bAcParam);
196 break;
197
198 case AC2_VI:
199 rtl92e_writel(dev, EDCAPARA_VI, u4bAcParam);
200 break;
201
202 case AC3_VO:
203 rtl92e_writel(dev, EDCAPARA_VO, u4bAcParam);
204 break;
205
206 default:
207 netdev_info(dev, "SetHwReg8185(): invalid ACI: %d !\n",
208 eACI);
209 break;
210 }
211 priv->rtllib->SetHwRegHandler(dev, HW_VAR_ACM_CTRL,
212 &pAcParam);
213 break;
214 }
215
216 case HW_VAR_ACM_CTRL:
217 {
218 struct rtllib_qos_parameters *qos_parameters =
219 &priv->rtllib->current_network.qos_data.parameters;
220 u8 pAcParam = *val;
221 u32 eACI = pAcParam;
222 union aci_aifsn *pAciAifsn = (union aci_aifsn *)&
223 (qos_parameters->aifs[0]);
224 u8 acm = pAciAifsn->f.acm;
225 u8 AcmCtrl = rtl92e_readb(dev, AcmHwCtrl);
226
227 AcmCtrl = AcmCtrl | ((priv->AcmMethod == 2) ? 0x0 : 0x1);
228
229 if (acm) {
230 switch (eACI) {
231 case AC0_BE:
232 AcmCtrl |= AcmHw_BeqEn;
233 break;
234
235 case AC2_VI:
236 AcmCtrl |= AcmHw_ViqEn;
237 break;
238
239 case AC3_VO:
240 AcmCtrl |= AcmHw_VoqEn;
241 break;
242 }
243 } else {
244 switch (eACI) {
245 case AC0_BE:
246 AcmCtrl &= (~AcmHw_BeqEn);
247 break;
248
249 case AC2_VI:
250 AcmCtrl &= (~AcmHw_ViqEn);
251 break;
252
253 case AC3_VO:
254 AcmCtrl &= (~AcmHw_BeqEn);
255 break;
256
257 default:
258 break;
259 }
260 }
261 rtl92e_writeb(dev, AcmHwCtrl, AcmCtrl);
262 break;
263 }
264
265 case HW_VAR_SIFS:
266 rtl92e_writeb(dev, SIFS, val[0]);
267 rtl92e_writeb(dev, SIFS+1, val[0]);
268 break;
269
270 case HW_VAR_RF_TIMING:
271 {
272 u8 Rf_Timing = *val;
273
274 rtl92e_writeb(dev, rFPGA0_RFTiming1, Rf_Timing);
275 break;
276 }
277
278 default:
279 break;
280 }
281
282 }
283
_rtl92e_read_eeprom_info(struct net_device * dev)284 static void _rtl92e_read_eeprom_info(struct net_device *dev)
285 {
286 struct r8192_priv *priv = rtllib_priv(dev);
287 const u8 bMac_Tmp_Addr[ETH_ALEN] = {0x00, 0xe0, 0x4c, 0x00, 0x00, 0x01};
288 u8 tempval;
289 u8 ICVer8192, ICVer8256;
290 u16 i, usValue, IC_Version;
291 u16 EEPROMId;
292
293 EEPROMId = rtl92e_eeprom_read(dev, 0);
294 if (EEPROMId != RTL8190_EEPROM_ID) {
295 netdev_err(dev, "%s(): Invalid EEPROM ID: %x\n", __func__,
296 EEPROMId);
297 priv->AutoloadFailFlag = true;
298 } else {
299 priv->AutoloadFailFlag = false;
300 }
301
302 if (!priv->AutoloadFailFlag) {
303 priv->eeprom_vid = rtl92e_eeprom_read(dev, EEPROM_VID >> 1);
304 priv->eeprom_did = rtl92e_eeprom_read(dev, EEPROM_DID >> 1);
305
306 usValue = rtl92e_eeprom_read(dev,
307 (EEPROM_Customer_ID >> 1)) >> 8;
308 priv->eeprom_CustomerID = usValue & 0xff;
309 usValue = rtl92e_eeprom_read(dev,
310 EEPROM_ICVersion_ChannelPlan>>1);
311 priv->eeprom_ChannelPlan = usValue&0xff;
312 IC_Version = (usValue & 0xff00)>>8;
313
314 ICVer8192 = IC_Version & 0xf;
315 ICVer8256 = (IC_Version & 0xf0)>>4;
316 if (ICVer8192 == 0x2) {
317 if (ICVer8256 == 0x5)
318 priv->card_8192_version = VERSION_8190_BE;
319 }
320 switch (priv->card_8192_version) {
321 case VERSION_8190_BD:
322 case VERSION_8190_BE:
323 break;
324 default:
325 priv->card_8192_version = VERSION_8190_BD;
326 break;
327 }
328 } else {
329 priv->card_8192_version = VERSION_8190_BD;
330 priv->eeprom_vid = 0;
331 priv->eeprom_did = 0;
332 priv->eeprom_CustomerID = 0;
333 priv->eeprom_ChannelPlan = 0;
334 }
335
336 if (!priv->AutoloadFailFlag) {
337 u8 addr[ETH_ALEN];
338
339 for (i = 0; i < 6; i += 2) {
340 usValue = rtl92e_eeprom_read(dev,
341 (EEPROM_NODE_ADDRESS_BYTE_0 + i) >> 1);
342 *(u16 *)(&addr[i]) = usValue;
343 }
344 eth_hw_addr_set(dev, addr);
345 } else {
346 eth_hw_addr_set(dev, bMac_Tmp_Addr);
347 }
348
349 if (priv->card_8192_version > VERSION_8190_BD)
350 priv->bTXPowerDataReadFromEEPORM = true;
351 else
352 priv->bTXPowerDataReadFromEEPORM = false;
353
354 priv->rf_type = RTL819X_DEFAULT_RF_TYPE;
355
356 if (priv->card_8192_version > VERSION_8190_BD) {
357 if (!priv->AutoloadFailFlag) {
358 tempval = (rtl92e_eeprom_read(dev,
359 (EEPROM_RFInd_PowerDiff >> 1))) & 0xff;
360 priv->EEPROMLegacyHTTxPowerDiff = tempval & 0xf;
361
362 if (tempval&0x80)
363 priv->rf_type = RF_1T2R;
364 else
365 priv->rf_type = RF_2T4R;
366 } else {
367 priv->EEPROMLegacyHTTxPowerDiff = 0x04;
368 }
369
370 if (!priv->AutoloadFailFlag)
371 priv->EEPROMThermalMeter = ((rtl92e_eeprom_read(dev,
372 (EEPROM_ThermalMeter>>1))) &
373 0xff00) >> 8;
374 else
375 priv->EEPROMThermalMeter = EEPROM_Default_ThermalMeter;
376 priv->TSSI_13dBm = priv->EEPROMThermalMeter * 100;
377
378 if (priv->epromtype == EEPROM_93C46) {
379 if (!priv->AutoloadFailFlag) {
380 usValue = rtl92e_eeprom_read(dev,
381 EEPROM_TxPwDiff_CrystalCap >> 1);
382 priv->EEPROMAntPwDiff = usValue & 0x0fff;
383 priv->EEPROMCrystalCap = (usValue & 0xf000)
384 >> 12;
385 } else {
386 priv->EEPROMAntPwDiff =
387 EEPROM_Default_AntTxPowerDiff;
388 priv->EEPROMCrystalCap =
389 EEPROM_Default_TxPwDiff_CrystalCap;
390 }
391
392 for (i = 0; i < 14; i += 2) {
393 if (!priv->AutoloadFailFlag)
394 usValue = rtl92e_eeprom_read(dev,
395 (EEPROM_TxPwIndex_CCK + i) >> 1);
396 else
397 usValue = EEPROM_Default_TxPower;
398 *((u16 *)(&priv->EEPROMTxPowerLevelCCK[i])) =
399 usValue;
400 }
401 for (i = 0; i < 14; i += 2) {
402 if (!priv->AutoloadFailFlag)
403 usValue = rtl92e_eeprom_read(dev,
404 (EEPROM_TxPwIndex_OFDM_24G + i) >> 1);
405 else
406 usValue = EEPROM_Default_TxPower;
407 *((u16 *)(&priv->EEPROMTxPowerLevelOFDM24G[i]))
408 = usValue;
409 }
410 }
411 if (priv->epromtype == EEPROM_93C46) {
412 for (i = 0; i < 14; i++) {
413 priv->TxPowerLevelCCK[i] =
414 priv->EEPROMTxPowerLevelCCK[i];
415 priv->TxPowerLevelOFDM24G[i] =
416 priv->EEPROMTxPowerLevelOFDM24G[i];
417 }
418 priv->LegacyHTTxPowerDiff =
419 priv->EEPROMLegacyHTTxPowerDiff;
420 priv->AntennaTxPwDiff[0] = priv->EEPROMAntPwDiff & 0xf;
421 priv->AntennaTxPwDiff[1] = (priv->EEPROMAntPwDiff &
422 0xf0) >> 4;
423 priv->AntennaTxPwDiff[2] = (priv->EEPROMAntPwDiff &
424 0xf00) >> 8;
425 priv->CrystalCap = priv->EEPROMCrystalCap;
426 priv->ThermalMeter[0] = priv->EEPROMThermalMeter & 0xf;
427 priv->ThermalMeter[1] = (priv->EEPROMThermalMeter &
428 0xf0) >> 4;
429 } else if (priv->epromtype == EEPROM_93C56) {
430
431 for (i = 0; i < 3; i++) {
432 priv->TxPowerLevelCCK_A[i] =
433 priv->EEPROMRfACCKChnl1TxPwLevel[0];
434 priv->TxPowerLevelOFDM24G_A[i] =
435 priv->EEPROMRfAOfdmChnlTxPwLevel[0];
436 priv->TxPowerLevelCCK_C[i] =
437 priv->EEPROMRfCCCKChnl1TxPwLevel[0];
438 priv->TxPowerLevelOFDM24G_C[i] =
439 priv->EEPROMRfCOfdmChnlTxPwLevel[0];
440 }
441 for (i = 3; i < 9; i++) {
442 priv->TxPowerLevelCCK_A[i] =
443 priv->EEPROMRfACCKChnl1TxPwLevel[1];
444 priv->TxPowerLevelOFDM24G_A[i] =
445 priv->EEPROMRfAOfdmChnlTxPwLevel[1];
446 priv->TxPowerLevelCCK_C[i] =
447 priv->EEPROMRfCCCKChnl1TxPwLevel[1];
448 priv->TxPowerLevelOFDM24G_C[i] =
449 priv->EEPROMRfCOfdmChnlTxPwLevel[1];
450 }
451 for (i = 9; i < 14; i++) {
452 priv->TxPowerLevelCCK_A[i] =
453 priv->EEPROMRfACCKChnl1TxPwLevel[2];
454 priv->TxPowerLevelOFDM24G_A[i] =
455 priv->EEPROMRfAOfdmChnlTxPwLevel[2];
456 priv->TxPowerLevelCCK_C[i] =
457 priv->EEPROMRfCCCKChnl1TxPwLevel[2];
458 priv->TxPowerLevelOFDM24G_C[i] =
459 priv->EEPROMRfCOfdmChnlTxPwLevel[2];
460 }
461 priv->LegacyHTTxPowerDiff =
462 priv->EEPROMLegacyHTTxPowerDiff;
463 priv->AntennaTxPwDiff[0] = 0;
464 priv->AntennaTxPwDiff[1] = 0;
465 priv->AntennaTxPwDiff[2] = 0;
466 priv->CrystalCap = priv->EEPROMCrystalCap;
467 priv->ThermalMeter[0] = priv->EEPROMThermalMeter & 0xf;
468 priv->ThermalMeter[1] = (priv->EEPROMThermalMeter &
469 0xf0) >> 4;
470 }
471 }
472
473 rtl92e_init_adaptive_rate(dev);
474
475 priv->rf_chip = RF_8256;
476
477 if (priv->RegChannelPlan == 0xf)
478 priv->ChannelPlan = priv->eeprom_ChannelPlan;
479 else
480 priv->ChannelPlan = priv->RegChannelPlan;
481
482 if (priv->eeprom_vid == 0x1186 && priv->eeprom_did == 0x3304)
483 priv->CustomerID = RT_CID_DLINK;
484
485 switch (priv->eeprom_CustomerID) {
486 case EEPROM_CID_DEFAULT:
487 priv->CustomerID = RT_CID_DEFAULT;
488 break;
489 case EEPROM_CID_CAMEO:
490 priv->CustomerID = RT_CID_819x_CAMEO;
491 break;
492 case EEPROM_CID_RUNTOP:
493 priv->CustomerID = RT_CID_819x_RUNTOP;
494 break;
495 case EEPROM_CID_NetCore:
496 priv->CustomerID = RT_CID_819x_Netcore;
497 break;
498 case EEPROM_CID_TOSHIBA:
499 priv->CustomerID = RT_CID_TOSHIBA;
500 if (priv->eeprom_ChannelPlan&0x80)
501 priv->ChannelPlan = priv->eeprom_ChannelPlan&0x7f;
502 else
503 priv->ChannelPlan = 0x0;
504 break;
505 case EEPROM_CID_Nettronix:
506 priv->ScanDelay = 100;
507 priv->CustomerID = RT_CID_Nettronix;
508 break;
509 case EEPROM_CID_Pronet:
510 priv->CustomerID = RT_CID_PRONET;
511 break;
512 case EEPROM_CID_DLINK:
513 priv->CustomerID = RT_CID_DLINK;
514 break;
515
516 case EEPROM_CID_WHQL:
517 break;
518 default:
519 break;
520 }
521
522 if (priv->ChannelPlan > CHANNEL_PLAN_LEN - 1)
523 priv->ChannelPlan = 0;
524 priv->ChannelPlan = COUNTRY_CODE_WORLD_WIDE_13;
525
526 if (priv->eeprom_vid == 0x1186 && priv->eeprom_did == 0x3304)
527 priv->rtllib->bSupportRemoteWakeUp = true;
528 else
529 priv->rtllib->bSupportRemoteWakeUp = false;
530 }
531
rtl92e_get_eeprom_size(struct net_device * dev)532 void rtl92e_get_eeprom_size(struct net_device *dev)
533 {
534 u16 curCR;
535 struct r8192_priv *priv = rtllib_priv(dev);
536
537 curCR = rtl92e_readw(dev, EPROM_CMD);
538 priv->epromtype = (curCR & EPROM_CMD_9356SEL) ? EEPROM_93C56 :
539 EEPROM_93C46;
540 _rtl92e_read_eeprom_info(dev);
541 }
542
_rtl92e_hwconfig(struct net_device * dev)543 static void _rtl92e_hwconfig(struct net_device *dev)
544 {
545 u32 regRATR = 0, regRRSR = 0;
546 u8 regBwOpMode = 0, regTmp = 0;
547 struct r8192_priv *priv = rtllib_priv(dev);
548
549 switch (priv->rtllib->mode) {
550 case WIRELESS_MODE_B:
551 regBwOpMode = BW_OPMODE_20MHZ;
552 regRATR = RATE_ALL_CCK;
553 regRRSR = RATE_ALL_CCK;
554 break;
555 case WIRELESS_MODE_A:
556 regBwOpMode = BW_OPMODE_5G | BW_OPMODE_20MHZ;
557 regRATR = RATE_ALL_OFDM_AG;
558 regRRSR = RATE_ALL_OFDM_AG;
559 break;
560 case WIRELESS_MODE_G:
561 regBwOpMode = BW_OPMODE_20MHZ;
562 regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
563 regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
564 break;
565 case WIRELESS_MODE_AUTO:
566 case WIRELESS_MODE_N_24G:
567 regBwOpMode = BW_OPMODE_20MHZ;
568 regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG |
569 RATE_ALL_OFDM_1SS | RATE_ALL_OFDM_2SS;
570 regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
571 break;
572 case WIRELESS_MODE_N_5G:
573 regBwOpMode = BW_OPMODE_5G;
574 regRATR = RATE_ALL_OFDM_AG | RATE_ALL_OFDM_1SS |
575 RATE_ALL_OFDM_2SS;
576 regRRSR = RATE_ALL_OFDM_AG;
577 break;
578 default:
579 regBwOpMode = BW_OPMODE_20MHZ;
580 regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
581 regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
582 break;
583 }
584
585 rtl92e_writeb(dev, BW_OPMODE, regBwOpMode);
586 {
587 u32 ratr_value;
588
589 ratr_value = regRATR;
590 if (priv->rf_type == RF_1T2R)
591 ratr_value &= ~(RATE_ALL_OFDM_2SS);
592 rtl92e_writel(dev, RATR0, ratr_value);
593 rtl92e_writeb(dev, UFWP, 1);
594 }
595 regTmp = rtl92e_readb(dev, 0x313);
596 regRRSR = ((regTmp) << 24) | (regRRSR & 0x00ffffff);
597 rtl92e_writel(dev, RRSR, regRRSR);
598
599 rtl92e_writew(dev, RETRY_LIMIT,
600 priv->ShortRetryLimit << RETRY_LIMIT_SHORT_SHIFT |
601 priv->LongRetryLimit << RETRY_LIMIT_LONG_SHIFT);
602 }
603
rtl92e_start_adapter(struct net_device * dev)604 bool rtl92e_start_adapter(struct net_device *dev)
605 {
606 struct r8192_priv *priv = rtllib_priv(dev);
607 u32 ulRegRead;
608 bool rtStatus = true;
609 u8 tmpvalue;
610 u8 ICVersion, SwitchingRegulatorOutput;
611 bool bfirmwareok = true;
612 u32 tmpRegA, TempCCk;
613 int i = 0;
614 u32 retry_times = 0;
615
616 priv->being_init_adapter = true;
617
618 start:
619 rtl92e_reset_desc_ring(dev);
620 priv->Rf_Mode = RF_OP_By_SW_3wire;
621 if (priv->ResetProgress == RESET_TYPE_NORESET) {
622 rtl92e_writeb(dev, ANAPAR, 0x37);
623 mdelay(500);
624 }
625 priv->pFirmware->status = FW_STATUS_0_INIT;
626
627 if (priv->RegRfOff)
628 priv->rtllib->rf_power_state = rf_off;
629
630 ulRegRead = rtl92e_readl(dev, CPU_GEN);
631 if (priv->pFirmware->status == FW_STATUS_0_INIT)
632 ulRegRead |= CPU_GEN_SYSTEM_RESET;
633 else if (priv->pFirmware->status == FW_STATUS_5_READY)
634 ulRegRead |= CPU_GEN_FIRMWARE_RESET;
635 else
636 netdev_err(dev, "%s(): undefined firmware state: %d.\n",
637 __func__, priv->pFirmware->status);
638
639 rtl92e_writel(dev, CPU_GEN, ulRegRead);
640
641 ICVersion = rtl92e_readb(dev, IC_VERRSION);
642 if (ICVersion >= 0x4) {
643 SwitchingRegulatorOutput = rtl92e_readb(dev, SWREGULATOR);
644 if (SwitchingRegulatorOutput != 0xb8) {
645 rtl92e_writeb(dev, SWREGULATOR, 0xa8);
646 mdelay(1);
647 rtl92e_writeb(dev, SWREGULATOR, 0xb8);
648 }
649 }
650 rtStatus = rtl92e_config_bb(dev);
651 if (!rtStatus) {
652 netdev_warn(dev, "%s(): Failed to configure BB\n", __func__);
653 return rtStatus;
654 }
655
656 priv->LoopbackMode = RTL819X_NO_LOOPBACK;
657 if (priv->ResetProgress == RESET_TYPE_NORESET) {
658 ulRegRead = rtl92e_readl(dev, CPU_GEN);
659 if (priv->LoopbackMode == RTL819X_NO_LOOPBACK)
660 ulRegRead = (ulRegRead & CPU_GEN_NO_LOOPBACK_MSK) |
661 CPU_GEN_NO_LOOPBACK_SET;
662 else if (priv->LoopbackMode == RTL819X_MAC_LOOPBACK)
663 ulRegRead |= CPU_CCK_LOOPBACK;
664 else
665 netdev_err(dev, "%s: Invalid loopback mode setting.\n",
666 __func__);
667
668 rtl92e_writel(dev, CPU_GEN, ulRegRead);
669
670 udelay(500);
671 }
672 _rtl92e_hwconfig(dev);
673 rtl92e_writeb(dev, CMDR, CR_RE | CR_TE);
674
675 rtl92e_writeb(dev, PCIF, ((MXDMA2_NoLimit<<MXDMA2_RX_SHIFT) |
676 (MXDMA2_NoLimit<<MXDMA2_TX_SHIFT)));
677 rtl92e_writel(dev, MAC0, ((u32 *)dev->dev_addr)[0]);
678 rtl92e_writew(dev, MAC4, ((u16 *)(dev->dev_addr + 4))[0]);
679 rtl92e_writel(dev, RCR, priv->ReceiveConfig);
680
681 rtl92e_writel(dev, RQPN1, NUM_OF_PAGE_IN_FW_QUEUE_BK <<
682 RSVD_FW_QUEUE_PAGE_BK_SHIFT |
683 NUM_OF_PAGE_IN_FW_QUEUE_BE <<
684 RSVD_FW_QUEUE_PAGE_BE_SHIFT |
685 NUM_OF_PAGE_IN_FW_QUEUE_VI <<
686 RSVD_FW_QUEUE_PAGE_VI_SHIFT |
687 NUM_OF_PAGE_IN_FW_QUEUE_VO <<
688 RSVD_FW_QUEUE_PAGE_VO_SHIFT);
689 rtl92e_writel(dev, RQPN2, NUM_OF_PAGE_IN_FW_QUEUE_MGNT <<
690 RSVD_FW_QUEUE_PAGE_MGNT_SHIFT);
691 rtl92e_writel(dev, RQPN3, APPLIED_RESERVED_QUEUE_IN_FW |
692 NUM_OF_PAGE_IN_FW_QUEUE_BCN <<
693 RSVD_FW_QUEUE_PAGE_BCN_SHIFT|
694 NUM_OF_PAGE_IN_FW_QUEUE_PUB <<
695 RSVD_FW_QUEUE_PAGE_PUB_SHIFT);
696
697 rtl92e_tx_enable(dev);
698 rtl92e_rx_enable(dev);
699 ulRegRead = (0xFFF00000 & rtl92e_readl(dev, RRSR)) |
700 RATE_ALL_OFDM_AG | RATE_ALL_CCK;
701 rtl92e_writel(dev, RRSR, ulRegRead);
702 rtl92e_writel(dev, RATR0+4*7, (RATE_ALL_OFDM_AG | RATE_ALL_CCK));
703
704 rtl92e_writeb(dev, ACK_TIMEOUT, 0x30);
705
706 if (priv->ResetProgress == RESET_TYPE_NORESET)
707 rtl92e_set_wireless_mode(dev, priv->rtllib->mode);
708 rtl92e_cam_reset(dev);
709 {
710 u8 SECR_value = 0x0;
711
712 SECR_value |= SCR_TxEncEnable;
713 SECR_value |= SCR_RxDecEnable;
714 SECR_value |= SCR_NoSKMC;
715 rtl92e_writeb(dev, SECR, SECR_value);
716 }
717 rtl92e_writew(dev, ATIMWND, 2);
718 rtl92e_writew(dev, BCN_INTERVAL, 100);
719
720 for (i = 0; i < QOS_QUEUE_NUM; i++)
721 rtl92e_writel(dev, WDCAPARA_ADD[i], 0x005e4332);
722
723 rtl92e_writeb(dev, 0xbe, 0xc0);
724
725 rtl92e_config_mac(dev);
726
727 if (priv->card_8192_version > VERSION_8190_BD) {
728 rtl92e_get_tx_power(dev);
729 rtl92e_set_tx_power(dev, priv->chan);
730 }
731
732 tmpvalue = rtl92e_readb(dev, IC_VERRSION);
733 priv->IC_Cut = tmpvalue;
734
735 bfirmwareok = rtl92e_init_fw(dev);
736 if (!bfirmwareok) {
737 if (retry_times < 10) {
738 retry_times++;
739 goto start;
740 } else {
741 rtStatus = false;
742 goto end;
743 }
744 }
745
746 if (priv->ResetProgress == RESET_TYPE_NORESET) {
747 rtStatus = rtl92e_config_phy(dev);
748 if (!rtStatus) {
749 netdev_info(dev, "RF Config failed\n");
750 return rtStatus;
751 }
752 }
753
754 rtl92e_set_bb_reg(dev, rFPGA0_RFMOD, bCCKEn, 0x1);
755 rtl92e_set_bb_reg(dev, rFPGA0_RFMOD, bOFDMEn, 0x1);
756
757 rtl92e_writeb(dev, 0x87, 0x0);
758
759 if (priv->RegRfOff) {
760 rtl92e_set_rf_state(dev, rf_off, RF_CHANGE_BY_SW);
761 } else if (priv->rtllib->rf_off_reason > RF_CHANGE_BY_PS) {
762 rtl92e_set_rf_state(dev, rf_off, priv->rtllib->rf_off_reason);
763 } else if (priv->rtllib->rf_off_reason >= RF_CHANGE_BY_IPS) {
764 rtl92e_set_rf_state(dev, rf_off, priv->rtllib->rf_off_reason);
765 } else {
766 priv->rtllib->rf_power_state = rf_on;
767 priv->rtllib->rf_off_reason = 0;
768 }
769
770 if (priv->rtllib->FwRWRF)
771 priv->Rf_Mode = RF_OP_By_FW;
772 else
773 priv->Rf_Mode = RF_OP_By_SW_3wire;
774
775 if (priv->ResetProgress == RESET_TYPE_NORESET) {
776 rtl92e_dm_init_txpower_tracking(dev);
777
778 if (priv->IC_Cut >= IC_VersionCut_D) {
779 tmpRegA = rtl92e_get_bb_reg(dev, rOFDM0_XATxIQImbalance,
780 bMaskDWord);
781 rtl92e_get_bb_reg(dev, rOFDM0_XCTxIQImbalance, bMaskDWord);
782
783 for (i = 0; i < TxBBGainTableLength; i++) {
784 if (tmpRegA == dm_tx_bb_gain[i]) {
785 priv->rfa_txpowertrackingindex = i;
786 priv->rfa_txpowertrackingindex_real = i;
787 priv->rfa_txpowertracking_default =
788 priv->rfa_txpowertrackingindex;
789 break;
790 }
791 }
792
793 TempCCk = rtl92e_get_bb_reg(dev, rCCK0_TxFilter1,
794 bMaskByte2);
795
796 for (i = 0; i < CCKTxBBGainTableLength; i++) {
797 if (TempCCk == dm_cck_tx_bb_gain[i][0]) {
798 priv->CCKPresentAttentuation_20Mdefault = i;
799 break;
800 }
801 }
802 priv->CCKPresentAttentuation_40Mdefault = 0;
803 priv->CCKPresentAttentuation_difference = 0;
804 priv->CCKPresentAttentuation =
805 priv->CCKPresentAttentuation_20Mdefault;
806 priv->btxpower_tracking = false;
807 }
808 }
809 rtl92e_irq_enable(dev);
810 end:
811 priv->being_init_adapter = false;
812 return rtStatus;
813 }
814
_rtl92e_net_update(struct net_device * dev)815 static void _rtl92e_net_update(struct net_device *dev)
816 {
817
818 struct r8192_priv *priv = rtllib_priv(dev);
819 struct rtllib_network *net;
820 u16 BcnTimeCfg = 0, BcnCW = 6, BcnIFS = 0xf;
821 u16 rate_config = 0;
822
823 net = &priv->rtllib->current_network;
824 rtl92e_config_rate(dev, &rate_config);
825 priv->dot11_current_preamble_mode = PREAMBLE_AUTO;
826 priv->basic_rate = rate_config &= 0x15f;
827 rtl92e_writew(dev, BSSIDR, *(u16 *)net->bssid);
828 rtl92e_writel(dev, BSSIDR + 2, *(u32 *)(net->bssid + 2));
829
830 if (priv->rtllib->iw_mode == IW_MODE_ADHOC) {
831 rtl92e_writew(dev, ATIMWND, 2);
832 rtl92e_writew(dev, BCN_DMATIME, 256);
833 rtl92e_writew(dev, BCN_INTERVAL, net->beacon_interval);
834 rtl92e_writew(dev, BCN_DRV_EARLY_INT, 10);
835 rtl92e_writeb(dev, BCN_ERR_THRESH, 100);
836
837 BcnTimeCfg |= (BcnCW<<BCN_TCFG_CW_SHIFT);
838 BcnTimeCfg |= BcnIFS<<BCN_TCFG_IFS;
839
840 rtl92e_writew(dev, BCN_TCFG, BcnTimeCfg);
841 }
842 }
843
rtl92e_link_change(struct net_device * dev)844 void rtl92e_link_change(struct net_device *dev)
845 {
846 struct r8192_priv *priv = rtllib_priv(dev);
847 struct rtllib_device *ieee = priv->rtllib;
848
849 if (!priv->up)
850 return;
851
852 if (ieee->state == RTLLIB_LINKED) {
853 _rtl92e_net_update(dev);
854 priv->ops->update_ratr_table(dev);
855 if ((ieee->pairwise_key_type == KEY_TYPE_WEP40) ||
856 (ieee->pairwise_key_type == KEY_TYPE_WEP104))
857 rtl92e_enable_hw_security_config(dev);
858 } else {
859 rtl92e_writeb(dev, 0x173, 0);
860 }
861 _rtl92e_update_msr(dev);
862
863 if (ieee->iw_mode == IW_MODE_INFRA || ieee->iw_mode == IW_MODE_ADHOC) {
864 u32 reg;
865
866 reg = rtl92e_readl(dev, RCR);
867 if (priv->rtllib->state == RTLLIB_LINKED) {
868 if (ieee->IntelPromiscuousModeInfo.bPromiscuousOn)
869 ;
870 else
871 priv->ReceiveConfig = reg |= RCR_CBSSID;
872 } else
873 priv->ReceiveConfig = reg &= ~RCR_CBSSID;
874
875 rtl92e_writel(dev, RCR, reg);
876 }
877 }
878
rtl92e_set_monitor_mode(struct net_device * dev,bool bAllowAllDA,bool WriteIntoReg)879 void rtl92e_set_monitor_mode(struct net_device *dev, bool bAllowAllDA,
880 bool WriteIntoReg)
881 {
882 struct r8192_priv *priv = rtllib_priv(dev);
883
884 if (bAllowAllDA)
885 priv->ReceiveConfig |= RCR_AAP;
886 else
887 priv->ReceiveConfig &= ~RCR_AAP;
888
889 if (WriteIntoReg)
890 rtl92e_writel(dev, RCR, priv->ReceiveConfig);
891 }
892
_rtl92e_rate_mgn_to_hw(u8 rate)893 static u8 _rtl92e_rate_mgn_to_hw(u8 rate)
894 {
895 u8 ret = DESC90_RATE1M;
896
897 switch (rate) {
898 case MGN_1M:
899 ret = DESC90_RATE1M;
900 break;
901 case MGN_2M:
902 ret = DESC90_RATE2M;
903 break;
904 case MGN_5_5M:
905 ret = DESC90_RATE5_5M;
906 break;
907 case MGN_11M:
908 ret = DESC90_RATE11M;
909 break;
910 case MGN_6M:
911 ret = DESC90_RATE6M;
912 break;
913 case MGN_9M:
914 ret = DESC90_RATE9M;
915 break;
916 case MGN_12M:
917 ret = DESC90_RATE12M;
918 break;
919 case MGN_18M:
920 ret = DESC90_RATE18M;
921 break;
922 case MGN_24M:
923 ret = DESC90_RATE24M;
924 break;
925 case MGN_36M:
926 ret = DESC90_RATE36M;
927 break;
928 case MGN_48M:
929 ret = DESC90_RATE48M;
930 break;
931 case MGN_54M:
932 ret = DESC90_RATE54M;
933 break;
934 case MGN_MCS0:
935 ret = DESC90_RATEMCS0;
936 break;
937 case MGN_MCS1:
938 ret = DESC90_RATEMCS1;
939 break;
940 case MGN_MCS2:
941 ret = DESC90_RATEMCS2;
942 break;
943 case MGN_MCS3:
944 ret = DESC90_RATEMCS3;
945 break;
946 case MGN_MCS4:
947 ret = DESC90_RATEMCS4;
948 break;
949 case MGN_MCS5:
950 ret = DESC90_RATEMCS5;
951 break;
952 case MGN_MCS6:
953 ret = DESC90_RATEMCS6;
954 break;
955 case MGN_MCS7:
956 ret = DESC90_RATEMCS7;
957 break;
958 case MGN_MCS8:
959 ret = DESC90_RATEMCS8;
960 break;
961 case MGN_MCS9:
962 ret = DESC90_RATEMCS9;
963 break;
964 case MGN_MCS10:
965 ret = DESC90_RATEMCS10;
966 break;
967 case MGN_MCS11:
968 ret = DESC90_RATEMCS11;
969 break;
970 case MGN_MCS12:
971 ret = DESC90_RATEMCS12;
972 break;
973 case MGN_MCS13:
974 ret = DESC90_RATEMCS13;
975 break;
976 case MGN_MCS14:
977 ret = DESC90_RATEMCS14;
978 break;
979 case MGN_MCS15:
980 ret = DESC90_RATEMCS15;
981 break;
982 case (0x80|0x20):
983 ret = DESC90_RATEMCS32;
984 break;
985 default:
986 break;
987 }
988 return ret;
989 }
990
_rtl92e_hw_queue_to_fw_queue(struct net_device * dev,u8 QueueID,u8 priority)991 static u8 _rtl92e_hw_queue_to_fw_queue(struct net_device *dev, u8 QueueID,
992 u8 priority)
993 {
994 u8 QueueSelect = 0x0;
995
996 switch (QueueID) {
997 case BE_QUEUE:
998 QueueSelect = QSLT_BE;
999 break;
1000
1001 case BK_QUEUE:
1002 QueueSelect = QSLT_BK;
1003 break;
1004
1005 case VO_QUEUE:
1006 QueueSelect = QSLT_VO;
1007 break;
1008
1009 case VI_QUEUE:
1010 QueueSelect = QSLT_VI;
1011 break;
1012 case MGNT_QUEUE:
1013 QueueSelect = QSLT_MGNT;
1014 break;
1015 case BEACON_QUEUE:
1016 QueueSelect = QSLT_BEACON;
1017 break;
1018 case TXCMD_QUEUE:
1019 QueueSelect = QSLT_CMD;
1020 break;
1021 case HIGH_QUEUE:
1022 QueueSelect = QSLT_HIGH;
1023 break;
1024 default:
1025 netdev_warn(dev, "%s(): Impossible Queue Selection: %d\n",
1026 __func__, QueueID);
1027 break;
1028 }
1029 return QueueSelect;
1030 }
1031
_rtl92e_query_is_short(u8 TxHT,u8 TxRate,struct cb_desc * tcb_desc)1032 static u8 _rtl92e_query_is_short(u8 TxHT, u8 TxRate, struct cb_desc *tcb_desc)
1033 {
1034 u8 tmp_Short;
1035
1036 tmp_Short = (TxHT == 1) ? ((tcb_desc->bUseShortGI) ? 1 : 0) :
1037 ((tcb_desc->bUseShortPreamble) ? 1 : 0);
1038 if (TxHT == 1 && TxRate != DESC90_RATEMCS15)
1039 tmp_Short = 0;
1040
1041 return tmp_Short;
1042 }
1043
rtl92e_fill_tx_desc(struct net_device * dev,struct tx_desc * pdesc,struct cb_desc * cb_desc,struct sk_buff * skb)1044 void rtl92e_fill_tx_desc(struct net_device *dev, struct tx_desc *pdesc,
1045 struct cb_desc *cb_desc, struct sk_buff *skb)
1046 {
1047 struct r8192_priv *priv = rtllib_priv(dev);
1048 dma_addr_t mapping;
1049 struct tx_fwinfo_8190pci *pTxFwInfo;
1050
1051 pTxFwInfo = (struct tx_fwinfo_8190pci *)skb->data;
1052 memset(pTxFwInfo, 0, sizeof(struct tx_fwinfo_8190pci));
1053 pTxFwInfo->TxHT = (cb_desc->data_rate & 0x80) ? 1 : 0;
1054 pTxFwInfo->TxRate = _rtl92e_rate_mgn_to_hw(cb_desc->data_rate);
1055 pTxFwInfo->EnableCPUDur = cb_desc->bTxEnableFwCalcDur;
1056 pTxFwInfo->Short = _rtl92e_query_is_short(pTxFwInfo->TxHT,
1057 pTxFwInfo->TxRate, cb_desc);
1058
1059 if (cb_desc->bAMPDUEnable) {
1060 pTxFwInfo->AllowAggregation = 1;
1061 pTxFwInfo->RxMF = cb_desc->ampdu_factor;
1062 pTxFwInfo->RxAMD = cb_desc->ampdu_density;
1063 } else {
1064 pTxFwInfo->AllowAggregation = 0;
1065 pTxFwInfo->RxMF = 0;
1066 pTxFwInfo->RxAMD = 0;
1067 }
1068
1069 pTxFwInfo->RtsEnable = (cb_desc->bRTSEnable) ? 1 : 0;
1070 pTxFwInfo->CtsEnable = (cb_desc->bCTSEnable) ? 1 : 0;
1071 pTxFwInfo->RtsSTBC = (cb_desc->bRTSSTBC) ? 1 : 0;
1072 pTxFwInfo->RtsHT = (cb_desc->rts_rate&0x80) ? 1 : 0;
1073 pTxFwInfo->RtsRate = _rtl92e_rate_mgn_to_hw(cb_desc->rts_rate);
1074 pTxFwInfo->RtsBandwidth = 0;
1075 pTxFwInfo->RtsSubcarrier = cb_desc->RTSSC;
1076 pTxFwInfo->RtsShort = (pTxFwInfo->RtsHT == 0) ?
1077 (cb_desc->bRTSUseShortPreamble ? 1 : 0) :
1078 (cb_desc->bRTSUseShortGI ? 1 : 0);
1079 if (priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20_40) {
1080 if (cb_desc->bPacketBW) {
1081 pTxFwInfo->TxBandwidth = 1;
1082 pTxFwInfo->TxSubCarrier = 0;
1083 } else {
1084 pTxFwInfo->TxBandwidth = 0;
1085 pTxFwInfo->TxSubCarrier = priv->nCur40MhzPrimeSC;
1086 }
1087 } else {
1088 pTxFwInfo->TxBandwidth = 0;
1089 pTxFwInfo->TxSubCarrier = 0;
1090 }
1091
1092 memset((u8 *)pdesc, 0, 12);
1093
1094 mapping = dma_map_single(&priv->pdev->dev, skb->data, skb->len,
1095 DMA_TO_DEVICE);
1096 if (dma_mapping_error(&priv->pdev->dev, mapping)) {
1097 netdev_err(dev, "%s(): DMA Mapping error\n", __func__);
1098 return;
1099 }
1100
1101 pdesc->LINIP = 0;
1102 pdesc->CmdInit = 1;
1103 pdesc->Offset = sizeof(struct tx_fwinfo_8190pci) + 8;
1104 pdesc->PktSize = skb->len - sizeof(struct tx_fwinfo_8190pci);
1105
1106 pdesc->SecCAMID = 0;
1107 pdesc->RATid = cb_desc->RATRIndex;
1108
1109
1110 pdesc->NoEnc = 1;
1111 pdesc->SecType = 0x0;
1112 if (cb_desc->bHwSec) {
1113 static u8 tmp;
1114
1115 if (!tmp) {
1116 tmp = 1;
1117 }
1118 switch (priv->rtllib->pairwise_key_type) {
1119 case KEY_TYPE_WEP40:
1120 case KEY_TYPE_WEP104:
1121 pdesc->SecType = 0x1;
1122 pdesc->NoEnc = 0;
1123 break;
1124 case KEY_TYPE_TKIP:
1125 pdesc->SecType = 0x2;
1126 pdesc->NoEnc = 0;
1127 break;
1128 case KEY_TYPE_CCMP:
1129 pdesc->SecType = 0x3;
1130 pdesc->NoEnc = 0;
1131 break;
1132 case KEY_TYPE_NA:
1133 pdesc->SecType = 0x0;
1134 pdesc->NoEnc = 1;
1135 break;
1136 }
1137 }
1138
1139 pdesc->PktId = 0x0;
1140
1141 pdesc->QueueSelect = _rtl92e_hw_queue_to_fw_queue(dev,
1142 cb_desc->queue_index,
1143 cb_desc->priority);
1144 pdesc->TxFWInfoSize = sizeof(struct tx_fwinfo_8190pci);
1145
1146 pdesc->DISFB = cb_desc->bTxDisableRateFallBack;
1147 pdesc->USERATE = cb_desc->bTxUseDriverAssingedRate;
1148
1149 pdesc->FirstSeg = 1;
1150 pdesc->LastSeg = 1;
1151 pdesc->TxBufferSize = skb->len;
1152
1153 pdesc->TxBuffAddr = mapping;
1154 }
1155
rtl92e_fill_tx_cmd_desc(struct net_device * dev,struct tx_desc_cmd * entry,struct cb_desc * cb_desc,struct sk_buff * skb)1156 void rtl92e_fill_tx_cmd_desc(struct net_device *dev, struct tx_desc_cmd *entry,
1157 struct cb_desc *cb_desc, struct sk_buff *skb)
1158 {
1159 struct r8192_priv *priv = rtllib_priv(dev);
1160 dma_addr_t mapping = dma_map_single(&priv->pdev->dev, skb->data,
1161 skb->len, DMA_TO_DEVICE);
1162
1163 if (dma_mapping_error(&priv->pdev->dev, mapping))
1164 netdev_err(dev, "%s(): DMA Mapping error\n", __func__);
1165 memset(entry, 0, 12);
1166 entry->LINIP = cb_desc->bLastIniPkt;
1167 entry->FirstSeg = 1;
1168 entry->LastSeg = 1;
1169 if (cb_desc->bCmdOrInit == DESC_PACKET_TYPE_INIT) {
1170 entry->CmdInit = DESC_PACKET_TYPE_INIT;
1171 } else {
1172 struct tx_desc *entry_tmp = (struct tx_desc *)entry;
1173
1174 entry_tmp->CmdInit = DESC_PACKET_TYPE_NORMAL;
1175 entry_tmp->Offset = sizeof(struct tx_fwinfo_8190pci) + 8;
1176 entry_tmp->PktSize = cb_desc->pkt_size + entry_tmp->Offset;
1177 entry_tmp->QueueSelect = QSLT_CMD;
1178 entry_tmp->TxFWInfoSize = 0x08;
1179 entry_tmp->RATid = DESC_PACKET_TYPE_INIT;
1180 }
1181 entry->TxBufferSize = skb->len;
1182 entry->TxBuffAddr = mapping;
1183 entry->OWN = 1;
1184 }
1185
_rtl92e_rate_hw_to_mgn(bool bIsHT,u8 rate)1186 static u8 _rtl92e_rate_hw_to_mgn(bool bIsHT, u8 rate)
1187 {
1188 u8 ret_rate = 0x02;
1189
1190 if (!bIsHT) {
1191 switch (rate) {
1192 case DESC90_RATE1M:
1193 ret_rate = MGN_1M;
1194 break;
1195 case DESC90_RATE2M:
1196 ret_rate = MGN_2M;
1197 break;
1198 case DESC90_RATE5_5M:
1199 ret_rate = MGN_5_5M;
1200 break;
1201 case DESC90_RATE11M:
1202 ret_rate = MGN_11M;
1203 break;
1204 case DESC90_RATE6M:
1205 ret_rate = MGN_6M;
1206 break;
1207 case DESC90_RATE9M:
1208 ret_rate = MGN_9M;
1209 break;
1210 case DESC90_RATE12M:
1211 ret_rate = MGN_12M;
1212 break;
1213 case DESC90_RATE18M:
1214 ret_rate = MGN_18M;
1215 break;
1216 case DESC90_RATE24M:
1217 ret_rate = MGN_24M;
1218 break;
1219 case DESC90_RATE36M:
1220 ret_rate = MGN_36M;
1221 break;
1222 case DESC90_RATE48M:
1223 ret_rate = MGN_48M;
1224 break;
1225 case DESC90_RATE54M:
1226 ret_rate = MGN_54M;
1227 break;
1228 }
1229
1230 } else {
1231 switch (rate) {
1232 case DESC90_RATEMCS0:
1233 ret_rate = MGN_MCS0;
1234 break;
1235 case DESC90_RATEMCS1:
1236 ret_rate = MGN_MCS1;
1237 break;
1238 case DESC90_RATEMCS2:
1239 ret_rate = MGN_MCS2;
1240 break;
1241 case DESC90_RATEMCS3:
1242 ret_rate = MGN_MCS3;
1243 break;
1244 case DESC90_RATEMCS4:
1245 ret_rate = MGN_MCS4;
1246 break;
1247 case DESC90_RATEMCS5:
1248 ret_rate = MGN_MCS5;
1249 break;
1250 case DESC90_RATEMCS6:
1251 ret_rate = MGN_MCS6;
1252 break;
1253 case DESC90_RATEMCS7:
1254 ret_rate = MGN_MCS7;
1255 break;
1256 case DESC90_RATEMCS8:
1257 ret_rate = MGN_MCS8;
1258 break;
1259 case DESC90_RATEMCS9:
1260 ret_rate = MGN_MCS9;
1261 break;
1262 case DESC90_RATEMCS10:
1263 ret_rate = MGN_MCS10;
1264 break;
1265 case DESC90_RATEMCS11:
1266 ret_rate = MGN_MCS11;
1267 break;
1268 case DESC90_RATEMCS12:
1269 ret_rate = MGN_MCS12;
1270 break;
1271 case DESC90_RATEMCS13:
1272 ret_rate = MGN_MCS13;
1273 break;
1274 case DESC90_RATEMCS14:
1275 ret_rate = MGN_MCS14;
1276 break;
1277 case DESC90_RATEMCS15:
1278 ret_rate = MGN_MCS15;
1279 break;
1280 case DESC90_RATEMCS32:
1281 ret_rate = 0x80 | 0x20;
1282 break;
1283 }
1284 }
1285
1286 return ret_rate;
1287 }
1288
_rtl92e_signal_scale_mapping(struct r8192_priv * priv,long currsig)1289 static long _rtl92e_signal_scale_mapping(struct r8192_priv *priv, long currsig)
1290 {
1291 long retsig;
1292
1293 if (currsig >= 61 && currsig <= 100)
1294 retsig = 90 + ((currsig - 60) / 4);
1295 else if (currsig >= 41 && currsig <= 60)
1296 retsig = 78 + ((currsig - 40) / 2);
1297 else if (currsig >= 31 && currsig <= 40)
1298 retsig = 66 + (currsig - 30);
1299 else if (currsig >= 21 && currsig <= 30)
1300 retsig = 54 + (currsig - 20);
1301 else if (currsig >= 5 && currsig <= 20)
1302 retsig = 42 + (((currsig - 5) * 2) / 3);
1303 else if (currsig == 4)
1304 retsig = 36;
1305 else if (currsig == 3)
1306 retsig = 27;
1307 else if (currsig == 2)
1308 retsig = 18;
1309 else if (currsig == 1)
1310 retsig = 9;
1311 else
1312 retsig = currsig;
1313
1314 return retsig;
1315 }
1316
1317
1318 #define rx_hal_is_cck_rate(_pdrvinfo)\
1319 ((_pdrvinfo->RxRate == DESC90_RATE1M ||\
1320 _pdrvinfo->RxRate == DESC90_RATE2M ||\
1321 _pdrvinfo->RxRate == DESC90_RATE5_5M ||\
1322 _pdrvinfo->RxRate == DESC90_RATE11M) &&\
1323 !_pdrvinfo->RxHT)
1324
_rtl92e_query_rxphystatus(struct r8192_priv * priv,struct rtllib_rx_stats * pstats,struct rx_desc * pdesc,struct rx_fwinfo * pdrvinfo,struct rtllib_rx_stats * precord_stats,bool bpacket_match_bssid,bool bpacket_toself,bool bPacketBeacon,bool bToSelfBA)1325 static void _rtl92e_query_rxphystatus(
1326 struct r8192_priv *priv,
1327 struct rtllib_rx_stats *pstats,
1328 struct rx_desc *pdesc,
1329 struct rx_fwinfo *pdrvinfo,
1330 struct rtllib_rx_stats *precord_stats,
1331 bool bpacket_match_bssid,
1332 bool bpacket_toself,
1333 bool bPacketBeacon,
1334 bool bToSelfBA
1335 )
1336 {
1337 struct phy_sts_ofdm_819xpci *pofdm_buf;
1338 struct phy_sts_cck_819xpci *pcck_buf;
1339 struct phy_ofdm_rx_status_rxsc_sgien_exintfflag *prxsc;
1340 u8 *prxpkt;
1341 u8 i, max_spatial_stream, tmp_rxsnr, tmp_rxevm, rxsc_sgien_exflg;
1342 s8 rx_pwr[4], rx_pwr_all = 0;
1343 s8 rx_snrX, rx_evmX;
1344 u8 evm, pwdb_all;
1345 u32 RSSI, total_rssi = 0;
1346 u8 is_cck_rate = 0;
1347 u8 rf_rx_num = 0;
1348 static u8 check_reg824;
1349 static u32 reg824_bit9;
1350
1351 priv->stats.numqry_phystatus++;
1352
1353 is_cck_rate = rx_hal_is_cck_rate(pdrvinfo);
1354 memset(precord_stats, 0, sizeof(struct rtllib_rx_stats));
1355 pstats->bPacketMatchBSSID = precord_stats->bPacketMatchBSSID =
1356 bpacket_match_bssid;
1357 pstats->bPacketToSelf = precord_stats->bPacketToSelf = bpacket_toself;
1358 pstats->bIsCCK = precord_stats->bIsCCK = is_cck_rate;
1359 pstats->bPacketBeacon = precord_stats->bPacketBeacon = bPacketBeacon;
1360 pstats->bToSelfBA = precord_stats->bToSelfBA = bToSelfBA;
1361 if (check_reg824 == 0) {
1362 reg824_bit9 = rtl92e_get_bb_reg(priv->rtllib->dev,
1363 rFPGA0_XA_HSSIParameter2,
1364 0x200);
1365 check_reg824 = 1;
1366 }
1367
1368
1369 prxpkt = (u8 *)pdrvinfo;
1370
1371 prxpkt += sizeof(struct rx_fwinfo);
1372
1373 pcck_buf = (struct phy_sts_cck_819xpci *)prxpkt;
1374 pofdm_buf = (struct phy_sts_ofdm_819xpci *)prxpkt;
1375
1376 pstats->RxMIMOSignalQuality[0] = -1;
1377 pstats->RxMIMOSignalQuality[1] = -1;
1378 precord_stats->RxMIMOSignalQuality[0] = -1;
1379 precord_stats->RxMIMOSignalQuality[1] = -1;
1380
1381 if (is_cck_rate) {
1382 u8 report;
1383
1384 priv->stats.numqry_phystatusCCK++;
1385 if (!reg824_bit9) {
1386 report = pcck_buf->cck_agc_rpt & 0xc0;
1387 report >>= 6;
1388 switch (report) {
1389 case 0x3:
1390 rx_pwr_all = -35 - (pcck_buf->cck_agc_rpt &
1391 0x3e);
1392 break;
1393 case 0x2:
1394 rx_pwr_all = -23 - (pcck_buf->cck_agc_rpt &
1395 0x3e);
1396 break;
1397 case 0x1:
1398 rx_pwr_all = -11 - (pcck_buf->cck_agc_rpt &
1399 0x3e);
1400 break;
1401 case 0x0:
1402 rx_pwr_all = 8 - (pcck_buf->cck_agc_rpt & 0x3e);
1403 break;
1404 }
1405 } else {
1406 report = pcck_buf->cck_agc_rpt & 0x60;
1407 report >>= 5;
1408 switch (report) {
1409 case 0x3:
1410 rx_pwr_all = -35 -
1411 ((pcck_buf->cck_agc_rpt &
1412 0x1f) << 1);
1413 break;
1414 case 0x2:
1415 rx_pwr_all = -23 -
1416 ((pcck_buf->cck_agc_rpt &
1417 0x1f) << 1);
1418 break;
1419 case 0x1:
1420 rx_pwr_all = -11 -
1421 ((pcck_buf->cck_agc_rpt &
1422 0x1f) << 1);
1423 break;
1424 case 0x0:
1425 rx_pwr_all = -8 -
1426 ((pcck_buf->cck_agc_rpt &
1427 0x1f) << 1);
1428 break;
1429 }
1430 }
1431
1432 pwdb_all = rtl92e_rx_db_to_percent(rx_pwr_all);
1433 pstats->RxPWDBAll = precord_stats->RxPWDBAll = pwdb_all;
1434 pstats->RecvSignalPower = rx_pwr_all;
1435
1436 if (bpacket_match_bssid) {
1437 u8 sq;
1438
1439 if (pstats->RxPWDBAll > 40) {
1440 sq = 100;
1441 } else {
1442 sq = pcck_buf->sq_rpt;
1443
1444 if (pcck_buf->sq_rpt > 64)
1445 sq = 0;
1446 else if (pcck_buf->sq_rpt < 20)
1447 sq = 100;
1448 else
1449 sq = ((64-sq) * 100) / 44;
1450 }
1451 pstats->SignalQuality = sq;
1452 precord_stats->SignalQuality = sq;
1453 pstats->RxMIMOSignalQuality[0] = sq;
1454 precord_stats->RxMIMOSignalQuality[0] = sq;
1455 pstats->RxMIMOSignalQuality[1] = -1;
1456 precord_stats->RxMIMOSignalQuality[1] = -1;
1457 }
1458 } else {
1459 priv->stats.numqry_phystatusHT++;
1460 for (i = RF90_PATH_A; i < RF90_PATH_MAX; i++) {
1461 if (priv->brfpath_rxenable[i])
1462 rf_rx_num++;
1463
1464 rx_pwr[i] = ((pofdm_buf->trsw_gain_X[i] & 0x3F) *
1465 2) - 110;
1466
1467 tmp_rxsnr = pofdm_buf->rxsnr_X[i];
1468 rx_snrX = (s8)(tmp_rxsnr);
1469 rx_snrX /= 2;
1470 priv->stats.rxSNRdB[i] = (long)rx_snrX;
1471
1472 RSSI = rtl92e_rx_db_to_percent(rx_pwr[i]);
1473 if (priv->brfpath_rxenable[i])
1474 total_rssi += RSSI;
1475
1476 if (bpacket_match_bssid) {
1477 pstats->RxMIMOSignalStrength[i] = RSSI;
1478 precord_stats->RxMIMOSignalStrength[i] = RSSI;
1479 }
1480 }
1481
1482
1483 rx_pwr_all = (((pofdm_buf->pwdb_all) >> 1) & 0x7f) - 106;
1484 pwdb_all = rtl92e_rx_db_to_percent(rx_pwr_all);
1485
1486 pstats->RxPWDBAll = precord_stats->RxPWDBAll = pwdb_all;
1487 pstats->RxPower = precord_stats->RxPower = rx_pwr_all;
1488 pstats->RecvSignalPower = rx_pwr_all;
1489 if (pdrvinfo->RxHT && pdrvinfo->RxRate >= DESC90_RATEMCS8 &&
1490 pdrvinfo->RxRate <= DESC90_RATEMCS15)
1491 max_spatial_stream = 2;
1492 else
1493 max_spatial_stream = 1;
1494
1495 for (i = 0; i < max_spatial_stream; i++) {
1496 tmp_rxevm = pofdm_buf->rxevm_X[i];
1497 rx_evmX = (s8)(tmp_rxevm);
1498
1499 rx_evmX /= 2;
1500
1501 evm = rtl92e_evm_db_to_percent(rx_evmX);
1502 if (bpacket_match_bssid) {
1503 if (i == 0) {
1504 pstats->SignalQuality = evm & 0xff;
1505 precord_stats->SignalQuality = evm & 0xff;
1506 }
1507 pstats->RxMIMOSignalQuality[i] = evm & 0xff;
1508 precord_stats->RxMIMOSignalQuality[i] = evm & 0xff;
1509 }
1510 }
1511
1512
1513 rxsc_sgien_exflg = pofdm_buf->rxsc_sgien_exflg;
1514 prxsc = (struct phy_ofdm_rx_status_rxsc_sgien_exintfflag *)
1515 &rxsc_sgien_exflg;
1516 if (pdrvinfo->BW)
1517 priv->stats.received_bwtype[1+prxsc->rxsc]++;
1518 else
1519 priv->stats.received_bwtype[0]++;
1520 }
1521
1522 if (is_cck_rate) {
1523 pstats->SignalStrength = precord_stats->SignalStrength =
1524 _rtl92e_signal_scale_mapping(priv,
1525 (long)pwdb_all);
1526
1527 } else {
1528 if (rf_rx_num != 0)
1529 pstats->SignalStrength = precord_stats->SignalStrength =
1530 _rtl92e_signal_scale_mapping(priv,
1531 (long)(total_rssi /= rf_rx_num));
1532 }
1533 }
1534
_rtl92e_process_phyinfo(struct r8192_priv * priv,u8 * buffer,struct rtllib_rx_stats * prev_st,struct rtllib_rx_stats * curr_st)1535 static void _rtl92e_process_phyinfo(struct r8192_priv *priv, u8 *buffer,
1536 struct rtllib_rx_stats *prev_st,
1537 struct rtllib_rx_stats *curr_st)
1538 {
1539 bool bcheck = false;
1540 u8 rfpath;
1541 u32 ij, tmp_val;
1542 static u32 slide_rssi_index, slide_rssi_statistics;
1543 static u32 slide_evm_index, slide_evm_statistics;
1544 static u32 last_rssi, last_evm;
1545 static u32 slide_beacon_adc_pwdb_index;
1546 static u32 slide_beacon_adc_pwdb_statistics;
1547 static u32 last_beacon_adc_pwdb;
1548 struct rtllib_hdr_3addr *hdr;
1549 u16 sc;
1550 unsigned int seq;
1551
1552 hdr = (struct rtllib_hdr_3addr *)buffer;
1553 sc = le16_to_cpu(hdr->seq_ctl);
1554 seq = WLAN_GET_SEQ_SEQ(sc);
1555 curr_st->Seq_Num = seq;
1556 if (!prev_st->bIsAMPDU)
1557 bcheck = true;
1558
1559 if (slide_rssi_statistics++ >= PHY_RSSI_SLID_WIN_MAX) {
1560 slide_rssi_statistics = PHY_RSSI_SLID_WIN_MAX;
1561 last_rssi = priv->stats.slide_signal_strength[slide_rssi_index];
1562 priv->stats.slide_rssi_total -= last_rssi;
1563 }
1564 priv->stats.slide_rssi_total += prev_st->SignalStrength;
1565
1566 priv->stats.slide_signal_strength[slide_rssi_index++] =
1567 prev_st->SignalStrength;
1568 if (slide_rssi_index >= PHY_RSSI_SLID_WIN_MAX)
1569 slide_rssi_index = 0;
1570
1571 tmp_val = priv->stats.slide_rssi_total/slide_rssi_statistics;
1572 priv->stats.signal_strength = rtl92e_translate_to_dbm(priv, tmp_val);
1573 curr_st->rssi = priv->stats.signal_strength;
1574 if (!prev_st->bPacketMatchBSSID) {
1575 if (!prev_st->bToSelfBA)
1576 return;
1577 }
1578
1579 if (!bcheck)
1580 return;
1581
1582 priv->stats.num_process_phyinfo++;
1583 if (!prev_st->bIsCCK && prev_st->bPacketToSelf) {
1584 for (rfpath = RF90_PATH_A; rfpath < RF90_PATH_C; rfpath++) {
1585 if (!rtl92e_is_legal_rf_path(priv->rtllib->dev, rfpath))
1586 continue;
1587 if (priv->stats.rx_rssi_percentage[rfpath] == 0) {
1588 priv->stats.rx_rssi_percentage[rfpath] =
1589 prev_st->RxMIMOSignalStrength[rfpath];
1590 }
1591 if (prev_st->RxMIMOSignalStrength[rfpath] >
1592 priv->stats.rx_rssi_percentage[rfpath]) {
1593 priv->stats.rx_rssi_percentage[rfpath] =
1594 ((priv->stats.rx_rssi_percentage[rfpath]
1595 * (RX_SMOOTH - 1)) +
1596 (prev_st->RxMIMOSignalStrength
1597 [rfpath])) / (RX_SMOOTH);
1598 priv->stats.rx_rssi_percentage[rfpath] =
1599 priv->stats.rx_rssi_percentage[rfpath]
1600 + 1;
1601 } else {
1602 priv->stats.rx_rssi_percentage[rfpath] =
1603 ((priv->stats.rx_rssi_percentage[rfpath] *
1604 (RX_SMOOTH-1)) +
1605 (prev_st->RxMIMOSignalStrength[rfpath])) /
1606 (RX_SMOOTH);
1607 }
1608 }
1609 }
1610
1611
1612 if (prev_st->bPacketBeacon) {
1613 if (slide_beacon_adc_pwdb_statistics++ >=
1614 PHY_Beacon_RSSI_SLID_WIN_MAX) {
1615 slide_beacon_adc_pwdb_statistics =
1616 PHY_Beacon_RSSI_SLID_WIN_MAX;
1617 last_beacon_adc_pwdb = priv->stats.Slide_Beacon_pwdb
1618 [slide_beacon_adc_pwdb_index];
1619 priv->stats.Slide_Beacon_Total -= last_beacon_adc_pwdb;
1620 }
1621 priv->stats.Slide_Beacon_Total += prev_st->RxPWDBAll;
1622 priv->stats.Slide_Beacon_pwdb[slide_beacon_adc_pwdb_index] =
1623 prev_st->RxPWDBAll;
1624 slide_beacon_adc_pwdb_index++;
1625 if (slide_beacon_adc_pwdb_index >= PHY_Beacon_RSSI_SLID_WIN_MAX)
1626 slide_beacon_adc_pwdb_index = 0;
1627 prev_st->RxPWDBAll = priv->stats.Slide_Beacon_Total /
1628 slide_beacon_adc_pwdb_statistics;
1629 if (prev_st->RxPWDBAll >= 3)
1630 prev_st->RxPWDBAll -= 3;
1631 }
1632 if (prev_st->bPacketToSelf || prev_st->bPacketBeacon ||
1633 prev_st->bToSelfBA) {
1634 if (priv->undecorated_smoothed_pwdb < 0)
1635 priv->undecorated_smoothed_pwdb = prev_st->RxPWDBAll;
1636 if (prev_st->RxPWDBAll > (u32)priv->undecorated_smoothed_pwdb) {
1637 priv->undecorated_smoothed_pwdb =
1638 (((priv->undecorated_smoothed_pwdb) *
1639 (RX_SMOOTH-1)) +
1640 (prev_st->RxPWDBAll)) / (RX_SMOOTH);
1641 priv->undecorated_smoothed_pwdb =
1642 priv->undecorated_smoothed_pwdb + 1;
1643 } else {
1644 priv->undecorated_smoothed_pwdb =
1645 (((priv->undecorated_smoothed_pwdb) *
1646 (RX_SMOOTH-1)) +
1647 (prev_st->RxPWDBAll)) / (RX_SMOOTH);
1648 }
1649 rtl92e_update_rx_statistics(priv, prev_st);
1650 }
1651
1652 if (prev_st->SignalQuality != 0) {
1653 if (prev_st->bPacketToSelf || prev_st->bPacketBeacon ||
1654 prev_st->bToSelfBA) {
1655 if (slide_evm_statistics++ >= PHY_RSSI_SLID_WIN_MAX) {
1656 slide_evm_statistics = PHY_RSSI_SLID_WIN_MAX;
1657 last_evm =
1658 priv->stats.slide_evm[slide_evm_index];
1659 priv->stats.slide_evm_total -= last_evm;
1660 }
1661
1662 priv->stats.slide_evm_total += prev_st->SignalQuality;
1663
1664 priv->stats.slide_evm[slide_evm_index++] =
1665 prev_st->SignalQuality;
1666 if (slide_evm_index >= PHY_RSSI_SLID_WIN_MAX)
1667 slide_evm_index = 0;
1668
1669 tmp_val = priv->stats.slide_evm_total /
1670 slide_evm_statistics;
1671 priv->stats.signal_quality = tmp_val;
1672 priv->stats.last_signal_strength_inpercent = tmp_val;
1673 }
1674
1675 if (prev_st->bPacketToSelf ||
1676 prev_st->bPacketBeacon ||
1677 prev_st->bToSelfBA) {
1678 for (ij = 0; ij < 2; ij++) {
1679 if (prev_st->RxMIMOSignalQuality[ij] != -1) {
1680 if (priv->stats.rx_evm_percentage[ij] == 0)
1681 priv->stats.rx_evm_percentage[ij] =
1682 prev_st->RxMIMOSignalQuality[ij];
1683 priv->stats.rx_evm_percentage[ij] =
1684 ((priv->stats.rx_evm_percentage[ij] *
1685 (RX_SMOOTH - 1)) +
1686 (prev_st->RxMIMOSignalQuality[ij])) /
1687 (RX_SMOOTH);
1688 }
1689 }
1690 }
1691 }
1692 }
1693
_rtl92e_translate_rx_signal_stats(struct net_device * dev,struct sk_buff * skb,struct rtllib_rx_stats * pstats,struct rx_desc * pdesc,struct rx_fwinfo * pdrvinfo)1694 static void _rtl92e_translate_rx_signal_stats(struct net_device *dev,
1695 struct sk_buff *skb,
1696 struct rtllib_rx_stats *pstats,
1697 struct rx_desc *pdesc,
1698 struct rx_fwinfo *pdrvinfo)
1699 {
1700 struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev);
1701 bool bpacket_match_bssid, bpacket_toself;
1702 bool bPacketBeacon = false;
1703 struct rtllib_hdr_3addr *hdr;
1704 bool bToSelfBA = false;
1705 static struct rtllib_rx_stats previous_stats;
1706 u16 fc, type;
1707 u8 *tmp_buf;
1708 u8 *praddr;
1709
1710 tmp_buf = skb->data + pstats->RxDrvInfoSize + pstats->RxBufShift;
1711
1712 hdr = (struct rtllib_hdr_3addr *)tmp_buf;
1713 fc = le16_to_cpu(hdr->frame_ctl);
1714 type = WLAN_FC_GET_TYPE(fc);
1715 praddr = hdr->addr1;
1716
1717 bpacket_match_bssid =
1718 ((type != RTLLIB_FTYPE_CTL) &&
1719 ether_addr_equal(priv->rtllib->current_network.bssid,
1720 (fc & RTLLIB_FCTL_TODS) ? hdr->addr1 :
1721 (fc & RTLLIB_FCTL_FROMDS) ? hdr->addr2 :
1722 hdr->addr3) &&
1723 (!pstats->bHwError) && (!pstats->bCRC) && (!pstats->bICV));
1724 bpacket_toself = bpacket_match_bssid && /* check this */
1725 ether_addr_equal(praddr, priv->rtllib->dev->dev_addr);
1726 if (WLAN_FC_GET_FRAMETYPE(fc) == RTLLIB_STYPE_BEACON)
1727 bPacketBeacon = true;
1728 if (bpacket_match_bssid)
1729 priv->stats.numpacket_matchbssid++;
1730 if (bpacket_toself)
1731 priv->stats.numpacket_toself++;
1732 _rtl92e_process_phyinfo(priv, tmp_buf, &previous_stats, pstats);
1733 _rtl92e_query_rxphystatus(priv, pstats, pdesc, pdrvinfo,
1734 &previous_stats, bpacket_match_bssid,
1735 bpacket_toself, bPacketBeacon, bToSelfBA);
1736 rtl92e_copy_mpdu_stats(pstats, &previous_stats);
1737 }
1738
_rtl92e_update_received_rate_histogram_stats(struct net_device * dev,struct rtllib_rx_stats * pstats)1739 static void _rtl92e_update_received_rate_histogram_stats(
1740 struct net_device *dev,
1741 struct rtllib_rx_stats *pstats)
1742 {
1743 struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev);
1744 u32 rcvType = 1;
1745 u32 rateIndex;
1746 u32 preamble_guardinterval;
1747
1748 if (pstats->bCRC)
1749 rcvType = 2;
1750 else if (pstats->bICV)
1751 rcvType = 3;
1752
1753 if (pstats->bShortPreamble)
1754 preamble_guardinterval = 1;
1755 else
1756 preamble_guardinterval = 0;
1757
1758 switch (pstats->rate) {
1759 case MGN_1M:
1760 rateIndex = 0;
1761 break;
1762 case MGN_2M:
1763 rateIndex = 1;
1764 break;
1765 case MGN_5_5M:
1766 rateIndex = 2;
1767 break;
1768 case MGN_11M:
1769 rateIndex = 3;
1770 break;
1771 case MGN_6M:
1772 rateIndex = 4;
1773 break;
1774 case MGN_9M:
1775 rateIndex = 5;
1776 break;
1777 case MGN_12M:
1778 rateIndex = 6;
1779 break;
1780 case MGN_18M:
1781 rateIndex = 7;
1782 break;
1783 case MGN_24M:
1784 rateIndex = 8;
1785 break;
1786 case MGN_36M:
1787 rateIndex = 9;
1788 break;
1789 case MGN_48M:
1790 rateIndex = 10;
1791 break;
1792 case MGN_54M:
1793 rateIndex = 11;
1794 break;
1795 case MGN_MCS0:
1796 rateIndex = 12;
1797 break;
1798 case MGN_MCS1:
1799 rateIndex = 13;
1800 break;
1801 case MGN_MCS2:
1802 rateIndex = 14;
1803 break;
1804 case MGN_MCS3:
1805 rateIndex = 15;
1806 break;
1807 case MGN_MCS4:
1808 rateIndex = 16;
1809 break;
1810 case MGN_MCS5:
1811 rateIndex = 17;
1812 break;
1813 case MGN_MCS6:
1814 rateIndex = 18;
1815 break;
1816 case MGN_MCS7:
1817 rateIndex = 19;
1818 break;
1819 case MGN_MCS8:
1820 rateIndex = 20;
1821 break;
1822 case MGN_MCS9:
1823 rateIndex = 21;
1824 break;
1825 case MGN_MCS10:
1826 rateIndex = 22;
1827 break;
1828 case MGN_MCS11:
1829 rateIndex = 23;
1830 break;
1831 case MGN_MCS12:
1832 rateIndex = 24;
1833 break;
1834 case MGN_MCS13:
1835 rateIndex = 25;
1836 break;
1837 case MGN_MCS14:
1838 rateIndex = 26;
1839 break;
1840 case MGN_MCS15:
1841 rateIndex = 27;
1842 break;
1843 default:
1844 rateIndex = 28;
1845 break;
1846 }
1847 priv->stats.received_preamble_GI[preamble_guardinterval][rateIndex]++;
1848 priv->stats.received_rate_histogram[0][rateIndex]++;
1849 priv->stats.received_rate_histogram[rcvType][rateIndex]++;
1850 }
1851
rtl92e_get_rx_stats(struct net_device * dev,struct rtllib_rx_stats * stats,struct rx_desc * pdesc,struct sk_buff * skb)1852 bool rtl92e_get_rx_stats(struct net_device *dev, struct rtllib_rx_stats *stats,
1853 struct rx_desc *pdesc, struct sk_buff *skb)
1854 {
1855 struct r8192_priv *priv = rtllib_priv(dev);
1856 struct rx_fwinfo *pDrvInfo = NULL;
1857
1858 stats->bICV = pdesc->ICV;
1859 stats->bCRC = pdesc->CRC32;
1860 stats->bHwError = pdesc->CRC32 | pdesc->ICV;
1861
1862 stats->Length = pdesc->Length;
1863 if (stats->Length < 24)
1864 stats->bHwError |= 1;
1865
1866 if (stats->bHwError) {
1867 stats->bShift = false;
1868
1869 if (pdesc->CRC32) {
1870 if (pdesc->Length < 500)
1871 priv->stats.rxcrcerrmin++;
1872 else if (pdesc->Length > 1000)
1873 priv->stats.rxcrcerrmax++;
1874 else
1875 priv->stats.rxcrcerrmid++;
1876 }
1877 return false;
1878 }
1879
1880 stats->RxDrvInfoSize = pdesc->RxDrvInfoSize;
1881 stats->RxBufShift = (pdesc->Shift) & 0x03;
1882 stats->Decrypted = !pdesc->SWDec;
1883
1884 pDrvInfo = (struct rx_fwinfo *)(skb->data + stats->RxBufShift);
1885
1886 stats->rate = _rtl92e_rate_hw_to_mgn((bool)pDrvInfo->RxHT,
1887 pDrvInfo->RxRate);
1888 stats->bShortPreamble = pDrvInfo->SPLCP;
1889
1890 _rtl92e_update_received_rate_histogram_stats(dev, stats);
1891
1892 stats->bIsAMPDU = (pDrvInfo->PartAggr == 1);
1893 stats->bFirstMPDU = (pDrvInfo->PartAggr == 1) &&
1894 (pDrvInfo->FirstAGGR == 1);
1895
1896 stats->TimeStampLow = pDrvInfo->TSFL;
1897 stats->TimeStampHigh = rtl92e_readl(dev, TSFR+4);
1898
1899 rtl92e_update_rx_pkt_timestamp(dev, stats);
1900
1901 if ((stats->RxBufShift + stats->RxDrvInfoSize) > 0)
1902 stats->bShift = 1;
1903
1904 stats->RxIs40MHzPacket = pDrvInfo->BW;
1905
1906 _rtl92e_translate_rx_signal_stats(dev, skb, stats, pdesc, pDrvInfo);
1907 skb_trim(skb, skb->len - 4/*sCrcLng*/);
1908
1909
1910 stats->packetlength = stats->Length-4;
1911 stats->fraglength = stats->packetlength;
1912 stats->fragoffset = 0;
1913 stats->ntotalfrag = 1;
1914 return true;
1915 }
1916
rtl92e_stop_adapter(struct net_device * dev,bool reset)1917 void rtl92e_stop_adapter(struct net_device *dev, bool reset)
1918 {
1919 struct r8192_priv *priv = rtllib_priv(dev);
1920 int i;
1921 u8 OpMode;
1922 u8 u1bTmp;
1923 u32 ulRegRead;
1924
1925 OpMode = RT_OP_MODE_NO_LINK;
1926 priv->rtllib->SetHwRegHandler(dev, HW_VAR_MEDIA_STATUS, &OpMode);
1927
1928 if (!priv->rtllib->bSupportRemoteWakeUp) {
1929 u1bTmp = 0x0;
1930 rtl92e_writeb(dev, CMDR, u1bTmp);
1931 }
1932
1933 mdelay(20);
1934
1935 if (!reset) {
1936 mdelay(150);
1937
1938 priv->bHwRfOffAction = 2;
1939
1940 if (!priv->rtllib->bSupportRemoteWakeUp) {
1941 rtl92e_set_rf_off(dev);
1942 ulRegRead = rtl92e_readl(dev, CPU_GEN);
1943 ulRegRead |= CPU_GEN_SYSTEM_RESET;
1944 rtl92e_writel(dev, CPU_GEN, ulRegRead);
1945 } else {
1946 rtl92e_writel(dev, WFCRC0, 0xffffffff);
1947 rtl92e_writel(dev, WFCRC1, 0xffffffff);
1948 rtl92e_writel(dev, WFCRC2, 0xffffffff);
1949
1950
1951 rtl92e_writeb(dev, PMR, 0x5);
1952 rtl92e_writeb(dev, MacBlkCtrl, 0xa);
1953 }
1954 }
1955
1956 for (i = 0; i < MAX_QUEUE_SIZE; i++)
1957 skb_queue_purge(&priv->rtllib->skb_waitQ[i]);
1958 for (i = 0; i < MAX_QUEUE_SIZE; i++)
1959 skb_queue_purge(&priv->rtllib->skb_aggQ[i]);
1960
1961 skb_queue_purge(&priv->skb_queue);
1962 }
1963
rtl92e_update_ratr_table(struct net_device * dev)1964 void rtl92e_update_ratr_table(struct net_device *dev)
1965 {
1966 struct r8192_priv *priv = rtllib_priv(dev);
1967 struct rtllib_device *ieee = priv->rtllib;
1968 u8 *pMcsRate = ieee->dot11HTOperationalRateSet;
1969 u32 ratr_value = 0;
1970 u16 rate_config = 0;
1971 u8 rate_index = 0;
1972
1973 rtl92e_config_rate(dev, &rate_config);
1974 ratr_value = rate_config | *pMcsRate << 12;
1975 switch (ieee->mode) {
1976 case IEEE_A:
1977 ratr_value &= 0x00000FF0;
1978 break;
1979 case IEEE_B:
1980 ratr_value &= 0x0000000F;
1981 break;
1982 case IEEE_G:
1983 case IEEE_G|IEEE_B:
1984 ratr_value &= 0x00000FF7;
1985 break;
1986 case IEEE_N_24G:
1987 case IEEE_N_5G:
1988 if (ieee->pHTInfo->peer_mimo_ps == 0) {
1989 ratr_value &= 0x0007F007;
1990 } else {
1991 if (priv->rf_type == RF_1T2R)
1992 ratr_value &= 0x000FF007;
1993 else
1994 ratr_value &= 0x0F81F007;
1995 }
1996 break;
1997 default:
1998 break;
1999 }
2000 ratr_value &= 0x0FFFFFFF;
2001 if (ieee->pHTInfo->cur_tx_bw40mhz &&
2002 ieee->pHTInfo->bCurShortGI40MHz)
2003 ratr_value |= 0x80000000;
2004 else if (!ieee->pHTInfo->cur_tx_bw40mhz &&
2005 ieee->pHTInfo->bCurShortGI20MHz)
2006 ratr_value |= 0x80000000;
2007 rtl92e_writel(dev, RATR0+rate_index*4, ratr_value);
2008 rtl92e_writeb(dev, UFWP, 1);
2009 }
2010
2011 void
rtl92e_init_variables(struct net_device * dev)2012 rtl92e_init_variables(struct net_device *dev)
2013 {
2014 struct r8192_priv *priv = rtllib_priv(dev);
2015
2016 strscpy(priv->nick, "rtl8192E", sizeof(priv->nick));
2017
2018 priv->rtllib->softmac_features = IEEE_SOFTMAC_SCAN |
2019 IEEE_SOFTMAC_ASSOCIATE | IEEE_SOFTMAC_PROBERQ |
2020 IEEE_SOFTMAC_PROBERS | IEEE_SOFTMAC_TX_QUEUE;
2021
2022 priv->rtllib->tx_headroom = sizeof(struct tx_fwinfo_8190pci);
2023
2024 priv->ShortRetryLimit = 0x30;
2025 priv->LongRetryLimit = 0x30;
2026
2027 priv->ReceiveConfig = RCR_ADD3 |
2028 RCR_AMF | RCR_ADF |
2029 RCR_AICV |
2030 RCR_AB | RCR_AM | RCR_APM |
2031 RCR_AAP | ((u32)7<<RCR_MXDMA_OFFSET) |
2032 ((u32)7 << RCR_FIFO_OFFSET) | RCR_ONLYERLPKT;
2033
2034 priv->irq_mask[0] = (u32)(IMR_ROK | IMR_VODOK | IMR_VIDOK |
2035 IMR_BEDOK | IMR_BKDOK | IMR_HCCADOK |
2036 IMR_MGNTDOK | IMR_COMDOK | IMR_HIGHDOK |
2037 IMR_BDOK | IMR_RXCMDOK | IMR_TIMEOUT0 |
2038 IMR_RDU | IMR_RXFOVW | IMR_TXFOVW |
2039 IMR_BcnInt | IMR_TBDOK | IMR_TBDER);
2040
2041 priv->PwrDomainProtect = false;
2042
2043 priv->bfirst_after_down = false;
2044 }
2045
rtl92e_enable_irq(struct net_device * dev)2046 void rtl92e_enable_irq(struct net_device *dev)
2047 {
2048 struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev);
2049
2050 priv->irq_enabled = 1;
2051
2052 rtl92e_writel(dev, INTA_MASK, priv->irq_mask[0]);
2053
2054 }
2055
rtl92e_disable_irq(struct net_device * dev)2056 void rtl92e_disable_irq(struct net_device *dev)
2057 {
2058 struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev);
2059
2060 rtl92e_writel(dev, INTA_MASK, 0);
2061
2062 priv->irq_enabled = 0;
2063 }
2064
rtl92e_clear_irq(struct net_device * dev)2065 void rtl92e_clear_irq(struct net_device *dev)
2066 {
2067 u32 tmp;
2068
2069 tmp = rtl92e_readl(dev, ISR);
2070 rtl92e_writel(dev, ISR, tmp);
2071 }
2072
2073
rtl92e_enable_rx(struct net_device * dev)2074 void rtl92e_enable_rx(struct net_device *dev)
2075 {
2076 struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev);
2077
2078 rtl92e_writel(dev, RDQDA, priv->rx_ring_dma[RX_MPDU_QUEUE]);
2079 }
2080
2081 static const u32 TX_DESC_BASE[] = {
2082 BKQDA, BEQDA, VIQDA, VOQDA, HCCAQDA, CQDA, MQDA, HQDA, BQDA
2083 };
2084
rtl92e_enable_tx(struct net_device * dev)2085 void rtl92e_enable_tx(struct net_device *dev)
2086 {
2087 struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev);
2088 u32 i;
2089
2090 for (i = 0; i < MAX_TX_QUEUE_COUNT; i++)
2091 rtl92e_writel(dev, TX_DESC_BASE[i], priv->tx_ring[i].dma);
2092 }
2093
2094
rtl92e_ack_irq(struct net_device * dev,u32 * p_inta,u32 * p_intb)2095 void rtl92e_ack_irq(struct net_device *dev, u32 *p_inta, u32 *p_intb)
2096 {
2097 *p_inta = rtl92e_readl(dev, ISR);
2098 rtl92e_writel(dev, ISR, *p_inta);
2099 }
2100
rtl92e_is_rx_stuck(struct net_device * dev)2101 bool rtl92e_is_rx_stuck(struct net_device *dev)
2102 {
2103 struct r8192_priv *priv = rtllib_priv(dev);
2104 u16 RegRxCounter = rtl92e_readw(dev, 0x130);
2105 bool bStuck = false;
2106 static u8 rx_chk_cnt;
2107 u32 SlotIndex = 0, TotalRxStuckCount = 0;
2108 u8 i;
2109 u8 SilentResetRxSoltNum = 4;
2110
2111 rx_chk_cnt++;
2112 if (priv->undecorated_smoothed_pwdb >= (RateAdaptiveTH_High+5)) {
2113 rx_chk_cnt = 0;
2114 } else if ((priv->undecorated_smoothed_pwdb < (RateAdaptiveTH_High + 5))
2115 && (((priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) &&
2116 (priv->undecorated_smoothed_pwdb >= RateAdaptiveTH_Low_40M))
2117 || ((priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20) &&
2118 (priv->undecorated_smoothed_pwdb >= RateAdaptiveTH_Low_20M)))) {
2119 if (rx_chk_cnt < 2)
2120 return bStuck;
2121 rx_chk_cnt = 0;
2122 } else if ((((priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) &&
2123 (priv->undecorated_smoothed_pwdb < RateAdaptiveTH_Low_40M)) ||
2124 ((priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20) &&
2125 (priv->undecorated_smoothed_pwdb < RateAdaptiveTH_Low_20M))) &&
2126 priv->undecorated_smoothed_pwdb >= VeryLowRSSI) {
2127 if (rx_chk_cnt < 4)
2128 return bStuck;
2129 rx_chk_cnt = 0;
2130 } else {
2131 if (rx_chk_cnt < 8)
2132 return bStuck;
2133 rx_chk_cnt = 0;
2134 }
2135
2136
2137 SlotIndex = (priv->SilentResetRxSlotIndex++)%SilentResetRxSoltNum;
2138
2139 if (priv->RxCounter == RegRxCounter) {
2140 priv->SilentResetRxStuckEvent[SlotIndex] = 1;
2141
2142 for (i = 0; i < SilentResetRxSoltNum; i++)
2143 TotalRxStuckCount += priv->SilentResetRxStuckEvent[i];
2144
2145 if (TotalRxStuckCount == SilentResetRxSoltNum) {
2146 bStuck = true;
2147 for (i = 0; i < SilentResetRxSoltNum; i++)
2148 TotalRxStuckCount +=
2149 priv->SilentResetRxStuckEvent[i];
2150 }
2151
2152
2153 } else {
2154 priv->SilentResetRxStuckEvent[SlotIndex] = 0;
2155 }
2156
2157 priv->RxCounter = RegRxCounter;
2158
2159 return bStuck;
2160 }
2161
rtl92e_is_tx_stuck(struct net_device * dev)2162 bool rtl92e_is_tx_stuck(struct net_device *dev)
2163 {
2164 struct r8192_priv *priv = rtllib_priv(dev);
2165 bool bStuck = false;
2166 u16 RegTxCounter = rtl92e_readw(dev, 0x128);
2167
2168 if (priv->TxCounter == RegTxCounter)
2169 bStuck = true;
2170
2171 priv->TxCounter = RegTxCounter;
2172
2173 return bStuck;
2174 }
2175
rtl92e_get_nmode_support_by_sec(struct net_device * dev)2176 bool rtl92e_get_nmode_support_by_sec(struct net_device *dev)
2177 {
2178 struct r8192_priv *priv = rtllib_priv(dev);
2179 struct rtllib_device *ieee = priv->rtllib;
2180
2181 if (ieee->rtllib_ap_sec_type &&
2182 (ieee->rtllib_ap_sec_type(priv->rtllib)&(SEC_ALG_WEP |
2183 SEC_ALG_TKIP))) {
2184 return false;
2185 } else {
2186 return true;
2187 }
2188 }
2189
rtl92e_is_halfn_supported_by_ap(struct net_device * dev)2190 bool rtl92e_is_halfn_supported_by_ap(struct net_device *dev)
2191 {
2192 struct r8192_priv *priv = rtllib_priv(dev);
2193 struct rtllib_device *ieee = priv->rtllib;
2194
2195 return ieee->bHalfWirelessN24GMode;
2196 }
2197
