1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved.
4 *
5 * Based on the r8180 driver, which is:
6 * Copyright 2004-2005 Andrea Merello <andrea.merello@gmail.com>, et al.
7 *
8 * Contact Information: wlanfae <wlanfae@realtek.com>
9 */
10 #include "rtl_core.h"
11 #include "r8192E_phy.h"
12 #include "r8192E_phyreg.h"
13 #include "r8190P_rtl8256.h"
14 #include "r8192E_cmdpkt.h"
15 #include "rtl_dm.h"
16 #include "rtl_wx.h"
17
18 static int WDCAPARA_ADD[] = {EDCAPARA_BE, EDCAPARA_BK, EDCAPARA_VI,
19 EDCAPARA_VO};
20
rtl92e_start_beacon(struct net_device * dev)21 void rtl92e_start_beacon(struct net_device *dev)
22 {
23 struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev);
24 struct rtllib_network *net = &priv->rtllib->current_network;
25 u16 BcnTimeCfg = 0;
26 u16 BcnCW = 6;
27 u16 BcnIFS = 0xf;
28
29 rtl92e_irq_disable(dev);
30
31 rtl92e_writew(dev, ATIMWND, 2);
32
33 rtl92e_writew(dev, BCN_INTERVAL, net->beacon_interval);
34 rtl92e_writew(dev, BCN_DRV_EARLY_INT, 10);
35 rtl92e_writew(dev, BCN_DMATIME, 256);
36
37 rtl92e_writeb(dev, BCN_ERR_THRESH, 100);
38
39 BcnTimeCfg |= BcnCW<<BCN_TCFG_CW_SHIFT;
40 BcnTimeCfg |= BcnIFS<<BCN_TCFG_IFS;
41 rtl92e_writew(dev, BCN_TCFG, BcnTimeCfg);
42 rtl92e_irq_enable(dev);
43 }
44
_rtl92e_update_msr(struct net_device * dev)45 static void _rtl92e_update_msr(struct net_device *dev)
46 {
47 struct r8192_priv *priv = rtllib_priv(dev);
48 u8 msr;
49 enum led_ctl_mode LedAction = LED_CTL_NO_LINK;
50
51 msr = rtl92e_readb(dev, MSR);
52 msr &= ~MSR_LINK_MASK;
53
54 switch (priv->rtllib->iw_mode) {
55 case IW_MODE_INFRA:
56 if (priv->rtllib->state == RTLLIB_LINKED)
57 msr |= (MSR_LINK_MANAGED << MSR_LINK_SHIFT);
58 else
59 msr |= (MSR_LINK_NONE << MSR_LINK_SHIFT);
60 LedAction = LED_CTL_LINK;
61 break;
62 case IW_MODE_ADHOC:
63 if (priv->rtllib->state == RTLLIB_LINKED)
64 msr |= (MSR_LINK_ADHOC << MSR_LINK_SHIFT);
65 else
66 msr |= (MSR_LINK_NONE << MSR_LINK_SHIFT);
67 break;
68 case IW_MODE_MASTER:
69 if (priv->rtllib->state == RTLLIB_LINKED)
70 msr |= (MSR_LINK_MASTER << MSR_LINK_SHIFT);
71 else
72 msr |= (MSR_LINK_NONE << MSR_LINK_SHIFT);
73 break;
74 default:
75 break;
76 }
77
78 rtl92e_writeb(dev, MSR, msr);
79 if (priv->rtllib->LedControlHandler)
80 priv->rtllib->LedControlHandler(dev, LedAction);
81 }
82
rtl92e_set_reg(struct net_device * dev,u8 variable,u8 * val)83 void rtl92e_set_reg(struct net_device *dev, u8 variable, u8 *val)
84 {
85 struct r8192_priv *priv = rtllib_priv(dev);
86
87 switch (variable) {
88 case HW_VAR_BSSID:
89 /* BSSIDR 2 byte alignment */
90 rtl92e_writew(dev, BSSIDR, *(u16 *)val);
91 rtl92e_writel(dev, BSSIDR + 2, *(u32 *)(val + 2));
92 break;
93
94 case HW_VAR_MEDIA_STATUS:
95 {
96 enum rt_op_mode OpMode = *((enum rt_op_mode *)(val));
97 u8 btMsr = rtl92e_readb(dev, MSR);
98
99 btMsr &= 0xfc;
100
101 switch (OpMode) {
102 case RT_OP_MODE_INFRASTRUCTURE:
103 btMsr |= MSR_INFRA;
104 break;
105
106 case RT_OP_MODE_IBSS:
107 btMsr |= MSR_ADHOC;
108 break;
109
110 case RT_OP_MODE_AP:
111 btMsr |= MSR_AP;
112 break;
113
114 default:
115 btMsr |= MSR_NOLINK;
116 break;
117 }
118
119 rtl92e_writeb(dev, MSR, btMsr);
120
121 }
122 break;
123
124 case HW_VAR_CECHK_BSSID:
125 {
126 u32 RegRCR, Type;
127
128 Type = val[0];
129 RegRCR = rtl92e_readl(dev, RCR);
130 priv->ReceiveConfig = RegRCR;
131
132 if (Type)
133 RegRCR |= (RCR_CBSSID);
134 else
135 RegRCR &= (~RCR_CBSSID);
136
137 rtl92e_writel(dev, RCR, RegRCR);
138 priv->ReceiveConfig = RegRCR;
139
140 }
141 break;
142
143 case HW_VAR_SLOT_TIME:
144
145 priv->slot_time = val[0];
146 rtl92e_writeb(dev, SLOT_TIME, val[0]);
147
148 break;
149
150 case HW_VAR_ACK_PREAMBLE:
151 {
152 u32 regTmp;
153
154 priv->short_preamble = (bool)*val;
155 regTmp = priv->basic_rate;
156 if (priv->short_preamble)
157 regTmp |= BRSR_AckShortPmb;
158 rtl92e_writel(dev, RRSR, regTmp);
159 break;
160 }
161
162 case HW_VAR_CPU_RST:
163 rtl92e_writel(dev, CPU_GEN, ((u32 *)(val))[0]);
164 break;
165
166 case HW_VAR_AC_PARAM:
167 {
168 u8 pAcParam = *val;
169 u32 eACI = pAcParam;
170 u8 u1bAIFS;
171 u32 u4bAcParam;
172 u8 mode = priv->rtllib->mode;
173 struct rtllib_qos_parameters *qop =
174 &priv->rtllib->current_network.qos_data.parameters;
175
176 u1bAIFS = qop->aifs[pAcParam] *
177 ((mode&(IEEE_G|IEEE_N_24G)) ? 9 : 20) + aSifsTime;
178
179 rtl92e_dm_init_edca_turbo(dev);
180
181 u4bAcParam = (le16_to_cpu(qop->tx_op_limit[pAcParam]) <<
182 AC_PARAM_TXOP_LIMIT_OFFSET) |
183 ((le16_to_cpu(qop->cw_max[pAcParam])) <<
184 AC_PARAM_ECW_MAX_OFFSET) |
185 ((le16_to_cpu(qop->cw_min[pAcParam])) <<
186 AC_PARAM_ECW_MIN_OFFSET) |
187 (((u32)u1bAIFS) << AC_PARAM_AIFS_OFFSET);
188
189 RT_TRACE(COMP_DBG, "%s():HW_VAR_AC_PARAM eACI:%x:%x\n",
190 __func__, eACI, u4bAcParam);
191 switch (eACI) {
192 case AC1_BK:
193 rtl92e_writel(dev, EDCAPARA_BK, u4bAcParam);
194 break;
195
196 case AC0_BE:
197 rtl92e_writel(dev, EDCAPARA_BE, u4bAcParam);
198 break;
199
200 case AC2_VI:
201 rtl92e_writel(dev, EDCAPARA_VI, u4bAcParam);
202 break;
203
204 case AC3_VO:
205 rtl92e_writel(dev, EDCAPARA_VO, u4bAcParam);
206 break;
207
208 default:
209 netdev_info(dev, "SetHwReg8185(): invalid ACI: %d !\n",
210 eACI);
211 break;
212 }
213 priv->rtllib->SetHwRegHandler(dev, HW_VAR_ACM_CTRL,
214 &pAcParam);
215 break;
216 }
217
218 case HW_VAR_ACM_CTRL:
219 {
220 struct rtllib_qos_parameters *qos_parameters =
221 &priv->rtllib->current_network.qos_data.parameters;
222 u8 pAcParam = *val;
223 u32 eACI = pAcParam;
224 union aci_aifsn *pAciAifsn = (union aci_aifsn *) &
225 (qos_parameters->aifs[0]);
226 u8 acm = pAciAifsn->f.acm;
227 u8 AcmCtrl = rtl92e_readb(dev, AcmHwCtrl);
228
229 RT_TRACE(COMP_DBG, "===========>%s():HW_VAR_ACM_CTRL:%x\n",
230 __func__, eACI);
231 AcmCtrl = AcmCtrl | ((priv->AcmMethod == 2) ? 0x0 : 0x1);
232
233 if (acm) {
234 switch (eACI) {
235 case AC0_BE:
236 AcmCtrl |= AcmHw_BeqEn;
237 break;
238
239 case AC2_VI:
240 AcmCtrl |= AcmHw_ViqEn;
241 break;
242
243 case AC3_VO:
244 AcmCtrl |= AcmHw_VoqEn;
245 break;
246
247 default:
248 RT_TRACE(COMP_QOS,
249 "SetHwReg8185(): [HW_VAR_ACM_CTRL] acm set failed: eACI is %d\n",
250 eACI);
251 break;
252 }
253 } else {
254 switch (eACI) {
255 case AC0_BE:
256 AcmCtrl &= (~AcmHw_BeqEn);
257 break;
258
259 case AC2_VI:
260 AcmCtrl &= (~AcmHw_ViqEn);
261 break;
262
263 case AC3_VO:
264 AcmCtrl &= (~AcmHw_BeqEn);
265 break;
266
267 default:
268 break;
269 }
270 }
271
272 RT_TRACE(COMP_QOS,
273 "SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n",
274 AcmCtrl);
275 rtl92e_writeb(dev, AcmHwCtrl, AcmCtrl);
276 break;
277 }
278
279 case HW_VAR_SIFS:
280 rtl92e_writeb(dev, SIFS, val[0]);
281 rtl92e_writeb(dev, SIFS+1, val[0]);
282 break;
283
284 case HW_VAR_RF_TIMING:
285 {
286 u8 Rf_Timing = *val;
287
288 rtl92e_writeb(dev, rFPGA0_RFTiming1, Rf_Timing);
289 break;
290 }
291
292 default:
293 break;
294 }
295
296 }
297
_rtl92e_read_eeprom_info(struct net_device * dev)298 static void _rtl92e_read_eeprom_info(struct net_device *dev)
299 {
300 struct r8192_priv *priv = rtllib_priv(dev);
301 const u8 bMac_Tmp_Addr[ETH_ALEN] = {0x00, 0xe0, 0x4c, 0x00, 0x00, 0x01};
302 u8 tempval;
303 u8 ICVer8192, ICVer8256;
304 u16 i, usValue, IC_Version;
305 u16 EEPROMId;
306
307 RT_TRACE(COMP_INIT, "====> %s\n", __func__);
308
309 EEPROMId = rtl92e_eeprom_read(dev, 0);
310 if (EEPROMId != RTL8190_EEPROM_ID) {
311 netdev_err(dev, "%s(): Invalid EEPROM ID: %x\n", __func__,
312 EEPROMId);
313 priv->AutoloadFailFlag = true;
314 } else {
315 priv->AutoloadFailFlag = false;
316 }
317
318 if (!priv->AutoloadFailFlag) {
319 priv->eeprom_vid = rtl92e_eeprom_read(dev, EEPROM_VID >> 1);
320 priv->eeprom_did = rtl92e_eeprom_read(dev, EEPROM_DID >> 1);
321
322 usValue = rtl92e_eeprom_read(dev,
323 (u16)(EEPROM_Customer_ID>>1)) >> 8;
324 priv->eeprom_CustomerID = (u8)(usValue & 0xff);
325 usValue = rtl92e_eeprom_read(dev,
326 EEPROM_ICVersion_ChannelPlan>>1);
327 priv->eeprom_ChannelPlan = usValue&0xff;
328 IC_Version = (usValue & 0xff00)>>8;
329
330 ICVer8192 = IC_Version & 0xf;
331 ICVer8256 = (IC_Version & 0xf0)>>4;
332 RT_TRACE(COMP_INIT, "\nICVer8192 = 0x%x\n", ICVer8192);
333 RT_TRACE(COMP_INIT, "\nICVer8256 = 0x%x\n", ICVer8256);
334 if (ICVer8192 == 0x2) {
335 if (ICVer8256 == 0x5)
336 priv->card_8192_version = VERSION_8190_BE;
337 }
338 switch (priv->card_8192_version) {
339 case VERSION_8190_BD:
340 case VERSION_8190_BE:
341 break;
342 default:
343 priv->card_8192_version = VERSION_8190_BD;
344 break;
345 }
346 RT_TRACE(COMP_INIT, "\nIC Version = 0x%x\n",
347 priv->card_8192_version);
348 } else {
349 priv->card_8192_version = VERSION_8190_BD;
350 priv->eeprom_vid = 0;
351 priv->eeprom_did = 0;
352 priv->eeprom_CustomerID = 0;
353 priv->eeprom_ChannelPlan = 0;
354 RT_TRACE(COMP_INIT, "\nIC Version = 0x%x\n", 0xff);
355 }
356
357 RT_TRACE(COMP_INIT, "EEPROM VID = 0x%4x\n", priv->eeprom_vid);
358 RT_TRACE(COMP_INIT, "EEPROM DID = 0x%4x\n", priv->eeprom_did);
359 RT_TRACE(COMP_INIT, "EEPROM Customer ID: 0x%2x\n",
360 priv->eeprom_CustomerID);
361
362 if (!priv->AutoloadFailFlag) {
363 for (i = 0; i < 6; i += 2) {
364 usValue = rtl92e_eeprom_read(dev,
365 (EEPROM_NODE_ADDRESS_BYTE_0 + i) >> 1);
366 *(u16 *)(&dev->dev_addr[i]) = usValue;
367 }
368 } else {
369 ether_addr_copy(dev->dev_addr, bMac_Tmp_Addr);
370 }
371
372 RT_TRACE(COMP_INIT, "Permanent Address = %pM\n",
373 dev->dev_addr);
374
375 if (priv->card_8192_version > VERSION_8190_BD)
376 priv->bTXPowerDataReadFromEEPORM = true;
377 else
378 priv->bTXPowerDataReadFromEEPORM = false;
379
380 priv->rf_type = RTL819X_DEFAULT_RF_TYPE;
381
382 if (priv->card_8192_version > VERSION_8190_BD) {
383 if (!priv->AutoloadFailFlag) {
384 tempval = (rtl92e_eeprom_read(dev,
385 (EEPROM_RFInd_PowerDiff >> 1))) & 0xff;
386 priv->EEPROMLegacyHTTxPowerDiff = tempval & 0xf;
387
388 if (tempval&0x80)
389 priv->rf_type = RF_1T2R;
390 else
391 priv->rf_type = RF_2T4R;
392 } else {
393 priv->EEPROMLegacyHTTxPowerDiff = 0x04;
394 }
395 RT_TRACE(COMP_INIT, "EEPROMLegacyHTTxPowerDiff = %d\n",
396 priv->EEPROMLegacyHTTxPowerDiff);
397
398 if (!priv->AutoloadFailFlag)
399 priv->EEPROMThermalMeter = (u8)(((rtl92e_eeprom_read(dev,
400 (EEPROM_ThermalMeter>>1))) &
401 0xff00)>>8);
402 else
403 priv->EEPROMThermalMeter = EEPROM_Default_ThermalMeter;
404 RT_TRACE(COMP_INIT, "ThermalMeter = %d\n",
405 priv->EEPROMThermalMeter);
406 priv->TSSI_13dBm = priv->EEPROMThermalMeter * 100;
407
408 if (priv->epromtype == EEPROM_93C46) {
409 if (!priv->AutoloadFailFlag) {
410 usValue = rtl92e_eeprom_read(dev,
411 EEPROM_TxPwDiff_CrystalCap >> 1);
412 priv->EEPROMAntPwDiff = usValue & 0x0fff;
413 priv->EEPROMCrystalCap = (u8)((usValue & 0xf000)
414 >> 12);
415 } else {
416 priv->EEPROMAntPwDiff =
417 EEPROM_Default_AntTxPowerDiff;
418 priv->EEPROMCrystalCap =
419 EEPROM_Default_TxPwDiff_CrystalCap;
420 }
421 RT_TRACE(COMP_INIT, "EEPROMAntPwDiff = %d\n",
422 priv->EEPROMAntPwDiff);
423 RT_TRACE(COMP_INIT, "EEPROMCrystalCap = %d\n",
424 priv->EEPROMCrystalCap);
425
426 for (i = 0; i < 14; i += 2) {
427 if (!priv->AutoloadFailFlag)
428 usValue = rtl92e_eeprom_read(dev,
429 (EEPROM_TxPwIndex_CCK + i) >> 1);
430 else
431 usValue = EEPROM_Default_TxPower;
432 *((u16 *)(&priv->EEPROMTxPowerLevelCCK[i])) =
433 usValue;
434 RT_TRACE(COMP_INIT,
435 "CCK Tx Power Level, Index %d = 0x%02x\n",
436 i, priv->EEPROMTxPowerLevelCCK[i]);
437 RT_TRACE(COMP_INIT,
438 "CCK Tx Power Level, Index %d = 0x%02x\n",
439 i+1, priv->EEPROMTxPowerLevelCCK[i+1]);
440 }
441 for (i = 0; i < 14; i += 2) {
442 if (!priv->AutoloadFailFlag)
443 usValue = rtl92e_eeprom_read(dev,
444 (EEPROM_TxPwIndex_OFDM_24G + i) >> 1);
445 else
446 usValue = EEPROM_Default_TxPower;
447 *((u16 *)(&priv->EEPROMTxPowerLevelOFDM24G[i]))
448 = usValue;
449 RT_TRACE(COMP_INIT,
450 "OFDM 2.4G Tx Power Level, Index %d = 0x%02x\n",
451 i, priv->EEPROMTxPowerLevelOFDM24G[i]);
452 RT_TRACE(COMP_INIT,
453 "OFDM 2.4G Tx Power Level, Index %d = 0x%02x\n",
454 i + 1,
455 priv->EEPROMTxPowerLevelOFDM24G[i+1]);
456 }
457 }
458 if (priv->epromtype == EEPROM_93C46) {
459 for (i = 0; i < 14; i++) {
460 priv->TxPowerLevelCCK[i] =
461 priv->EEPROMTxPowerLevelCCK[i];
462 priv->TxPowerLevelOFDM24G[i] =
463 priv->EEPROMTxPowerLevelOFDM24G[i];
464 }
465 priv->LegacyHTTxPowerDiff =
466 priv->EEPROMLegacyHTTxPowerDiff;
467 priv->AntennaTxPwDiff[0] = priv->EEPROMAntPwDiff & 0xf;
468 priv->AntennaTxPwDiff[1] = (priv->EEPROMAntPwDiff &
469 0xf0) >> 4;
470 priv->AntennaTxPwDiff[2] = (priv->EEPROMAntPwDiff &
471 0xf00) >> 8;
472 priv->CrystalCap = priv->EEPROMCrystalCap;
473 priv->ThermalMeter[0] = priv->EEPROMThermalMeter & 0xf;
474 priv->ThermalMeter[1] = (priv->EEPROMThermalMeter &
475 0xf0) >> 4;
476 } else if (priv->epromtype == EEPROM_93C56) {
477
478 for (i = 0; i < 3; i++) {
479 priv->TxPowerLevelCCK_A[i] =
480 priv->EEPROMRfACCKChnl1TxPwLevel[0];
481 priv->TxPowerLevelOFDM24G_A[i] =
482 priv->EEPROMRfAOfdmChnlTxPwLevel[0];
483 priv->TxPowerLevelCCK_C[i] =
484 priv->EEPROMRfCCCKChnl1TxPwLevel[0];
485 priv->TxPowerLevelOFDM24G_C[i] =
486 priv->EEPROMRfCOfdmChnlTxPwLevel[0];
487 }
488 for (i = 3; i < 9; i++) {
489 priv->TxPowerLevelCCK_A[i] =
490 priv->EEPROMRfACCKChnl1TxPwLevel[1];
491 priv->TxPowerLevelOFDM24G_A[i] =
492 priv->EEPROMRfAOfdmChnlTxPwLevel[1];
493 priv->TxPowerLevelCCK_C[i] =
494 priv->EEPROMRfCCCKChnl1TxPwLevel[1];
495 priv->TxPowerLevelOFDM24G_C[i] =
496 priv->EEPROMRfCOfdmChnlTxPwLevel[1];
497 }
498 for (i = 9; i < 14; i++) {
499 priv->TxPowerLevelCCK_A[i] =
500 priv->EEPROMRfACCKChnl1TxPwLevel[2];
501 priv->TxPowerLevelOFDM24G_A[i] =
502 priv->EEPROMRfAOfdmChnlTxPwLevel[2];
503 priv->TxPowerLevelCCK_C[i] =
504 priv->EEPROMRfCCCKChnl1TxPwLevel[2];
505 priv->TxPowerLevelOFDM24G_C[i] =
506 priv->EEPROMRfCOfdmChnlTxPwLevel[2];
507 }
508 for (i = 0; i < 14; i++)
509 RT_TRACE(COMP_INIT,
510 "priv->TxPowerLevelCCK_A[%d] = 0x%x\n",
511 i, priv->TxPowerLevelCCK_A[i]);
512 for (i = 0; i < 14; i++)
513 RT_TRACE(COMP_INIT,
514 "priv->TxPowerLevelOFDM24G_A[%d] = 0x%x\n",
515 i, priv->TxPowerLevelOFDM24G_A[i]);
516 for (i = 0; i < 14; i++)
517 RT_TRACE(COMP_INIT,
518 "priv->TxPowerLevelCCK_C[%d] = 0x%x\n",
519 i, priv->TxPowerLevelCCK_C[i]);
520 for (i = 0; i < 14; i++)
521 RT_TRACE(COMP_INIT,
522 "priv->TxPowerLevelOFDM24G_C[%d] = 0x%x\n",
523 i, priv->TxPowerLevelOFDM24G_C[i]);
524 priv->LegacyHTTxPowerDiff =
525 priv->EEPROMLegacyHTTxPowerDiff;
526 priv->AntennaTxPwDiff[0] = 0;
527 priv->AntennaTxPwDiff[1] = 0;
528 priv->AntennaTxPwDiff[2] = 0;
529 priv->CrystalCap = priv->EEPROMCrystalCap;
530 priv->ThermalMeter[0] = priv->EEPROMThermalMeter & 0xf;
531 priv->ThermalMeter[1] = (priv->EEPROMThermalMeter &
532 0xf0) >> 4;
533 }
534 }
535
536 if (priv->rf_type == RF_1T2R) {
537 /* no matter what checkpatch says, the braces are needed */
538 RT_TRACE(COMP_INIT, "\n1T2R config\n");
539 } else if (priv->rf_type == RF_2T4R) {
540 RT_TRACE(COMP_INIT, "\n2T4R config\n");
541 }
542
543 rtl92e_init_adaptive_rate(dev);
544
545 priv->rf_chip = RF_8256;
546
547 if (priv->RegChannelPlan == 0xf)
548 priv->ChannelPlan = priv->eeprom_ChannelPlan;
549 else
550 priv->ChannelPlan = priv->RegChannelPlan;
551
552 if (priv->eeprom_vid == 0x1186 && priv->eeprom_did == 0x3304)
553 priv->CustomerID = RT_CID_DLINK;
554
555 switch (priv->eeprom_CustomerID) {
556 case EEPROM_CID_DEFAULT:
557 priv->CustomerID = RT_CID_DEFAULT;
558 break;
559 case EEPROM_CID_CAMEO:
560 priv->CustomerID = RT_CID_819x_CAMEO;
561 break;
562 case EEPROM_CID_RUNTOP:
563 priv->CustomerID = RT_CID_819x_RUNTOP;
564 break;
565 case EEPROM_CID_NetCore:
566 priv->CustomerID = RT_CID_819x_Netcore;
567 break;
568 case EEPROM_CID_TOSHIBA:
569 priv->CustomerID = RT_CID_TOSHIBA;
570 if (priv->eeprom_ChannelPlan&0x80)
571 priv->ChannelPlan = priv->eeprom_ChannelPlan&0x7f;
572 else
573 priv->ChannelPlan = 0x0;
574 RT_TRACE(COMP_INIT, "Toshiba ChannelPlan = 0x%x\n",
575 priv->ChannelPlan);
576 break;
577 case EEPROM_CID_Nettronix:
578 priv->ScanDelay = 100;
579 priv->CustomerID = RT_CID_Nettronix;
580 break;
581 case EEPROM_CID_Pronet:
582 priv->CustomerID = RT_CID_PRONET;
583 break;
584 case EEPROM_CID_DLINK:
585 priv->CustomerID = RT_CID_DLINK;
586 break;
587
588 case EEPROM_CID_WHQL:
589 break;
590 default:
591 break;
592 }
593
594 if (priv->ChannelPlan > CHANNEL_PLAN_LEN - 1)
595 priv->ChannelPlan = 0;
596 priv->ChannelPlan = COUNTRY_CODE_WORLD_WIDE_13;
597
598 if (priv->eeprom_vid == 0x1186 && priv->eeprom_did == 0x3304)
599 priv->rtllib->bSupportRemoteWakeUp = true;
600 else
601 priv->rtllib->bSupportRemoteWakeUp = false;
602
603 RT_TRACE(COMP_INIT, "RegChannelPlan(%d)\n", priv->RegChannelPlan);
604 RT_TRACE(COMP_INIT, "ChannelPlan = %d\n", priv->ChannelPlan);
605 RT_TRACE(COMP_TRACE, "<==== ReadAdapterInfo\n");
606 }
607
rtl92e_get_eeprom_size(struct net_device * dev)608 void rtl92e_get_eeprom_size(struct net_device *dev)
609 {
610 u16 curCR;
611 struct r8192_priv *priv = rtllib_priv(dev);
612
613 RT_TRACE(COMP_INIT, "===========>%s()\n", __func__);
614 curCR = rtl92e_readw(dev, EPROM_CMD);
615 RT_TRACE(COMP_INIT, "read from Reg Cmd9346CR(%x):%x\n", EPROM_CMD,
616 curCR);
617 priv->epromtype = (curCR & EPROM_CMD_9356SEL) ? EEPROM_93C56 :
618 EEPROM_93C46;
619 RT_TRACE(COMP_INIT, "<===========%s(), epromtype:%d\n", __func__,
620 priv->epromtype);
621 _rtl92e_read_eeprom_info(dev);
622 }
623
_rtl92e_hwconfig(struct net_device * dev)624 static void _rtl92e_hwconfig(struct net_device *dev)
625 {
626 u32 regRATR = 0, regRRSR = 0;
627 u8 regBwOpMode = 0, regTmp = 0;
628 struct r8192_priv *priv = rtllib_priv(dev);
629
630 switch (priv->rtllib->mode) {
631 case WIRELESS_MODE_B:
632 regBwOpMode = BW_OPMODE_20MHZ;
633 regRATR = RATE_ALL_CCK;
634 regRRSR = RATE_ALL_CCK;
635 break;
636 case WIRELESS_MODE_A:
637 regBwOpMode = BW_OPMODE_5G | BW_OPMODE_20MHZ;
638 regRATR = RATE_ALL_OFDM_AG;
639 regRRSR = RATE_ALL_OFDM_AG;
640 break;
641 case WIRELESS_MODE_G:
642 regBwOpMode = BW_OPMODE_20MHZ;
643 regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
644 regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
645 break;
646 case WIRELESS_MODE_AUTO:
647 case WIRELESS_MODE_N_24G:
648 regBwOpMode = BW_OPMODE_20MHZ;
649 regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG |
650 RATE_ALL_OFDM_1SS | RATE_ALL_OFDM_2SS;
651 regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
652 break;
653 case WIRELESS_MODE_N_5G:
654 regBwOpMode = BW_OPMODE_5G;
655 regRATR = RATE_ALL_OFDM_AG | RATE_ALL_OFDM_1SS |
656 RATE_ALL_OFDM_2SS;
657 regRRSR = RATE_ALL_OFDM_AG;
658 break;
659 default:
660 regBwOpMode = BW_OPMODE_20MHZ;
661 regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
662 regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
663 break;
664 }
665
666 rtl92e_writeb(dev, BW_OPMODE, regBwOpMode);
667 {
668 u32 ratr_value;
669
670 ratr_value = regRATR;
671 if (priv->rf_type == RF_1T2R)
672 ratr_value &= ~(RATE_ALL_OFDM_2SS);
673 rtl92e_writel(dev, RATR0, ratr_value);
674 rtl92e_writeb(dev, UFWP, 1);
675 }
676 regTmp = rtl92e_readb(dev, 0x313);
677 regRRSR = ((regTmp) << 24) | (regRRSR & 0x00ffffff);
678 rtl92e_writel(dev, RRSR, regRRSR);
679
680 rtl92e_writew(dev, RETRY_LIMIT,
681 priv->ShortRetryLimit << RETRY_LIMIT_SHORT_SHIFT |
682 priv->LongRetryLimit << RETRY_LIMIT_LONG_SHIFT);
683 }
684
rtl92e_start_adapter(struct net_device * dev)685 bool rtl92e_start_adapter(struct net_device *dev)
686 {
687 struct r8192_priv *priv = rtllib_priv(dev);
688 u32 ulRegRead;
689 bool rtStatus = true;
690 u8 tmpvalue;
691 u8 ICVersion, SwitchingRegulatorOutput;
692 bool bfirmwareok = true;
693 u32 tmpRegA, TempCCk;
694 int i = 0;
695 u32 retry_times = 0;
696
697 RT_TRACE(COMP_INIT, "====>%s()\n", __func__);
698 priv->being_init_adapter = true;
699
700 start:
701 rtl92e_reset_desc_ring(dev);
702 priv->Rf_Mode = RF_OP_By_SW_3wire;
703 if (priv->ResetProgress == RESET_TYPE_NORESET) {
704 rtl92e_writeb(dev, ANAPAR, 0x37);
705 mdelay(500);
706 }
707 priv->pFirmware->status = FW_STATUS_0_INIT;
708
709 if (priv->RegRfOff)
710 priv->rtllib->eRFPowerState = eRfOff;
711
712 ulRegRead = rtl92e_readl(dev, CPU_GEN);
713 if (priv->pFirmware->status == FW_STATUS_0_INIT)
714 ulRegRead |= CPU_GEN_SYSTEM_RESET;
715 else if (priv->pFirmware->status == FW_STATUS_5_READY)
716 ulRegRead |= CPU_GEN_FIRMWARE_RESET;
717 else
718 netdev_err(dev, "%s(): undefined firmware state: %d.\n",
719 __func__, priv->pFirmware->status);
720
721 rtl92e_writel(dev, CPU_GEN, ulRegRead);
722
723 ICVersion = rtl92e_readb(dev, IC_VERRSION);
724 if (ICVersion >= 0x4) {
725 SwitchingRegulatorOutput = rtl92e_readb(dev, SWREGULATOR);
726 if (SwitchingRegulatorOutput != 0xb8) {
727 rtl92e_writeb(dev, SWREGULATOR, 0xa8);
728 mdelay(1);
729 rtl92e_writeb(dev, SWREGULATOR, 0xb8);
730 }
731 }
732 RT_TRACE(COMP_INIT, "BB Config Start!\n");
733 rtStatus = rtl92e_config_bb(dev);
734 if (!rtStatus) {
735 netdev_warn(dev, "%s(): Failed to configure BB\n", __func__);
736 return rtStatus;
737 }
738 RT_TRACE(COMP_INIT, "BB Config Finished!\n");
739
740 priv->LoopbackMode = RTL819X_NO_LOOPBACK;
741 if (priv->ResetProgress == RESET_TYPE_NORESET) {
742 ulRegRead = rtl92e_readl(dev, CPU_GEN);
743 if (priv->LoopbackMode == RTL819X_NO_LOOPBACK)
744 ulRegRead = (ulRegRead & CPU_GEN_NO_LOOPBACK_MSK) |
745 CPU_GEN_NO_LOOPBACK_SET;
746 else if (priv->LoopbackMode == RTL819X_MAC_LOOPBACK)
747 ulRegRead |= CPU_CCK_LOOPBACK;
748 else
749 netdev_err(dev, "%s: Invalid loopback mode setting.\n",
750 __func__);
751
752 rtl92e_writel(dev, CPU_GEN, ulRegRead);
753
754 udelay(500);
755 }
756 _rtl92e_hwconfig(dev);
757 rtl92e_writeb(dev, CMDR, CR_RE | CR_TE);
758
759 rtl92e_writeb(dev, PCIF, ((MXDMA2_NoLimit<<MXDMA2_RX_SHIFT) |
760 (MXDMA2_NoLimit<<MXDMA2_TX_SHIFT)));
761 rtl92e_writel(dev, MAC0, ((u32 *)dev->dev_addr)[0]);
762 rtl92e_writew(dev, MAC4, ((u16 *)(dev->dev_addr + 4))[0]);
763 rtl92e_writel(dev, RCR, priv->ReceiveConfig);
764
765 rtl92e_writel(dev, RQPN1, NUM_OF_PAGE_IN_FW_QUEUE_BK <<
766 RSVD_FW_QUEUE_PAGE_BK_SHIFT |
767 NUM_OF_PAGE_IN_FW_QUEUE_BE <<
768 RSVD_FW_QUEUE_PAGE_BE_SHIFT |
769 NUM_OF_PAGE_IN_FW_QUEUE_VI <<
770 RSVD_FW_QUEUE_PAGE_VI_SHIFT |
771 NUM_OF_PAGE_IN_FW_QUEUE_VO <<
772 RSVD_FW_QUEUE_PAGE_VO_SHIFT);
773 rtl92e_writel(dev, RQPN2, NUM_OF_PAGE_IN_FW_QUEUE_MGNT <<
774 RSVD_FW_QUEUE_PAGE_MGNT_SHIFT);
775 rtl92e_writel(dev, RQPN3, APPLIED_RESERVED_QUEUE_IN_FW |
776 NUM_OF_PAGE_IN_FW_QUEUE_BCN <<
777 RSVD_FW_QUEUE_PAGE_BCN_SHIFT|
778 NUM_OF_PAGE_IN_FW_QUEUE_PUB <<
779 RSVD_FW_QUEUE_PAGE_PUB_SHIFT);
780
781 rtl92e_tx_enable(dev);
782 rtl92e_rx_enable(dev);
783 ulRegRead = (0xFFF00000 & rtl92e_readl(dev, RRSR)) |
784 RATE_ALL_OFDM_AG | RATE_ALL_CCK;
785 rtl92e_writel(dev, RRSR, ulRegRead);
786 rtl92e_writel(dev, RATR0+4*7, (RATE_ALL_OFDM_AG | RATE_ALL_CCK));
787
788 rtl92e_writeb(dev, ACK_TIMEOUT, 0x30);
789
790 if (priv->ResetProgress == RESET_TYPE_NORESET)
791 rtl92e_set_wireless_mode(dev, priv->rtllib->mode);
792 rtl92e_cam_reset(dev);
793 {
794 u8 SECR_value = 0x0;
795
796 SECR_value |= SCR_TxEncEnable;
797 SECR_value |= SCR_RxDecEnable;
798 SECR_value |= SCR_NoSKMC;
799 rtl92e_writeb(dev, SECR, SECR_value);
800 }
801 rtl92e_writew(dev, ATIMWND, 2);
802 rtl92e_writew(dev, BCN_INTERVAL, 100);
803
804 for (i = 0; i < QOS_QUEUE_NUM; i++)
805 rtl92e_writel(dev, WDCAPARA_ADD[i], 0x005e4332);
806
807 rtl92e_writeb(dev, 0xbe, 0xc0);
808
809 rtl92e_config_mac(dev);
810
811 if (priv->card_8192_version > (u8) VERSION_8190_BD) {
812 rtl92e_get_tx_power(dev);
813 rtl92e_set_tx_power(dev, priv->chan);
814 }
815
816 tmpvalue = rtl92e_readb(dev, IC_VERRSION);
817 priv->IC_Cut = tmpvalue;
818 RT_TRACE(COMP_INIT, "priv->IC_Cut= 0x%x\n", priv->IC_Cut);
819 if (priv->IC_Cut >= IC_VersionCut_D) {
820 if (priv->IC_Cut == IC_VersionCut_D) {
821 /* no matter what checkpatch says, braces are needed */
822 RT_TRACE(COMP_INIT, "D-cut\n");
823 } else if (priv->IC_Cut == IC_VersionCut_E) {
824 RT_TRACE(COMP_INIT, "E-cut\n");
825 }
826 } else {
827 RT_TRACE(COMP_INIT, "Before C-cut\n");
828 }
829
830 RT_TRACE(COMP_INIT, "Load Firmware!\n");
831 bfirmwareok = rtl92e_init_fw(dev);
832 if (!bfirmwareok) {
833 if (retry_times < 10) {
834 retry_times++;
835 goto start;
836 } else {
837 rtStatus = false;
838 goto end;
839 }
840 }
841 RT_TRACE(COMP_INIT, "Load Firmware finished!\n");
842 if (priv->ResetProgress == RESET_TYPE_NORESET) {
843 RT_TRACE(COMP_INIT, "RF Config Started!\n");
844 rtStatus = rtl92e_config_phy(dev);
845 if (!rtStatus) {
846 netdev_info(dev, "RF Config failed\n");
847 return rtStatus;
848 }
849 RT_TRACE(COMP_INIT, "RF Config Finished!\n");
850 }
851
852 rtl92e_set_bb_reg(dev, rFPGA0_RFMOD, bCCKEn, 0x1);
853 rtl92e_set_bb_reg(dev, rFPGA0_RFMOD, bOFDMEn, 0x1);
854
855 rtl92e_writeb(dev, 0x87, 0x0);
856
857 if (priv->RegRfOff) {
858 RT_TRACE((COMP_INIT | COMP_RF | COMP_POWER),
859 "%s(): Turn off RF for RegRfOff ----------\n",
860 __func__);
861 rtl92e_set_rf_state(dev, eRfOff, RF_CHANGE_BY_SW);
862 } else if (priv->rtllib->RfOffReason > RF_CHANGE_BY_PS) {
863 RT_TRACE((COMP_INIT|COMP_RF|COMP_POWER),
864 "%s(): Turn off RF for RfOffReason(%d) ----------\n",
865 __func__, priv->rtllib->RfOffReason);
866 rtl92e_set_rf_state(dev, eRfOff, priv->rtllib->RfOffReason);
867 } else if (priv->rtllib->RfOffReason >= RF_CHANGE_BY_IPS) {
868 RT_TRACE((COMP_INIT|COMP_RF|COMP_POWER),
869 "%s(): Turn off RF for RfOffReason(%d) ----------\n",
870 __func__, priv->rtllib->RfOffReason);
871 rtl92e_set_rf_state(dev, eRfOff, priv->rtllib->RfOffReason);
872 } else {
873 RT_TRACE((COMP_INIT|COMP_RF|COMP_POWER), "%s(): RF-ON\n",
874 __func__);
875 priv->rtllib->eRFPowerState = eRfOn;
876 priv->rtllib->RfOffReason = 0;
877 }
878
879 if (priv->rtllib->FwRWRF)
880 priv->Rf_Mode = RF_OP_By_FW;
881 else
882 priv->Rf_Mode = RF_OP_By_SW_3wire;
883
884 if (priv->ResetProgress == RESET_TYPE_NORESET) {
885 rtl92e_dm_init_txpower_tracking(dev);
886
887 if (priv->IC_Cut >= IC_VersionCut_D) {
888 tmpRegA = rtl92e_get_bb_reg(dev, rOFDM0_XATxIQImbalance,
889 bMaskDWord);
890 rtl92e_get_bb_reg(dev, rOFDM0_XCTxIQImbalance, bMaskDWord);
891
892 for (i = 0; i < TxBBGainTableLength; i++) {
893 if (tmpRegA == dm_tx_bb_gain[i]) {
894 priv->rfa_txpowertrackingindex = (u8)i;
895 priv->rfa_txpowertrackingindex_real =
896 (u8)i;
897 priv->rfa_txpowertracking_default =
898 priv->rfa_txpowertrackingindex;
899 break;
900 }
901 }
902
903 TempCCk = rtl92e_get_bb_reg(dev, rCCK0_TxFilter1,
904 bMaskByte2);
905
906 for (i = 0; i < CCKTxBBGainTableLength; i++) {
907 if (TempCCk == dm_cck_tx_bb_gain[i][0]) {
908 priv->CCKPresentAttentuation_20Mdefault = (u8)i;
909 break;
910 }
911 }
912 priv->CCKPresentAttentuation_40Mdefault = 0;
913 priv->CCKPresentAttentuation_difference = 0;
914 priv->CCKPresentAttentuation =
915 priv->CCKPresentAttentuation_20Mdefault;
916 RT_TRACE(COMP_POWER_TRACKING,
917 "priv->rfa_txpowertrackingindex_initial = %d\n",
918 priv->rfa_txpowertrackingindex);
919 RT_TRACE(COMP_POWER_TRACKING,
920 "priv->rfa_txpowertrackingindex_real__initial = %d\n",
921 priv->rfa_txpowertrackingindex_real);
922 RT_TRACE(COMP_POWER_TRACKING,
923 "priv->CCKPresentAttentuation_difference_initial = %d\n",
924 priv->CCKPresentAttentuation_difference);
925 RT_TRACE(COMP_POWER_TRACKING,
926 "priv->CCKPresentAttentuation_initial = %d\n",
927 priv->CCKPresentAttentuation);
928 priv->btxpower_tracking = false;
929 }
930 }
931 rtl92e_irq_enable(dev);
932 end:
933 priv->being_init_adapter = false;
934 return rtStatus;
935 }
936
_rtl92e_net_update(struct net_device * dev)937 static void _rtl92e_net_update(struct net_device *dev)
938 {
939
940 struct r8192_priv *priv = rtllib_priv(dev);
941 struct rtllib_network *net;
942 u16 BcnTimeCfg = 0, BcnCW = 6, BcnIFS = 0xf;
943 u16 rate_config = 0;
944
945 net = &priv->rtllib->current_network;
946 rtl92e_config_rate(dev, &rate_config);
947 priv->dot11CurrentPreambleMode = PREAMBLE_AUTO;
948 priv->basic_rate = rate_config &= 0x15f;
949 rtl92e_writew(dev, BSSIDR, *(u16 *)net->bssid);
950 rtl92e_writel(dev, BSSIDR + 2, *(u32 *)(net->bssid + 2));
951
952 if (priv->rtllib->iw_mode == IW_MODE_ADHOC) {
953 rtl92e_writew(dev, ATIMWND, 2);
954 rtl92e_writew(dev, BCN_DMATIME, 256);
955 rtl92e_writew(dev, BCN_INTERVAL, net->beacon_interval);
956 rtl92e_writew(dev, BCN_DRV_EARLY_INT, 10);
957 rtl92e_writeb(dev, BCN_ERR_THRESH, 100);
958
959 BcnTimeCfg |= (BcnCW<<BCN_TCFG_CW_SHIFT);
960 BcnTimeCfg |= BcnIFS<<BCN_TCFG_IFS;
961
962 rtl92e_writew(dev, BCN_TCFG, BcnTimeCfg);
963 }
964 }
965
rtl92e_link_change(struct net_device * dev)966 void rtl92e_link_change(struct net_device *dev)
967 {
968 struct r8192_priv *priv = rtllib_priv(dev);
969 struct rtllib_device *ieee = priv->rtllib;
970
971 if (!priv->up)
972 return;
973
974 if (ieee->state == RTLLIB_LINKED) {
975 _rtl92e_net_update(dev);
976 priv->ops->update_ratr_table(dev);
977 if ((ieee->pairwise_key_type == KEY_TYPE_WEP40) ||
978 (ieee->pairwise_key_type == KEY_TYPE_WEP104))
979 rtl92e_enable_hw_security_config(dev);
980 } else {
981 rtl92e_writeb(dev, 0x173, 0);
982 }
983 _rtl92e_update_msr(dev);
984
985 if (ieee->iw_mode == IW_MODE_INFRA || ieee->iw_mode == IW_MODE_ADHOC) {
986 u32 reg;
987
988 reg = rtl92e_readl(dev, RCR);
989 if (priv->rtllib->state == RTLLIB_LINKED) {
990 if (ieee->IntelPromiscuousModeInfo.bPromiscuousOn)
991 ;
992 else
993 priv->ReceiveConfig = reg |= RCR_CBSSID;
994 } else
995 priv->ReceiveConfig = reg &= ~RCR_CBSSID;
996
997 rtl92e_writel(dev, RCR, reg);
998 }
999 }
1000
rtl92e_set_monitor_mode(struct net_device * dev,bool bAllowAllDA,bool WriteIntoReg)1001 void rtl92e_set_monitor_mode(struct net_device *dev, bool bAllowAllDA,
1002 bool WriteIntoReg)
1003 {
1004 struct r8192_priv *priv = rtllib_priv(dev);
1005
1006 if (bAllowAllDA)
1007 priv->ReceiveConfig |= RCR_AAP;
1008 else
1009 priv->ReceiveConfig &= ~RCR_AAP;
1010
1011 if (WriteIntoReg)
1012 rtl92e_writel(dev, RCR, priv->ReceiveConfig);
1013 }
1014
_rtl92e_rate_mgn_to_hw(u8 rate)1015 static u8 _rtl92e_rate_mgn_to_hw(u8 rate)
1016 {
1017 u8 ret = DESC90_RATE1M;
1018
1019 switch (rate) {
1020 case MGN_1M:
1021 ret = DESC90_RATE1M;
1022 break;
1023 case MGN_2M:
1024 ret = DESC90_RATE2M;
1025 break;
1026 case MGN_5_5M:
1027 ret = DESC90_RATE5_5M;
1028 break;
1029 case MGN_11M:
1030 ret = DESC90_RATE11M;
1031 break;
1032 case MGN_6M:
1033 ret = DESC90_RATE6M;
1034 break;
1035 case MGN_9M:
1036 ret = DESC90_RATE9M;
1037 break;
1038 case MGN_12M:
1039 ret = DESC90_RATE12M;
1040 break;
1041 case MGN_18M:
1042 ret = DESC90_RATE18M;
1043 break;
1044 case MGN_24M:
1045 ret = DESC90_RATE24M;
1046 break;
1047 case MGN_36M:
1048 ret = DESC90_RATE36M;
1049 break;
1050 case MGN_48M:
1051 ret = DESC90_RATE48M;
1052 break;
1053 case MGN_54M:
1054 ret = DESC90_RATE54M;
1055 break;
1056 case MGN_MCS0:
1057 ret = DESC90_RATEMCS0;
1058 break;
1059 case MGN_MCS1:
1060 ret = DESC90_RATEMCS1;
1061 break;
1062 case MGN_MCS2:
1063 ret = DESC90_RATEMCS2;
1064 break;
1065 case MGN_MCS3:
1066 ret = DESC90_RATEMCS3;
1067 break;
1068 case MGN_MCS4:
1069 ret = DESC90_RATEMCS4;
1070 break;
1071 case MGN_MCS5:
1072 ret = DESC90_RATEMCS5;
1073 break;
1074 case MGN_MCS6:
1075 ret = DESC90_RATEMCS6;
1076 break;
1077 case MGN_MCS7:
1078 ret = DESC90_RATEMCS7;
1079 break;
1080 case MGN_MCS8:
1081 ret = DESC90_RATEMCS8;
1082 break;
1083 case MGN_MCS9:
1084 ret = DESC90_RATEMCS9;
1085 break;
1086 case MGN_MCS10:
1087 ret = DESC90_RATEMCS10;
1088 break;
1089 case MGN_MCS11:
1090 ret = DESC90_RATEMCS11;
1091 break;
1092 case MGN_MCS12:
1093 ret = DESC90_RATEMCS12;
1094 break;
1095 case MGN_MCS13:
1096 ret = DESC90_RATEMCS13;
1097 break;
1098 case MGN_MCS14:
1099 ret = DESC90_RATEMCS14;
1100 break;
1101 case MGN_MCS15:
1102 ret = DESC90_RATEMCS15;
1103 break;
1104 case (0x80|0x20):
1105 ret = DESC90_RATEMCS32;
1106 break;
1107 default:
1108 break;
1109 }
1110 return ret;
1111 }
1112
_rtl92e_hw_queue_to_fw_queue(struct net_device * dev,u8 QueueID,u8 priority)1113 static u8 _rtl92e_hw_queue_to_fw_queue(struct net_device *dev, u8 QueueID,
1114 u8 priority)
1115 {
1116 u8 QueueSelect = 0x0;
1117
1118 switch (QueueID) {
1119 case BE_QUEUE:
1120 QueueSelect = QSLT_BE;
1121 break;
1122
1123 case BK_QUEUE:
1124 QueueSelect = QSLT_BK;
1125 break;
1126
1127 case VO_QUEUE:
1128 QueueSelect = QSLT_VO;
1129 break;
1130
1131 case VI_QUEUE:
1132 QueueSelect = QSLT_VI;
1133 break;
1134 case MGNT_QUEUE:
1135 QueueSelect = QSLT_MGNT;
1136 break;
1137 case BEACON_QUEUE:
1138 QueueSelect = QSLT_BEACON;
1139 break;
1140 case TXCMD_QUEUE:
1141 QueueSelect = QSLT_CMD;
1142 break;
1143 case HIGH_QUEUE:
1144 QueueSelect = QSLT_HIGH;
1145 break;
1146 default:
1147 netdev_warn(dev, "%s(): Impossible Queue Selection: %d\n",
1148 __func__, QueueID);
1149 break;
1150 }
1151 return QueueSelect;
1152 }
1153
_rtl92e_query_is_short(u8 TxHT,u8 TxRate,struct cb_desc * tcb_desc)1154 static u8 _rtl92e_query_is_short(u8 TxHT, u8 TxRate, struct cb_desc *tcb_desc)
1155 {
1156 u8 tmp_Short;
1157
1158 tmp_Short = (TxHT == 1) ? ((tcb_desc->bUseShortGI) ? 1 : 0) :
1159 ((tcb_desc->bUseShortPreamble) ? 1 : 0);
1160 if (TxHT == 1 && TxRate != DESC90_RATEMCS15)
1161 tmp_Short = 0;
1162
1163 return tmp_Short;
1164 }
1165
rtl92e_fill_tx_desc(struct net_device * dev,struct tx_desc * pdesc,struct cb_desc * cb_desc,struct sk_buff * skb)1166 void rtl92e_fill_tx_desc(struct net_device *dev, struct tx_desc *pdesc,
1167 struct cb_desc *cb_desc, struct sk_buff *skb)
1168 {
1169 struct r8192_priv *priv = rtllib_priv(dev);
1170 dma_addr_t mapping;
1171 struct tx_fwinfo_8190pci *pTxFwInfo;
1172
1173 pTxFwInfo = (struct tx_fwinfo_8190pci *)skb->data;
1174 memset(pTxFwInfo, 0, sizeof(struct tx_fwinfo_8190pci));
1175 pTxFwInfo->TxHT = (cb_desc->data_rate & 0x80) ? 1 : 0;
1176 pTxFwInfo->TxRate = _rtl92e_rate_mgn_to_hw((u8)cb_desc->data_rate);
1177 pTxFwInfo->EnableCPUDur = cb_desc->bTxEnableFwCalcDur;
1178 pTxFwInfo->Short = _rtl92e_query_is_short(pTxFwInfo->TxHT,
1179 pTxFwInfo->TxRate, cb_desc);
1180
1181 if (cb_desc->bAMPDUEnable) {
1182 pTxFwInfo->AllowAggregation = 1;
1183 pTxFwInfo->RxMF = cb_desc->ampdu_factor;
1184 pTxFwInfo->RxAMD = cb_desc->ampdu_density;
1185 } else {
1186 pTxFwInfo->AllowAggregation = 0;
1187 pTxFwInfo->RxMF = 0;
1188 pTxFwInfo->RxAMD = 0;
1189 }
1190
1191 pTxFwInfo->RtsEnable = (cb_desc->bRTSEnable) ? 1 : 0;
1192 pTxFwInfo->CtsEnable = (cb_desc->bCTSEnable) ? 1 : 0;
1193 pTxFwInfo->RtsSTBC = (cb_desc->bRTSSTBC) ? 1 : 0;
1194 pTxFwInfo->RtsHT = (cb_desc->rts_rate&0x80) ? 1 : 0;
1195 pTxFwInfo->RtsRate = _rtl92e_rate_mgn_to_hw((u8)cb_desc->rts_rate);
1196 pTxFwInfo->RtsBandwidth = 0;
1197 pTxFwInfo->RtsSubcarrier = cb_desc->RTSSC;
1198 pTxFwInfo->RtsShort = (pTxFwInfo->RtsHT == 0) ?
1199 (cb_desc->bRTSUseShortPreamble ? 1 : 0) :
1200 (cb_desc->bRTSUseShortGI ? 1 : 0);
1201 if (priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20_40) {
1202 if (cb_desc->bPacketBW) {
1203 pTxFwInfo->TxBandwidth = 1;
1204 pTxFwInfo->TxSubCarrier = 0;
1205 } else {
1206 pTxFwInfo->TxBandwidth = 0;
1207 pTxFwInfo->TxSubCarrier = priv->nCur40MhzPrimeSC;
1208 }
1209 } else {
1210 pTxFwInfo->TxBandwidth = 0;
1211 pTxFwInfo->TxSubCarrier = 0;
1212 }
1213
1214 memset((u8 *)pdesc, 0, 12);
1215
1216 mapping = dma_map_single(&priv->pdev->dev, skb->data, skb->len,
1217 DMA_TO_DEVICE);
1218 if (dma_mapping_error(&priv->pdev->dev, mapping)) {
1219 netdev_err(dev, "%s(): DMA Mapping error\n", __func__);
1220 return;
1221 }
1222
1223 pdesc->LINIP = 0;
1224 pdesc->CmdInit = 1;
1225 pdesc->Offset = sizeof(struct tx_fwinfo_8190pci) + 8;
1226 pdesc->PktSize = (u16)skb->len-sizeof(struct tx_fwinfo_8190pci);
1227
1228 pdesc->SecCAMID = 0;
1229 pdesc->RATid = cb_desc->RATRIndex;
1230
1231
1232 pdesc->NoEnc = 1;
1233 pdesc->SecType = 0x0;
1234 if (cb_desc->bHwSec) {
1235 static u8 tmp;
1236
1237 if (!tmp) {
1238 RT_TRACE(COMP_DBG, "==>================hw sec\n");
1239 tmp = 1;
1240 }
1241 switch (priv->rtllib->pairwise_key_type) {
1242 case KEY_TYPE_WEP40:
1243 case KEY_TYPE_WEP104:
1244 pdesc->SecType = 0x1;
1245 pdesc->NoEnc = 0;
1246 break;
1247 case KEY_TYPE_TKIP:
1248 pdesc->SecType = 0x2;
1249 pdesc->NoEnc = 0;
1250 break;
1251 case KEY_TYPE_CCMP:
1252 pdesc->SecType = 0x3;
1253 pdesc->NoEnc = 0;
1254 break;
1255 case KEY_TYPE_NA:
1256 pdesc->SecType = 0x0;
1257 pdesc->NoEnc = 1;
1258 break;
1259 }
1260 }
1261
1262 pdesc->PktId = 0x0;
1263
1264 pdesc->QueueSelect = _rtl92e_hw_queue_to_fw_queue(dev,
1265 cb_desc->queue_index,
1266 cb_desc->priority);
1267 pdesc->TxFWInfoSize = sizeof(struct tx_fwinfo_8190pci);
1268
1269 pdesc->DISFB = cb_desc->bTxDisableRateFallBack;
1270 pdesc->USERATE = cb_desc->bTxUseDriverAssingedRate;
1271
1272 pdesc->FirstSeg = 1;
1273 pdesc->LastSeg = 1;
1274 pdesc->TxBufferSize = skb->len;
1275
1276 pdesc->TxBuffAddr = mapping;
1277 }
1278
rtl92e_fill_tx_cmd_desc(struct net_device * dev,struct tx_desc_cmd * entry,struct cb_desc * cb_desc,struct sk_buff * skb)1279 void rtl92e_fill_tx_cmd_desc(struct net_device *dev, struct tx_desc_cmd *entry,
1280 struct cb_desc *cb_desc, struct sk_buff *skb)
1281 {
1282 struct r8192_priv *priv = rtllib_priv(dev);
1283 dma_addr_t mapping = dma_map_single(&priv->pdev->dev, skb->data,
1284 skb->len, DMA_TO_DEVICE);
1285
1286 if (dma_mapping_error(&priv->pdev->dev, mapping))
1287 netdev_err(dev, "%s(): DMA Mapping error\n", __func__);
1288 memset(entry, 0, 12);
1289 entry->LINIP = cb_desc->bLastIniPkt;
1290 entry->FirstSeg = 1;
1291 entry->LastSeg = 1;
1292 if (cb_desc->bCmdOrInit == DESC_PACKET_TYPE_INIT) {
1293 entry->CmdInit = DESC_PACKET_TYPE_INIT;
1294 } else {
1295 struct tx_desc *entry_tmp = (struct tx_desc *)entry;
1296
1297 entry_tmp->CmdInit = DESC_PACKET_TYPE_NORMAL;
1298 entry_tmp->Offset = sizeof(struct tx_fwinfo_8190pci) + 8;
1299 entry_tmp->PktSize = (u16)(cb_desc->pkt_size +
1300 entry_tmp->Offset);
1301 entry_tmp->QueueSelect = QSLT_CMD;
1302 entry_tmp->TxFWInfoSize = 0x08;
1303 entry_tmp->RATid = (u8)DESC_PACKET_TYPE_INIT;
1304 }
1305 entry->TxBufferSize = skb->len;
1306 entry->TxBuffAddr = mapping;
1307 entry->OWN = 1;
1308 }
1309
_rtl92e_rate_hw_to_mgn(bool bIsHT,u8 rate)1310 static u8 _rtl92e_rate_hw_to_mgn(bool bIsHT, u8 rate)
1311 {
1312 u8 ret_rate = 0x02;
1313
1314 if (!bIsHT) {
1315 switch (rate) {
1316 case DESC90_RATE1M:
1317 ret_rate = MGN_1M;
1318 break;
1319 case DESC90_RATE2M:
1320 ret_rate = MGN_2M;
1321 break;
1322 case DESC90_RATE5_5M:
1323 ret_rate = MGN_5_5M;
1324 break;
1325 case DESC90_RATE11M:
1326 ret_rate = MGN_11M;
1327 break;
1328 case DESC90_RATE6M:
1329 ret_rate = MGN_6M;
1330 break;
1331 case DESC90_RATE9M:
1332 ret_rate = MGN_9M;
1333 break;
1334 case DESC90_RATE12M:
1335 ret_rate = MGN_12M;
1336 break;
1337 case DESC90_RATE18M:
1338 ret_rate = MGN_18M;
1339 break;
1340 case DESC90_RATE24M:
1341 ret_rate = MGN_24M;
1342 break;
1343 case DESC90_RATE36M:
1344 ret_rate = MGN_36M;
1345 break;
1346 case DESC90_RATE48M:
1347 ret_rate = MGN_48M;
1348 break;
1349 case DESC90_RATE54M:
1350 ret_rate = MGN_54M;
1351 break;
1352
1353 default:
1354 RT_TRACE(COMP_RECV,
1355 "%s: Non supportedRate [%x], bIsHT = %d!!!\n",
1356 __func__, rate, bIsHT);
1357 break;
1358 }
1359
1360 } else {
1361 switch (rate) {
1362 case DESC90_RATEMCS0:
1363 ret_rate = MGN_MCS0;
1364 break;
1365 case DESC90_RATEMCS1:
1366 ret_rate = MGN_MCS1;
1367 break;
1368 case DESC90_RATEMCS2:
1369 ret_rate = MGN_MCS2;
1370 break;
1371 case DESC90_RATEMCS3:
1372 ret_rate = MGN_MCS3;
1373 break;
1374 case DESC90_RATEMCS4:
1375 ret_rate = MGN_MCS4;
1376 break;
1377 case DESC90_RATEMCS5:
1378 ret_rate = MGN_MCS5;
1379 break;
1380 case DESC90_RATEMCS6:
1381 ret_rate = MGN_MCS6;
1382 break;
1383 case DESC90_RATEMCS7:
1384 ret_rate = MGN_MCS7;
1385 break;
1386 case DESC90_RATEMCS8:
1387 ret_rate = MGN_MCS8;
1388 break;
1389 case DESC90_RATEMCS9:
1390 ret_rate = MGN_MCS9;
1391 break;
1392 case DESC90_RATEMCS10:
1393 ret_rate = MGN_MCS10;
1394 break;
1395 case DESC90_RATEMCS11:
1396 ret_rate = MGN_MCS11;
1397 break;
1398 case DESC90_RATEMCS12:
1399 ret_rate = MGN_MCS12;
1400 break;
1401 case DESC90_RATEMCS13:
1402 ret_rate = MGN_MCS13;
1403 break;
1404 case DESC90_RATEMCS14:
1405 ret_rate = MGN_MCS14;
1406 break;
1407 case DESC90_RATEMCS15:
1408 ret_rate = MGN_MCS15;
1409 break;
1410 case DESC90_RATEMCS32:
1411 ret_rate = 0x80 | 0x20;
1412 break;
1413
1414 default:
1415 RT_TRACE(COMP_RECV,
1416 "%s: Non supported Rate [%x], bIsHT = %d!!!\n",
1417 __func__, rate, bIsHT);
1418 break;
1419 }
1420 }
1421
1422 return ret_rate;
1423 }
1424
_rtl92e_signal_scale_mapping(struct r8192_priv * priv,long currsig)1425 static long _rtl92e_signal_scale_mapping(struct r8192_priv *priv, long currsig)
1426 {
1427 long retsig;
1428
1429 if (currsig >= 61 && currsig <= 100)
1430 retsig = 90 + ((currsig - 60) / 4);
1431 else if (currsig >= 41 && currsig <= 60)
1432 retsig = 78 + ((currsig - 40) / 2);
1433 else if (currsig >= 31 && currsig <= 40)
1434 retsig = 66 + (currsig - 30);
1435 else if (currsig >= 21 && currsig <= 30)
1436 retsig = 54 + (currsig - 20);
1437 else if (currsig >= 5 && currsig <= 20)
1438 retsig = 42 + (((currsig - 5) * 2) / 3);
1439 else if (currsig == 4)
1440 retsig = 36;
1441 else if (currsig == 3)
1442 retsig = 27;
1443 else if (currsig == 2)
1444 retsig = 18;
1445 else if (currsig == 1)
1446 retsig = 9;
1447 else
1448 retsig = currsig;
1449
1450 return retsig;
1451 }
1452
1453
1454 #define rx_hal_is_cck_rate(_pdrvinfo)\
1455 ((_pdrvinfo->RxRate == DESC90_RATE1M ||\
1456 _pdrvinfo->RxRate == DESC90_RATE2M ||\
1457 _pdrvinfo->RxRate == DESC90_RATE5_5M ||\
1458 _pdrvinfo->RxRate == DESC90_RATE11M) &&\
1459 !_pdrvinfo->RxHT)
1460
_rtl92e_query_rxphystatus(struct r8192_priv * priv,struct rtllib_rx_stats * pstats,struct rx_desc * pdesc,struct rx_fwinfo * pdrvinfo,struct rtllib_rx_stats * precord_stats,bool bpacket_match_bssid,bool bpacket_toself,bool bPacketBeacon,bool bToSelfBA)1461 static void _rtl92e_query_rxphystatus(
1462 struct r8192_priv *priv,
1463 struct rtllib_rx_stats *pstats,
1464 struct rx_desc *pdesc,
1465 struct rx_fwinfo *pdrvinfo,
1466 struct rtllib_rx_stats *precord_stats,
1467 bool bpacket_match_bssid,
1468 bool bpacket_toself,
1469 bool bPacketBeacon,
1470 bool bToSelfBA
1471 )
1472 {
1473 struct phy_sts_ofdm_819xpci *pofdm_buf;
1474 struct phy_sts_cck_819xpci *pcck_buf;
1475 struct phy_ofdm_rx_status_rxsc_sgien_exintfflag *prxsc;
1476 u8 *prxpkt;
1477 u8 i, max_spatial_stream, tmp_rxsnr, tmp_rxevm, rxsc_sgien_exflg;
1478 s8 rx_pwr[4], rx_pwr_all = 0;
1479 s8 rx_snrX, rx_evmX;
1480 u8 evm, pwdb_all;
1481 u32 RSSI, total_rssi = 0;
1482 u8 is_cck_rate = 0;
1483 u8 rf_rx_num = 0;
1484 static u8 check_reg824;
1485 static u32 reg824_bit9;
1486
1487 priv->stats.numqry_phystatus++;
1488
1489 is_cck_rate = rx_hal_is_cck_rate(pdrvinfo);
1490 memset(precord_stats, 0, sizeof(struct rtllib_rx_stats));
1491 pstats->bPacketMatchBSSID = precord_stats->bPacketMatchBSSID =
1492 bpacket_match_bssid;
1493 pstats->bPacketToSelf = precord_stats->bPacketToSelf = bpacket_toself;
1494 pstats->bIsCCK = precord_stats->bIsCCK = is_cck_rate;
1495 pstats->bPacketBeacon = precord_stats->bPacketBeacon = bPacketBeacon;
1496 pstats->bToSelfBA = precord_stats->bToSelfBA = bToSelfBA;
1497 if (check_reg824 == 0) {
1498 reg824_bit9 = rtl92e_get_bb_reg(priv->rtllib->dev,
1499 rFPGA0_XA_HSSIParameter2,
1500 0x200);
1501 check_reg824 = 1;
1502 }
1503
1504
1505 prxpkt = (u8 *)pdrvinfo;
1506
1507 prxpkt += sizeof(struct rx_fwinfo);
1508
1509 pcck_buf = (struct phy_sts_cck_819xpci *)prxpkt;
1510 pofdm_buf = (struct phy_sts_ofdm_819xpci *)prxpkt;
1511
1512 pstats->RxMIMOSignalQuality[0] = -1;
1513 pstats->RxMIMOSignalQuality[1] = -1;
1514 precord_stats->RxMIMOSignalQuality[0] = -1;
1515 precord_stats->RxMIMOSignalQuality[1] = -1;
1516
1517 if (is_cck_rate) {
1518 u8 report;
1519
1520 priv->stats.numqry_phystatusCCK++;
1521 if (!reg824_bit9) {
1522 report = pcck_buf->cck_agc_rpt & 0xc0;
1523 report >>= 6;
1524 switch (report) {
1525 case 0x3:
1526 rx_pwr_all = -35 - (pcck_buf->cck_agc_rpt &
1527 0x3e);
1528 break;
1529 case 0x2:
1530 rx_pwr_all = -23 - (pcck_buf->cck_agc_rpt &
1531 0x3e);
1532 break;
1533 case 0x1:
1534 rx_pwr_all = -11 - (pcck_buf->cck_agc_rpt &
1535 0x3e);
1536 break;
1537 case 0x0:
1538 rx_pwr_all = 8 - (pcck_buf->cck_agc_rpt & 0x3e);
1539 break;
1540 }
1541 } else {
1542 report = pcck_buf->cck_agc_rpt & 0x60;
1543 report >>= 5;
1544 switch (report) {
1545 case 0x3:
1546 rx_pwr_all = -35 -
1547 ((pcck_buf->cck_agc_rpt &
1548 0x1f) << 1);
1549 break;
1550 case 0x2:
1551 rx_pwr_all = -23 -
1552 ((pcck_buf->cck_agc_rpt &
1553 0x1f) << 1);
1554 break;
1555 case 0x1:
1556 rx_pwr_all = -11 -
1557 ((pcck_buf->cck_agc_rpt &
1558 0x1f) << 1);
1559 break;
1560 case 0x0:
1561 rx_pwr_all = -8 -
1562 ((pcck_buf->cck_agc_rpt &
1563 0x1f) << 1);
1564 break;
1565 }
1566 }
1567
1568 pwdb_all = rtl92e_rx_db_to_percent(rx_pwr_all);
1569 pstats->RxPWDBAll = precord_stats->RxPWDBAll = pwdb_all;
1570 pstats->RecvSignalPower = rx_pwr_all;
1571
1572 if (bpacket_match_bssid) {
1573 u8 sq;
1574
1575 if (pstats->RxPWDBAll > 40) {
1576 sq = 100;
1577 } else {
1578 sq = pcck_buf->sq_rpt;
1579
1580 if (pcck_buf->sq_rpt > 64)
1581 sq = 0;
1582 else if (pcck_buf->sq_rpt < 20)
1583 sq = 100;
1584 else
1585 sq = ((64-sq) * 100) / 44;
1586 }
1587 pstats->SignalQuality = sq;
1588 precord_stats->SignalQuality = sq;
1589 pstats->RxMIMOSignalQuality[0] = sq;
1590 precord_stats->RxMIMOSignalQuality[0] = sq;
1591 pstats->RxMIMOSignalQuality[1] = -1;
1592 precord_stats->RxMIMOSignalQuality[1] = -1;
1593 }
1594 } else {
1595 priv->stats.numqry_phystatusHT++;
1596 for (i = RF90_PATH_A; i < RF90_PATH_MAX; i++) {
1597 if (priv->brfpath_rxenable[i])
1598 rf_rx_num++;
1599
1600 rx_pwr[i] = ((pofdm_buf->trsw_gain_X[i] & 0x3F) *
1601 2) - 110;
1602
1603 tmp_rxsnr = pofdm_buf->rxsnr_X[i];
1604 rx_snrX = (s8)(tmp_rxsnr);
1605 rx_snrX /= 2;
1606 priv->stats.rxSNRdB[i] = (long)rx_snrX;
1607
1608 RSSI = rtl92e_rx_db_to_percent(rx_pwr[i]);
1609 if (priv->brfpath_rxenable[i])
1610 total_rssi += RSSI;
1611
1612 if (bpacket_match_bssid) {
1613 pstats->RxMIMOSignalStrength[i] = (u8) RSSI;
1614 precord_stats->RxMIMOSignalStrength[i] =
1615 (u8) RSSI;
1616 }
1617 }
1618
1619
1620 rx_pwr_all = (((pofdm_buf->pwdb_all) >> 1) & 0x7f) - 106;
1621 pwdb_all = rtl92e_rx_db_to_percent(rx_pwr_all);
1622
1623 pstats->RxPWDBAll = precord_stats->RxPWDBAll = pwdb_all;
1624 pstats->RxPower = precord_stats->RxPower = rx_pwr_all;
1625 pstats->RecvSignalPower = rx_pwr_all;
1626 if (pdrvinfo->RxHT && pdrvinfo->RxRate >= DESC90_RATEMCS8 &&
1627 pdrvinfo->RxRate <= DESC90_RATEMCS15)
1628 max_spatial_stream = 2;
1629 else
1630 max_spatial_stream = 1;
1631
1632 for (i = 0; i < max_spatial_stream; i++) {
1633 tmp_rxevm = pofdm_buf->rxevm_X[i];
1634 rx_evmX = (s8)(tmp_rxevm);
1635
1636 rx_evmX /= 2;
1637
1638 evm = rtl92e_evm_db_to_percent(rx_evmX);
1639 if (bpacket_match_bssid) {
1640 if (i == 0) {
1641 pstats->SignalQuality = evm & 0xff;
1642 precord_stats->SignalQuality = evm & 0xff;
1643 }
1644 pstats->RxMIMOSignalQuality[i] = evm & 0xff;
1645 precord_stats->RxMIMOSignalQuality[i] = evm & 0xff;
1646 }
1647 }
1648
1649
1650 rxsc_sgien_exflg = pofdm_buf->rxsc_sgien_exflg;
1651 prxsc = (struct phy_ofdm_rx_status_rxsc_sgien_exintfflag *)
1652 &rxsc_sgien_exflg;
1653 if (pdrvinfo->BW)
1654 priv->stats.received_bwtype[1+prxsc->rxsc]++;
1655 else
1656 priv->stats.received_bwtype[0]++;
1657 }
1658
1659 if (is_cck_rate) {
1660 pstats->SignalStrength = precord_stats->SignalStrength =
1661 (u8)(_rtl92e_signal_scale_mapping(priv,
1662 (long)pwdb_all));
1663
1664 } else {
1665 if (rf_rx_num != 0)
1666 pstats->SignalStrength = precord_stats->SignalStrength =
1667 (u8)(_rtl92e_signal_scale_mapping(priv,
1668 (long)(total_rssi /= rf_rx_num)));
1669 }
1670 }
1671
_rtl92e_process_phyinfo(struct r8192_priv * priv,u8 * buffer,struct rtllib_rx_stats * prev_st,struct rtllib_rx_stats * curr_st)1672 static void _rtl92e_process_phyinfo(struct r8192_priv *priv, u8 *buffer,
1673 struct rtllib_rx_stats *prev_st,
1674 struct rtllib_rx_stats *curr_st)
1675 {
1676 bool bcheck = false;
1677 u8 rfpath;
1678 u32 ij, tmp_val;
1679 static u32 slide_rssi_index, slide_rssi_statistics;
1680 static u32 slide_evm_index, slide_evm_statistics;
1681 static u32 last_rssi, last_evm;
1682 static u32 slide_beacon_adc_pwdb_index;
1683 static u32 slide_beacon_adc_pwdb_statistics;
1684 static u32 last_beacon_adc_pwdb;
1685 struct rtllib_hdr_3addr *hdr;
1686 u16 sc;
1687 unsigned int seq;
1688
1689 hdr = (struct rtllib_hdr_3addr *)buffer;
1690 sc = le16_to_cpu(hdr->seq_ctl);
1691 seq = WLAN_GET_SEQ_SEQ(sc);
1692 curr_st->Seq_Num = seq;
1693 if (!prev_st->bIsAMPDU)
1694 bcheck = true;
1695
1696 if (slide_rssi_statistics++ >= PHY_RSSI_SLID_WIN_MAX) {
1697 slide_rssi_statistics = PHY_RSSI_SLID_WIN_MAX;
1698 last_rssi = priv->stats.slide_signal_strength[slide_rssi_index];
1699 priv->stats.slide_rssi_total -= last_rssi;
1700 }
1701 priv->stats.slide_rssi_total += prev_st->SignalStrength;
1702
1703 priv->stats.slide_signal_strength[slide_rssi_index++] =
1704 prev_st->SignalStrength;
1705 if (slide_rssi_index >= PHY_RSSI_SLID_WIN_MAX)
1706 slide_rssi_index = 0;
1707
1708 tmp_val = priv->stats.slide_rssi_total/slide_rssi_statistics;
1709 priv->stats.signal_strength = rtl92e_translate_to_dbm(priv,
1710 (u8)tmp_val);
1711 curr_st->rssi = priv->stats.signal_strength;
1712 if (!prev_st->bPacketMatchBSSID) {
1713 if (!prev_st->bToSelfBA)
1714 return;
1715 }
1716
1717 if (!bcheck)
1718 return;
1719
1720 priv->stats.num_process_phyinfo++;
1721 if (!prev_st->bIsCCK && prev_st->bPacketToSelf) {
1722 for (rfpath = RF90_PATH_A; rfpath < RF90_PATH_C; rfpath++) {
1723 if (!rtl92e_is_legal_rf_path(priv->rtllib->dev, rfpath))
1724 continue;
1725 RT_TRACE(COMP_DBG,
1726 "Jacken -> pPreviousstats->RxMIMOSignalStrength[rfpath] = %d\n",
1727 prev_st->RxMIMOSignalStrength[rfpath]);
1728 if (priv->stats.rx_rssi_percentage[rfpath] == 0) {
1729 priv->stats.rx_rssi_percentage[rfpath] =
1730 prev_st->RxMIMOSignalStrength[rfpath];
1731 }
1732 if (prev_st->RxMIMOSignalStrength[rfpath] >
1733 priv->stats.rx_rssi_percentage[rfpath]) {
1734 priv->stats.rx_rssi_percentage[rfpath] =
1735 ((priv->stats.rx_rssi_percentage[rfpath]
1736 * (RX_SMOOTH - 1)) +
1737 (prev_st->RxMIMOSignalStrength
1738 [rfpath])) / (RX_SMOOTH);
1739 priv->stats.rx_rssi_percentage[rfpath] =
1740 priv->stats.rx_rssi_percentage[rfpath]
1741 + 1;
1742 } else {
1743 priv->stats.rx_rssi_percentage[rfpath] =
1744 ((priv->stats.rx_rssi_percentage[rfpath] *
1745 (RX_SMOOTH-1)) +
1746 (prev_st->RxMIMOSignalStrength[rfpath])) /
1747 (RX_SMOOTH);
1748 }
1749 RT_TRACE(COMP_DBG,
1750 "Jacken -> priv->RxStats.RxRSSIPercentage[rfPath] = %d\n",
1751 priv->stats.rx_rssi_percentage[rfpath]);
1752 }
1753 }
1754
1755
1756 if (prev_st->bPacketBeacon) {
1757 if (slide_beacon_adc_pwdb_statistics++ >=
1758 PHY_Beacon_RSSI_SLID_WIN_MAX) {
1759 slide_beacon_adc_pwdb_statistics =
1760 PHY_Beacon_RSSI_SLID_WIN_MAX;
1761 last_beacon_adc_pwdb = priv->stats.Slide_Beacon_pwdb
1762 [slide_beacon_adc_pwdb_index];
1763 priv->stats.Slide_Beacon_Total -= last_beacon_adc_pwdb;
1764 }
1765 priv->stats.Slide_Beacon_Total += prev_st->RxPWDBAll;
1766 priv->stats.Slide_Beacon_pwdb[slide_beacon_adc_pwdb_index] =
1767 prev_st->RxPWDBAll;
1768 slide_beacon_adc_pwdb_index++;
1769 if (slide_beacon_adc_pwdb_index >= PHY_Beacon_RSSI_SLID_WIN_MAX)
1770 slide_beacon_adc_pwdb_index = 0;
1771 prev_st->RxPWDBAll = priv->stats.Slide_Beacon_Total /
1772 slide_beacon_adc_pwdb_statistics;
1773 if (prev_st->RxPWDBAll >= 3)
1774 prev_st->RxPWDBAll -= 3;
1775 }
1776
1777 RT_TRACE(COMP_RXDESC, "Smooth %s PWDB = %d\n",
1778 prev_st->bIsCCK ? "CCK" : "OFDM",
1779 prev_st->RxPWDBAll);
1780
1781 if (prev_st->bPacketToSelf || prev_st->bPacketBeacon ||
1782 prev_st->bToSelfBA) {
1783 if (priv->undecorated_smoothed_pwdb < 0)
1784 priv->undecorated_smoothed_pwdb = prev_st->RxPWDBAll;
1785 if (prev_st->RxPWDBAll > (u32)priv->undecorated_smoothed_pwdb) {
1786 priv->undecorated_smoothed_pwdb =
1787 (((priv->undecorated_smoothed_pwdb) *
1788 (RX_SMOOTH-1)) +
1789 (prev_st->RxPWDBAll)) / (RX_SMOOTH);
1790 priv->undecorated_smoothed_pwdb =
1791 priv->undecorated_smoothed_pwdb + 1;
1792 } else {
1793 priv->undecorated_smoothed_pwdb =
1794 (((priv->undecorated_smoothed_pwdb) *
1795 (RX_SMOOTH-1)) +
1796 (prev_st->RxPWDBAll)) / (RX_SMOOTH);
1797 }
1798 rtl92e_update_rx_statistics(priv, prev_st);
1799 }
1800
1801 if (prev_st->SignalQuality != 0) {
1802 if (prev_st->bPacketToSelf || prev_st->bPacketBeacon ||
1803 prev_st->bToSelfBA) {
1804 if (slide_evm_statistics++ >= PHY_RSSI_SLID_WIN_MAX) {
1805 slide_evm_statistics = PHY_RSSI_SLID_WIN_MAX;
1806 last_evm =
1807 priv->stats.slide_evm[slide_evm_index];
1808 priv->stats.slide_evm_total -= last_evm;
1809 }
1810
1811 priv->stats.slide_evm_total += prev_st->SignalQuality;
1812
1813 priv->stats.slide_evm[slide_evm_index++] =
1814 prev_st->SignalQuality;
1815 if (slide_evm_index >= PHY_RSSI_SLID_WIN_MAX)
1816 slide_evm_index = 0;
1817
1818 tmp_val = priv->stats.slide_evm_total /
1819 slide_evm_statistics;
1820 priv->stats.signal_quality = tmp_val;
1821 priv->stats.last_signal_strength_inpercent = tmp_val;
1822 }
1823
1824 if (prev_st->bPacketToSelf ||
1825 prev_st->bPacketBeacon ||
1826 prev_st->bToSelfBA) {
1827 for (ij = 0; ij < 2; ij++) {
1828 if (prev_st->RxMIMOSignalQuality[ij] != -1) {
1829 if (priv->stats.rx_evm_percentage[ij] == 0)
1830 priv->stats.rx_evm_percentage[ij] =
1831 prev_st->RxMIMOSignalQuality[ij];
1832 priv->stats.rx_evm_percentage[ij] =
1833 ((priv->stats.rx_evm_percentage[ij] *
1834 (RX_SMOOTH - 1)) +
1835 (prev_st->RxMIMOSignalQuality[ij])) /
1836 (RX_SMOOTH);
1837 }
1838 }
1839 }
1840 }
1841 }
1842
_rtl92e_translate_rx_signal_stats(struct net_device * dev,struct sk_buff * skb,struct rtllib_rx_stats * pstats,struct rx_desc * pdesc,struct rx_fwinfo * pdrvinfo)1843 static void _rtl92e_translate_rx_signal_stats(struct net_device *dev,
1844 struct sk_buff *skb,
1845 struct rtllib_rx_stats *pstats,
1846 struct rx_desc *pdesc,
1847 struct rx_fwinfo *pdrvinfo)
1848 {
1849 struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev);
1850 bool bpacket_match_bssid, bpacket_toself;
1851 bool bPacketBeacon = false;
1852 struct rtllib_hdr_3addr *hdr;
1853 bool bToSelfBA = false;
1854 static struct rtllib_rx_stats previous_stats;
1855 u16 fc, type;
1856 u8 *tmp_buf;
1857 u8 *praddr;
1858
1859 tmp_buf = skb->data + pstats->RxDrvInfoSize + pstats->RxBufShift;
1860
1861 hdr = (struct rtllib_hdr_3addr *)tmp_buf;
1862 fc = le16_to_cpu(hdr->frame_ctl);
1863 type = WLAN_FC_GET_TYPE(fc);
1864 praddr = hdr->addr1;
1865
1866 bpacket_match_bssid =
1867 ((type != RTLLIB_FTYPE_CTL) &&
1868 ether_addr_equal(priv->rtllib->current_network.bssid,
1869 (fc & RTLLIB_FCTL_TODS) ? hdr->addr1 :
1870 (fc & RTLLIB_FCTL_FROMDS) ? hdr->addr2 :
1871 hdr->addr3) &&
1872 (!pstats->bHwError) && (!pstats->bCRC) && (!pstats->bICV));
1873 bpacket_toself = bpacket_match_bssid && /* check this */
1874 ether_addr_equal(praddr, priv->rtllib->dev->dev_addr);
1875 if (WLAN_FC_GET_FRAMETYPE(fc) == RTLLIB_STYPE_BEACON)
1876 bPacketBeacon = true;
1877 if (bpacket_match_bssid)
1878 priv->stats.numpacket_matchbssid++;
1879 if (bpacket_toself)
1880 priv->stats.numpacket_toself++;
1881 _rtl92e_process_phyinfo(priv, tmp_buf, &previous_stats, pstats);
1882 _rtl92e_query_rxphystatus(priv, pstats, pdesc, pdrvinfo,
1883 &previous_stats, bpacket_match_bssid,
1884 bpacket_toself, bPacketBeacon, bToSelfBA);
1885 rtl92e_copy_mpdu_stats(pstats, &previous_stats);
1886 }
1887
_rtl92e_update_received_rate_histogram_stats(struct net_device * dev,struct rtllib_rx_stats * pstats)1888 static void _rtl92e_update_received_rate_histogram_stats(
1889 struct net_device *dev,
1890 struct rtllib_rx_stats *pstats)
1891 {
1892 struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev);
1893 u32 rcvType = 1;
1894 u32 rateIndex;
1895 u32 preamble_guardinterval;
1896
1897 if (pstats->bCRC)
1898 rcvType = 2;
1899 else if (pstats->bICV)
1900 rcvType = 3;
1901
1902 if (pstats->bShortPreamble)
1903 preamble_guardinterval = 1;
1904 else
1905 preamble_guardinterval = 0;
1906
1907 switch (pstats->rate) {
1908 case MGN_1M:
1909 rateIndex = 0;
1910 break;
1911 case MGN_2M:
1912 rateIndex = 1;
1913 break;
1914 case MGN_5_5M:
1915 rateIndex = 2;
1916 break;
1917 case MGN_11M:
1918 rateIndex = 3;
1919 break;
1920 case MGN_6M:
1921 rateIndex = 4;
1922 break;
1923 case MGN_9M:
1924 rateIndex = 5;
1925 break;
1926 case MGN_12M:
1927 rateIndex = 6;
1928 break;
1929 case MGN_18M:
1930 rateIndex = 7;
1931 break;
1932 case MGN_24M:
1933 rateIndex = 8;
1934 break;
1935 case MGN_36M:
1936 rateIndex = 9;
1937 break;
1938 case MGN_48M:
1939 rateIndex = 10;
1940 break;
1941 case MGN_54M:
1942 rateIndex = 11;
1943 break;
1944 case MGN_MCS0:
1945 rateIndex = 12;
1946 break;
1947 case MGN_MCS1:
1948 rateIndex = 13;
1949 break;
1950 case MGN_MCS2:
1951 rateIndex = 14;
1952 break;
1953 case MGN_MCS3:
1954 rateIndex = 15;
1955 break;
1956 case MGN_MCS4:
1957 rateIndex = 16;
1958 break;
1959 case MGN_MCS5:
1960 rateIndex = 17;
1961 break;
1962 case MGN_MCS6:
1963 rateIndex = 18;
1964 break;
1965 case MGN_MCS7:
1966 rateIndex = 19;
1967 break;
1968 case MGN_MCS8:
1969 rateIndex = 20;
1970 break;
1971 case MGN_MCS9:
1972 rateIndex = 21;
1973 break;
1974 case MGN_MCS10:
1975 rateIndex = 22;
1976 break;
1977 case MGN_MCS11:
1978 rateIndex = 23;
1979 break;
1980 case MGN_MCS12:
1981 rateIndex = 24;
1982 break;
1983 case MGN_MCS13:
1984 rateIndex = 25;
1985 break;
1986 case MGN_MCS14:
1987 rateIndex = 26;
1988 break;
1989 case MGN_MCS15:
1990 rateIndex = 27;
1991 break;
1992 default:
1993 rateIndex = 28;
1994 break;
1995 }
1996 priv->stats.received_preamble_GI[preamble_guardinterval][rateIndex]++;
1997 priv->stats.received_rate_histogram[0][rateIndex]++;
1998 priv->stats.received_rate_histogram[rcvType][rateIndex]++;
1999 }
2000
rtl92e_get_rx_stats(struct net_device * dev,struct rtllib_rx_stats * stats,struct rx_desc * pdesc,struct sk_buff * skb)2001 bool rtl92e_get_rx_stats(struct net_device *dev, struct rtllib_rx_stats *stats,
2002 struct rx_desc *pdesc, struct sk_buff *skb)
2003 {
2004 struct r8192_priv *priv = rtllib_priv(dev);
2005 struct rx_fwinfo *pDrvInfo = NULL;
2006
2007 stats->bICV = pdesc->ICV;
2008 stats->bCRC = pdesc->CRC32;
2009 stats->bHwError = pdesc->CRC32 | pdesc->ICV;
2010
2011 stats->Length = pdesc->Length;
2012 if (stats->Length < 24)
2013 stats->bHwError |= 1;
2014
2015 if (stats->bHwError) {
2016 stats->bShift = false;
2017
2018 if (pdesc->CRC32) {
2019 if (pdesc->Length < 500)
2020 priv->stats.rxcrcerrmin++;
2021 else if (pdesc->Length > 1000)
2022 priv->stats.rxcrcerrmax++;
2023 else
2024 priv->stats.rxcrcerrmid++;
2025 }
2026 return false;
2027 }
2028
2029 stats->RxDrvInfoSize = pdesc->RxDrvInfoSize;
2030 stats->RxBufShift = (pdesc->Shift) & 0x03;
2031 stats->Decrypted = !pdesc->SWDec;
2032
2033 pDrvInfo = (struct rx_fwinfo *)(skb->data + stats->RxBufShift);
2034
2035 stats->rate = _rtl92e_rate_hw_to_mgn((bool)pDrvInfo->RxHT,
2036 (u8)pDrvInfo->RxRate);
2037 stats->bShortPreamble = pDrvInfo->SPLCP;
2038
2039 _rtl92e_update_received_rate_histogram_stats(dev, stats);
2040
2041 stats->bIsAMPDU = (pDrvInfo->PartAggr == 1);
2042 stats->bFirstMPDU = (pDrvInfo->PartAggr == 1) &&
2043 (pDrvInfo->FirstAGGR == 1);
2044
2045 stats->TimeStampLow = pDrvInfo->TSFL;
2046 stats->TimeStampHigh = rtl92e_readl(dev, TSFR+4);
2047
2048 rtl92e_update_rx_pkt_timestamp(dev, stats);
2049
2050 if ((stats->RxBufShift + stats->RxDrvInfoSize) > 0)
2051 stats->bShift = 1;
2052
2053 stats->RxIs40MHzPacket = pDrvInfo->BW;
2054
2055 _rtl92e_translate_rx_signal_stats(dev, skb, stats, pdesc, pDrvInfo);
2056
2057 if (pDrvInfo->FirstAGGR == 1 || pDrvInfo->PartAggr == 1)
2058 RT_TRACE(COMP_RXDESC,
2059 "pDrvInfo->FirstAGGR = %d, pDrvInfo->PartAggr = %d\n",
2060 pDrvInfo->FirstAGGR, pDrvInfo->PartAggr);
2061 skb_trim(skb, skb->len - 4/*sCrcLng*/);
2062
2063
2064 stats->packetlength = stats->Length-4;
2065 stats->fraglength = stats->packetlength;
2066 stats->fragoffset = 0;
2067 stats->ntotalfrag = 1;
2068 return true;
2069 }
2070
rtl92e_stop_adapter(struct net_device * dev,bool reset)2071 void rtl92e_stop_adapter(struct net_device *dev, bool reset)
2072 {
2073 struct r8192_priv *priv = rtllib_priv(dev);
2074 int i;
2075 u8 OpMode;
2076 u8 u1bTmp;
2077 u32 ulRegRead;
2078
2079 OpMode = RT_OP_MODE_NO_LINK;
2080 priv->rtllib->SetHwRegHandler(dev, HW_VAR_MEDIA_STATUS, &OpMode);
2081
2082 if (!priv->rtllib->bSupportRemoteWakeUp) {
2083 u1bTmp = 0x0;
2084 rtl92e_writeb(dev, CMDR, u1bTmp);
2085 }
2086
2087 mdelay(20);
2088
2089 if (!reset) {
2090 mdelay(150);
2091
2092 priv->bHwRfOffAction = 2;
2093
2094 if (!priv->rtllib->bSupportRemoteWakeUp) {
2095 rtl92e_set_rf_off(dev);
2096 ulRegRead = rtl92e_readl(dev, CPU_GEN);
2097 ulRegRead |= CPU_GEN_SYSTEM_RESET;
2098 rtl92e_writel(dev, CPU_GEN, ulRegRead);
2099 } else {
2100 rtl92e_writel(dev, WFCRC0, 0xffffffff);
2101 rtl92e_writel(dev, WFCRC1, 0xffffffff);
2102 rtl92e_writel(dev, WFCRC2, 0xffffffff);
2103
2104
2105 rtl92e_writeb(dev, PMR, 0x5);
2106 rtl92e_writeb(dev, MacBlkCtrl, 0xa);
2107 }
2108 }
2109
2110 for (i = 0; i < MAX_QUEUE_SIZE; i++)
2111 skb_queue_purge(&priv->rtllib->skb_waitQ[i]);
2112 for (i = 0; i < MAX_QUEUE_SIZE; i++)
2113 skb_queue_purge(&priv->rtllib->skb_aggQ[i]);
2114
2115 skb_queue_purge(&priv->skb_queue);
2116 }
2117
rtl92e_update_ratr_table(struct net_device * dev)2118 void rtl92e_update_ratr_table(struct net_device *dev)
2119 {
2120 struct r8192_priv *priv = rtllib_priv(dev);
2121 struct rtllib_device *ieee = priv->rtllib;
2122 u8 *pMcsRate = ieee->dot11HTOperationalRateSet;
2123 u32 ratr_value = 0;
2124 u16 rate_config = 0;
2125 u8 rate_index = 0;
2126
2127 rtl92e_config_rate(dev, &rate_config);
2128 ratr_value = rate_config | *pMcsRate << 12;
2129 switch (ieee->mode) {
2130 case IEEE_A:
2131 ratr_value &= 0x00000FF0;
2132 break;
2133 case IEEE_B:
2134 ratr_value &= 0x0000000F;
2135 break;
2136 case IEEE_G:
2137 case IEEE_G|IEEE_B:
2138 ratr_value &= 0x00000FF7;
2139 break;
2140 case IEEE_N_24G:
2141 case IEEE_N_5G:
2142 if (ieee->pHTInfo->PeerMimoPs == 0) {
2143 ratr_value &= 0x0007F007;
2144 } else {
2145 if (priv->rf_type == RF_1T2R)
2146 ratr_value &= 0x000FF007;
2147 else
2148 ratr_value &= 0x0F81F007;
2149 }
2150 break;
2151 default:
2152 break;
2153 }
2154 ratr_value &= 0x0FFFFFFF;
2155 if (ieee->pHTInfo->bCurTxBW40MHz &&
2156 ieee->pHTInfo->bCurShortGI40MHz)
2157 ratr_value |= 0x80000000;
2158 else if (!ieee->pHTInfo->bCurTxBW40MHz &&
2159 ieee->pHTInfo->bCurShortGI20MHz)
2160 ratr_value |= 0x80000000;
2161 rtl92e_writel(dev, RATR0+rate_index*4, ratr_value);
2162 rtl92e_writeb(dev, UFWP, 1);
2163 }
2164
2165 void
rtl92e_init_variables(struct net_device * dev)2166 rtl92e_init_variables(struct net_device *dev)
2167 {
2168 struct r8192_priv *priv = rtllib_priv(dev);
2169
2170 strscpy(priv->nick, "rtl8192E", sizeof(priv->nick));
2171
2172 priv->rtllib->softmac_features = IEEE_SOFTMAC_SCAN |
2173 IEEE_SOFTMAC_ASSOCIATE | IEEE_SOFTMAC_PROBERQ |
2174 IEEE_SOFTMAC_PROBERS | IEEE_SOFTMAC_TX_QUEUE;
2175
2176 priv->rtllib->tx_headroom = sizeof(struct tx_fwinfo_8190pci);
2177
2178 priv->ShortRetryLimit = 0x30;
2179 priv->LongRetryLimit = 0x30;
2180
2181 priv->ReceiveConfig = RCR_ADD3 |
2182 RCR_AMF | RCR_ADF |
2183 RCR_AICV |
2184 RCR_AB | RCR_AM | RCR_APM |
2185 RCR_AAP | ((u32)7<<RCR_MXDMA_OFFSET) |
2186 ((u32)7 << RCR_FIFO_OFFSET) | RCR_ONLYERLPKT;
2187
2188 priv->irq_mask[0] = (u32)(IMR_ROK | IMR_VODOK | IMR_VIDOK |
2189 IMR_BEDOK | IMR_BKDOK | IMR_HCCADOK |
2190 IMR_MGNTDOK | IMR_COMDOK | IMR_HIGHDOK |
2191 IMR_BDOK | IMR_RXCMDOK | IMR_TIMEOUT0 |
2192 IMR_RDU | IMR_RXFOVW | IMR_TXFOVW |
2193 IMR_BcnInt | IMR_TBDOK | IMR_TBDER);
2194
2195 priv->PwrDomainProtect = false;
2196
2197 priv->bfirst_after_down = false;
2198 }
2199
rtl92e_enable_irq(struct net_device * dev)2200 void rtl92e_enable_irq(struct net_device *dev)
2201 {
2202 struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev);
2203
2204 priv->irq_enabled = 1;
2205
2206 rtl92e_writel(dev, INTA_MASK, priv->irq_mask[0]);
2207
2208 }
2209
rtl92e_disable_irq(struct net_device * dev)2210 void rtl92e_disable_irq(struct net_device *dev)
2211 {
2212 struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev);
2213
2214 rtl92e_writel(dev, INTA_MASK, 0);
2215
2216 priv->irq_enabled = 0;
2217 }
2218
rtl92e_clear_irq(struct net_device * dev)2219 void rtl92e_clear_irq(struct net_device *dev)
2220 {
2221 u32 tmp;
2222
2223 tmp = rtl92e_readl(dev, ISR);
2224 rtl92e_writel(dev, ISR, tmp);
2225 }
2226
2227
rtl92e_enable_rx(struct net_device * dev)2228 void rtl92e_enable_rx(struct net_device *dev)
2229 {
2230 struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev);
2231
2232 rtl92e_writel(dev, RDQDA, priv->rx_ring_dma[RX_MPDU_QUEUE]);
2233 }
2234
2235 static const u32 TX_DESC_BASE[] = {
2236 BKQDA, BEQDA, VIQDA, VOQDA, HCCAQDA, CQDA, MQDA, HQDA, BQDA
2237 };
2238
rtl92e_enable_tx(struct net_device * dev)2239 void rtl92e_enable_tx(struct net_device *dev)
2240 {
2241 struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev);
2242 u32 i;
2243
2244 for (i = 0; i < MAX_TX_QUEUE_COUNT; i++)
2245 rtl92e_writel(dev, TX_DESC_BASE[i], priv->tx_ring[i].dma);
2246 }
2247
2248
rtl92e_ack_irq(struct net_device * dev,u32 * p_inta,u32 * p_intb)2249 void rtl92e_ack_irq(struct net_device *dev, u32 *p_inta, u32 *p_intb)
2250 {
2251 *p_inta = rtl92e_readl(dev, ISR);
2252 rtl92e_writel(dev, ISR, *p_inta);
2253 }
2254
rtl92e_is_rx_stuck(struct net_device * dev)2255 bool rtl92e_is_rx_stuck(struct net_device *dev)
2256 {
2257 struct r8192_priv *priv = rtllib_priv(dev);
2258 u16 RegRxCounter = rtl92e_readw(dev, 0x130);
2259 bool bStuck = false;
2260 static u8 rx_chk_cnt;
2261 u32 SlotIndex = 0, TotalRxStuckCount = 0;
2262 u8 i;
2263 u8 SilentResetRxSoltNum = 4;
2264
2265 RT_TRACE(COMP_RESET, "%s(): RegRxCounter is %d, RxCounter is %d\n",
2266 __func__, RegRxCounter, priv->RxCounter);
2267
2268 rx_chk_cnt++;
2269 if (priv->undecorated_smoothed_pwdb >= (RateAdaptiveTH_High+5)) {
2270 rx_chk_cnt = 0;
2271 } else if ((priv->undecorated_smoothed_pwdb < (RateAdaptiveTH_High + 5))
2272 && (((priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) &&
2273 (priv->undecorated_smoothed_pwdb >= RateAdaptiveTH_Low_40M))
2274 || ((priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20) &&
2275 (priv->undecorated_smoothed_pwdb >= RateAdaptiveTH_Low_20M)))) {
2276 if (rx_chk_cnt < 2)
2277 return bStuck;
2278 rx_chk_cnt = 0;
2279 } else if ((((priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) &&
2280 (priv->undecorated_smoothed_pwdb < RateAdaptiveTH_Low_40M)) ||
2281 ((priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20) &&
2282 (priv->undecorated_smoothed_pwdb < RateAdaptiveTH_Low_20M))) &&
2283 priv->undecorated_smoothed_pwdb >= VeryLowRSSI) {
2284 if (rx_chk_cnt < 4)
2285 return bStuck;
2286 rx_chk_cnt = 0;
2287 } else {
2288 if (rx_chk_cnt < 8)
2289 return bStuck;
2290 rx_chk_cnt = 0;
2291 }
2292
2293
2294 SlotIndex = (priv->SilentResetRxSlotIndex++)%SilentResetRxSoltNum;
2295
2296 if (priv->RxCounter == RegRxCounter) {
2297 priv->SilentResetRxStuckEvent[SlotIndex] = 1;
2298
2299 for (i = 0; i < SilentResetRxSoltNum; i++)
2300 TotalRxStuckCount += priv->SilentResetRxStuckEvent[i];
2301
2302 if (TotalRxStuckCount == SilentResetRxSoltNum) {
2303 bStuck = true;
2304 for (i = 0; i < SilentResetRxSoltNum; i++)
2305 TotalRxStuckCount +=
2306 priv->SilentResetRxStuckEvent[i];
2307 }
2308
2309
2310 } else {
2311 priv->SilentResetRxStuckEvent[SlotIndex] = 0;
2312 }
2313
2314 priv->RxCounter = RegRxCounter;
2315
2316 return bStuck;
2317 }
2318
rtl92e_is_tx_stuck(struct net_device * dev)2319 bool rtl92e_is_tx_stuck(struct net_device *dev)
2320 {
2321 struct r8192_priv *priv = rtllib_priv(dev);
2322 bool bStuck = false;
2323 u16 RegTxCounter = rtl92e_readw(dev, 0x128);
2324
2325 RT_TRACE(COMP_RESET, "%s():RegTxCounter is %d,TxCounter is %d\n",
2326 __func__, RegTxCounter, priv->TxCounter);
2327
2328 if (priv->TxCounter == RegTxCounter)
2329 bStuck = true;
2330
2331 priv->TxCounter = RegTxCounter;
2332
2333 return bStuck;
2334 }
2335
rtl92e_get_nmode_support_by_sec(struct net_device * dev)2336 bool rtl92e_get_nmode_support_by_sec(struct net_device *dev)
2337 {
2338 struct r8192_priv *priv = rtllib_priv(dev);
2339 struct rtllib_device *ieee = priv->rtllib;
2340
2341 if (ieee->rtllib_ap_sec_type &&
2342 (ieee->rtllib_ap_sec_type(priv->rtllib)&(SEC_ALG_WEP |
2343 SEC_ALG_TKIP))) {
2344 return false;
2345 } else {
2346 return true;
2347 }
2348 }
2349
rtl92e_is_halfn_supported_by_ap(struct net_device * dev)2350 bool rtl92e_is_halfn_supported_by_ap(struct net_device *dev)
2351 {
2352 struct r8192_priv *priv = rtllib_priv(dev);
2353 struct rtllib_device *ieee = priv->rtllib;
2354
2355 return ieee->bHalfWirelessN24GMode;
2356 }
2357
