1 /* 2 * Copyright 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef __DAL_DCN30_AFMT_H__ 27 #define __DAL_DCN30_AFMT_H__ 28 29 30 #define DCN30_AFMT_FROM_AFMT(afmt)\ 31 container_of(afmt, struct dcn30_afmt, base) 32 33 #define AFMT_DCN3_REG_LIST(id) \ 34 SRI(AFMT_INFOFRAME_CONTROL0, AFMT, id), \ 35 SRI(AFMT_VBI_PACKET_CONTROL, AFMT, id), \ 36 SRI(AFMT_AUDIO_PACKET_CONTROL, AFMT, id), \ 37 SRI(AFMT_AUDIO_PACKET_CONTROL2, AFMT, id), \ 38 SRI(AFMT_AUDIO_SRC_CONTROL, AFMT, id), \ 39 SRI(AFMT_60958_0, AFMT, id), \ 40 SRI(AFMT_60958_1, AFMT, id), \ 41 SRI(AFMT_60958_2, AFMT, id), \ 42 SRI(AFMT_MEM_PWR, AFMT, id) 43 44 struct dcn30_afmt_registers { 45 uint32_t AFMT_INFOFRAME_CONTROL0; 46 uint32_t AFMT_VBI_PACKET_CONTROL; 47 uint32_t AFMT_AUDIO_PACKET_CONTROL; 48 uint32_t AFMT_AUDIO_PACKET_CONTROL2; 49 uint32_t AFMT_AUDIO_SRC_CONTROL; 50 uint32_t AFMT_60958_0; 51 uint32_t AFMT_60958_1; 52 uint32_t AFMT_60958_2; 53 uint32_t AFMT_MEM_PWR; 54 }; 55 56 #define DCN3_AFMT_MASK_SH_LIST(mask_sh)\ 57 SE_SF(AFMT0_AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, mask_sh),\ 58 SE_SF(AFMT0_AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, mask_sh),\ 59 SE_SF(AFMT0_AFMT_AUDIO_PACKET_CONTROL2, AFMT_AUDIO_CHANNEL_ENABLE, mask_sh),\ 60 SE_SF(AFMT0_AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, mask_sh),\ 61 SE_SF(AFMT0_AFMT_AUDIO_PACKET_CONTROL2, AFMT_AUDIO_LAYOUT_OVRD, mask_sh),\ 62 SE_SF(AFMT0_AFMT_AUDIO_PACKET_CONTROL2, AFMT_60958_OSF_OVRD, mask_sh),\ 63 SE_SF(AFMT0_AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, mask_sh),\ 64 SE_SF(AFMT0_AFMT_60958_0, AFMT_60958_CS_CLOCK_ACCURACY, mask_sh),\ 65 SE_SF(AFMT0_AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, mask_sh),\ 66 SE_SF(AFMT0_AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, mask_sh),\ 67 SE_SF(AFMT0_AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_3, mask_sh),\ 68 SE_SF(AFMT0_AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_4, mask_sh),\ 69 SE_SF(AFMT0_AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_5, mask_sh),\ 70 SE_SF(AFMT0_AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, mask_sh),\ 71 SE_SF(AFMT0_AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, mask_sh),\ 72 SE_SF(AFMT0_AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, mask_sh),\ 73 SE_SF(AFMT0_AFMT_MEM_PWR, AFMT_MEM_PWR_FORCE, mask_sh) 74 75 #define AFMT_DCN3_REG_FIELD_LIST(type) \ 76 type AFMT_AUDIO_INFO_UPDATE;\ 77 type AFMT_AUDIO_SRC_SELECT;\ 78 type AFMT_AUDIO_CHANNEL_ENABLE;\ 79 type AFMT_60958_CS_UPDATE;\ 80 type AFMT_AUDIO_LAYOUT_OVRD;\ 81 type AFMT_60958_OSF_OVRD;\ 82 type AFMT_60958_CS_CHANNEL_NUMBER_L;\ 83 type AFMT_60958_CS_CLOCK_ACCURACY;\ 84 type AFMT_60958_CS_CHANNEL_NUMBER_R;\ 85 type AFMT_60958_CS_CHANNEL_NUMBER_2;\ 86 type AFMT_60958_CS_CHANNEL_NUMBER_3;\ 87 type AFMT_60958_CS_CHANNEL_NUMBER_4;\ 88 type AFMT_60958_CS_CHANNEL_NUMBER_5;\ 89 type AFMT_60958_CS_CHANNEL_NUMBER_6;\ 90 type AFMT_60958_CS_CHANNEL_NUMBER_7;\ 91 type AFMT_AUDIO_SAMPLE_SEND;\ 92 type AFMT_MEM_PWR_FORCE 93 94 struct dcn30_afmt_shift { 95 AFMT_DCN3_REG_FIELD_LIST(uint8_t); 96 }; 97 98 struct dcn30_afmt_mask { 99 AFMT_DCN3_REG_FIELD_LIST(uint32_t); 100 }; 101 102 103 /** 104 * speakersToChannels 105 * 106 * @brief 107 * translate speakers to channels 108 * 109 * FL - Front Left 110 * FR - Front Right 111 * RL - Rear Left 112 * RR - Rear Right 113 * RC - Rear Center 114 * FC - Front Center 115 * FLC - Front Left Center 116 * FRC - Front Right Center 117 * RLC - Rear Left Center 118 * RRC - Rear Right Center 119 * LFE - Low Freq Effect 120 * 121 * FC 122 * FLC FRC 123 * FL FR 124 * 125 * LFE 126 * () 127 * 128 * 129 * RL RR 130 * RLC RRC 131 * RC 132 * 133 * ch 8 7 6 5 4 3 2 1 134 * 0b00000011 - - - - - - FR FL 135 * 0b00000111 - - - - - LFE FR FL 136 * 0b00001011 - - - - FC - FR FL 137 * 0b00001111 - - - - FC LFE FR FL 138 * 0b00010011 - - - RC - - FR FL 139 * 0b00010111 - - - RC - LFE FR FL 140 * 0b00011011 - - - RC FC - FR FL 141 * 0b00011111 - - - RC FC LFE FR FL 142 * 0b00110011 - - RR RL - - FR FL 143 * 0b00110111 - - RR RL - LFE FR FL 144 * 0b00111011 - - RR RL FC - FR FL 145 * 0b00111111 - - RR RL FC LFE FR FL 146 * 0b01110011 - RC RR RL - - FR FL 147 * 0b01110111 - RC RR RL - LFE FR FL 148 * 0b01111011 - RC RR RL FC - FR FL 149 * 0b01111111 - RC RR RL FC LFE FR FL 150 * 0b11110011 RRC RLC RR RL - - FR FL 151 * 0b11110111 RRC RLC RR RL - LFE FR FL 152 * 0b11111011 RRC RLC RR RL FC - FR FL 153 * 0b11111111 RRC RLC RR RL FC LFE FR FL 154 * 0b11000011 FRC FLC - - - - FR FL 155 * 0b11000111 FRC FLC - - - LFE FR FL 156 * 0b11001011 FRC FLC - - FC - FR FL 157 * 0b11001111 FRC FLC - - FC LFE FR FL 158 * 0b11010011 FRC FLC - RC - - FR FL 159 * 0b11010111 FRC FLC - RC - LFE FR FL 160 * 0b11011011 FRC FLC - RC FC - FR FL 161 * 0b11011111 FRC FLC - RC FC LFE FR FL 162 * 0b11110011 FRC FLC RR RL - - FR FL 163 * 0b11110111 FRC FLC RR RL - LFE FR FL 164 * 0b11111011 FRC FLC RR RL FC - FR FL 165 * 0b11111111 FRC FLC RR RL FC LFE FR FL 166 * 167 * @param 168 * speakers - speaker information as it comes from CEA audio block 169 */ 170 /* translate speakers to channels */ 171 172 union audio_cea_channels { 173 uint8_t all; 174 struct audio_cea_channels_bits { 175 uint32_t FL:1; 176 uint32_t FR:1; 177 uint32_t LFE:1; 178 uint32_t FC:1; 179 uint32_t RL_RC:1; 180 uint32_t RR:1; 181 uint32_t RC_RLC_FLC:1; 182 uint32_t RRC_FRC:1; 183 } channels; 184 }; 185 186 struct afmt; 187 188 struct afmt_funcs { 189 190 void (*setup_hdmi_audio)( 191 struct afmt *afmt); 192 193 void (*se_audio_setup)( 194 struct afmt *afmt, 195 unsigned int az_inst, 196 struct audio_info *audio_info); 197 198 void (*audio_mute_control)( 199 struct afmt *afmt, 200 bool mute); 201 202 void (*audio_info_immediate_update)( 203 struct afmt *afmt); 204 205 void (*setup_dp_audio)( 206 struct afmt *afmt); 207 }; 208 209 struct afmt { 210 const struct afmt_funcs *funcs; 211 struct dc_context *ctx; 212 int inst; 213 }; 214 215 struct dcn30_afmt { 216 struct afmt base; 217 const struct dcn30_afmt_registers *regs; 218 const struct dcn30_afmt_shift *afmt_shift; 219 const struct dcn30_afmt_mask *afmt_mask; 220 }; 221 222 void afmt3_construct(struct dcn30_afmt *afmt3, 223 struct dc_context *ctx, 224 uint32_t inst, 225 const struct dcn30_afmt_registers *afmt_regs, 226 const struct dcn30_afmt_shift *afmt_shift, 227 const struct dcn30_afmt_mask *afmt_mask); 228 229 230 #endif 231
