1 /*
2 * Copyright (c) 2008-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include <linux/nl80211.h>
18 #include <linux/delay.h>
19 #include "ath9k.h"
20 #include "btcoex.h"
21
22 static void ath9k_flush(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
23 u32 queues, bool drop);
24
ath9k_parse_mpdudensity(u8 mpdudensity)25 u8 ath9k_parse_mpdudensity(u8 mpdudensity)
26 {
27 /*
28 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
29 * 0 for no restriction
30 * 1 for 1/4 us
31 * 2 for 1/2 us
32 * 3 for 1 us
33 * 4 for 2 us
34 * 5 for 4 us
35 * 6 for 8 us
36 * 7 for 16 us
37 */
38 switch (mpdudensity) {
39 case 0:
40 return 0;
41 case 1:
42 case 2:
43 case 3:
44 /* Our lower layer calculations limit our precision to
45 1 microsecond */
46 return 1;
47 case 4:
48 return 2;
49 case 5:
50 return 4;
51 case 6:
52 return 8;
53 case 7:
54 return 16;
55 default:
56 return 0;
57 }
58 }
59
ath9k_has_pending_frames(struct ath_softc * sc,struct ath_txq * txq,bool sw_pending)60 static bool ath9k_has_pending_frames(struct ath_softc *sc, struct ath_txq *txq,
61 bool sw_pending)
62 {
63 bool pending = false;
64
65 spin_lock_bh(&txq->axq_lock);
66
67 if (txq->axq_depth) {
68 pending = true;
69 goto out;
70 }
71
72 if (!sw_pending)
73 goto out;
74
75 if (txq->mac80211_qnum >= 0) {
76 struct ath_acq *acq;
77
78 acq = &sc->cur_chan->acq[txq->mac80211_qnum];
79 if (!list_empty(&acq->acq_new) || !list_empty(&acq->acq_old))
80 pending = true;
81 }
82 out:
83 spin_unlock_bh(&txq->axq_lock);
84 return pending;
85 }
86
ath9k_setpower(struct ath_softc * sc,enum ath9k_power_mode mode)87 static bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode)
88 {
89 unsigned long flags;
90 bool ret;
91
92 spin_lock_irqsave(&sc->sc_pm_lock, flags);
93 ret = ath9k_hw_setpower(sc->sc_ah, mode);
94 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
95
96 return ret;
97 }
98
ath_ps_full_sleep(struct timer_list * t)99 void ath_ps_full_sleep(struct timer_list *t)
100 {
101 struct ath_softc *sc = from_timer(sc, t, sleep_timer);
102 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
103 unsigned long flags;
104 bool reset;
105
106 spin_lock_irqsave(&common->cc_lock, flags);
107 ath_hw_cycle_counters_update(common);
108 spin_unlock_irqrestore(&common->cc_lock, flags);
109
110 ath9k_hw_setrxabort(sc->sc_ah, 1);
111 ath9k_hw_stopdmarecv(sc->sc_ah, &reset);
112
113 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_FULL_SLEEP);
114 }
115
ath9k_ps_wakeup(struct ath_softc * sc)116 void ath9k_ps_wakeup(struct ath_softc *sc)
117 {
118 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
119 unsigned long flags;
120 enum ath9k_power_mode power_mode;
121
122 spin_lock_irqsave(&sc->sc_pm_lock, flags);
123 if (++sc->ps_usecount != 1)
124 goto unlock;
125
126 del_timer_sync(&sc->sleep_timer);
127 power_mode = sc->sc_ah->power_mode;
128 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
129
130 /*
131 * While the hardware is asleep, the cycle counters contain no
132 * useful data. Better clear them now so that they don't mess up
133 * survey data results.
134 */
135 if (power_mode != ATH9K_PM_AWAKE) {
136 spin_lock(&common->cc_lock);
137 ath_hw_cycle_counters_update(common);
138 memset(&common->cc_survey, 0, sizeof(common->cc_survey));
139 memset(&common->cc_ani, 0, sizeof(common->cc_ani));
140 spin_unlock(&common->cc_lock);
141 }
142
143 unlock:
144 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
145 }
146
ath9k_ps_restore(struct ath_softc * sc)147 void ath9k_ps_restore(struct ath_softc *sc)
148 {
149 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
150 enum ath9k_power_mode mode;
151 unsigned long flags;
152
153 spin_lock_irqsave(&sc->sc_pm_lock, flags);
154 if (--sc->ps_usecount != 0)
155 goto unlock;
156
157 if (sc->ps_idle) {
158 mod_timer(&sc->sleep_timer, jiffies + HZ / 10);
159 goto unlock;
160 }
161
162 if (sc->ps_enabled &&
163 !(sc->ps_flags & (PS_WAIT_FOR_BEACON |
164 PS_WAIT_FOR_CAB |
165 PS_WAIT_FOR_PSPOLL_DATA |
166 PS_WAIT_FOR_TX_ACK |
167 PS_WAIT_FOR_ANI))) {
168 mode = ATH9K_PM_NETWORK_SLEEP;
169 if (ath9k_hw_btcoex_is_enabled(sc->sc_ah))
170 ath9k_btcoex_stop_gen_timer(sc);
171 } else {
172 goto unlock;
173 }
174
175 spin_lock(&common->cc_lock);
176 ath_hw_cycle_counters_update(common);
177 spin_unlock(&common->cc_lock);
178
179 ath9k_hw_setpower(sc->sc_ah, mode);
180
181 unlock:
182 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
183 }
184
__ath_cancel_work(struct ath_softc * sc)185 static void __ath_cancel_work(struct ath_softc *sc)
186 {
187 cancel_work_sync(&sc->paprd_work);
188 cancel_delayed_work_sync(&sc->hw_check_work);
189 cancel_delayed_work_sync(&sc->hw_pll_work);
190
191 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
192 if (ath9k_hw_mci_is_enabled(sc->sc_ah))
193 cancel_work_sync(&sc->mci_work);
194 #endif
195 }
196
ath_cancel_work(struct ath_softc * sc)197 void ath_cancel_work(struct ath_softc *sc)
198 {
199 __ath_cancel_work(sc);
200 cancel_work_sync(&sc->hw_reset_work);
201 }
202
ath_restart_work(struct ath_softc * sc)203 void ath_restart_work(struct ath_softc *sc)
204 {
205 ieee80211_queue_delayed_work(sc->hw, &sc->hw_check_work,
206 ATH_HW_CHECK_POLL_INT);
207
208 if (AR_SREV_9340(sc->sc_ah) || AR_SREV_9330(sc->sc_ah))
209 ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work,
210 msecs_to_jiffies(ATH_PLL_WORK_INTERVAL));
211
212 ath_start_ani(sc);
213 }
214
ath_prepare_reset(struct ath_softc * sc)215 static bool ath_prepare_reset(struct ath_softc *sc)
216 {
217 struct ath_hw *ah = sc->sc_ah;
218 bool ret = true;
219
220 ieee80211_stop_queues(sc->hw);
221 ath_stop_ani(sc);
222 ath9k_hw_disable_interrupts(ah);
223
224 if (AR_SREV_9300_20_OR_LATER(ah)) {
225 ret &= ath_stoprecv(sc);
226 ret &= ath_drain_all_txq(sc);
227 } else {
228 ret &= ath_drain_all_txq(sc);
229 ret &= ath_stoprecv(sc);
230 }
231
232 return ret;
233 }
234
ath_complete_reset(struct ath_softc * sc,bool start)235 static bool ath_complete_reset(struct ath_softc *sc, bool start)
236 {
237 struct ath_hw *ah = sc->sc_ah;
238 struct ath_common *common = ath9k_hw_common(ah);
239 unsigned long flags;
240
241 ath9k_calculate_summary_state(sc, sc->cur_chan);
242 ath_startrecv(sc);
243 ath9k_cmn_update_txpow(ah, sc->cur_chan->cur_txpower,
244 sc->cur_chan->txpower,
245 &sc->cur_chan->cur_txpower);
246 clear_bit(ATH_OP_HW_RESET, &common->op_flags);
247
248 if (!sc->cur_chan->offchannel && start) {
249 /* restore per chanctx TSF timer */
250 if (sc->cur_chan->tsf_val) {
251 u32 offset;
252
253 offset = ath9k_hw_get_tsf_offset(&sc->cur_chan->tsf_ts,
254 NULL);
255 ath9k_hw_settsf64(ah, sc->cur_chan->tsf_val + offset);
256 }
257
258
259 if (!test_bit(ATH_OP_BEACONS, &common->op_flags))
260 goto work;
261
262 if (ah->opmode == NL80211_IFTYPE_STATION &&
263 test_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags)) {
264 spin_lock_irqsave(&sc->sc_pm_lock, flags);
265 sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;
266 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
267 } else {
268 ath9k_set_beacon(sc);
269 }
270 work:
271 ath_restart_work(sc);
272 ath_txq_schedule_all(sc);
273 }
274
275 sc->gtt_cnt = 0;
276
277 ath9k_hw_set_interrupts(ah);
278 ath9k_hw_enable_interrupts(ah);
279 ieee80211_wake_queues(sc->hw);
280 ath9k_p2p_ps_timer(sc);
281
282 return true;
283 }
284
ath_reset_internal(struct ath_softc * sc,struct ath9k_channel * hchan)285 static int ath_reset_internal(struct ath_softc *sc, struct ath9k_channel *hchan)
286 {
287 struct ath_hw *ah = sc->sc_ah;
288 struct ath_common *common = ath9k_hw_common(ah);
289 struct ath9k_hw_cal_data *caldata = NULL;
290 bool fastcc = true;
291 int r;
292
293 __ath_cancel_work(sc);
294
295 disable_irq(sc->irq);
296 tasklet_disable(&sc->intr_tq);
297 tasklet_disable(&sc->bcon_tasklet);
298 spin_lock_bh(&sc->sc_pcu_lock);
299
300 if (!sc->cur_chan->offchannel) {
301 fastcc = false;
302 caldata = &sc->cur_chan->caldata;
303 }
304
305 if (!hchan) {
306 fastcc = false;
307 hchan = ah->curchan;
308 }
309
310 if (!ath_prepare_reset(sc))
311 fastcc = false;
312
313 if (ath9k_is_chanctx_enabled())
314 fastcc = false;
315
316 spin_lock_bh(&sc->chan_lock);
317 sc->cur_chandef = sc->cur_chan->chandef;
318 spin_unlock_bh(&sc->chan_lock);
319
320 ath_dbg(common, CONFIG, "Reset to %u MHz, HT40: %d fastcc: %d\n",
321 hchan->channel, IS_CHAN_HT40(hchan), fastcc);
322
323 r = ath9k_hw_reset(ah, hchan, caldata, fastcc);
324 if (r) {
325 ath_err(common,
326 "Unable to reset channel, reset status %d\n", r);
327
328 ath9k_hw_enable_interrupts(ah);
329 ath9k_queue_reset(sc, RESET_TYPE_BB_HANG);
330
331 goto out;
332 }
333
334 if (ath9k_hw_mci_is_enabled(sc->sc_ah) &&
335 sc->cur_chan->offchannel)
336 ath9k_mci_set_txpower(sc, true, false);
337
338 if (!ath_complete_reset(sc, true))
339 r = -EIO;
340
341 out:
342 enable_irq(sc->irq);
343 spin_unlock_bh(&sc->sc_pcu_lock);
344 tasklet_enable(&sc->bcon_tasklet);
345 tasklet_enable(&sc->intr_tq);
346
347 return r;
348 }
349
ath_node_attach(struct ath_softc * sc,struct ieee80211_sta * sta,struct ieee80211_vif * vif)350 static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta,
351 struct ieee80211_vif *vif)
352 {
353 struct ath_node *an;
354 an = (struct ath_node *)sta->drv_priv;
355
356 an->sc = sc;
357 an->sta = sta;
358 an->vif = vif;
359 memset(&an->key_idx, 0, sizeof(an->key_idx));
360
361 ath_tx_node_init(sc, an);
362
363 ath_dynack_node_init(sc->sc_ah, an);
364 }
365
ath_node_detach(struct ath_softc * sc,struct ieee80211_sta * sta)366 static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
367 {
368 struct ath_node *an = (struct ath_node *)sta->drv_priv;
369 ath_tx_node_cleanup(sc, an);
370
371 ath_dynack_node_deinit(sc->sc_ah, an);
372 }
373
ath9k_tasklet(struct tasklet_struct * t)374 void ath9k_tasklet(struct tasklet_struct *t)
375 {
376 struct ath_softc *sc = from_tasklet(sc, t, intr_tq);
377 struct ath_hw *ah = sc->sc_ah;
378 struct ath_common *common = ath9k_hw_common(ah);
379 enum ath_reset_type type;
380 unsigned long flags;
381 u32 status;
382 u32 rxmask;
383
384 spin_lock_irqsave(&sc->intr_lock, flags);
385 status = sc->intrstatus;
386 sc->intrstatus = 0;
387 spin_unlock_irqrestore(&sc->intr_lock, flags);
388
389 ath9k_ps_wakeup(sc);
390 spin_lock(&sc->sc_pcu_lock);
391
392 if (status & ATH9K_INT_FATAL) {
393 type = RESET_TYPE_FATAL_INT;
394 ath9k_queue_reset(sc, type);
395 ath_dbg(common, RESET, "FATAL: Skipping interrupts\n");
396 goto out;
397 }
398
399 if ((ah->config.hw_hang_checks & HW_BB_WATCHDOG) &&
400 (status & ATH9K_INT_BB_WATCHDOG)) {
401 spin_lock_irqsave(&common->cc_lock, flags);
402 ath_hw_cycle_counters_update(common);
403 ar9003_hw_bb_watchdog_dbg_info(ah);
404 spin_unlock_irqrestore(&common->cc_lock, flags);
405
406 if (ar9003_hw_bb_watchdog_check(ah)) {
407 type = RESET_TYPE_BB_WATCHDOG;
408 ath9k_queue_reset(sc, type);
409
410 ath_dbg(common, RESET,
411 "BB_WATCHDOG: Skipping interrupts\n");
412 goto out;
413 }
414 }
415
416 if (status & ATH9K_INT_GTT) {
417 sc->gtt_cnt++;
418
419 if ((sc->gtt_cnt >= MAX_GTT_CNT) && !ath9k_hw_check_alive(ah)) {
420 type = RESET_TYPE_TX_GTT;
421 ath9k_queue_reset(sc, type);
422 ath_dbg(common, RESET,
423 "GTT: Skipping interrupts\n");
424 goto out;
425 }
426 }
427
428 spin_lock_irqsave(&sc->sc_pm_lock, flags);
429 if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {
430 /*
431 * TSF sync does not look correct; remain awake to sync with
432 * the next Beacon.
433 */
434 ath_dbg(common, PS, "TSFOOR - Sync with next Beacon\n");
435 sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC;
436 }
437 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
438
439 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
440 rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL |
441 ATH9K_INT_RXORN);
442 else
443 rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
444
445 if (status & rxmask) {
446 /* Check for high priority Rx first */
447 if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
448 (status & ATH9K_INT_RXHP))
449 ath_rx_tasklet(sc, 0, true);
450
451 ath_rx_tasklet(sc, 0, false);
452 }
453
454 if (status & ATH9K_INT_TX) {
455 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
456 /*
457 * For EDMA chips, TX completion is enabled for the
458 * beacon queue, so if a beacon has been transmitted
459 * successfully after a GTT interrupt, the GTT counter
460 * gets reset to zero here.
461 */
462 sc->gtt_cnt = 0;
463
464 ath_tx_edma_tasklet(sc);
465 } else {
466 ath_tx_tasklet(sc);
467 }
468
469 wake_up(&sc->tx_wait);
470 }
471
472 if (status & ATH9K_INT_GENTIMER)
473 ath_gen_timer_isr(sc->sc_ah);
474
475 ath9k_btcoex_handle_interrupt(sc, status);
476
477 /* re-enable hardware interrupt */
478 ath9k_hw_resume_interrupts(ah);
479 out:
480 spin_unlock(&sc->sc_pcu_lock);
481 ath9k_ps_restore(sc);
482 }
483
ath_isr(int irq,void * dev)484 irqreturn_t ath_isr(int irq, void *dev)
485 {
486 #define SCHED_INTR ( \
487 ATH9K_INT_FATAL | \
488 ATH9K_INT_BB_WATCHDOG | \
489 ATH9K_INT_RXORN | \
490 ATH9K_INT_RXEOL | \
491 ATH9K_INT_RX | \
492 ATH9K_INT_RXLP | \
493 ATH9K_INT_RXHP | \
494 ATH9K_INT_TX | \
495 ATH9K_INT_BMISS | \
496 ATH9K_INT_CST | \
497 ATH9K_INT_GTT | \
498 ATH9K_INT_TSFOOR | \
499 ATH9K_INT_GENTIMER | \
500 ATH9K_INT_MCI)
501
502 struct ath_softc *sc = dev;
503 struct ath_hw *ah = sc->sc_ah;
504 struct ath_common *common = ath9k_hw_common(ah);
505 enum ath9k_int status;
506 u32 sync_cause = 0;
507 bool sched = false;
508
509 /*
510 * The hardware is not ready/present, don't
511 * touch anything. Note this can happen early
512 * on if the IRQ is shared.
513 */
514 if (!ah || test_bit(ATH_OP_INVALID, &common->op_flags))
515 return IRQ_NONE;
516
517 /* shared irq, not for us */
518 if (!ath9k_hw_intrpend(ah))
519 return IRQ_NONE;
520
521 /*
522 * Figure out the reason(s) for the interrupt. Note
523 * that the hal returns a pseudo-ISR that may include
524 * bits we haven't explicitly enabled so we mask the
525 * value to insure we only process bits we requested.
526 */
527 ath9k_hw_getisr(ah, &status, &sync_cause); /* NB: clears ISR too */
528 ath9k_debug_sync_cause(sc, sync_cause);
529 status &= ah->imask; /* discard unasked-for bits */
530
531 if (test_bit(ATH_OP_HW_RESET, &common->op_flags))
532 return IRQ_HANDLED;
533
534 /*
535 * If there are no status bits set, then this interrupt was not
536 * for me (should have been caught above).
537 */
538 if (!status)
539 return IRQ_NONE;
540
541 /* Cache the status */
542 spin_lock(&sc->intr_lock);
543 sc->intrstatus |= status;
544 spin_unlock(&sc->intr_lock);
545
546 if (status & SCHED_INTR)
547 sched = true;
548
549 /*
550 * If a FATAL interrupt is received, we have to reset the chip
551 * immediately.
552 */
553 if (status & ATH9K_INT_FATAL)
554 goto chip_reset;
555
556 if ((ah->config.hw_hang_checks & HW_BB_WATCHDOG) &&
557 (status & ATH9K_INT_BB_WATCHDOG))
558 goto chip_reset;
559
560 if (status & ATH9K_INT_SWBA)
561 tasklet_schedule(&sc->bcon_tasklet);
562
563 if (status & ATH9K_INT_TXURN)
564 ath9k_hw_updatetxtriglevel(ah, true);
565
566 if (status & ATH9K_INT_RXEOL) {
567 ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
568 ath9k_hw_set_interrupts(ah);
569 }
570
571 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
572 if (status & ATH9K_INT_TIM_TIMER) {
573 if (ATH_DBG_WARN_ON_ONCE(sc->ps_idle))
574 goto chip_reset;
575 /* Clear RxAbort bit so that we can
576 * receive frames */
577 ath9k_setpower(sc, ATH9K_PM_AWAKE);
578 spin_lock(&sc->sc_pm_lock);
579 ath9k_hw_setrxabort(sc->sc_ah, 0);
580 sc->ps_flags |= PS_WAIT_FOR_BEACON;
581 spin_unlock(&sc->sc_pm_lock);
582 }
583
584 chip_reset:
585
586 ath_debug_stat_interrupt(sc, status);
587
588 if (sched) {
589 /* turn off every interrupt */
590 ath9k_hw_kill_interrupts(ah);
591 tasklet_schedule(&sc->intr_tq);
592 }
593
594 return IRQ_HANDLED;
595
596 #undef SCHED_INTR
597 }
598
599 /*
600 * This function is called when a HW reset cannot be deferred
601 * and has to be immediate.
602 */
ath_reset(struct ath_softc * sc,struct ath9k_channel * hchan)603 int ath_reset(struct ath_softc *sc, struct ath9k_channel *hchan)
604 {
605 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
606 int r;
607
608 ath9k_hw_kill_interrupts(sc->sc_ah);
609 set_bit(ATH_OP_HW_RESET, &common->op_flags);
610
611 ath9k_ps_wakeup(sc);
612 r = ath_reset_internal(sc, hchan);
613 ath9k_ps_restore(sc);
614
615 return r;
616 }
617
618 /*
619 * When a HW reset can be deferred, it is added to the
620 * hw_reset_work workqueue, but we set ATH_OP_HW_RESET before
621 * queueing.
622 */
ath9k_queue_reset(struct ath_softc * sc,enum ath_reset_type type)623 void ath9k_queue_reset(struct ath_softc *sc, enum ath_reset_type type)
624 {
625 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
626 #ifdef CONFIG_ATH9K_DEBUGFS
627 RESET_STAT_INC(sc, type);
628 #endif
629 ath9k_hw_kill_interrupts(sc->sc_ah);
630 set_bit(ATH_OP_HW_RESET, &common->op_flags);
631 ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
632 }
633
ath_reset_work(struct work_struct * work)634 void ath_reset_work(struct work_struct *work)
635 {
636 struct ath_softc *sc = container_of(work, struct ath_softc, hw_reset_work);
637
638 ath9k_ps_wakeup(sc);
639 ath_reset_internal(sc, NULL);
640 ath9k_ps_restore(sc);
641 }
642
643 /**********************/
644 /* mac80211 callbacks */
645 /**********************/
646
ath9k_start(struct ieee80211_hw * hw)647 static int ath9k_start(struct ieee80211_hw *hw)
648 {
649 struct ath_softc *sc = hw->priv;
650 struct ath_hw *ah = sc->sc_ah;
651 struct ath_common *common = ath9k_hw_common(ah);
652 struct ieee80211_channel *curchan = sc->cur_chan->chandef.chan;
653 struct ath_chanctx *ctx = sc->cur_chan;
654 struct ath9k_channel *init_channel;
655 int r;
656
657 ath_dbg(common, CONFIG,
658 "Starting driver with initial channel: %d MHz\n",
659 curchan->center_freq);
660
661 ath9k_ps_wakeup(sc);
662 mutex_lock(&sc->mutex);
663
664 init_channel = ath9k_cmn_get_channel(hw, ah, &ctx->chandef);
665 sc->cur_chandef = hw->conf.chandef;
666
667 /* Reset SERDES registers */
668 ath9k_hw_configpcipowersave(ah, false);
669
670 /*
671 * The basic interface to setting the hardware in a good
672 * state is ``reset''. On return the hardware is known to
673 * be powered up and with interrupts disabled. This must
674 * be followed by initialization of the appropriate bits
675 * and then setup of the interrupt mask.
676 */
677 spin_lock_bh(&sc->sc_pcu_lock);
678
679 atomic_set(&ah->intr_ref_cnt, -1);
680
681 r = ath9k_hw_reset(ah, init_channel, ah->caldata, false);
682 if (r) {
683 ath_err(common,
684 "Unable to reset hardware; reset status %d (freq %u MHz)\n",
685 r, curchan->center_freq);
686 ah->reset_power_on = false;
687 }
688
689 /* Setup our intr mask. */
690 ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL |
691 ATH9K_INT_RXORN | ATH9K_INT_FATAL |
692 ATH9K_INT_GLOBAL;
693
694 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
695 ah->imask |= ATH9K_INT_RXHP |
696 ATH9K_INT_RXLP;
697 else
698 ah->imask |= ATH9K_INT_RX;
699
700 if (ah->config.hw_hang_checks & HW_BB_WATCHDOG)
701 ah->imask |= ATH9K_INT_BB_WATCHDOG;
702
703 /*
704 * Enable GTT interrupts only for AR9003/AR9004 chips
705 * for now.
706 */
707 if (AR_SREV_9300_20_OR_LATER(ah))
708 ah->imask |= ATH9K_INT_GTT;
709
710 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT)
711 ah->imask |= ATH9K_INT_CST;
712
713 ath_mci_enable(sc);
714
715 clear_bit(ATH_OP_INVALID, &common->op_flags);
716 sc->sc_ah->is_monitoring = false;
717
718 if (!ath_complete_reset(sc, false))
719 ah->reset_power_on = false;
720
721 if (ah->led_pin >= 0) {
722 ath9k_hw_set_gpio(ah, ah->led_pin,
723 (ah->config.led_active_high) ? 1 : 0);
724 ath9k_hw_gpio_request_out(ah, ah->led_pin, NULL,
725 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
726 }
727
728 /*
729 * Reset key cache to sane defaults (all entries cleared) instead of
730 * semi-random values after suspend/resume.
731 */
732 ath9k_cmn_init_crypto(sc->sc_ah);
733
734 ath9k_hw_reset_tsf(ah);
735
736 spin_unlock_bh(&sc->sc_pcu_lock);
737
738 ath9k_rng_start(sc);
739
740 mutex_unlock(&sc->mutex);
741
742 ath9k_ps_restore(sc);
743
744 return 0;
745 }
746
ath9k_tx(struct ieee80211_hw * hw,struct ieee80211_tx_control * control,struct sk_buff * skb)747 static void ath9k_tx(struct ieee80211_hw *hw,
748 struct ieee80211_tx_control *control,
749 struct sk_buff *skb)
750 {
751 struct ath_softc *sc = hw->priv;
752 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
753 struct ath_tx_control txctl;
754 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
755 unsigned long flags;
756
757 if (sc->ps_enabled) {
758 /*
759 * mac80211 does not set PM field for normal data frames, so we
760 * need to update that based on the current PS mode.
761 */
762 if (ieee80211_is_data(hdr->frame_control) &&
763 !ieee80211_is_nullfunc(hdr->frame_control) &&
764 !ieee80211_has_pm(hdr->frame_control)) {
765 ath_dbg(common, PS,
766 "Add PM=1 for a TX frame while in PS mode\n");
767 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
768 }
769 }
770
771 if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_NETWORK_SLEEP)) {
772 /*
773 * We are using PS-Poll and mac80211 can request TX while in
774 * power save mode. Need to wake up hardware for the TX to be
775 * completed and if needed, also for RX of buffered frames.
776 */
777 ath9k_ps_wakeup(sc);
778 spin_lock_irqsave(&sc->sc_pm_lock, flags);
779 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
780 ath9k_hw_setrxabort(sc->sc_ah, 0);
781 if (ieee80211_is_pspoll(hdr->frame_control)) {
782 ath_dbg(common, PS,
783 "Sending PS-Poll to pick a buffered frame\n");
784 sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA;
785 } else {
786 ath_dbg(common, PS, "Wake up to complete TX\n");
787 sc->ps_flags |= PS_WAIT_FOR_TX_ACK;
788 }
789 /*
790 * The actual restore operation will happen only after
791 * the ps_flags bit is cleared. We are just dropping
792 * the ps_usecount here.
793 */
794 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
795 ath9k_ps_restore(sc);
796 }
797
798 /*
799 * Cannot tx while the hardware is in full sleep, it first needs a full
800 * chip reset to recover from that
801 */
802 if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_FULL_SLEEP)) {
803 ath_err(common, "TX while HW is in FULL_SLEEP mode\n");
804 goto exit;
805 }
806
807 memset(&txctl, 0, sizeof(struct ath_tx_control));
808 txctl.txq = sc->tx.txq_map[skb_get_queue_mapping(skb)];
809 txctl.sta = control->sta;
810
811 ath_dbg(common, XMIT, "transmitting packet, skb: %p\n", skb);
812
813 if (ath_tx_start(hw, skb, &txctl) != 0) {
814 ath_dbg(common, XMIT, "TX failed\n");
815 TX_STAT_INC(sc, txctl.txq->axq_qnum, txfailed);
816 goto exit;
817 }
818
819 return;
820 exit:
821 ieee80211_free_txskb(hw, skb);
822 }
823
ath9k_stop(struct ieee80211_hw * hw)824 static void ath9k_stop(struct ieee80211_hw *hw)
825 {
826 struct ath_softc *sc = hw->priv;
827 struct ath_hw *ah = sc->sc_ah;
828 struct ath_common *common = ath9k_hw_common(ah);
829 bool prev_idle;
830
831 ath9k_deinit_channel_context(sc);
832
833 mutex_lock(&sc->mutex);
834
835 ath9k_rng_stop(sc);
836
837 ath_cancel_work(sc);
838
839 if (test_bit(ATH_OP_INVALID, &common->op_flags)) {
840 ath_dbg(common, ANY, "Device not present\n");
841 mutex_unlock(&sc->mutex);
842 return;
843 }
844
845 /* Ensure HW is awake when we try to shut it down. */
846 ath9k_ps_wakeup(sc);
847
848 spin_lock_bh(&sc->sc_pcu_lock);
849
850 /* prevent tasklets to enable interrupts once we disable them */
851 ah->imask &= ~ATH9K_INT_GLOBAL;
852
853 /* make sure h/w will not generate any interrupt
854 * before setting the invalid flag. */
855 ath9k_hw_disable_interrupts(ah);
856
857 spin_unlock_bh(&sc->sc_pcu_lock);
858
859 /* we can now sync irq and kill any running tasklets, since we already
860 * disabled interrupts and not holding a spin lock */
861 synchronize_irq(sc->irq);
862 tasklet_kill(&sc->intr_tq);
863 tasklet_kill(&sc->bcon_tasklet);
864
865 prev_idle = sc->ps_idle;
866 sc->ps_idle = true;
867
868 spin_lock_bh(&sc->sc_pcu_lock);
869
870 if (ah->led_pin >= 0) {
871 ath9k_hw_set_gpio(ah, ah->led_pin,
872 (ah->config.led_active_high) ? 0 : 1);
873 ath9k_hw_gpio_request_in(ah, ah->led_pin, NULL);
874 }
875
876 ath_prepare_reset(sc);
877
878 if (sc->rx.frag) {
879 dev_kfree_skb_any(sc->rx.frag);
880 sc->rx.frag = NULL;
881 }
882
883 if (!ah->curchan)
884 ah->curchan = ath9k_cmn_get_channel(hw, ah,
885 &sc->cur_chan->chandef);
886
887 ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
888
889 set_bit(ATH_OP_INVALID, &common->op_flags);
890
891 ath9k_hw_phy_disable(ah);
892
893 ath9k_hw_configpcipowersave(ah, true);
894
895 spin_unlock_bh(&sc->sc_pcu_lock);
896
897 ath9k_ps_restore(sc);
898
899 sc->ps_idle = prev_idle;
900
901 mutex_unlock(&sc->mutex);
902
903 ath_dbg(common, CONFIG, "Driver halt\n");
904 }
905
ath9k_uses_beacons(int type)906 static bool ath9k_uses_beacons(int type)
907 {
908 switch (type) {
909 case NL80211_IFTYPE_AP:
910 case NL80211_IFTYPE_ADHOC:
911 case NL80211_IFTYPE_MESH_POINT:
912 return true;
913 default:
914 return false;
915 }
916 }
917
ath9k_vif_iter_set_beacon(struct ath9k_vif_iter_data * iter_data,struct ieee80211_vif * vif)918 static void ath9k_vif_iter_set_beacon(struct ath9k_vif_iter_data *iter_data,
919 struct ieee80211_vif *vif)
920 {
921 /* Use the first (configured) interface, but prefering AP interfaces. */
922 if (!iter_data->primary_beacon_vif) {
923 iter_data->primary_beacon_vif = vif;
924 } else {
925 if (iter_data->primary_beacon_vif->type != NL80211_IFTYPE_AP &&
926 vif->type == NL80211_IFTYPE_AP)
927 iter_data->primary_beacon_vif = vif;
928 }
929
930 iter_data->beacons = true;
931 iter_data->nbcnvifs += 1;
932 }
933
ath9k_vif_iter(struct ath9k_vif_iter_data * iter_data,u8 * mac,struct ieee80211_vif * vif)934 static void ath9k_vif_iter(struct ath9k_vif_iter_data *iter_data,
935 u8 *mac, struct ieee80211_vif *vif)
936 {
937 struct ath_vif *avp = (struct ath_vif *)vif->drv_priv;
938 int i;
939
940 if (iter_data->has_hw_macaddr) {
941 for (i = 0; i < ETH_ALEN; i++)
942 iter_data->mask[i] &=
943 ~(iter_data->hw_macaddr[i] ^ mac[i]);
944 } else {
945 memcpy(iter_data->hw_macaddr, mac, ETH_ALEN);
946 iter_data->has_hw_macaddr = true;
947 }
948
949 if (!vif->bss_conf.use_short_slot)
950 iter_data->slottime = 20;
951
952 switch (vif->type) {
953 case NL80211_IFTYPE_AP:
954 iter_data->naps++;
955 if (vif->bss_conf.enable_beacon)
956 ath9k_vif_iter_set_beacon(iter_data, vif);
957 break;
958 case NL80211_IFTYPE_STATION:
959 iter_data->nstations++;
960 if (avp->assoc && !iter_data->primary_sta)
961 iter_data->primary_sta = vif;
962 break;
963 case NL80211_IFTYPE_OCB:
964 iter_data->nocbs++;
965 break;
966 case NL80211_IFTYPE_ADHOC:
967 iter_data->nadhocs++;
968 if (vif->bss_conf.enable_beacon)
969 ath9k_vif_iter_set_beacon(iter_data, vif);
970 break;
971 case NL80211_IFTYPE_MESH_POINT:
972 iter_data->nmeshes++;
973 if (vif->bss_conf.enable_beacon)
974 ath9k_vif_iter_set_beacon(iter_data, vif);
975 break;
976 case NL80211_IFTYPE_WDS:
977 iter_data->nwds++;
978 break;
979 default:
980 break;
981 }
982 }
983
ath9k_update_bssid_mask(struct ath_softc * sc,struct ath_chanctx * ctx,struct ath9k_vif_iter_data * iter_data)984 static void ath9k_update_bssid_mask(struct ath_softc *sc,
985 struct ath_chanctx *ctx,
986 struct ath9k_vif_iter_data *iter_data)
987 {
988 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
989 struct ath_vif *avp;
990 int i;
991
992 if (!ath9k_is_chanctx_enabled())
993 return;
994
995 list_for_each_entry(avp, &ctx->vifs, list) {
996 if (ctx->nvifs_assigned != 1)
997 continue;
998
999 if (!iter_data->has_hw_macaddr)
1000 continue;
1001
1002 ether_addr_copy(common->curbssid, avp->bssid);
1003
1004 /* perm_addr will be used as the p2p device address. */
1005 for (i = 0; i < ETH_ALEN; i++)
1006 iter_data->mask[i] &=
1007 ~(iter_data->hw_macaddr[i] ^
1008 sc->hw->wiphy->perm_addr[i]);
1009 }
1010 }
1011
1012 /* Called with sc->mutex held. */
ath9k_calculate_iter_data(struct ath_softc * sc,struct ath_chanctx * ctx,struct ath9k_vif_iter_data * iter_data)1013 void ath9k_calculate_iter_data(struct ath_softc *sc,
1014 struct ath_chanctx *ctx,
1015 struct ath9k_vif_iter_data *iter_data)
1016 {
1017 struct ath_vif *avp;
1018
1019 /*
1020 * The hardware will use primary station addr together with the
1021 * BSSID mask when matching addresses.
1022 */
1023 memset(iter_data, 0, sizeof(*iter_data));
1024 eth_broadcast_addr(iter_data->mask);
1025 iter_data->slottime = 9;
1026
1027 list_for_each_entry(avp, &ctx->vifs, list)
1028 ath9k_vif_iter(iter_data, avp->vif->addr, avp->vif);
1029
1030 ath9k_update_bssid_mask(sc, ctx, iter_data);
1031 }
1032
ath9k_set_assoc_state(struct ath_softc * sc,struct ieee80211_vif * vif,bool changed)1033 static void ath9k_set_assoc_state(struct ath_softc *sc,
1034 struct ieee80211_vif *vif, bool changed)
1035 {
1036 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1037 struct ath_vif *avp = (struct ath_vif *)vif->drv_priv;
1038 unsigned long flags;
1039
1040 set_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags);
1041
1042 ether_addr_copy(common->curbssid, avp->bssid);
1043 common->curaid = avp->aid;
1044 ath9k_hw_write_associd(sc->sc_ah);
1045
1046 if (changed) {
1047 common->last_rssi = ATH_RSSI_DUMMY_MARKER;
1048 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
1049
1050 spin_lock_irqsave(&sc->sc_pm_lock, flags);
1051 sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;
1052 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
1053 }
1054
1055 if (ath9k_hw_mci_is_enabled(sc->sc_ah))
1056 ath9k_mci_update_wlan_channels(sc, false);
1057
1058 ath_dbg(common, CONFIG,
1059 "Primary Station interface: %pM, BSSID: %pM\n",
1060 vif->addr, common->curbssid);
1061 }
1062
1063 #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
ath9k_set_offchannel_state(struct ath_softc * sc)1064 static void ath9k_set_offchannel_state(struct ath_softc *sc)
1065 {
1066 struct ath_hw *ah = sc->sc_ah;
1067 struct ath_common *common = ath9k_hw_common(ah);
1068 struct ieee80211_vif *vif = NULL;
1069
1070 ath9k_ps_wakeup(sc);
1071
1072 if (sc->offchannel.state < ATH_OFFCHANNEL_ROC_START)
1073 vif = sc->offchannel.scan_vif;
1074 else
1075 vif = sc->offchannel.roc_vif;
1076
1077 if (WARN_ON(!vif))
1078 goto exit;
1079
1080 eth_zero_addr(common->curbssid);
1081 eth_broadcast_addr(common->bssidmask);
1082 memcpy(common->macaddr, vif->addr, ETH_ALEN);
1083 common->curaid = 0;
1084 ah->opmode = vif->type;
1085 ah->imask &= ~ATH9K_INT_SWBA;
1086 ah->imask &= ~ATH9K_INT_TSFOOR;
1087 ah->slottime = 9;
1088
1089 ath_hw_setbssidmask(common);
1090 ath9k_hw_setopmode(ah);
1091 ath9k_hw_write_associd(sc->sc_ah);
1092 ath9k_hw_set_interrupts(ah);
1093 ath9k_hw_init_global_settings(ah);
1094
1095 exit:
1096 ath9k_ps_restore(sc);
1097 }
1098 #endif
1099
1100 /* Called with sc->mutex held. */
ath9k_calculate_summary_state(struct ath_softc * sc,struct ath_chanctx * ctx)1101 void ath9k_calculate_summary_state(struct ath_softc *sc,
1102 struct ath_chanctx *ctx)
1103 {
1104 struct ath_hw *ah = sc->sc_ah;
1105 struct ath_common *common = ath9k_hw_common(ah);
1106 struct ath9k_vif_iter_data iter_data;
1107
1108 ath_chanctx_check_active(sc, ctx);
1109
1110 if (ctx != sc->cur_chan)
1111 return;
1112
1113 #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
1114 if (ctx == &sc->offchannel.chan)
1115 return ath9k_set_offchannel_state(sc);
1116 #endif
1117
1118 ath9k_ps_wakeup(sc);
1119 ath9k_calculate_iter_data(sc, ctx, &iter_data);
1120
1121 if (iter_data.has_hw_macaddr)
1122 memcpy(common->macaddr, iter_data.hw_macaddr, ETH_ALEN);
1123
1124 memcpy(common->bssidmask, iter_data.mask, ETH_ALEN);
1125 ath_hw_setbssidmask(common);
1126
1127 if (iter_data.naps > 0) {
1128 ath9k_hw_set_tsfadjust(ah, true);
1129 ah->opmode = NL80211_IFTYPE_AP;
1130 } else {
1131 ath9k_hw_set_tsfadjust(ah, false);
1132 if (iter_data.beacons)
1133 ath9k_beacon_ensure_primary_slot(sc);
1134
1135 if (iter_data.nmeshes)
1136 ah->opmode = NL80211_IFTYPE_MESH_POINT;
1137 else if (iter_data.nocbs)
1138 ah->opmode = NL80211_IFTYPE_OCB;
1139 else if (iter_data.nwds)
1140 ah->opmode = NL80211_IFTYPE_AP;
1141 else if (iter_data.nadhocs)
1142 ah->opmode = NL80211_IFTYPE_ADHOC;
1143 else
1144 ah->opmode = NL80211_IFTYPE_STATION;
1145 }
1146
1147 ath9k_hw_setopmode(ah);
1148
1149 ctx->switch_after_beacon = false;
1150 if ((iter_data.nstations + iter_data.nadhocs + iter_data.nmeshes) > 0)
1151 ah->imask |= ATH9K_INT_TSFOOR;
1152 else {
1153 ah->imask &= ~ATH9K_INT_TSFOOR;
1154 if (iter_data.naps == 1 && iter_data.beacons)
1155 ctx->switch_after_beacon = true;
1156 }
1157
1158 if (ah->opmode == NL80211_IFTYPE_STATION) {
1159 bool changed = (iter_data.primary_sta != ctx->primary_sta);
1160
1161 if (iter_data.primary_sta) {
1162 iter_data.primary_beacon_vif = iter_data.primary_sta;
1163 iter_data.beacons = true;
1164 ath9k_set_assoc_state(sc, iter_data.primary_sta,
1165 changed);
1166 ctx->primary_sta = iter_data.primary_sta;
1167 } else {
1168 ctx->primary_sta = NULL;
1169 eth_zero_addr(common->curbssid);
1170 common->curaid = 0;
1171 ath9k_hw_write_associd(sc->sc_ah);
1172 if (ath9k_hw_mci_is_enabled(sc->sc_ah))
1173 ath9k_mci_update_wlan_channels(sc, true);
1174 }
1175 }
1176 sc->nbcnvifs = iter_data.nbcnvifs;
1177 ath9k_beacon_config(sc, iter_data.primary_beacon_vif,
1178 iter_data.beacons);
1179 ath9k_hw_set_interrupts(ah);
1180
1181 if (ah->slottime != iter_data.slottime) {
1182 ah->slottime = iter_data.slottime;
1183 ath9k_hw_init_global_settings(ah);
1184 }
1185
1186 if (iter_data.primary_sta)
1187 set_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags);
1188 else
1189 clear_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags);
1190
1191 ath_dbg(common, CONFIG,
1192 "macaddr: %pM, bssid: %pM, bssidmask: %pM\n",
1193 common->macaddr, common->curbssid, common->bssidmask);
1194
1195 ath9k_ps_restore(sc);
1196 }
1197
ath9k_tpc_vif_iter(void * data,u8 * mac,struct ieee80211_vif * vif)1198 static void ath9k_tpc_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
1199 {
1200 int *power = data;
1201
1202 if (vif->bss_conf.txpower == INT_MIN)
1203 return;
1204
1205 if (*power < vif->bss_conf.txpower)
1206 *power = vif->bss_conf.txpower;
1207 }
1208
1209 /* Called with sc->mutex held. */
ath9k_set_txpower(struct ath_softc * sc,struct ieee80211_vif * vif)1210 void ath9k_set_txpower(struct ath_softc *sc, struct ieee80211_vif *vif)
1211 {
1212 int power;
1213 struct ath_hw *ah = sc->sc_ah;
1214 struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
1215
1216 ath9k_ps_wakeup(sc);
1217 if (ah->tpc_enabled) {
1218 power = (vif) ? vif->bss_conf.txpower : -1;
1219 ieee80211_iterate_active_interfaces_atomic(
1220 sc->hw, IEEE80211_IFACE_ITER_RESUME_ALL,
1221 ath9k_tpc_vif_iter, &power);
1222 if (power == -1)
1223 power = sc->hw->conf.power_level;
1224 } else {
1225 power = sc->hw->conf.power_level;
1226 }
1227 sc->cur_chan->txpower = 2 * power;
1228 ath9k_hw_set_txpowerlimit(ah, sc->cur_chan->txpower, false);
1229 sc->cur_chan->cur_txpower = reg->max_power_level;
1230 ath9k_ps_restore(sc);
1231 }
1232
ath9k_assign_hw_queues(struct ieee80211_hw * hw,struct ieee80211_vif * vif)1233 static void ath9k_assign_hw_queues(struct ieee80211_hw *hw,
1234 struct ieee80211_vif *vif)
1235 {
1236 int i;
1237
1238 if (!ath9k_is_chanctx_enabled())
1239 return;
1240
1241 for (i = 0; i < IEEE80211_NUM_ACS; i++)
1242 vif->hw_queue[i] = i;
1243
1244 if (vif->type == NL80211_IFTYPE_AP ||
1245 vif->type == NL80211_IFTYPE_MESH_POINT)
1246 vif->cab_queue = hw->queues - 2;
1247 else
1248 vif->cab_queue = IEEE80211_INVAL_HW_QUEUE;
1249 }
1250
ath9k_add_interface(struct ieee80211_hw * hw,struct ieee80211_vif * vif)1251 static int ath9k_add_interface(struct ieee80211_hw *hw,
1252 struct ieee80211_vif *vif)
1253 {
1254 struct ath_softc *sc = hw->priv;
1255 struct ath_hw *ah = sc->sc_ah;
1256 struct ath_common *common = ath9k_hw_common(ah);
1257 struct ath_vif *avp = (void *)vif->drv_priv;
1258 struct ath_node *an = &avp->mcast_node;
1259
1260 mutex_lock(&sc->mutex);
1261 if (IS_ENABLED(CONFIG_ATH9K_TX99)) {
1262 if (sc->cur_chan->nvifs >= 1) {
1263 mutex_unlock(&sc->mutex);
1264 return -EOPNOTSUPP;
1265 }
1266 sc->tx99_vif = vif;
1267 }
1268
1269 ath_dbg(common, CONFIG, "Attach a VIF of type: %d\n", vif->type);
1270 sc->cur_chan->nvifs++;
1271
1272 if (vif->type == NL80211_IFTYPE_STATION && ath9k_is_chanctx_enabled())
1273 vif->driver_flags |= IEEE80211_VIF_GET_NOA_UPDATE;
1274
1275 if (ath9k_uses_beacons(vif->type))
1276 ath9k_beacon_assign_slot(sc, vif);
1277
1278 avp->vif = vif;
1279 if (!ath9k_is_chanctx_enabled()) {
1280 avp->chanctx = sc->cur_chan;
1281 list_add_tail(&avp->list, &avp->chanctx->vifs);
1282 }
1283
1284 ath9k_calculate_summary_state(sc, avp->chanctx);
1285
1286 ath9k_assign_hw_queues(hw, vif);
1287
1288 ath9k_set_txpower(sc, vif);
1289
1290 an->sc = sc;
1291 an->sta = NULL;
1292 an->vif = vif;
1293 an->no_ps_filter = true;
1294 ath_tx_node_init(sc, an);
1295
1296 mutex_unlock(&sc->mutex);
1297 return 0;
1298 }
1299
ath9k_change_interface(struct ieee80211_hw * hw,struct ieee80211_vif * vif,enum nl80211_iftype new_type,bool p2p)1300 static int ath9k_change_interface(struct ieee80211_hw *hw,
1301 struct ieee80211_vif *vif,
1302 enum nl80211_iftype new_type,
1303 bool p2p)
1304 {
1305 struct ath_softc *sc = hw->priv;
1306 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1307 struct ath_vif *avp = (void *)vif->drv_priv;
1308
1309 mutex_lock(&sc->mutex);
1310
1311 if (IS_ENABLED(CONFIG_ATH9K_TX99)) {
1312 mutex_unlock(&sc->mutex);
1313 return -EOPNOTSUPP;
1314 }
1315
1316 ath_dbg(common, CONFIG, "Change Interface\n");
1317
1318 if (ath9k_uses_beacons(vif->type))
1319 ath9k_beacon_remove_slot(sc, vif);
1320
1321 vif->type = new_type;
1322 vif->p2p = p2p;
1323
1324 if (ath9k_uses_beacons(vif->type))
1325 ath9k_beacon_assign_slot(sc, vif);
1326
1327 ath9k_assign_hw_queues(hw, vif);
1328 ath9k_calculate_summary_state(sc, avp->chanctx);
1329
1330 ath9k_set_txpower(sc, vif);
1331
1332 mutex_unlock(&sc->mutex);
1333 return 0;
1334 }
1335
ath9k_remove_interface(struct ieee80211_hw * hw,struct ieee80211_vif * vif)1336 static void ath9k_remove_interface(struct ieee80211_hw *hw,
1337 struct ieee80211_vif *vif)
1338 {
1339 struct ath_softc *sc = hw->priv;
1340 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1341 struct ath_vif *avp = (void *)vif->drv_priv;
1342
1343 ath_dbg(common, CONFIG, "Detach Interface\n");
1344
1345 mutex_lock(&sc->mutex);
1346
1347 ath9k_p2p_remove_vif(sc, vif);
1348
1349 sc->cur_chan->nvifs--;
1350 sc->tx99_vif = NULL;
1351 if (!ath9k_is_chanctx_enabled())
1352 list_del(&avp->list);
1353
1354 if (ath9k_uses_beacons(vif->type))
1355 ath9k_beacon_remove_slot(sc, vif);
1356
1357 ath_tx_node_cleanup(sc, &avp->mcast_node);
1358
1359 ath9k_calculate_summary_state(sc, avp->chanctx);
1360
1361 ath9k_set_txpower(sc, NULL);
1362
1363 mutex_unlock(&sc->mutex);
1364 }
1365
ath9k_enable_ps(struct ath_softc * sc)1366 static void ath9k_enable_ps(struct ath_softc *sc)
1367 {
1368 struct ath_hw *ah = sc->sc_ah;
1369 struct ath_common *common = ath9k_hw_common(ah);
1370
1371 if (IS_ENABLED(CONFIG_ATH9K_TX99))
1372 return;
1373
1374 sc->ps_enabled = true;
1375 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1376 if ((ah->imask & ATH9K_INT_TIM_TIMER) == 0) {
1377 ah->imask |= ATH9K_INT_TIM_TIMER;
1378 ath9k_hw_set_interrupts(ah);
1379 }
1380 ath9k_hw_setrxabort(ah, 1);
1381 }
1382 ath_dbg(common, PS, "PowerSave enabled\n");
1383 }
1384
ath9k_disable_ps(struct ath_softc * sc)1385 static void ath9k_disable_ps(struct ath_softc *sc)
1386 {
1387 struct ath_hw *ah = sc->sc_ah;
1388 struct ath_common *common = ath9k_hw_common(ah);
1389
1390 if (IS_ENABLED(CONFIG_ATH9K_TX99))
1391 return;
1392
1393 sc->ps_enabled = false;
1394 ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
1395 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1396 ath9k_hw_setrxabort(ah, 0);
1397 sc->ps_flags &= ~(PS_WAIT_FOR_BEACON |
1398 PS_WAIT_FOR_CAB |
1399 PS_WAIT_FOR_PSPOLL_DATA |
1400 PS_WAIT_FOR_TX_ACK);
1401 if (ah->imask & ATH9K_INT_TIM_TIMER) {
1402 ah->imask &= ~ATH9K_INT_TIM_TIMER;
1403 ath9k_hw_set_interrupts(ah);
1404 }
1405 }
1406 ath_dbg(common, PS, "PowerSave disabled\n");
1407 }
1408
ath9k_config(struct ieee80211_hw * hw,u32 changed)1409 static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
1410 {
1411 struct ath_softc *sc = hw->priv;
1412 struct ath_hw *ah = sc->sc_ah;
1413 struct ath_common *common = ath9k_hw_common(ah);
1414 struct ieee80211_conf *conf = &hw->conf;
1415 struct ath_chanctx *ctx = sc->cur_chan;
1416
1417 ath9k_ps_wakeup(sc);
1418 mutex_lock(&sc->mutex);
1419
1420 if (changed & IEEE80211_CONF_CHANGE_IDLE) {
1421 sc->ps_idle = !!(conf->flags & IEEE80211_CONF_IDLE);
1422 if (sc->ps_idle) {
1423 ath_cancel_work(sc);
1424 ath9k_stop_btcoex(sc);
1425 } else {
1426 ath9k_start_btcoex(sc);
1427 /*
1428 * The chip needs a reset to properly wake up from
1429 * full sleep
1430 */
1431 ath_chanctx_set_channel(sc, ctx, &ctx->chandef);
1432 }
1433 }
1434
1435 /*
1436 * We just prepare to enable PS. We have to wait until our AP has
1437 * ACK'd our null data frame to disable RX otherwise we'll ignore
1438 * those ACKs and end up retransmitting the same null data frames.
1439 * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode.
1440 */
1441 if (changed & IEEE80211_CONF_CHANGE_PS) {
1442 unsigned long flags;
1443 spin_lock_irqsave(&sc->sc_pm_lock, flags);
1444 if (conf->flags & IEEE80211_CONF_PS)
1445 ath9k_enable_ps(sc);
1446 else
1447 ath9k_disable_ps(sc);
1448 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
1449 }
1450
1451 if (changed & IEEE80211_CONF_CHANGE_MONITOR) {
1452 if (conf->flags & IEEE80211_CONF_MONITOR) {
1453 ath_dbg(common, CONFIG, "Monitor mode is enabled\n");
1454 sc->sc_ah->is_monitoring = true;
1455 } else {
1456 ath_dbg(common, CONFIG, "Monitor mode is disabled\n");
1457 sc->sc_ah->is_monitoring = false;
1458 }
1459 }
1460
1461 if (!ath9k_is_chanctx_enabled() && (changed & IEEE80211_CONF_CHANGE_CHANNEL)) {
1462 ctx->offchannel = !!(conf->flags & IEEE80211_CONF_OFFCHANNEL);
1463 ath_chanctx_set_channel(sc, ctx, &hw->conf.chandef);
1464 }
1465
1466 if (changed & IEEE80211_CONF_CHANGE_POWER)
1467 ath9k_set_txpower(sc, NULL);
1468
1469 mutex_unlock(&sc->mutex);
1470 ath9k_ps_restore(sc);
1471
1472 return 0;
1473 }
1474
1475 #define SUPPORTED_FILTERS \
1476 (FIF_ALLMULTI | \
1477 FIF_CONTROL | \
1478 FIF_PSPOLL | \
1479 FIF_OTHER_BSS | \
1480 FIF_BCN_PRBRESP_PROMISC | \
1481 FIF_PROBE_REQ | \
1482 FIF_MCAST_ACTION | \
1483 FIF_FCSFAIL)
1484
1485 /* FIXME: sc->sc_full_reset ? */
ath9k_configure_filter(struct ieee80211_hw * hw,unsigned int changed_flags,unsigned int * total_flags,u64 multicast)1486 static void ath9k_configure_filter(struct ieee80211_hw *hw,
1487 unsigned int changed_flags,
1488 unsigned int *total_flags,
1489 u64 multicast)
1490 {
1491 struct ath_softc *sc = hw->priv;
1492 struct ath_chanctx *ctx;
1493 u32 rfilt;
1494
1495 changed_flags &= SUPPORTED_FILTERS;
1496 *total_flags &= SUPPORTED_FILTERS;
1497
1498 spin_lock_bh(&sc->chan_lock);
1499 ath_for_each_chanctx(sc, ctx)
1500 ctx->rxfilter = *total_flags;
1501 #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
1502 sc->offchannel.chan.rxfilter = *total_flags;
1503 #endif
1504 spin_unlock_bh(&sc->chan_lock);
1505
1506 ath9k_ps_wakeup(sc);
1507 rfilt = ath_calcrxfilter(sc);
1508 ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
1509 ath9k_ps_restore(sc);
1510
1511 ath_dbg(ath9k_hw_common(sc->sc_ah), CONFIG, "Set HW RX filter: 0x%x\n",
1512 rfilt);
1513 }
1514
ath9k_sta_add(struct ieee80211_hw * hw,struct ieee80211_vif * vif,struct ieee80211_sta * sta)1515 static int ath9k_sta_add(struct ieee80211_hw *hw,
1516 struct ieee80211_vif *vif,
1517 struct ieee80211_sta *sta)
1518 {
1519 struct ath_softc *sc = hw->priv;
1520 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1521 struct ath_node *an = (struct ath_node *) sta->drv_priv;
1522 struct ieee80211_key_conf ps_key = { };
1523 int key;
1524
1525 ath_node_attach(sc, sta, vif);
1526
1527 if (vif->type != NL80211_IFTYPE_AP &&
1528 vif->type != NL80211_IFTYPE_AP_VLAN)
1529 return 0;
1530
1531 key = ath_key_config(common, vif, sta, &ps_key);
1532 if (key > 0) {
1533 an->ps_key = key;
1534 an->key_idx[0] = key;
1535 }
1536
1537 return 0;
1538 }
1539
ath9k_del_ps_key(struct ath_softc * sc,struct ieee80211_vif * vif,struct ieee80211_sta * sta)1540 static void ath9k_del_ps_key(struct ath_softc *sc,
1541 struct ieee80211_vif *vif,
1542 struct ieee80211_sta *sta)
1543 {
1544 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1545 struct ath_node *an = (struct ath_node *) sta->drv_priv;
1546 struct ieee80211_key_conf ps_key = { .hw_key_idx = an->ps_key };
1547
1548 if (!an->ps_key)
1549 return;
1550
1551 ath_key_delete(common, &ps_key);
1552 an->ps_key = 0;
1553 an->key_idx[0] = 0;
1554 }
1555
ath9k_sta_remove(struct ieee80211_hw * hw,struct ieee80211_vif * vif,struct ieee80211_sta * sta)1556 static int ath9k_sta_remove(struct ieee80211_hw *hw,
1557 struct ieee80211_vif *vif,
1558 struct ieee80211_sta *sta)
1559 {
1560 struct ath_softc *sc = hw->priv;
1561
1562 ath9k_del_ps_key(sc, vif, sta);
1563 ath_node_detach(sc, sta);
1564
1565 return 0;
1566 }
1567
ath9k_sta_state(struct ieee80211_hw * hw,struct ieee80211_vif * vif,struct ieee80211_sta * sta,enum ieee80211_sta_state old_state,enum ieee80211_sta_state new_state)1568 static int ath9k_sta_state(struct ieee80211_hw *hw,
1569 struct ieee80211_vif *vif,
1570 struct ieee80211_sta *sta,
1571 enum ieee80211_sta_state old_state,
1572 enum ieee80211_sta_state new_state)
1573 {
1574 struct ath_softc *sc = hw->priv;
1575 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1576 int ret = 0;
1577
1578 if (old_state == IEEE80211_STA_NOTEXIST &&
1579 new_state == IEEE80211_STA_NONE) {
1580 ret = ath9k_sta_add(hw, vif, sta);
1581 ath_dbg(common, CONFIG,
1582 "Add station: %pM\n", sta->addr);
1583 } else if (old_state == IEEE80211_STA_NONE &&
1584 new_state == IEEE80211_STA_NOTEXIST) {
1585 ret = ath9k_sta_remove(hw, vif, sta);
1586 ath_dbg(common, CONFIG,
1587 "Remove station: %pM\n", sta->addr);
1588 }
1589
1590 if (ath9k_is_chanctx_enabled()) {
1591 if (vif->type == NL80211_IFTYPE_STATION) {
1592 if (old_state == IEEE80211_STA_ASSOC &&
1593 new_state == IEEE80211_STA_AUTHORIZED)
1594 ath_chanctx_event(sc, vif,
1595 ATH_CHANCTX_EVENT_AUTHORIZED);
1596 }
1597 }
1598
1599 return ret;
1600 }
1601
ath9k_sta_set_tx_filter(struct ath_hw * ah,struct ath_node * an,bool set)1602 static void ath9k_sta_set_tx_filter(struct ath_hw *ah,
1603 struct ath_node *an,
1604 bool set)
1605 {
1606 int i;
1607
1608 for (i = 0; i < ARRAY_SIZE(an->key_idx); i++) {
1609 if (!an->key_idx[i])
1610 continue;
1611 ath9k_hw_set_tx_filter(ah, an->key_idx[i], set);
1612 }
1613 }
1614
ath9k_sta_notify(struct ieee80211_hw * hw,struct ieee80211_vif * vif,enum sta_notify_cmd cmd,struct ieee80211_sta * sta)1615 static void ath9k_sta_notify(struct ieee80211_hw *hw,
1616 struct ieee80211_vif *vif,
1617 enum sta_notify_cmd cmd,
1618 struct ieee80211_sta *sta)
1619 {
1620 struct ath_softc *sc = hw->priv;
1621 struct ath_node *an = (struct ath_node *) sta->drv_priv;
1622
1623 switch (cmd) {
1624 case STA_NOTIFY_SLEEP:
1625 an->sleeping = true;
1626 ath_tx_aggr_sleep(sta, sc, an);
1627 ath9k_sta_set_tx_filter(sc->sc_ah, an, true);
1628 break;
1629 case STA_NOTIFY_AWAKE:
1630 ath9k_sta_set_tx_filter(sc->sc_ah, an, false);
1631 an->sleeping = false;
1632 ath_tx_aggr_wakeup(sc, an);
1633 break;
1634 }
1635 }
1636
ath9k_conf_tx(struct ieee80211_hw * hw,struct ieee80211_vif * vif,u16 queue,const struct ieee80211_tx_queue_params * params)1637 static int ath9k_conf_tx(struct ieee80211_hw *hw,
1638 struct ieee80211_vif *vif, u16 queue,
1639 const struct ieee80211_tx_queue_params *params)
1640 {
1641 struct ath_softc *sc = hw->priv;
1642 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1643 struct ath_txq *txq;
1644 struct ath9k_tx_queue_info qi;
1645 int ret = 0;
1646
1647 if (queue >= IEEE80211_NUM_ACS)
1648 return 0;
1649
1650 txq = sc->tx.txq_map[queue];
1651
1652 ath9k_ps_wakeup(sc);
1653 mutex_lock(&sc->mutex);
1654
1655 memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
1656
1657 qi.tqi_aifs = params->aifs;
1658 qi.tqi_cwmin = params->cw_min;
1659 qi.tqi_cwmax = params->cw_max;
1660 qi.tqi_burstTime = params->txop * 32;
1661
1662 ath_dbg(common, CONFIG,
1663 "Configure tx [queue/halq] [%d/%d], aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
1664 queue, txq->axq_qnum, params->aifs, params->cw_min,
1665 params->cw_max, params->txop);
1666
1667 ath_update_max_aggr_framelen(sc, queue, qi.tqi_burstTime);
1668 ret = ath_txq_update(sc, txq->axq_qnum, &qi);
1669 if (ret)
1670 ath_err(common, "TXQ Update failed\n");
1671
1672 mutex_unlock(&sc->mutex);
1673 ath9k_ps_restore(sc);
1674
1675 return ret;
1676 }
1677
ath9k_set_key(struct ieee80211_hw * hw,enum set_key_cmd cmd,struct ieee80211_vif * vif,struct ieee80211_sta * sta,struct ieee80211_key_conf * key)1678 static int ath9k_set_key(struct ieee80211_hw *hw,
1679 enum set_key_cmd cmd,
1680 struct ieee80211_vif *vif,
1681 struct ieee80211_sta *sta,
1682 struct ieee80211_key_conf *key)
1683 {
1684 struct ath_softc *sc = hw->priv;
1685 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1686 struct ath_node *an = NULL;
1687 int ret = 0, i;
1688
1689 if (ath9k_modparam_nohwcrypt)
1690 return -ENOSPC;
1691
1692 if ((vif->type == NL80211_IFTYPE_ADHOC ||
1693 vif->type == NL80211_IFTYPE_MESH_POINT) &&
1694 (key->cipher == WLAN_CIPHER_SUITE_TKIP ||
1695 key->cipher == WLAN_CIPHER_SUITE_CCMP) &&
1696 !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
1697 /*
1698 * For now, disable hw crypto for the RSN IBSS group keys. This
1699 * could be optimized in the future to use a modified key cache
1700 * design to support per-STA RX GTK, but until that gets
1701 * implemented, use of software crypto for group addressed
1702 * frames is a acceptable to allow RSN IBSS to be used.
1703 */
1704 return -EOPNOTSUPP;
1705 }
1706
1707 /* There may be MPDUs queued for the outgoing PTK key. Flush queues to
1708 * make sure these are not send unencrypted or with a wrong (new) key
1709 */
1710 if (cmd == DISABLE_KEY && key->flags & IEEE80211_KEY_FLAG_PAIRWISE) {
1711 ieee80211_stop_queues(hw);
1712 ath9k_flush(hw, vif, 0, true);
1713 ieee80211_wake_queues(hw);
1714 }
1715
1716 mutex_lock(&sc->mutex);
1717 ath9k_ps_wakeup(sc);
1718 ath_dbg(common, CONFIG, "Set HW Key %d\n", cmd);
1719 if (sta)
1720 an = (struct ath_node *)sta->drv_priv;
1721
1722 switch (cmd) {
1723 case SET_KEY:
1724 if (sta)
1725 ath9k_del_ps_key(sc, vif, sta);
1726
1727 key->hw_key_idx = 0;
1728 ret = ath_key_config(common, vif, sta, key);
1729 if (ret >= 0) {
1730 key->hw_key_idx = ret;
1731 /* push IV and Michael MIC generation to stack */
1732 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
1733 if (key->cipher == WLAN_CIPHER_SUITE_TKIP)
1734 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
1735 if (sc->sc_ah->sw_mgmt_crypto_tx &&
1736 key->cipher == WLAN_CIPHER_SUITE_CCMP)
1737 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT_TX;
1738 ret = 0;
1739 }
1740 if (an && key->hw_key_idx) {
1741 for (i = 0; i < ARRAY_SIZE(an->key_idx); i++) {
1742 if (an->key_idx[i])
1743 continue;
1744 an->key_idx[i] = key->hw_key_idx;
1745 break;
1746 }
1747 WARN_ON(i == ARRAY_SIZE(an->key_idx));
1748 }
1749 break;
1750 case DISABLE_KEY:
1751 ath_key_delete(common, key);
1752 if (an) {
1753 for (i = 0; i < ARRAY_SIZE(an->key_idx); i++) {
1754 if (an->key_idx[i] != key->hw_key_idx)
1755 continue;
1756 an->key_idx[i] = 0;
1757 break;
1758 }
1759 }
1760 key->hw_key_idx = 0;
1761 break;
1762 default:
1763 ret = -EINVAL;
1764 }
1765
1766 ath9k_ps_restore(sc);
1767 mutex_unlock(&sc->mutex);
1768
1769 return ret;
1770 }
1771
ath9k_bss_info_changed(struct ieee80211_hw * hw,struct ieee80211_vif * vif,struct ieee80211_bss_conf * bss_conf,u32 changed)1772 static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
1773 struct ieee80211_vif *vif,
1774 struct ieee80211_bss_conf *bss_conf,
1775 u32 changed)
1776 {
1777 #define CHECK_ANI \
1778 (BSS_CHANGED_ASSOC | \
1779 BSS_CHANGED_IBSS | \
1780 BSS_CHANGED_BEACON_ENABLED)
1781
1782 struct ath_softc *sc = hw->priv;
1783 struct ath_hw *ah = sc->sc_ah;
1784 struct ath_common *common = ath9k_hw_common(ah);
1785 struct ath_vif *avp = (void *)vif->drv_priv;
1786 int slottime;
1787
1788 ath9k_ps_wakeup(sc);
1789 mutex_lock(&sc->mutex);
1790
1791 if (changed & BSS_CHANGED_ASSOC) {
1792 ath_dbg(common, CONFIG, "BSSID %pM Changed ASSOC %d\n",
1793 bss_conf->bssid, bss_conf->assoc);
1794
1795 memcpy(avp->bssid, bss_conf->bssid, ETH_ALEN);
1796 avp->aid = bss_conf->aid;
1797 avp->assoc = bss_conf->assoc;
1798
1799 ath9k_calculate_summary_state(sc, avp->chanctx);
1800 }
1801
1802 if ((changed & BSS_CHANGED_IBSS) ||
1803 (changed & BSS_CHANGED_OCB)) {
1804 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
1805 common->curaid = bss_conf->aid;
1806 ath9k_hw_write_associd(sc->sc_ah);
1807 }
1808
1809 if ((changed & BSS_CHANGED_BEACON_ENABLED) ||
1810 (changed & BSS_CHANGED_BEACON_INT) ||
1811 (changed & BSS_CHANGED_BEACON_INFO)) {
1812 ath9k_calculate_summary_state(sc, avp->chanctx);
1813 }
1814
1815 if ((avp->chanctx == sc->cur_chan) &&
1816 (changed & BSS_CHANGED_ERP_SLOT)) {
1817 if (bss_conf->use_short_slot)
1818 slottime = 9;
1819 else
1820 slottime = 20;
1821
1822 if (vif->type == NL80211_IFTYPE_AP) {
1823 /*
1824 * Defer update, so that connected stations can adjust
1825 * their settings at the same time.
1826 * See beacon.c for more details
1827 */
1828 sc->beacon.slottime = slottime;
1829 sc->beacon.updateslot = UPDATE;
1830 } else {
1831 ah->slottime = slottime;
1832 ath9k_hw_init_global_settings(ah);
1833 }
1834 }
1835
1836 if (changed & BSS_CHANGED_P2P_PS)
1837 ath9k_p2p_bss_info_changed(sc, vif);
1838
1839 if (changed & CHECK_ANI)
1840 ath_check_ani(sc);
1841
1842 if (changed & BSS_CHANGED_TXPOWER) {
1843 ath_dbg(common, CONFIG, "vif %pM power %d dbm power_type %d\n",
1844 vif->addr, bss_conf->txpower, bss_conf->txpower_type);
1845 ath9k_set_txpower(sc, vif);
1846 }
1847
1848 mutex_unlock(&sc->mutex);
1849 ath9k_ps_restore(sc);
1850
1851 #undef CHECK_ANI
1852 }
1853
ath9k_get_tsf(struct ieee80211_hw * hw,struct ieee80211_vif * vif)1854 static u64 ath9k_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
1855 {
1856 struct ath_softc *sc = hw->priv;
1857 struct ath_vif *avp = (void *)vif->drv_priv;
1858 u64 tsf;
1859
1860 mutex_lock(&sc->mutex);
1861 ath9k_ps_wakeup(sc);
1862 /* Get current TSF either from HW or kernel time. */
1863 if (sc->cur_chan == avp->chanctx) {
1864 tsf = ath9k_hw_gettsf64(sc->sc_ah);
1865 } else {
1866 tsf = sc->cur_chan->tsf_val +
1867 ath9k_hw_get_tsf_offset(&sc->cur_chan->tsf_ts, NULL);
1868 }
1869 tsf += le64_to_cpu(avp->tsf_adjust);
1870 ath9k_ps_restore(sc);
1871 mutex_unlock(&sc->mutex);
1872
1873 return tsf;
1874 }
1875
ath9k_set_tsf(struct ieee80211_hw * hw,struct ieee80211_vif * vif,u64 tsf)1876 static void ath9k_set_tsf(struct ieee80211_hw *hw,
1877 struct ieee80211_vif *vif,
1878 u64 tsf)
1879 {
1880 struct ath_softc *sc = hw->priv;
1881 struct ath_vif *avp = (void *)vif->drv_priv;
1882
1883 mutex_lock(&sc->mutex);
1884 ath9k_ps_wakeup(sc);
1885 tsf -= le64_to_cpu(avp->tsf_adjust);
1886 ktime_get_raw_ts64(&avp->chanctx->tsf_ts);
1887 if (sc->cur_chan == avp->chanctx)
1888 ath9k_hw_settsf64(sc->sc_ah, tsf);
1889 avp->chanctx->tsf_val = tsf;
1890 ath9k_ps_restore(sc);
1891 mutex_unlock(&sc->mutex);
1892 }
1893
ath9k_reset_tsf(struct ieee80211_hw * hw,struct ieee80211_vif * vif)1894 static void ath9k_reset_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
1895 {
1896 struct ath_softc *sc = hw->priv;
1897 struct ath_vif *avp = (void *)vif->drv_priv;
1898
1899 mutex_lock(&sc->mutex);
1900
1901 ath9k_ps_wakeup(sc);
1902 ktime_get_raw_ts64(&avp->chanctx->tsf_ts);
1903 if (sc->cur_chan == avp->chanctx)
1904 ath9k_hw_reset_tsf(sc->sc_ah);
1905 avp->chanctx->tsf_val = 0;
1906 ath9k_ps_restore(sc);
1907
1908 mutex_unlock(&sc->mutex);
1909 }
1910
ath9k_ampdu_action(struct ieee80211_hw * hw,struct ieee80211_vif * vif,struct ieee80211_ampdu_params * params)1911 static int ath9k_ampdu_action(struct ieee80211_hw *hw,
1912 struct ieee80211_vif *vif,
1913 struct ieee80211_ampdu_params *params)
1914 {
1915 struct ath_softc *sc = hw->priv;
1916 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1917 bool flush = false;
1918 int ret = 0;
1919 struct ieee80211_sta *sta = params->sta;
1920 struct ath_node *an = (struct ath_node *)sta->drv_priv;
1921 enum ieee80211_ampdu_mlme_action action = params->action;
1922 u16 tid = params->tid;
1923 u16 *ssn = ¶ms->ssn;
1924 struct ath_atx_tid *atid;
1925
1926 mutex_lock(&sc->mutex);
1927
1928 switch (action) {
1929 case IEEE80211_AMPDU_RX_START:
1930 break;
1931 case IEEE80211_AMPDU_RX_STOP:
1932 break;
1933 case IEEE80211_AMPDU_TX_START:
1934 if (ath9k_is_chanctx_enabled()) {
1935 if (test_bit(ATH_OP_SCANNING, &common->op_flags)) {
1936 ret = -EBUSY;
1937 break;
1938 }
1939 }
1940 ath9k_ps_wakeup(sc);
1941 ret = ath_tx_aggr_start(sc, sta, tid, ssn);
1942 if (!ret)
1943 ret = IEEE80211_AMPDU_TX_START_IMMEDIATE;
1944 ath9k_ps_restore(sc);
1945 break;
1946 case IEEE80211_AMPDU_TX_STOP_FLUSH:
1947 case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:
1948 flush = true;
1949 fallthrough;
1950 case IEEE80211_AMPDU_TX_STOP_CONT:
1951 ath9k_ps_wakeup(sc);
1952 ath_tx_aggr_stop(sc, sta, tid);
1953 if (!flush)
1954 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
1955 ath9k_ps_restore(sc);
1956 break;
1957 case IEEE80211_AMPDU_TX_OPERATIONAL:
1958 atid = ath_node_to_tid(an, tid);
1959 atid->baw_size = IEEE80211_MIN_AMPDU_BUF <<
1960 sta->ht_cap.ampdu_factor;
1961 break;
1962 default:
1963 ath_err(ath9k_hw_common(sc->sc_ah), "Unknown AMPDU action\n");
1964 }
1965
1966 mutex_unlock(&sc->mutex);
1967
1968 return ret;
1969 }
1970
ath9k_get_survey(struct ieee80211_hw * hw,int idx,struct survey_info * survey)1971 static int ath9k_get_survey(struct ieee80211_hw *hw, int idx,
1972 struct survey_info *survey)
1973 {
1974 struct ath_softc *sc = hw->priv;
1975 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1976 struct ieee80211_supported_band *sband;
1977 struct ieee80211_channel *chan;
1978 unsigned long flags;
1979 int pos;
1980
1981 if (IS_ENABLED(CONFIG_ATH9K_TX99))
1982 return -EOPNOTSUPP;
1983
1984 spin_lock_irqsave(&common->cc_lock, flags);
1985 if (idx == 0)
1986 ath_update_survey_stats(sc);
1987
1988 sband = hw->wiphy->bands[NL80211_BAND_2GHZ];
1989 if (sband && idx >= sband->n_channels) {
1990 idx -= sband->n_channels;
1991 sband = NULL;
1992 }
1993
1994 if (!sband)
1995 sband = hw->wiphy->bands[NL80211_BAND_5GHZ];
1996
1997 if (!sband || idx >= sband->n_channels) {
1998 spin_unlock_irqrestore(&common->cc_lock, flags);
1999 return -ENOENT;
2000 }
2001
2002 chan = &sband->channels[idx];
2003 pos = chan->hw_value;
2004 memcpy(survey, &sc->survey[pos], sizeof(*survey));
2005 survey->channel = chan;
2006 spin_unlock_irqrestore(&common->cc_lock, flags);
2007
2008 return 0;
2009 }
2010
ath9k_enable_dynack(struct ath_softc * sc)2011 static void ath9k_enable_dynack(struct ath_softc *sc)
2012 {
2013 #ifdef CONFIG_ATH9K_DYNACK
2014 u32 rfilt;
2015 struct ath_hw *ah = sc->sc_ah;
2016
2017 ath_dynack_reset(ah);
2018
2019 ah->dynack.enabled = true;
2020 rfilt = ath_calcrxfilter(sc);
2021 ath9k_hw_setrxfilter(ah, rfilt);
2022 #endif
2023 }
2024
ath9k_set_coverage_class(struct ieee80211_hw * hw,s16 coverage_class)2025 static void ath9k_set_coverage_class(struct ieee80211_hw *hw,
2026 s16 coverage_class)
2027 {
2028 struct ath_softc *sc = hw->priv;
2029 struct ath_hw *ah = sc->sc_ah;
2030
2031 if (IS_ENABLED(CONFIG_ATH9K_TX99))
2032 return;
2033
2034 mutex_lock(&sc->mutex);
2035
2036 if (coverage_class >= 0) {
2037 ah->coverage_class = coverage_class;
2038 if (ah->dynack.enabled) {
2039 u32 rfilt;
2040
2041 ah->dynack.enabled = false;
2042 rfilt = ath_calcrxfilter(sc);
2043 ath9k_hw_setrxfilter(ah, rfilt);
2044 }
2045 ath9k_ps_wakeup(sc);
2046 ath9k_hw_init_global_settings(ah);
2047 ath9k_ps_restore(sc);
2048 } else if (!ah->dynack.enabled) {
2049 ath9k_enable_dynack(sc);
2050 }
2051
2052 mutex_unlock(&sc->mutex);
2053 }
2054
ath9k_has_tx_pending(struct ath_softc * sc,bool sw_pending)2055 static bool ath9k_has_tx_pending(struct ath_softc *sc,
2056 bool sw_pending)
2057 {
2058 int i, npend = 0;
2059
2060 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2061 if (!ATH_TXQ_SETUP(sc, i))
2062 continue;
2063
2064 npend = ath9k_has_pending_frames(sc, &sc->tx.txq[i],
2065 sw_pending);
2066 if (npend)
2067 break;
2068 }
2069
2070 return !!npend;
2071 }
2072
ath9k_flush(struct ieee80211_hw * hw,struct ieee80211_vif * vif,u32 queues,bool drop)2073 static void ath9k_flush(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2074 u32 queues, bool drop)
2075 {
2076 struct ath_softc *sc = hw->priv;
2077 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2078
2079 if (ath9k_is_chanctx_enabled()) {
2080 if (!test_bit(ATH_OP_MULTI_CHANNEL, &common->op_flags))
2081 goto flush;
2082
2083 /*
2084 * If MCC is active, extend the flush timeout
2085 * and wait for the HW/SW queues to become
2086 * empty. This needs to be done outside the
2087 * sc->mutex lock to allow the channel scheduler
2088 * to switch channel contexts.
2089 *
2090 * The vif queues have been stopped in mac80211,
2091 * so there won't be any incoming frames.
2092 */
2093 __ath9k_flush(hw, queues, drop, true, true);
2094 return;
2095 }
2096 flush:
2097 mutex_lock(&sc->mutex);
2098 __ath9k_flush(hw, queues, drop, true, false);
2099 mutex_unlock(&sc->mutex);
2100 }
2101
__ath9k_flush(struct ieee80211_hw * hw,u32 queues,bool drop,bool sw_pending,bool timeout_override)2102 void __ath9k_flush(struct ieee80211_hw *hw, u32 queues, bool drop,
2103 bool sw_pending, bool timeout_override)
2104 {
2105 struct ath_softc *sc = hw->priv;
2106 struct ath_hw *ah = sc->sc_ah;
2107 struct ath_common *common = ath9k_hw_common(ah);
2108 int timeout;
2109 bool drain_txq;
2110
2111 cancel_delayed_work_sync(&sc->hw_check_work);
2112
2113 if (ah->ah_flags & AH_UNPLUGGED) {
2114 ath_dbg(common, ANY, "Device has been unplugged!\n");
2115 return;
2116 }
2117
2118 if (test_bit(ATH_OP_INVALID, &common->op_flags)) {
2119 ath_dbg(common, ANY, "Device not present\n");
2120 return;
2121 }
2122
2123 spin_lock_bh(&sc->chan_lock);
2124 if (timeout_override)
2125 timeout = HZ / 5;
2126 else
2127 timeout = sc->cur_chan->flush_timeout;
2128 spin_unlock_bh(&sc->chan_lock);
2129
2130 ath_dbg(common, CHAN_CTX,
2131 "Flush timeout: %d\n", jiffies_to_msecs(timeout));
2132
2133 if (wait_event_timeout(sc->tx_wait, !ath9k_has_tx_pending(sc, sw_pending),
2134 timeout) > 0)
2135 drop = false;
2136
2137 if (drop) {
2138 ath9k_ps_wakeup(sc);
2139 spin_lock_bh(&sc->sc_pcu_lock);
2140 drain_txq = ath_drain_all_txq(sc);
2141 spin_unlock_bh(&sc->sc_pcu_lock);
2142
2143 if (!drain_txq)
2144 ath_reset(sc, NULL);
2145
2146 ath9k_ps_restore(sc);
2147 }
2148
2149 ieee80211_queue_delayed_work(hw, &sc->hw_check_work,
2150 ATH_HW_CHECK_POLL_INT);
2151 }
2152
ath9k_tx_frames_pending(struct ieee80211_hw * hw)2153 static bool ath9k_tx_frames_pending(struct ieee80211_hw *hw)
2154 {
2155 struct ath_softc *sc = hw->priv;
2156
2157 return ath9k_has_tx_pending(sc, true);
2158 }
2159
ath9k_tx_last_beacon(struct ieee80211_hw * hw)2160 static int ath9k_tx_last_beacon(struct ieee80211_hw *hw)
2161 {
2162 struct ath_softc *sc = hw->priv;
2163 struct ath_hw *ah = sc->sc_ah;
2164 struct ieee80211_vif *vif;
2165 struct ath_vif *avp;
2166 struct ath_buf *bf;
2167 struct ath_tx_status ts;
2168 bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
2169 int status;
2170
2171 vif = sc->beacon.bslot[0];
2172 if (!vif)
2173 return 0;
2174
2175 if (!vif->bss_conf.enable_beacon)
2176 return 0;
2177
2178 avp = (void *)vif->drv_priv;
2179
2180 if (!sc->beacon.tx_processed && !edma) {
2181 tasklet_disable(&sc->bcon_tasklet);
2182
2183 bf = avp->av_bcbuf;
2184 if (!bf || !bf->bf_mpdu)
2185 goto skip;
2186
2187 status = ath9k_hw_txprocdesc(ah, bf->bf_desc, &ts);
2188 if (status == -EINPROGRESS)
2189 goto skip;
2190
2191 sc->beacon.tx_processed = true;
2192 sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK);
2193
2194 skip:
2195 tasklet_enable(&sc->bcon_tasklet);
2196 }
2197
2198 return sc->beacon.tx_last;
2199 }
2200
ath9k_get_stats(struct ieee80211_hw * hw,struct ieee80211_low_level_stats * stats)2201 static int ath9k_get_stats(struct ieee80211_hw *hw,
2202 struct ieee80211_low_level_stats *stats)
2203 {
2204 struct ath_softc *sc = hw->priv;
2205 struct ath_hw *ah = sc->sc_ah;
2206 struct ath9k_mib_stats *mib_stats = &ah->ah_mibStats;
2207
2208 stats->dot11ACKFailureCount = mib_stats->ackrcv_bad;
2209 stats->dot11RTSFailureCount = mib_stats->rts_bad;
2210 stats->dot11FCSErrorCount = mib_stats->fcs_bad;
2211 stats->dot11RTSSuccessCount = mib_stats->rts_good;
2212 return 0;
2213 }
2214
fill_chainmask(u32 cap,u32 new)2215 static u32 fill_chainmask(u32 cap, u32 new)
2216 {
2217 u32 filled = 0;
2218 int i;
2219
2220 for (i = 0; cap && new; i++, cap >>= 1) {
2221 if (!(cap & BIT(0)))
2222 continue;
2223
2224 if (new & BIT(0))
2225 filled |= BIT(i);
2226
2227 new >>= 1;
2228 }
2229
2230 return filled;
2231 }
2232
validate_antenna_mask(struct ath_hw * ah,u32 val)2233 static bool validate_antenna_mask(struct ath_hw *ah, u32 val)
2234 {
2235 if (AR_SREV_9300_20_OR_LATER(ah))
2236 return true;
2237
2238 switch (val & 0x7) {
2239 case 0x1:
2240 case 0x3:
2241 case 0x7:
2242 return true;
2243 case 0x2:
2244 return (ah->caps.rx_chainmask == 1);
2245 default:
2246 return false;
2247 }
2248 }
2249
ath9k_set_antenna(struct ieee80211_hw * hw,u32 tx_ant,u32 rx_ant)2250 static int ath9k_set_antenna(struct ieee80211_hw *hw, u32 tx_ant, u32 rx_ant)
2251 {
2252 struct ath_softc *sc = hw->priv;
2253 struct ath_hw *ah = sc->sc_ah;
2254
2255 if (ah->caps.rx_chainmask != 1)
2256 rx_ant |= tx_ant;
2257
2258 if (!validate_antenna_mask(ah, rx_ant) || !tx_ant)
2259 return -EINVAL;
2260
2261 sc->ant_rx = rx_ant;
2262 sc->ant_tx = tx_ant;
2263
2264 if (ah->caps.rx_chainmask == 1)
2265 return 0;
2266
2267 /* AR9100 runs into calibration issues if not all rx chains are enabled */
2268 if (AR_SREV_9100(ah))
2269 ah->rxchainmask = 0x7;
2270 else
2271 ah->rxchainmask = fill_chainmask(ah->caps.rx_chainmask, rx_ant);
2272
2273 ah->txchainmask = fill_chainmask(ah->caps.tx_chainmask, tx_ant);
2274 ath9k_cmn_reload_chainmask(ah);
2275
2276 return 0;
2277 }
2278
ath9k_get_antenna(struct ieee80211_hw * hw,u32 * tx_ant,u32 * rx_ant)2279 static int ath9k_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant)
2280 {
2281 struct ath_softc *sc = hw->priv;
2282
2283 *tx_ant = sc->ant_tx;
2284 *rx_ant = sc->ant_rx;
2285 return 0;
2286 }
2287
ath9k_sw_scan_start(struct ieee80211_hw * hw,struct ieee80211_vif * vif,const u8 * mac_addr)2288 static void ath9k_sw_scan_start(struct ieee80211_hw *hw,
2289 struct ieee80211_vif *vif,
2290 const u8 *mac_addr)
2291 {
2292 struct ath_softc *sc = hw->priv;
2293 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2294 set_bit(ATH_OP_SCANNING, &common->op_flags);
2295 }
2296
ath9k_sw_scan_complete(struct ieee80211_hw * hw,struct ieee80211_vif * vif)2297 static void ath9k_sw_scan_complete(struct ieee80211_hw *hw,
2298 struct ieee80211_vif *vif)
2299 {
2300 struct ath_softc *sc = hw->priv;
2301 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2302 clear_bit(ATH_OP_SCANNING, &common->op_flags);
2303 }
2304
2305 #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
2306
ath9k_cancel_pending_offchannel(struct ath_softc * sc)2307 static void ath9k_cancel_pending_offchannel(struct ath_softc *sc)
2308 {
2309 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2310
2311 if (sc->offchannel.roc_vif) {
2312 ath_dbg(common, CHAN_CTX,
2313 "%s: Aborting RoC\n", __func__);
2314
2315 del_timer_sync(&sc->offchannel.timer);
2316 if (sc->offchannel.state >= ATH_OFFCHANNEL_ROC_START)
2317 ath_roc_complete(sc, ATH_ROC_COMPLETE_ABORT);
2318 }
2319
2320 if (test_bit(ATH_OP_SCANNING, &common->op_flags)) {
2321 ath_dbg(common, CHAN_CTX,
2322 "%s: Aborting HW scan\n", __func__);
2323
2324 del_timer_sync(&sc->offchannel.timer);
2325 ath_scan_complete(sc, true);
2326 }
2327 }
2328
ath9k_hw_scan(struct ieee80211_hw * hw,struct ieee80211_vif * vif,struct ieee80211_scan_request * hw_req)2329 static int ath9k_hw_scan(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2330 struct ieee80211_scan_request *hw_req)
2331 {
2332 struct cfg80211_scan_request *req = &hw_req->req;
2333 struct ath_softc *sc = hw->priv;
2334 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2335 int ret = 0;
2336
2337 mutex_lock(&sc->mutex);
2338
2339 if (WARN_ON(sc->offchannel.scan_req)) {
2340 ret = -EBUSY;
2341 goto out;
2342 }
2343
2344 ath9k_ps_wakeup(sc);
2345 set_bit(ATH_OP_SCANNING, &common->op_flags);
2346 sc->offchannel.scan_vif = vif;
2347 sc->offchannel.scan_req = req;
2348 sc->offchannel.scan_idx = 0;
2349
2350 ath_dbg(common, CHAN_CTX, "HW scan request received on vif: %pM\n",
2351 vif->addr);
2352
2353 if (sc->offchannel.state == ATH_OFFCHANNEL_IDLE) {
2354 ath_dbg(common, CHAN_CTX, "Starting HW scan\n");
2355 ath_offchannel_next(sc);
2356 }
2357
2358 out:
2359 mutex_unlock(&sc->mutex);
2360
2361 return ret;
2362 }
2363
ath9k_cancel_hw_scan(struct ieee80211_hw * hw,struct ieee80211_vif * vif)2364 static void ath9k_cancel_hw_scan(struct ieee80211_hw *hw,
2365 struct ieee80211_vif *vif)
2366 {
2367 struct ath_softc *sc = hw->priv;
2368 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2369
2370 ath_dbg(common, CHAN_CTX, "Cancel HW scan on vif: %pM\n", vif->addr);
2371
2372 mutex_lock(&sc->mutex);
2373 del_timer_sync(&sc->offchannel.timer);
2374 ath_scan_complete(sc, true);
2375 mutex_unlock(&sc->mutex);
2376 }
2377
ath9k_remain_on_channel(struct ieee80211_hw * hw,struct ieee80211_vif * vif,struct ieee80211_channel * chan,int duration,enum ieee80211_roc_type type)2378 static int ath9k_remain_on_channel(struct ieee80211_hw *hw,
2379 struct ieee80211_vif *vif,
2380 struct ieee80211_channel *chan, int duration,
2381 enum ieee80211_roc_type type)
2382 {
2383 struct ath_softc *sc = hw->priv;
2384 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2385 int ret = 0;
2386
2387 mutex_lock(&sc->mutex);
2388
2389 if (WARN_ON(sc->offchannel.roc_vif)) {
2390 ret = -EBUSY;
2391 goto out;
2392 }
2393
2394 ath9k_ps_wakeup(sc);
2395 sc->offchannel.roc_vif = vif;
2396 sc->offchannel.roc_chan = chan;
2397 sc->offchannel.roc_duration = duration;
2398
2399 ath_dbg(common, CHAN_CTX,
2400 "RoC request on vif: %pM, type: %d duration: %d\n",
2401 vif->addr, type, duration);
2402
2403 if (sc->offchannel.state == ATH_OFFCHANNEL_IDLE) {
2404 ath_dbg(common, CHAN_CTX, "Starting RoC period\n");
2405 ath_offchannel_next(sc);
2406 }
2407
2408 out:
2409 mutex_unlock(&sc->mutex);
2410
2411 return ret;
2412 }
2413
ath9k_cancel_remain_on_channel(struct ieee80211_hw * hw,struct ieee80211_vif * vif)2414 static int ath9k_cancel_remain_on_channel(struct ieee80211_hw *hw,
2415 struct ieee80211_vif *vif)
2416 {
2417 struct ath_softc *sc = hw->priv;
2418 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2419
2420 mutex_lock(&sc->mutex);
2421
2422 ath_dbg(common, CHAN_CTX, "Cancel RoC\n");
2423 del_timer_sync(&sc->offchannel.timer);
2424
2425 if (sc->offchannel.roc_vif) {
2426 if (sc->offchannel.state >= ATH_OFFCHANNEL_ROC_START)
2427 ath_roc_complete(sc, ATH_ROC_COMPLETE_CANCEL);
2428 }
2429
2430 mutex_unlock(&sc->mutex);
2431
2432 return 0;
2433 }
2434
ath9k_add_chanctx(struct ieee80211_hw * hw,struct ieee80211_chanctx_conf * conf)2435 static int ath9k_add_chanctx(struct ieee80211_hw *hw,
2436 struct ieee80211_chanctx_conf *conf)
2437 {
2438 struct ath_softc *sc = hw->priv;
2439 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2440 struct ath_chanctx *ctx, **ptr;
2441 int pos;
2442
2443 mutex_lock(&sc->mutex);
2444
2445 ath_for_each_chanctx(sc, ctx) {
2446 if (ctx->assigned)
2447 continue;
2448
2449 ptr = (void *) conf->drv_priv;
2450 *ptr = ctx;
2451 ctx->assigned = true;
2452 pos = ctx - &sc->chanctx[0];
2453 ctx->hw_queue_base = pos * IEEE80211_NUM_ACS;
2454
2455 ath_dbg(common, CHAN_CTX,
2456 "Add channel context: %d MHz\n",
2457 conf->def.chan->center_freq);
2458
2459 ath_chanctx_set_channel(sc, ctx, &conf->def);
2460
2461 mutex_unlock(&sc->mutex);
2462 return 0;
2463 }
2464
2465 mutex_unlock(&sc->mutex);
2466 return -ENOSPC;
2467 }
2468
2469
ath9k_remove_chanctx(struct ieee80211_hw * hw,struct ieee80211_chanctx_conf * conf)2470 static void ath9k_remove_chanctx(struct ieee80211_hw *hw,
2471 struct ieee80211_chanctx_conf *conf)
2472 {
2473 struct ath_softc *sc = hw->priv;
2474 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2475 struct ath_chanctx *ctx = ath_chanctx_get(conf);
2476
2477 mutex_lock(&sc->mutex);
2478
2479 ath_dbg(common, CHAN_CTX,
2480 "Remove channel context: %d MHz\n",
2481 conf->def.chan->center_freq);
2482
2483 ctx->assigned = false;
2484 ctx->hw_queue_base = 0;
2485 ath_chanctx_event(sc, NULL, ATH_CHANCTX_EVENT_UNASSIGN);
2486
2487 mutex_unlock(&sc->mutex);
2488 }
2489
ath9k_change_chanctx(struct ieee80211_hw * hw,struct ieee80211_chanctx_conf * conf,u32 changed)2490 static void ath9k_change_chanctx(struct ieee80211_hw *hw,
2491 struct ieee80211_chanctx_conf *conf,
2492 u32 changed)
2493 {
2494 struct ath_softc *sc = hw->priv;
2495 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2496 struct ath_chanctx *ctx = ath_chanctx_get(conf);
2497
2498 mutex_lock(&sc->mutex);
2499 ath_dbg(common, CHAN_CTX,
2500 "Change channel context: %d MHz\n",
2501 conf->def.chan->center_freq);
2502 ath_chanctx_set_channel(sc, ctx, &conf->def);
2503 mutex_unlock(&sc->mutex);
2504 }
2505
ath9k_assign_vif_chanctx(struct ieee80211_hw * hw,struct ieee80211_vif * vif,struct ieee80211_chanctx_conf * conf)2506 static int ath9k_assign_vif_chanctx(struct ieee80211_hw *hw,
2507 struct ieee80211_vif *vif,
2508 struct ieee80211_chanctx_conf *conf)
2509 {
2510 struct ath_softc *sc = hw->priv;
2511 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2512 struct ath_vif *avp = (void *)vif->drv_priv;
2513 struct ath_chanctx *ctx = ath_chanctx_get(conf);
2514 int i;
2515
2516 ath9k_cancel_pending_offchannel(sc);
2517
2518 mutex_lock(&sc->mutex);
2519
2520 ath_dbg(common, CHAN_CTX,
2521 "Assign VIF (addr: %pM, type: %d, p2p: %d) to channel context: %d MHz\n",
2522 vif->addr, vif->type, vif->p2p,
2523 conf->def.chan->center_freq);
2524
2525 avp->chanctx = ctx;
2526 ctx->nvifs_assigned++;
2527 list_add_tail(&avp->list, &ctx->vifs);
2528 ath9k_calculate_summary_state(sc, ctx);
2529 for (i = 0; i < IEEE80211_NUM_ACS; i++)
2530 vif->hw_queue[i] = ctx->hw_queue_base + i;
2531
2532 mutex_unlock(&sc->mutex);
2533
2534 return 0;
2535 }
2536
ath9k_unassign_vif_chanctx(struct ieee80211_hw * hw,struct ieee80211_vif * vif,struct ieee80211_chanctx_conf * conf)2537 static void ath9k_unassign_vif_chanctx(struct ieee80211_hw *hw,
2538 struct ieee80211_vif *vif,
2539 struct ieee80211_chanctx_conf *conf)
2540 {
2541 struct ath_softc *sc = hw->priv;
2542 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2543 struct ath_vif *avp = (void *)vif->drv_priv;
2544 struct ath_chanctx *ctx = ath_chanctx_get(conf);
2545 int ac;
2546
2547 ath9k_cancel_pending_offchannel(sc);
2548
2549 mutex_lock(&sc->mutex);
2550
2551 ath_dbg(common, CHAN_CTX,
2552 "Remove VIF (addr: %pM, type: %d, p2p: %d) from channel context: %d MHz\n",
2553 vif->addr, vif->type, vif->p2p,
2554 conf->def.chan->center_freq);
2555
2556 avp->chanctx = NULL;
2557 ctx->nvifs_assigned--;
2558 list_del(&avp->list);
2559 ath9k_calculate_summary_state(sc, ctx);
2560 for (ac = 0; ac < IEEE80211_NUM_ACS; ac++)
2561 vif->hw_queue[ac] = IEEE80211_INVAL_HW_QUEUE;
2562
2563 mutex_unlock(&sc->mutex);
2564 }
2565
ath9k_mgd_prepare_tx(struct ieee80211_hw * hw,struct ieee80211_vif * vif,u16 duration)2566 static void ath9k_mgd_prepare_tx(struct ieee80211_hw *hw,
2567 struct ieee80211_vif *vif,
2568 u16 duration)
2569 {
2570 struct ath_softc *sc = hw->priv;
2571 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2572 struct ath_vif *avp = (struct ath_vif *) vif->drv_priv;
2573 struct ath_beacon_config *cur_conf;
2574 struct ath_chanctx *go_ctx;
2575 unsigned long timeout;
2576 bool changed = false;
2577 u32 beacon_int;
2578
2579 if (!test_bit(ATH_OP_MULTI_CHANNEL, &common->op_flags))
2580 return;
2581
2582 if (!avp->chanctx)
2583 return;
2584
2585 mutex_lock(&sc->mutex);
2586
2587 spin_lock_bh(&sc->chan_lock);
2588 if (sc->next_chan || (sc->cur_chan != avp->chanctx))
2589 changed = true;
2590 spin_unlock_bh(&sc->chan_lock);
2591
2592 if (!changed)
2593 goto out;
2594
2595 ath9k_cancel_pending_offchannel(sc);
2596
2597 go_ctx = ath_is_go_chanctx_present(sc);
2598
2599 if (go_ctx) {
2600 /*
2601 * Wait till the GO interface gets a chance
2602 * to send out an NoA.
2603 */
2604 spin_lock_bh(&sc->chan_lock);
2605 sc->sched.mgd_prepare_tx = true;
2606 cur_conf = &go_ctx->beacon;
2607 beacon_int = TU_TO_USEC(cur_conf->beacon_interval);
2608 spin_unlock_bh(&sc->chan_lock);
2609
2610 timeout = usecs_to_jiffies(beacon_int * 2);
2611 init_completion(&sc->go_beacon);
2612
2613 mutex_unlock(&sc->mutex);
2614
2615 if (wait_for_completion_timeout(&sc->go_beacon,
2616 timeout) == 0) {
2617 ath_dbg(common, CHAN_CTX,
2618 "Failed to send new NoA\n");
2619
2620 spin_lock_bh(&sc->chan_lock);
2621 sc->sched.mgd_prepare_tx = false;
2622 spin_unlock_bh(&sc->chan_lock);
2623 }
2624
2625 mutex_lock(&sc->mutex);
2626 }
2627
2628 ath_dbg(common, CHAN_CTX,
2629 "%s: Set chanctx state to FORCE_ACTIVE for vif: %pM\n",
2630 __func__, vif->addr);
2631
2632 spin_lock_bh(&sc->chan_lock);
2633 sc->next_chan = avp->chanctx;
2634 sc->sched.state = ATH_CHANCTX_STATE_FORCE_ACTIVE;
2635 spin_unlock_bh(&sc->chan_lock);
2636
2637 ath_chanctx_set_next(sc, true);
2638 out:
2639 mutex_unlock(&sc->mutex);
2640 }
2641
ath9k_fill_chanctx_ops(void)2642 void ath9k_fill_chanctx_ops(void)
2643 {
2644 if (!ath9k_is_chanctx_enabled())
2645 return;
2646
2647 ath9k_ops.hw_scan = ath9k_hw_scan;
2648 ath9k_ops.cancel_hw_scan = ath9k_cancel_hw_scan;
2649 ath9k_ops.remain_on_channel = ath9k_remain_on_channel;
2650 ath9k_ops.cancel_remain_on_channel = ath9k_cancel_remain_on_channel;
2651 ath9k_ops.add_chanctx = ath9k_add_chanctx;
2652 ath9k_ops.remove_chanctx = ath9k_remove_chanctx;
2653 ath9k_ops.change_chanctx = ath9k_change_chanctx;
2654 ath9k_ops.assign_vif_chanctx = ath9k_assign_vif_chanctx;
2655 ath9k_ops.unassign_vif_chanctx = ath9k_unassign_vif_chanctx;
2656 ath9k_ops.mgd_prepare_tx = ath9k_mgd_prepare_tx;
2657 }
2658
2659 #endif
2660
ath9k_get_txpower(struct ieee80211_hw * hw,struct ieee80211_vif * vif,int * dbm)2661 static int ath9k_get_txpower(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2662 int *dbm)
2663 {
2664 struct ath_softc *sc = hw->priv;
2665 struct ath_vif *avp = (void *)vif->drv_priv;
2666
2667 mutex_lock(&sc->mutex);
2668 if (avp->chanctx)
2669 *dbm = avp->chanctx->cur_txpower;
2670 else
2671 *dbm = sc->cur_chan->cur_txpower;
2672 mutex_unlock(&sc->mutex);
2673
2674 *dbm /= 2;
2675
2676 return 0;
2677 }
2678
2679 struct ieee80211_ops ath9k_ops = {
2680 .tx = ath9k_tx,
2681 .start = ath9k_start,
2682 .stop = ath9k_stop,
2683 .add_interface = ath9k_add_interface,
2684 .change_interface = ath9k_change_interface,
2685 .remove_interface = ath9k_remove_interface,
2686 .config = ath9k_config,
2687 .configure_filter = ath9k_configure_filter,
2688 .sta_state = ath9k_sta_state,
2689 .sta_notify = ath9k_sta_notify,
2690 .conf_tx = ath9k_conf_tx,
2691 .bss_info_changed = ath9k_bss_info_changed,
2692 .set_key = ath9k_set_key,
2693 .get_tsf = ath9k_get_tsf,
2694 .set_tsf = ath9k_set_tsf,
2695 .reset_tsf = ath9k_reset_tsf,
2696 .ampdu_action = ath9k_ampdu_action,
2697 .get_survey = ath9k_get_survey,
2698 .rfkill_poll = ath9k_rfkill_poll_state,
2699 .set_coverage_class = ath9k_set_coverage_class,
2700 .flush = ath9k_flush,
2701 .tx_frames_pending = ath9k_tx_frames_pending,
2702 .tx_last_beacon = ath9k_tx_last_beacon,
2703 .release_buffered_frames = ath9k_release_buffered_frames,
2704 .get_stats = ath9k_get_stats,
2705 .set_antenna = ath9k_set_antenna,
2706 .get_antenna = ath9k_get_antenna,
2707
2708 #ifdef CONFIG_ATH9K_WOW
2709 .suspend = ath9k_suspend,
2710 .resume = ath9k_resume,
2711 .set_wakeup = ath9k_set_wakeup,
2712 #endif
2713
2714 #ifdef CONFIG_ATH9K_DEBUGFS
2715 .get_et_sset_count = ath9k_get_et_sset_count,
2716 .get_et_stats = ath9k_get_et_stats,
2717 .get_et_strings = ath9k_get_et_strings,
2718 #endif
2719
2720 #if defined(CONFIG_MAC80211_DEBUGFS) && defined(CONFIG_ATH9K_STATION_STATISTICS)
2721 .sta_add_debugfs = ath9k_sta_add_debugfs,
2722 #endif
2723 .sw_scan_start = ath9k_sw_scan_start,
2724 .sw_scan_complete = ath9k_sw_scan_complete,
2725 .get_txpower = ath9k_get_txpower,
2726 .wake_tx_queue = ath9k_wake_tx_queue,
2727 };
2728
