1 /*
2 * Copyright (c) 2008-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #ifndef HW_H
18 #define HW_H
19
20 #include <linux/if_ether.h>
21 #include <linux/delay.h>
22 #include <linux/io.h>
23 #include <linux/firmware.h>
24
25 #include "mac.h"
26 #include "ani.h"
27 #include "eeprom.h"
28 #include "calib.h"
29 #include "reg.h"
30 #include "reg_mci.h"
31 #include "phy.h"
32 #include "btcoex.h"
33 #include "dynack.h"
34
35 #include "../regd.h"
36
37 #define ATHEROS_VENDOR_ID 0x168c
38
39 #define AR5416_DEVID_PCI 0x0023
40 #define AR5416_DEVID_PCIE 0x0024
41 #define AR9160_DEVID_PCI 0x0027
42 #define AR9280_DEVID_PCI 0x0029
43 #define AR9280_DEVID_PCIE 0x002a
44 #define AR9285_DEVID_PCIE 0x002b
45 #define AR2427_DEVID_PCIE 0x002c
46 #define AR9287_DEVID_PCI 0x002d
47 #define AR9287_DEVID_PCIE 0x002e
48 #define AR9300_DEVID_PCIE 0x0030
49 #define AR9300_DEVID_AR9340 0x0031
50 #define AR9300_DEVID_AR9485_PCIE 0x0032
51 #define AR9300_DEVID_AR9580 0x0033
52 #define AR9300_DEVID_AR9462 0x0034
53 #define AR9300_DEVID_AR9330 0x0035
54 #define AR9300_DEVID_QCA955X 0x0038
55 #define AR9485_DEVID_AR1111 0x0037
56 #define AR9300_DEVID_AR9565 0x0036
57 #define AR9300_DEVID_AR953X 0x003d
58 #define AR9300_DEVID_QCA956X 0x003f
59
60 #define AR5416_AR9100_DEVID 0x000b
61
62 #define AR_SUBVENDOR_ID_NOG 0x0e11
63 #define AR_SUBVENDOR_ID_NEW_A 0x7065
64 #define AR5416_MAGIC 0x19641014
65
66 #define AR9280_COEX2WIRE_SUBSYSID 0x309b
67 #define AT9285_COEX3WIRE_SA_SUBSYSID 0x30aa
68 #define AT9285_COEX3WIRE_DA_SUBSYSID 0x30ab
69
70 #define ATH_AMPDU_LIMIT_MAX (64 * 1024 - 1)
71
72 #define ATH_DEFAULT_NOISE_FLOOR -95
73
74 #define ATH9K_RSSI_BAD -128
75
76 #define ATH9K_NUM_CHANNELS 38
77
78 /* Register read/write primitives */
79 #define REG_WRITE(_ah, _reg, _val) \
80 (_ah)->reg_ops.write((_ah), (_val), (_reg))
81
82 #define REG_READ(_ah, _reg) \
83 (_ah)->reg_ops.read((_ah), (_reg))
84
85 #define REG_READ_MULTI(_ah, _addr, _val, _cnt) \
86 (_ah)->reg_ops.multi_read((_ah), (_addr), (_val), (_cnt))
87
88 #define REG_RMW(_ah, _reg, _set, _clr) \
89 (_ah)->reg_ops.rmw((_ah), (_reg), (_set), (_clr))
90
91 #define ENABLE_REGWRITE_BUFFER(_ah) \
92 do { \
93 if ((_ah)->reg_ops.enable_write_buffer) \
94 (_ah)->reg_ops.enable_write_buffer((_ah)); \
95 } while (0)
96
97 #define REGWRITE_BUFFER_FLUSH(_ah) \
98 do { \
99 if ((_ah)->reg_ops.write_flush) \
100 (_ah)->reg_ops.write_flush((_ah)); \
101 } while (0)
102
103 #define ENABLE_REG_RMW_BUFFER(_ah) \
104 do { \
105 if ((_ah)->reg_ops.enable_rmw_buffer) \
106 (_ah)->reg_ops.enable_rmw_buffer((_ah)); \
107 } while (0)
108
109 #define REG_RMW_BUFFER_FLUSH(_ah) \
110 do { \
111 if ((_ah)->reg_ops.rmw_flush) \
112 (_ah)->reg_ops.rmw_flush((_ah)); \
113 } while (0)
114
115 #define PR_EEP(_s, _val) \
116 do { \
117 len += scnprintf(buf + len, size - len, "%20s : %10d\n",\
118 _s, (_val)); \
119 } while (0)
120
121 #define SM(_v, _f) (((_v) << _f##_S) & _f)
122 #define MS(_v, _f) (((_v) & _f) >> _f##_S)
123 #define REG_RMW_FIELD(_a, _r, _f, _v) \
124 REG_RMW(_a, _r, (((_v) << _f##_S) & _f), (_f))
125 #define REG_READ_FIELD(_a, _r, _f) \
126 (((REG_READ(_a, _r) & _f) >> _f##_S))
127 #define REG_SET_BIT(_a, _r, _f) \
128 REG_RMW(_a, _r, (_f), 0)
129 #define REG_CLR_BIT(_a, _r, _f) \
130 REG_RMW(_a, _r, 0, (_f))
131
132 #define DO_DELAY(x) do { \
133 if (((++(x) % 64) == 0) && \
134 (ath9k_hw_common(ah)->bus_ops->ath_bus_type \
135 != ATH_USB)) \
136 udelay(1); \
137 } while (0)
138
139 #define REG_WRITE_ARRAY(iniarray, column, regWr) \
140 ath9k_hw_write_array(ah, iniarray, column, &(regWr))
141 #define REG_READ_ARRAY(ah, array, size) \
142 ath9k_hw_read_array(ah, array, size)
143
144 #define AR_GPIO_OUTPUT_MUX_AS_OUTPUT 0
145 #define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED 1
146 #define AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED 2
147 #define AR_GPIO_OUTPUT_MUX_AS_TX_FRAME 3
148 #define AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL 4
149 #define AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED 5
150 #define AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED 6
151 #define AR_GPIO_OUTPUT_MUX_AS_MCI_WLAN_DATA 0x16
152 #define AR_GPIO_OUTPUT_MUX_AS_MCI_WLAN_CLK 0x17
153 #define AR_GPIO_OUTPUT_MUX_AS_MCI_BT_DATA 0x18
154 #define AR_GPIO_OUTPUT_MUX_AS_MCI_BT_CLK 0x19
155 #define AR_GPIO_OUTPUT_MUX_AS_WL_IN_TX 0x14
156 #define AR_GPIO_OUTPUT_MUX_AS_WL_IN_RX 0x13
157 #define AR_GPIO_OUTPUT_MUX_AS_BT_IN_TX 9
158 #define AR_GPIO_OUTPUT_MUX_AS_BT_IN_RX 8
159 #define AR_GPIO_OUTPUT_MUX_AS_RUCKUS_STROBE 0x1d
160 #define AR_GPIO_OUTPUT_MUX_AS_RUCKUS_DATA 0x1e
161
162 #define AR_GPIOD_MASK 0x00001FFF
163
164 #define BASE_ACTIVATE_DELAY 100
165 #define RTC_PLL_SETTLE_DELAY (AR_SREV_9340(ah) ? 1000 : 100)
166 #define COEF_SCALE_S 24
167 #define HT40_CHANNEL_CENTER_SHIFT 10
168
169 #define ATH9K_ANTENNA0_CHAINMASK 0x1
170 #define ATH9K_ANTENNA1_CHAINMASK 0x2
171
172 #define ATH9K_NUM_DMA_DEBUG_REGS 8
173 #define ATH9K_NUM_QUEUES 10
174
175 #define MAX_RATE_POWER 63
176 #define AH_WAIT_TIMEOUT 100000 /* (us) */
177 #define AH_TSF_WRITE_TIMEOUT 100 /* (us) */
178 #define AH_TIME_QUANTUM 10
179 #define AR_KEYTABLE_SIZE 128
180 #define POWER_UP_TIME 10000
181 #define SPUR_RSSI_THRESH 40
182 #define UPPER_5G_SUB_BAND_START 5700
183 #define MID_5G_SUB_BAND_START 5400
184
185 #define CAB_TIMEOUT_VAL 10
186 #define BEACON_TIMEOUT_VAL 10
187 #define MIN_BEACON_TIMEOUT_VAL 1
188 #define SLEEP_SLOP TU_TO_USEC(3)
189
190 #define INIT_CONFIG_STATUS 0x00000000
191 #define INIT_RSSI_THR 0x00000700
192 #define INIT_BCON_CNTRL_REG 0x00000000
193
194 #define TU_TO_USEC(_tu) ((_tu) << 10)
195
196 #define ATH9K_HW_RX_HP_QDEPTH 16
197 #define ATH9K_HW_RX_LP_QDEPTH 128
198
199 #define PAPRD_GAIN_TABLE_ENTRIES 32
200 #define PAPRD_TABLE_SZ 24
201 #define PAPRD_IDEAL_AGC2_PWR_RANGE 0xe0
202
203 /*
204 * Wake on Wireless
205 */
206
207 /* Keep Alive Frame */
208 #define KAL_FRAME_LEN 28
209 #define KAL_FRAME_TYPE 0x2 /* data frame */
210 #define KAL_FRAME_SUB_TYPE 0x4 /* null data frame */
211 #define KAL_DURATION_ID 0x3d
212 #define KAL_NUM_DATA_WORDS 6
213 #define KAL_NUM_DESC_WORDS 12
214 #define KAL_ANTENNA_MODE 1
215 #define KAL_TO_DS 1
216 #define KAL_DELAY 4 /* delay of 4ms between 2 KAL frames */
217 #define KAL_TIMEOUT 900
218
219 #define MAX_PATTERN_SIZE 256
220 #define MAX_PATTERN_MASK_SIZE 32
221 #define MAX_NUM_PATTERN 16
222 #define MAX_NUM_PATTERN_LEGACY 8
223 #define MAX_NUM_USER_PATTERN 6 /* deducting the disassociate and
224 deauthenticate packets */
225
226 /*
227 * WoW trigger mapping to hardware code
228 */
229
230 #define AH_WOW_USER_PATTERN_EN BIT(0)
231 #define AH_WOW_MAGIC_PATTERN_EN BIT(1)
232 #define AH_WOW_LINK_CHANGE BIT(2)
233 #define AH_WOW_BEACON_MISS BIT(3)
234
235 enum ath_hw_txq_subtype {
236 ATH_TXQ_AC_BK = 0,
237 ATH_TXQ_AC_BE = 1,
238 ATH_TXQ_AC_VI = 2,
239 ATH_TXQ_AC_VO = 3,
240 };
241
242 enum ath_ini_subsys {
243 ATH_INI_PRE = 0,
244 ATH_INI_CORE,
245 ATH_INI_POST,
246 ATH_INI_NUM_SPLIT,
247 };
248
249 enum ath9k_hw_caps {
250 ATH9K_HW_CAP_HT = BIT(0),
251 ATH9K_HW_CAP_RFSILENT = BIT(1),
252 ATH9K_HW_CAP_AUTOSLEEP = BIT(2),
253 ATH9K_HW_CAP_4KB_SPLITTRANS = BIT(3),
254 ATH9K_HW_CAP_EDMA = BIT(4),
255 ATH9K_HW_CAP_RAC_SUPPORTED = BIT(5),
256 ATH9K_HW_CAP_LDPC = BIT(6),
257 ATH9K_HW_CAP_FASTCLOCK = BIT(7),
258 ATH9K_HW_CAP_SGI_20 = BIT(8),
259 ATH9K_HW_CAP_ANT_DIV_COMB = BIT(10),
260 ATH9K_HW_CAP_2GHZ = BIT(11),
261 ATH9K_HW_CAP_5GHZ = BIT(12),
262 ATH9K_HW_CAP_APM = BIT(13),
263 #ifdef CONFIG_ATH9K_PCOEM
264 ATH9K_HW_CAP_RTT = BIT(14),
265 ATH9K_HW_CAP_MCI = BIT(15),
266 ATH9K_HW_CAP_BT_ANT_DIV = BIT(17),
267 #else
268 ATH9K_HW_CAP_RTT = 0,
269 ATH9K_HW_CAP_MCI = 0,
270 ATH9K_HW_CAP_BT_ANT_DIV = 0,
271 #endif
272 ATH9K_HW_CAP_DFS = BIT(18),
273 ATH9K_HW_CAP_PAPRD = BIT(19),
274 ATH9K_HW_CAP_FCC_BAND_SWITCH = BIT(20),
275 };
276
277 /*
278 * WoW device capabilities
279 * @ATH9K_HW_WOW_DEVICE_CAPABLE: device revision is capable of WoW.
280 * @ATH9K_HW_WOW_PATTERN_MATCH_EXACT: device is capable of matching
281 * an exact user defined pattern or de-authentication/disassoc pattern.
282 * @ATH9K_HW_WOW_PATTERN_MATCH_DWORD: device requires the first four
283 * bytes of the pattern for user defined pattern, de-authentication and
284 * disassociation patterns for all types of possible frames recieved
285 * of those types.
286 */
287
288 struct ath9k_hw_wow {
289 u32 wow_event_mask;
290 u32 wow_event_mask2;
291 u8 max_patterns;
292 };
293
294 struct ath9k_hw_capabilities {
295 u32 hw_caps; /* ATH9K_HW_CAP_* from ath9k_hw_caps */
296 u16 rts_aggr_limit;
297 u8 tx_chainmask;
298 u8 rx_chainmask;
299 u8 chip_chainmask;
300 u8 max_txchains;
301 u8 max_rxchains;
302 u8 num_gpio_pins;
303 u32 gpio_mask;
304 u32 gpio_requested;
305 u8 rx_hp_qdepth;
306 u8 rx_lp_qdepth;
307 u8 rx_status_len;
308 u8 tx_desc_len;
309 u8 txs_len;
310 };
311
312 #define AR_NO_SPUR 0x8000
313 #define AR_BASE_FREQ_2GHZ 2300
314 #define AR_BASE_FREQ_5GHZ 4900
315 #define AR_SPUR_FEEQ_BOUND_HT40 19
316 #define AR_SPUR_FEEQ_BOUND_HT20 10
317
318 enum ath9k_hw_hang_checks {
319 HW_BB_WATCHDOG = BIT(0),
320 HW_PHYRESTART_CLC_WAR = BIT(1),
321 HW_BB_RIFS_HANG = BIT(2),
322 HW_BB_DFS_HANG = BIT(3),
323 HW_BB_RX_CLEAR_STUCK_HANG = BIT(4),
324 HW_MAC_HANG = BIT(5),
325 };
326
327 #define AR_PCIE_PLL_PWRSAVE_CONTROL BIT(0)
328 #define AR_PCIE_PLL_PWRSAVE_ON_D3 BIT(1)
329 #define AR_PCIE_PLL_PWRSAVE_ON_D0 BIT(2)
330 #define AR_PCIE_CDR_PWRSAVE_ON_D3 BIT(3)
331 #define AR_PCIE_CDR_PWRSAVE_ON_D0 BIT(4)
332
333 struct ath9k_ops_config {
334 int dma_beacon_response_time;
335 int sw_beacon_response_time;
336 bool cwm_ignore_extcca;
337 u32 pcie_waen;
338 u8 analog_shiftreg;
339 u32 ofdm_trig_low;
340 u32 ofdm_trig_high;
341 u32 cck_trig_high;
342 u32 cck_trig_low;
343 bool enable_paprd;
344 int serialize_regmode;
345 bool rx_intr_mitigation;
346 bool tx_intr_mitigation;
347 u8 max_txtrig_level;
348 u16 ani_poll_interval; /* ANI poll interval in ms */
349 u16 hw_hang_checks;
350 u16 rimt_first;
351 u16 rimt_last;
352
353 /* Platform specific config */
354 u32 aspm_l1_fix;
355 u32 xlna_gpio;
356 u32 ant_ctrl_comm2g_switch_enable;
357 bool xatten_margin_cfg;
358 bool alt_mingainidx;
359 u8 pll_pwrsave;
360 bool tx_gain_buffalo;
361 bool led_active_high;
362 };
363
364 enum ath9k_int {
365 ATH9K_INT_RX = 0x00000001,
366 ATH9K_INT_RXDESC = 0x00000002,
367 ATH9K_INT_RXHP = 0x00000001,
368 ATH9K_INT_RXLP = 0x00000002,
369 ATH9K_INT_RXNOFRM = 0x00000008,
370 ATH9K_INT_RXEOL = 0x00000010,
371 ATH9K_INT_RXORN = 0x00000020,
372 ATH9K_INT_TX = 0x00000040,
373 ATH9K_INT_TXDESC = 0x00000080,
374 ATH9K_INT_TIM_TIMER = 0x00000100,
375 ATH9K_INT_MCI = 0x00000200,
376 ATH9K_INT_BB_WATCHDOG = 0x00000400,
377 ATH9K_INT_TXURN = 0x00000800,
378 ATH9K_INT_MIB = 0x00001000,
379 ATH9K_INT_RXPHY = 0x00004000,
380 ATH9K_INT_RXKCM = 0x00008000,
381 ATH9K_INT_SWBA = 0x00010000,
382 ATH9K_INT_BMISS = 0x00040000,
383 ATH9K_INT_BNR = 0x00100000,
384 ATH9K_INT_TIM = 0x00200000,
385 ATH9K_INT_DTIM = 0x00400000,
386 ATH9K_INT_DTIMSYNC = 0x00800000,
387 ATH9K_INT_GPIO = 0x01000000,
388 ATH9K_INT_CABEND = 0x02000000,
389 ATH9K_INT_TSFOOR = 0x04000000,
390 ATH9K_INT_GENTIMER = 0x08000000,
391 ATH9K_INT_CST = 0x10000000,
392 ATH9K_INT_GTT = 0x20000000,
393 ATH9K_INT_FATAL = 0x40000000,
394 ATH9K_INT_GLOBAL = 0x80000000,
395 ATH9K_INT_BMISC = ATH9K_INT_TIM |
396 ATH9K_INT_DTIM |
397 ATH9K_INT_DTIMSYNC |
398 ATH9K_INT_TSFOOR |
399 ATH9K_INT_CABEND,
400 ATH9K_INT_COMMON = ATH9K_INT_RXNOFRM |
401 ATH9K_INT_RXDESC |
402 ATH9K_INT_RXEOL |
403 ATH9K_INT_RXORN |
404 ATH9K_INT_TXURN |
405 ATH9K_INT_TXDESC |
406 ATH9K_INT_MIB |
407 ATH9K_INT_RXPHY |
408 ATH9K_INT_RXKCM |
409 ATH9K_INT_SWBA |
410 ATH9K_INT_BMISS |
411 ATH9K_INT_GPIO,
412 ATH9K_INT_NOCARD = 0xffffffff
413 };
414
415 #define MAX_RTT_TABLE_ENTRY 6
416 #define MAX_IQCAL_MEASUREMENT 8
417 #define MAX_CL_TAB_ENTRY 16
418 #define CL_TAB_ENTRY(reg_base) (reg_base + (4 * j))
419
420 enum ath9k_cal_flags {
421 RTT_DONE,
422 PAPRD_PACKET_SENT,
423 PAPRD_DONE,
424 NFCAL_PENDING,
425 NFCAL_INTF,
426 TXIQCAL_DONE,
427 TXCLCAL_DONE,
428 SW_PKDET_DONE,
429 };
430
431 struct ath9k_hw_cal_data {
432 u16 channel;
433 u16 channelFlags;
434 unsigned long cal_flags;
435 int32_t CalValid;
436 int8_t iCoff;
437 int8_t qCoff;
438 u8 caldac[2];
439 u16 small_signal_gain[AR9300_MAX_CHAINS];
440 u32 pa_table[AR9300_MAX_CHAINS][PAPRD_TABLE_SZ];
441 u32 num_measures[AR9300_MAX_CHAINS];
442 int tx_corr_coeff[MAX_IQCAL_MEASUREMENT][AR9300_MAX_CHAINS];
443 u32 tx_clcal[AR9300_MAX_CHAINS][MAX_CL_TAB_ENTRY];
444 u32 rtt_table[AR9300_MAX_CHAINS][MAX_RTT_TABLE_ENTRY];
445 struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS];
446 };
447
448 struct ath9k_channel {
449 struct ieee80211_channel *chan;
450 u16 channel;
451 u16 channelFlags;
452 s16 noisefloor;
453 };
454
455 #define CHANNEL_5GHZ BIT(0)
456 #define CHANNEL_HALF BIT(1)
457 #define CHANNEL_QUARTER BIT(2)
458 #define CHANNEL_HT BIT(3)
459 #define CHANNEL_HT40PLUS BIT(4)
460 #define CHANNEL_HT40MINUS BIT(5)
461
462 #define IS_CHAN_5GHZ(_c) (!!((_c)->channelFlags & CHANNEL_5GHZ))
463 #define IS_CHAN_2GHZ(_c) (!IS_CHAN_5GHZ(_c))
464
465 #define IS_CHAN_HALF_RATE(_c) (!!((_c)->channelFlags & CHANNEL_HALF))
466 #define IS_CHAN_QUARTER_RATE(_c) (!!((_c)->channelFlags & CHANNEL_QUARTER))
467 #define IS_CHAN_A_FAST_CLOCK(_ah, _c) \
468 (IS_CHAN_5GHZ(_c) && ((_ah)->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK))
469
470 #define IS_CHAN_HT(_c) ((_c)->channelFlags & CHANNEL_HT)
471
472 #define IS_CHAN_HT20(_c) (IS_CHAN_HT(_c) && !IS_CHAN_HT40(_c))
473
474 #define IS_CHAN_HT40(_c) \
475 (!!((_c)->channelFlags & (CHANNEL_HT40PLUS | CHANNEL_HT40MINUS)))
476
477 #define IS_CHAN_HT40PLUS(_c) ((_c)->channelFlags & CHANNEL_HT40PLUS)
478 #define IS_CHAN_HT40MINUS(_c) ((_c)->channelFlags & CHANNEL_HT40MINUS)
479
480 enum ath9k_power_mode {
481 ATH9K_PM_AWAKE = 0,
482 ATH9K_PM_FULL_SLEEP,
483 ATH9K_PM_NETWORK_SLEEP,
484 ATH9K_PM_UNDEFINED
485 };
486
487 enum ser_reg_mode {
488 SER_REG_MODE_OFF = 0,
489 SER_REG_MODE_ON = 1,
490 SER_REG_MODE_AUTO = 2,
491 };
492
493 enum ath9k_rx_qtype {
494 ATH9K_RX_QUEUE_HP,
495 ATH9K_RX_QUEUE_LP,
496 ATH9K_RX_QUEUE_MAX,
497 };
498
499 struct ath9k_beacon_state {
500 u32 bs_nexttbtt;
501 u32 bs_nextdtim;
502 u32 bs_intval;
503 #define ATH9K_TSFOOR_THRESHOLD 0x00004240 /* 16k us */
504 u32 bs_dtimperiod;
505 u16 bs_bmissthreshold;
506 u32 bs_sleepduration;
507 u32 bs_tsfoor_threshold;
508 };
509
510 struct chan_centers {
511 u16 synth_center;
512 u16 ctl_center;
513 u16 ext_center;
514 };
515
516 enum {
517 ATH9K_RESET_POWER_ON,
518 ATH9K_RESET_WARM,
519 ATH9K_RESET_COLD,
520 };
521
522 struct ath9k_hw_version {
523 u32 magic;
524 u16 devid;
525 u16 subvendorid;
526 u32 macVersion;
527 u16 macRev;
528 u16 phyRev;
529 u16 analog5GhzRev;
530 u16 analog2GhzRev;
531 enum ath_usb_dev usbdev;
532 };
533
534 /* Generic TSF timer definitions */
535
536 #define ATH_MAX_GEN_TIMER 16
537
538 #define AR_GENTMR_BIT(_index) (1 << (_index))
539
540 struct ath_gen_timer_configuration {
541 u32 next_addr;
542 u32 period_addr;
543 u32 mode_addr;
544 u32 mode_mask;
545 };
546
547 struct ath_gen_timer {
548 void (*trigger)(void *arg);
549 void (*overflow)(void *arg);
550 void *arg;
551 u8 index;
552 };
553
554 struct ath_gen_timer_table {
555 struct ath_gen_timer *timers[ATH_MAX_GEN_TIMER];
556 u16 timer_mask;
557 bool tsf2_enabled;
558 };
559
560 struct ath_hw_antcomb_conf {
561 u8 main_lna_conf;
562 u8 alt_lna_conf;
563 u8 fast_div_bias;
564 u8 main_gaintb;
565 u8 alt_gaintb;
566 int lna1_lna2_delta;
567 int lna1_lna2_switch_delta;
568 u8 div_group;
569 };
570
571 /**
572 * struct ath_hw_radar_conf - radar detection initialization parameters
573 *
574 * @pulse_inband: threshold for checking the ratio of in-band power
575 * to total power for short radar pulses (half dB steps)
576 * @pulse_inband_step: threshold for checking an in-band power to total
577 * power ratio increase for short radar pulses (half dB steps)
578 * @pulse_height: threshold for detecting the beginning of a short
579 * radar pulse (dB step)
580 * @pulse_rssi: threshold for detecting if a short radar pulse is
581 * gone (dB step)
582 * @pulse_maxlen: maximum pulse length (0.8 us steps)
583 *
584 * @radar_rssi: RSSI threshold for starting long radar detection (dB steps)
585 * @radar_inband: threshold for checking the ratio of in-band power
586 * to total power for long radar pulses (half dB steps)
587 * @fir_power: threshold for detecting the end of a long radar pulse (dB)
588 *
589 * @ext_channel: enable extension channel radar detection
590 */
591 struct ath_hw_radar_conf {
592 unsigned int pulse_inband;
593 unsigned int pulse_inband_step;
594 unsigned int pulse_height;
595 unsigned int pulse_rssi;
596 unsigned int pulse_maxlen;
597
598 unsigned int radar_rssi;
599 unsigned int radar_inband;
600 int fir_power;
601
602 bool ext_channel;
603 };
604
605 /**
606 * struct ath_hw_private_ops - callbacks used internally by hardware code
607 *
608 * This structure contains private callbacks designed to only be used internally
609 * by the hardware core.
610 *
611 * @init_cal_settings: setup types of calibrations supported
612 * @init_cal: starts actual calibration
613 *
614 * @init_mode_gain_regs: Initialize TX/RX gain registers
615 *
616 * @rf_set_freq: change frequency
617 * @spur_mitigate_freq: spur mitigation
618 * @set_rf_regs:
619 * @compute_pll_control: compute the PLL control value to use for
620 * AR_RTC_PLL_CONTROL for a given channel
621 * @setup_calibration: set up calibration
622 * @iscal_supported: used to query if a type of calibration is supported
623 *
624 * @ani_cache_ini_regs: cache the values for ANI from the initial
625 * register settings through the register initialization.
626 */
627 struct ath_hw_private_ops {
628 void (*init_hang_checks)(struct ath_hw *ah);
629 bool (*detect_mac_hang)(struct ath_hw *ah);
630 bool (*detect_bb_hang)(struct ath_hw *ah);
631
632 /* Calibration ops */
633 void (*init_cal_settings)(struct ath_hw *ah);
634 bool (*init_cal)(struct ath_hw *ah, struct ath9k_channel *chan);
635
636 void (*init_mode_gain_regs)(struct ath_hw *ah);
637 void (*setup_calibration)(struct ath_hw *ah,
638 struct ath9k_cal_list *currCal);
639
640 /* PHY ops */
641 int (*rf_set_freq)(struct ath_hw *ah,
642 struct ath9k_channel *chan);
643 void (*spur_mitigate_freq)(struct ath_hw *ah,
644 struct ath9k_channel *chan);
645 bool (*set_rf_regs)(struct ath_hw *ah,
646 struct ath9k_channel *chan,
647 u16 modesIndex);
648 void (*set_channel_regs)(struct ath_hw *ah, struct ath9k_channel *chan);
649 void (*init_bb)(struct ath_hw *ah,
650 struct ath9k_channel *chan);
651 int (*process_ini)(struct ath_hw *ah, struct ath9k_channel *chan);
652 void (*olc_init)(struct ath_hw *ah);
653 void (*set_rfmode)(struct ath_hw *ah, struct ath9k_channel *chan);
654 void (*mark_phy_inactive)(struct ath_hw *ah);
655 void (*set_delta_slope)(struct ath_hw *ah, struct ath9k_channel *chan);
656 bool (*rfbus_req)(struct ath_hw *ah);
657 void (*rfbus_done)(struct ath_hw *ah);
658 void (*restore_chainmask)(struct ath_hw *ah);
659 u32 (*compute_pll_control)(struct ath_hw *ah,
660 struct ath9k_channel *chan);
661 bool (*ani_control)(struct ath_hw *ah, enum ath9k_ani_cmd cmd,
662 int param);
663 void (*do_getnf)(struct ath_hw *ah, int16_t nfarray[NUM_NF_READINGS]);
664 void (*set_radar_params)(struct ath_hw *ah,
665 struct ath_hw_radar_conf *conf);
666 int (*fast_chan_change)(struct ath_hw *ah, struct ath9k_channel *chan,
667 u8 *ini_reloaded);
668
669 /* ANI */
670 void (*ani_cache_ini_regs)(struct ath_hw *ah);
671
672 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
673 bool (*is_aic_enabled)(struct ath_hw *ah);
674 #endif /* CONFIG_ATH9K_BTCOEX_SUPPORT */
675 };
676
677 /**
678 * struct ath_spec_scan - parameters for Atheros spectral scan
679 *
680 * @enabled: enable/disable spectral scan
681 * @short_repeat: controls whether the chip is in spectral scan mode
682 * for 4 usec (enabled) or 204 usec (disabled)
683 * @count: number of scan results requested. There are special meanings
684 * in some chip revisions:
685 * AR92xx: highest bit set (>=128) for endless mode
686 * (spectral scan won't stopped until explicitly disabled)
687 * AR9300 and newer: 0 for endless mode
688 * @endless: true if endless mode is intended. Otherwise, count value is
689 * corrected to the next possible value.
690 * @period: time duration between successive spectral scan entry points
691 * (period*256*Tclk). Tclk = ath_common->clockrate
692 * @fft_period: PHY passes FFT frames to MAC every (fft_period+1)*4uS
693 *
694 * Note: Tclk = 40MHz or 44MHz depending upon operating mode.
695 * Typically it's 44MHz in 2/5GHz on later chips, but there's
696 * a "fast clock" check for this in 5GHz.
697 *
698 */
699 struct ath_spec_scan {
700 bool enabled;
701 bool short_repeat;
702 bool endless;
703 u8 count;
704 u8 period;
705 u8 fft_period;
706 };
707
708 /**
709 * struct ath_hw_ops - callbacks used by hardware code and driver code
710 *
711 * This structure contains callbacks designed to to be used internally by
712 * hardware code and also by the lower level driver.
713 *
714 * @config_pci_powersave:
715 * @calibrate: periodic calibration for NF, ANI, IQ, ADC gain, ADC-DC
716 *
717 * @spectral_scan_config: set parameters for spectral scan and enable/disable it
718 * @spectral_scan_trigger: trigger a spectral scan run
719 * @spectral_scan_wait: wait for a spectral scan run to finish
720 */
721 struct ath_hw_ops {
722 void (*config_pci_powersave)(struct ath_hw *ah,
723 bool power_off);
724 void (*rx_enable)(struct ath_hw *ah);
725 void (*set_desc_link)(void *ds, u32 link);
726 int (*calibrate)(struct ath_hw *ah, struct ath9k_channel *chan,
727 u8 rxchainmask, bool longcal);
728 bool (*get_isr)(struct ath_hw *ah, enum ath9k_int *masked,
729 u32 *sync_cause_p);
730 void (*set_txdesc)(struct ath_hw *ah, void *ds,
731 struct ath_tx_info *i);
732 int (*proc_txdesc)(struct ath_hw *ah, void *ds,
733 struct ath_tx_status *ts);
734 int (*get_duration)(struct ath_hw *ah, const void *ds, int index);
735 void (*antdiv_comb_conf_get)(struct ath_hw *ah,
736 struct ath_hw_antcomb_conf *antconf);
737 void (*antdiv_comb_conf_set)(struct ath_hw *ah,
738 struct ath_hw_antcomb_conf *antconf);
739 void (*spectral_scan_config)(struct ath_hw *ah,
740 struct ath_spec_scan *param);
741 void (*spectral_scan_trigger)(struct ath_hw *ah);
742 void (*spectral_scan_wait)(struct ath_hw *ah);
743
744 void (*tx99_start)(struct ath_hw *ah, u32 qnum);
745 void (*tx99_stop)(struct ath_hw *ah);
746 void (*tx99_set_txpower)(struct ath_hw *ah, u8 power);
747
748 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
749 void (*set_bt_ant_diversity)(struct ath_hw *hw, bool enable);
750 #endif
751 };
752
753 struct ath_nf_limits {
754 s16 max;
755 s16 min;
756 s16 nominal;
757 s16 cal[AR5416_MAX_CHAINS];
758 s16 pwr[AR5416_MAX_CHAINS];
759 };
760
761 enum ath_cal_list {
762 TX_IQ_CAL = BIT(0),
763 TX_IQ_ON_AGC_CAL = BIT(1),
764 TX_CL_CAL = BIT(2),
765 };
766
767 /* ah_flags */
768 #define AH_USE_EEPROM 0x1
769 #define AH_UNPLUGGED 0x2 /* The card has been physically removed. */
770 #define AH_FASTCC 0x4
771 #define AH_NO_EEP_SWAP 0x8 /* Do not swap EEPROM data */
772
773 struct ath_hw {
774 struct ath_ops reg_ops;
775
776 struct device *dev;
777 struct ieee80211_hw *hw;
778 struct ath_common common;
779 struct ath9k_hw_version hw_version;
780 struct ath9k_ops_config config;
781 struct ath9k_hw_capabilities caps;
782 struct ath9k_channel channels[ATH9K_NUM_CHANNELS];
783 struct ath9k_channel *curchan;
784
785 union {
786 struct ar5416_eeprom_def def;
787 struct ar5416_eeprom_4k map4k;
788 struct ar9287_eeprom map9287;
789 struct ar9300_eeprom ar9300_eep;
790 } eeprom;
791 const struct eeprom_ops *eep_ops;
792
793 bool sw_mgmt_crypto_tx;
794 bool sw_mgmt_crypto_rx;
795 bool is_pciexpress;
796 bool aspm_enabled;
797 bool is_monitoring;
798 bool need_an_top2_fixup;
799 u16 tx_trig_level;
800
801 u32 nf_regs[6];
802 struct ath_nf_limits nf_2g;
803 struct ath_nf_limits nf_5g;
804 u16 rfsilent;
805 u32 rfkill_gpio;
806 u32 rfkill_polarity;
807 u32 ah_flags;
808 s16 nf_override;
809
810 bool reset_power_on;
811 bool htc_reset_init;
812
813 enum nl80211_iftype opmode;
814 enum ath9k_power_mode power_mode;
815
816 s8 noise;
817 struct ath9k_hw_cal_data *caldata;
818 struct ath9k_pacal_info pacal_info;
819 struct ar5416Stats stats;
820 struct ath9k_tx_queue_info txq[ATH9K_NUM_TX_QUEUES];
821
822 enum ath9k_int imask;
823 u32 imrs2_reg;
824 u32 txok_interrupt_mask;
825 u32 txerr_interrupt_mask;
826 u32 txdesc_interrupt_mask;
827 u32 txeol_interrupt_mask;
828 u32 txurn_interrupt_mask;
829 atomic_t intr_ref_cnt;
830 bool chip_fullsleep;
831 u32 modes_index;
832
833 /* Calibration */
834 u32 supp_cals;
835 struct ath9k_cal_list iq_caldata;
836 struct ath9k_cal_list adcgain_caldata;
837 struct ath9k_cal_list adcdc_caldata;
838 struct ath9k_cal_list *cal_list;
839 struct ath9k_cal_list *cal_list_last;
840 struct ath9k_cal_list *cal_list_curr;
841 #define totalPowerMeasI meas0.unsign
842 #define totalPowerMeasQ meas1.unsign
843 #define totalIqCorrMeas meas2.sign
844 #define totalAdcIOddPhase meas0.unsign
845 #define totalAdcIEvenPhase meas1.unsign
846 #define totalAdcQOddPhase meas2.unsign
847 #define totalAdcQEvenPhase meas3.unsign
848 #define totalAdcDcOffsetIOddPhase meas0.sign
849 #define totalAdcDcOffsetIEvenPhase meas1.sign
850 #define totalAdcDcOffsetQOddPhase meas2.sign
851 #define totalAdcDcOffsetQEvenPhase meas3.sign
852 union {
853 u32 unsign[AR5416_MAX_CHAINS];
854 int32_t sign[AR5416_MAX_CHAINS];
855 } meas0;
856 union {
857 u32 unsign[AR5416_MAX_CHAINS];
858 int32_t sign[AR5416_MAX_CHAINS];
859 } meas1;
860 union {
861 u32 unsign[AR5416_MAX_CHAINS];
862 int32_t sign[AR5416_MAX_CHAINS];
863 } meas2;
864 union {
865 u32 unsign[AR5416_MAX_CHAINS];
866 int32_t sign[AR5416_MAX_CHAINS];
867 } meas3;
868 u16 cal_samples;
869 u8 enabled_cals;
870
871 u32 sta_id1_defaults;
872 u32 misc_mode;
873
874 /* Private to hardware code */
875 struct ath_hw_private_ops private_ops;
876 /* Accessed by the lower level driver */
877 struct ath_hw_ops ops;
878
879 /* Used to program the radio on non single-chip devices */
880 u32 *analogBank6Data;
881
882 int coverage_class;
883 u32 slottime;
884 u32 globaltxtimeout;
885
886 /* ANI */
887 u32 aniperiod;
888 enum ath9k_ani_cmd ani_function;
889 u32 ani_skip_count;
890 struct ar5416AniState ani;
891
892 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
893 struct ath_btcoex_hw btcoex_hw;
894 #endif
895
896 u32 intr_txqs;
897 u8 txchainmask;
898 u8 rxchainmask;
899
900 struct ath_hw_radar_conf radar_conf;
901
902 u32 originalGain[22];
903 int initPDADC;
904 int PDADCdelta;
905 int led_pin;
906 u32 gpio_mask;
907 u32 gpio_val;
908
909 struct ar5416IniArray ini_dfs;
910 struct ar5416IniArray iniModes;
911 struct ar5416IniArray iniCommon;
912 struct ar5416IniArray iniBB_RfGain;
913 struct ar5416IniArray iniBank6;
914 struct ar5416IniArray iniAddac;
915 struct ar5416IniArray iniPcieSerdes;
916 struct ar5416IniArray iniPcieSerdesLowPower;
917 struct ar5416IniArray iniModesFastClock;
918 struct ar5416IniArray iniAdditional;
919 struct ar5416IniArray iniModesRxGain;
920 struct ar5416IniArray ini_modes_rx_gain_bounds;
921 struct ar5416IniArray iniModesTxGain;
922 struct ar5416IniArray iniCckfirNormal;
923 struct ar5416IniArray iniCckfirJapan2484;
924 struct ar5416IniArray iniModes_9271_ANI_reg;
925 struct ar5416IniArray ini_radio_post_sys2ant;
926 struct ar5416IniArray ini_modes_rxgain_xlna;
927 struct ar5416IniArray ini_modes_rxgain_bb_core;
928 struct ar5416IniArray ini_modes_rxgain_bb_postamble;
929
930 struct ar5416IniArray iniMac[ATH_INI_NUM_SPLIT];
931 struct ar5416IniArray iniBB[ATH_INI_NUM_SPLIT];
932 struct ar5416IniArray iniRadio[ATH_INI_NUM_SPLIT];
933 struct ar5416IniArray iniSOC[ATH_INI_NUM_SPLIT];
934
935 u32 intr_gen_timer_trigger;
936 u32 intr_gen_timer_thresh;
937 struct ath_gen_timer_table hw_gen_timers;
938
939 struct ar9003_txs *ts_ring;
940 u32 ts_paddr_start;
941 u32 ts_paddr_end;
942 u16 ts_tail;
943 u16 ts_size;
944
945 u32 bb_watchdog_last_status;
946 u32 bb_watchdog_timeout_ms; /* in ms, 0 to disable */
947 u8 bb_hang_rx_ofdm; /* true if bb hang due to rx_ofdm */
948
949 unsigned int paprd_target_power;
950 unsigned int paprd_training_power;
951 unsigned int paprd_ratemask;
952 unsigned int paprd_ratemask_ht40;
953 bool paprd_table_write_done;
954 u32 paprd_gain_table_entries[PAPRD_GAIN_TABLE_ENTRIES];
955 u8 paprd_gain_table_index[PAPRD_GAIN_TABLE_ENTRIES];
956 /*
957 * Store the permanent value of Reg 0x4004in WARegVal
958 * so we dont have to R/M/W. We should not be reading
959 * this register when in sleep states.
960 */
961 u32 WARegVal;
962
963 /* Enterprise mode cap */
964 u32 ent_mode;
965
966 #ifdef CONFIG_ATH9K_WOW
967 struct ath9k_hw_wow wow;
968 #endif
969 bool is_clk_25mhz;
970 int (*get_mac_revision)(void);
971 int (*external_reset)(void);
972 bool disable_2ghz;
973 bool disable_5ghz;
974
975 const struct firmware *eeprom_blob;
976
977 struct ath_dynack dynack;
978
979 bool tpc_enabled;
980 u8 tx_power[Ar5416RateSize];
981 u8 tx_power_stbc[Ar5416RateSize];
982 bool msi_enabled;
983 u32 msi_mask;
984 u32 msi_reg;
985 };
986
987 struct ath_bus_ops {
988 enum ath_bus_type ath_bus_type;
989 void (*read_cachesize)(struct ath_common *common, int *csz);
990 bool (*eeprom_read)(struct ath_common *common, u32 off, u16 *data);
991 void (*bt_coex_prep)(struct ath_common *common);
992 void (*aspm_init)(struct ath_common *common);
993 };
994
ath9k_hw_common(struct ath_hw * ah)995 static inline struct ath_common *ath9k_hw_common(struct ath_hw *ah)
996 {
997 return &ah->common;
998 }
999
ath9k_hw_regulatory(struct ath_hw * ah)1000 static inline struct ath_regulatory *ath9k_hw_regulatory(struct ath_hw *ah)
1001 {
1002 return &(ath9k_hw_common(ah)->regulatory);
1003 }
1004
ath9k_hw_private_ops(struct ath_hw * ah)1005 static inline struct ath_hw_private_ops *ath9k_hw_private_ops(struct ath_hw *ah)
1006 {
1007 return &ah->private_ops;
1008 }
1009
ath9k_hw_ops(struct ath_hw * ah)1010 static inline struct ath_hw_ops *ath9k_hw_ops(struct ath_hw *ah)
1011 {
1012 return &ah->ops;
1013 }
1014
get_streams(int mask)1015 static inline u8 get_streams(int mask)
1016 {
1017 return !!(mask & BIT(0)) + !!(mask & BIT(1)) + !!(mask & BIT(2));
1018 }
1019
1020 /* Initialization, Detach, Reset */
1021 void ath9k_hw_deinit(struct ath_hw *ah);
1022 int ath9k_hw_init(struct ath_hw *ah);
1023 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1024 struct ath9k_hw_cal_data *caldata, bool fastcc);
1025 int ath9k_hw_fill_cap_info(struct ath_hw *ah);
1026 u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan);
1027
1028 /* GPIO / RFKILL / Antennae */
1029 void ath9k_hw_gpio_request_in(struct ath_hw *ah, u32 gpio, const char *label);
1030 void ath9k_hw_gpio_request_out(struct ath_hw *ah, u32 gpio, const char *label,
1031 u32 ah_signal_type);
1032 void ath9k_hw_gpio_free(struct ath_hw *ah, u32 gpio);
1033 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio);
1034 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val);
1035 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna);
1036
1037 /* General Operation */
1038 void ath9k_hw_synth_delay(struct ath_hw *ah, struct ath9k_channel *chan,
1039 int hw_delay);
1040 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout);
1041 void ath9k_hw_write_array(struct ath_hw *ah, const struct ar5416IniArray *array,
1042 int column, unsigned int *writecnt);
1043 void ath9k_hw_read_array(struct ath_hw *ah, u32 array[][2], int size);
1044 u32 ath9k_hw_reverse_bits(u32 val, u32 n);
1045 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
1046 u8 phy, int kbps,
1047 u32 frameLen, u16 rateix, bool shortPreamble);
1048 void ath9k_hw_get_channel_centers(struct ath_hw *ah,
1049 struct ath9k_channel *chan,
1050 struct chan_centers *centers);
1051 u32 ath9k_hw_getrxfilter(struct ath_hw *ah);
1052 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits);
1053 bool ath9k_hw_phy_disable(struct ath_hw *ah);
1054 bool ath9k_hw_disable(struct ath_hw *ah);
1055 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test);
1056 void ath9k_hw_setopmode(struct ath_hw *ah);
1057 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1);
1058 void ath9k_hw_write_associd(struct ath_hw *ah);
1059 u32 ath9k_hw_gettsf32(struct ath_hw *ah);
1060 u64 ath9k_hw_gettsf64(struct ath_hw *ah);
1061 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64);
1062 void ath9k_hw_reset_tsf(struct ath_hw *ah);
1063 u32 ath9k_hw_get_tsf_offset(struct timespec64 *last, struct timespec64 *cur);
1064 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, bool set);
1065 void ath9k_hw_init_global_settings(struct ath_hw *ah);
1066 u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah);
1067 void ath9k_hw_set11nmac2040(struct ath_hw *ah, struct ath9k_channel *chan);
1068 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period);
1069 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
1070 const struct ath9k_beacon_state *bs);
1071 void ath9k_hw_check_nav(struct ath_hw *ah);
1072 bool ath9k_hw_check_alive(struct ath_hw *ah);
1073
1074 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode);
1075
1076 /* Generic hw timer primitives */
1077 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
1078 void (*trigger)(void *),
1079 void (*overflow)(void *),
1080 void *arg,
1081 u8 timer_index);
1082 void ath9k_hw_gen_timer_start(struct ath_hw *ah,
1083 struct ath_gen_timer *timer,
1084 u32 timer_next,
1085 u32 timer_period);
1086 void ath9k_hw_gen_timer_start_tsf2(struct ath_hw *ah);
1087 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer);
1088
1089 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer);
1090 void ath_gen_timer_isr(struct ath_hw *hw);
1091
1092 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len);
1093
1094 /* PHY */
1095 void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
1096 u32 *coef_mantissa, u32 *coef_exponent);
1097 void ath9k_hw_apply_txpower(struct ath_hw *ah, struct ath9k_channel *chan,
1098 bool test);
1099
1100 /*
1101 * Code Specific to AR5008, AR9001 or AR9002,
1102 * we stuff these here to avoid callbacks for AR9003.
1103 */
1104 int ar9002_hw_rf_claim(struct ath_hw *ah);
1105 void ar9002_hw_enable_async_fifo(struct ath_hw *ah);
1106
1107 /*
1108 * Code specific to AR9003, we stuff these here to avoid callbacks
1109 * for older families
1110 */
1111 bool ar9003_hw_bb_watchdog_check(struct ath_hw *ah);
1112 void ar9003_hw_bb_watchdog_config(struct ath_hw *ah);
1113 void ar9003_hw_bb_watchdog_read(struct ath_hw *ah);
1114 void ar9003_hw_bb_watchdog_dbg_info(struct ath_hw *ah);
1115 void ar9003_hw_disable_phy_restart(struct ath_hw *ah);
1116 void ar9003_paprd_enable(struct ath_hw *ah, bool val);
1117 void ar9003_paprd_populate_single_table(struct ath_hw *ah,
1118 struct ath9k_hw_cal_data *caldata,
1119 int chain);
1120 int ar9003_paprd_create_curve(struct ath_hw *ah,
1121 struct ath9k_hw_cal_data *caldata, int chain);
1122 void ar9003_paprd_setup_gain_table(struct ath_hw *ah, int chain);
1123 int ar9003_paprd_init_table(struct ath_hw *ah);
1124 bool ar9003_paprd_is_done(struct ath_hw *ah);
1125 bool ar9003_is_paprd_enabled(struct ath_hw *ah);
1126 void ar9003_hw_set_chain_masks(struct ath_hw *ah, u8 rx, u8 tx);
1127 void ar9003_hw_init_rate_txpower(struct ath_hw *ah, u8 *rate_array,
1128 struct ath9k_channel *chan);
1129 void ar5008_hw_cmn_spur_mitigate(struct ath_hw *ah,
1130 struct ath9k_channel *chan, int bin);
1131 void ar5008_hw_init_rate_txpower(struct ath_hw *ah, int16_t *rate_array,
1132 struct ath9k_channel *chan, int ht40_delta);
1133
1134 /* Hardware family op attach helpers */
1135 int ar5008_hw_attach_phy_ops(struct ath_hw *ah);
1136 void ar9002_hw_attach_phy_ops(struct ath_hw *ah);
1137 void ar9003_hw_attach_phy_ops(struct ath_hw *ah);
1138
1139 void ar9002_hw_attach_calib_ops(struct ath_hw *ah);
1140 void ar9003_hw_attach_calib_ops(struct ath_hw *ah);
1141
1142 int ar9002_hw_attach_ops(struct ath_hw *ah);
1143 void ar9003_hw_attach_ops(struct ath_hw *ah);
1144
1145 void ar9002_hw_load_ani_reg(struct ath_hw *ah, struct ath9k_channel *chan);
1146
1147 void ath9k_ani_reset(struct ath_hw *ah, bool is_scanning);
1148 void ath9k_hw_ani_monitor(struct ath_hw *ah, struct ath9k_channel *chan);
1149
1150 void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us);
1151 void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us);
1152 void ath9k_hw_setslottime(struct ath_hw *ah, u32 us);
1153
1154 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
1155 void ar9003_hw_attach_aic_ops(struct ath_hw *ah);
ath9k_hw_btcoex_is_enabled(struct ath_hw * ah)1156 static inline bool ath9k_hw_btcoex_is_enabled(struct ath_hw *ah)
1157 {
1158 return ah->btcoex_hw.enabled;
1159 }
ath9k_hw_mci_is_enabled(struct ath_hw * ah)1160 static inline bool ath9k_hw_mci_is_enabled(struct ath_hw *ah)
1161 {
1162 return ah->common.btcoex_enabled &&
1163 (ah->caps.hw_caps & ATH9K_HW_CAP_MCI);
1164
1165 }
1166 void ath9k_hw_btcoex_enable(struct ath_hw *ah);
1167 static inline enum ath_btcoex_scheme
ath9k_hw_get_btcoex_scheme(struct ath_hw * ah)1168 ath9k_hw_get_btcoex_scheme(struct ath_hw *ah)
1169 {
1170 return ah->btcoex_hw.scheme;
1171 }
1172 #else
ar9003_hw_attach_aic_ops(struct ath_hw * ah)1173 static inline void ar9003_hw_attach_aic_ops(struct ath_hw *ah)
1174 {
1175 }
ath9k_hw_btcoex_is_enabled(struct ath_hw * ah)1176 static inline bool ath9k_hw_btcoex_is_enabled(struct ath_hw *ah)
1177 {
1178 return false;
1179 }
ath9k_hw_mci_is_enabled(struct ath_hw * ah)1180 static inline bool ath9k_hw_mci_is_enabled(struct ath_hw *ah)
1181 {
1182 return false;
1183 }
ath9k_hw_btcoex_enable(struct ath_hw * ah)1184 static inline void ath9k_hw_btcoex_enable(struct ath_hw *ah)
1185 {
1186 }
1187 static inline enum ath_btcoex_scheme
ath9k_hw_get_btcoex_scheme(struct ath_hw * ah)1188 ath9k_hw_get_btcoex_scheme(struct ath_hw *ah)
1189 {
1190 return ATH_BTCOEX_CFG_NONE;
1191 }
1192 #endif /* CONFIG_ATH9K_BTCOEX_SUPPORT */
1193
1194
1195 #ifdef CONFIG_ATH9K_WOW
1196 int ath9k_hw_wow_apply_pattern(struct ath_hw *ah, u8 *user_pattern,
1197 u8 *user_mask, int pattern_count,
1198 int pattern_len);
1199 u32 ath9k_hw_wow_wakeup(struct ath_hw *ah);
1200 void ath9k_hw_wow_enable(struct ath_hw *ah, u32 pattern_enable);
1201 #else
ath9k_hw_wow_apply_pattern(struct ath_hw * ah,u8 * user_pattern,u8 * user_mask,int pattern_count,int pattern_len)1202 static inline int ath9k_hw_wow_apply_pattern(struct ath_hw *ah,
1203 u8 *user_pattern,
1204 u8 *user_mask,
1205 int pattern_count,
1206 int pattern_len)
1207 {
1208 return 0;
1209 }
ath9k_hw_wow_wakeup(struct ath_hw * ah)1210 static inline u32 ath9k_hw_wow_wakeup(struct ath_hw *ah)
1211 {
1212 return 0;
1213 }
ath9k_hw_wow_enable(struct ath_hw * ah,u32 pattern_enable)1214 static inline void ath9k_hw_wow_enable(struct ath_hw *ah, u32 pattern_enable)
1215 {
1216 }
1217 #endif
1218
1219 #define ATH9K_CLOCK_RATE_CCK 22
1220 #define ATH9K_CLOCK_RATE_5GHZ_OFDM 40
1221 #define ATH9K_CLOCK_RATE_2GHZ_OFDM 44
1222 #define ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM 44
1223
1224 #endif
1225
