1 /*
2 * Atheros AR71XX/AR724X/AR913X common routines
3 *
4 * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
5 * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
6 *
7 * Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
12 */
13
14 #include <linux/kernel.h>
15 #include <linux/init.h>
16 #include <linux/err.h>
17 #include <linux/clk.h>
18 #include <linux/clkdev.h>
19 #include <linux/clk-provider.h>
20 #include <linux/of.h>
21 #include <linux/of_address.h>
22 #include <dt-bindings/clock/ath79-clk.h>
23
24 #include <asm/div64.h>
25
26 #include <asm/mach-ath79/ath79.h>
27 #include <asm/mach-ath79/ar71xx_regs.h>
28 #include "common.h"
29 #include "machtypes.h"
30
31 #define AR71XX_BASE_FREQ 40000000
32 #define AR724X_BASE_FREQ 40000000
33
34 static struct clk *clks[ATH79_CLK_END];
35 static struct clk_onecell_data clk_data = {
36 .clks = clks,
37 .clk_num = ARRAY_SIZE(clks),
38 };
39
ath79_add_sys_clkdev(const char * id,unsigned long rate)40 static struct clk *__init ath79_add_sys_clkdev(
41 const char *id, unsigned long rate)
42 {
43 struct clk *clk;
44 int err;
45
46 clk = clk_register_fixed_rate(NULL, id, NULL, 0, rate);
47 if (IS_ERR(clk))
48 panic("failed to allocate %s clock structure", id);
49
50 err = clk_register_clkdev(clk, id, NULL);
51 if (err)
52 panic("unable to register %s clock device", id);
53
54 return clk;
55 }
56
ar71xx_clocks_init(void)57 static void __init ar71xx_clocks_init(void)
58 {
59 unsigned long ref_rate;
60 unsigned long cpu_rate;
61 unsigned long ddr_rate;
62 unsigned long ahb_rate;
63 u32 pll;
64 u32 freq;
65 u32 div;
66
67 ref_rate = AR71XX_BASE_FREQ;
68
69 pll = ath79_pll_rr(AR71XX_PLL_REG_CPU_CONFIG);
70
71 div = ((pll >> AR71XX_PLL_FB_SHIFT) & AR71XX_PLL_FB_MASK) + 1;
72 freq = div * ref_rate;
73
74 div = ((pll >> AR71XX_CPU_DIV_SHIFT) & AR71XX_CPU_DIV_MASK) + 1;
75 cpu_rate = freq / div;
76
77 div = ((pll >> AR71XX_DDR_DIV_SHIFT) & AR71XX_DDR_DIV_MASK) + 1;
78 ddr_rate = freq / div;
79
80 div = (((pll >> AR71XX_AHB_DIV_SHIFT) & AR71XX_AHB_DIV_MASK) + 1) * 2;
81 ahb_rate = cpu_rate / div;
82
83 ath79_add_sys_clkdev("ref", ref_rate);
84 clks[ATH79_CLK_CPU] = ath79_add_sys_clkdev("cpu", cpu_rate);
85 clks[ATH79_CLK_DDR] = ath79_add_sys_clkdev("ddr", ddr_rate);
86 clks[ATH79_CLK_AHB] = ath79_add_sys_clkdev("ahb", ahb_rate);
87
88 clk_add_alias("wdt", NULL, "ahb", NULL);
89 clk_add_alias("uart", NULL, "ahb", NULL);
90 }
91
ath79_reg_ffclk(const char * name,const char * parent_name,unsigned int mult,unsigned int div)92 static struct clk * __init ath79_reg_ffclk(const char *name,
93 const char *parent_name, unsigned int mult, unsigned int div)
94 {
95 struct clk *clk;
96
97 clk = clk_register_fixed_factor(NULL, name, parent_name, 0, mult, div);
98 if (IS_ERR(clk))
99 panic("failed to allocate %s clock structure", name);
100
101 return clk;
102 }
103
ar724x_clk_init(struct clk * ref_clk,void __iomem * pll_base)104 static void __init ar724x_clk_init(struct clk *ref_clk, void __iomem *pll_base)
105 {
106 u32 pll;
107 u32 mult, div, ddr_div, ahb_div;
108
109 pll = __raw_readl(pll_base + AR724X_PLL_REG_CPU_CONFIG);
110
111 mult = ((pll >> AR724X_PLL_FB_SHIFT) & AR724X_PLL_FB_MASK);
112 div = ((pll >> AR724X_PLL_REF_DIV_SHIFT) & AR724X_PLL_REF_DIV_MASK) * 2;
113
114 ddr_div = ((pll >> AR724X_DDR_DIV_SHIFT) & AR724X_DDR_DIV_MASK) + 1;
115 ahb_div = (((pll >> AR724X_AHB_DIV_SHIFT) & AR724X_AHB_DIV_MASK) + 1) * 2;
116
117 clks[ATH79_CLK_CPU] = ath79_reg_ffclk("cpu", "ref", mult, div);
118 clks[ATH79_CLK_DDR] = ath79_reg_ffclk("ddr", "ref", mult, div * ddr_div);
119 clks[ATH79_CLK_AHB] = ath79_reg_ffclk("ahb", "ref", mult, div * ahb_div);
120 }
121
ar724x_clocks_init(void)122 static void __init ar724x_clocks_init(void)
123 {
124 struct clk *ref_clk;
125
126 ref_clk = ath79_add_sys_clkdev("ref", AR724X_BASE_FREQ);
127
128 ar724x_clk_init(ref_clk, ath79_pll_base);
129
130 /* just make happy plat_time_init() from arch/mips/ath79/setup.c */
131 clk_register_clkdev(clks[ATH79_CLK_CPU], "cpu", NULL);
132 clk_register_clkdev(clks[ATH79_CLK_DDR], "ddr", NULL);
133 clk_register_clkdev(clks[ATH79_CLK_AHB], "ahb", NULL);
134
135 clk_add_alias("wdt", NULL, "ahb", NULL);
136 clk_add_alias("uart", NULL, "ahb", NULL);
137 }
138
ar9330_clk_init(struct clk * ref_clk,void __iomem * pll_base)139 static void __init ar9330_clk_init(struct clk *ref_clk, void __iomem *pll_base)
140 {
141 u32 clock_ctrl;
142 u32 ref_div;
143 u32 ninit_mul;
144 u32 out_div;
145
146 u32 cpu_div;
147 u32 ddr_div;
148 u32 ahb_div;
149
150 clock_ctrl = __raw_readl(pll_base + AR933X_PLL_CLOCK_CTRL_REG);
151 if (clock_ctrl & AR933X_PLL_CLOCK_CTRL_BYPASS) {
152 ref_div = 1;
153 ninit_mul = 1;
154 out_div = 1;
155
156 cpu_div = 1;
157 ddr_div = 1;
158 ahb_div = 1;
159 } else {
160 u32 cpu_config;
161 u32 t;
162
163 cpu_config = __raw_readl(pll_base + AR933X_PLL_CPU_CONFIG_REG);
164
165 t = (cpu_config >> AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
166 AR933X_PLL_CPU_CONFIG_REFDIV_MASK;
167 ref_div = t;
168
169 ninit_mul = (cpu_config >> AR933X_PLL_CPU_CONFIG_NINT_SHIFT) &
170 AR933X_PLL_CPU_CONFIG_NINT_MASK;
171
172 t = (cpu_config >> AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
173 AR933X_PLL_CPU_CONFIG_OUTDIV_MASK;
174 if (t == 0)
175 t = 1;
176
177 out_div = (1 << t);
178
179 cpu_div = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT) &
180 AR933X_PLL_CLOCK_CTRL_CPU_DIV_MASK) + 1;
181
182 ddr_div = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT) &
183 AR933X_PLL_CLOCK_CTRL_DDR_DIV_MASK) + 1;
184
185 ahb_div = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT) &
186 AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK) + 1;
187 }
188
189 clks[ATH79_CLK_CPU] = ath79_reg_ffclk("cpu", "ref",
190 ninit_mul, ref_div * out_div * cpu_div);
191 clks[ATH79_CLK_DDR] = ath79_reg_ffclk("ddr", "ref",
192 ninit_mul, ref_div * out_div * ddr_div);
193 clks[ATH79_CLK_AHB] = ath79_reg_ffclk("ahb", "ref",
194 ninit_mul, ref_div * out_div * ahb_div);
195 }
196
ar933x_clocks_init(void)197 static void __init ar933x_clocks_init(void)
198 {
199 struct clk *ref_clk;
200 unsigned long ref_rate;
201 u32 t;
202
203 t = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP);
204 if (t & AR933X_BOOTSTRAP_REF_CLK_40)
205 ref_rate = (40 * 1000 * 1000);
206 else
207 ref_rate = (25 * 1000 * 1000);
208
209 ref_clk = ath79_add_sys_clkdev("ref", ref_rate);
210
211 ar9330_clk_init(ref_clk, ath79_pll_base);
212
213 /* just make happy plat_time_init() from arch/mips/ath79/setup.c */
214 clk_register_clkdev(clks[ATH79_CLK_CPU], "cpu", NULL);
215 clk_register_clkdev(clks[ATH79_CLK_DDR], "ddr", NULL);
216 clk_register_clkdev(clks[ATH79_CLK_AHB], "ahb", NULL);
217
218 clk_add_alias("wdt", NULL, "ahb", NULL);
219 clk_add_alias("uart", NULL, "ref", NULL);
220 }
221
ar934x_get_pll_freq(u32 ref,u32 ref_div,u32 nint,u32 nfrac,u32 frac,u32 out_div)222 static u32 __init ar934x_get_pll_freq(u32 ref, u32 ref_div, u32 nint, u32 nfrac,
223 u32 frac, u32 out_div)
224 {
225 u64 t;
226 u32 ret;
227
228 t = ref;
229 t *= nint;
230 do_div(t, ref_div);
231 ret = t;
232
233 t = ref;
234 t *= nfrac;
235 do_div(t, ref_div * frac);
236 ret += t;
237
238 ret /= (1 << out_div);
239 return ret;
240 }
241
ar934x_clocks_init(void)242 static void __init ar934x_clocks_init(void)
243 {
244 unsigned long ref_rate;
245 unsigned long cpu_rate;
246 unsigned long ddr_rate;
247 unsigned long ahb_rate;
248 u32 pll, out_div, ref_div, nint, nfrac, frac, clk_ctrl, postdiv;
249 u32 cpu_pll, ddr_pll;
250 u32 bootstrap;
251 void __iomem *dpll_base;
252
253 dpll_base = ioremap(AR934X_SRIF_BASE, AR934X_SRIF_SIZE);
254
255 bootstrap = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP);
256 if (bootstrap & AR934X_BOOTSTRAP_REF_CLK_40)
257 ref_rate = 40 * 1000 * 1000;
258 else
259 ref_rate = 25 * 1000 * 1000;
260
261 pll = __raw_readl(dpll_base + AR934X_SRIF_CPU_DPLL2_REG);
262 if (pll & AR934X_SRIF_DPLL2_LOCAL_PLL) {
263 out_div = (pll >> AR934X_SRIF_DPLL2_OUTDIV_SHIFT) &
264 AR934X_SRIF_DPLL2_OUTDIV_MASK;
265 pll = __raw_readl(dpll_base + AR934X_SRIF_CPU_DPLL1_REG);
266 nint = (pll >> AR934X_SRIF_DPLL1_NINT_SHIFT) &
267 AR934X_SRIF_DPLL1_NINT_MASK;
268 nfrac = pll & AR934X_SRIF_DPLL1_NFRAC_MASK;
269 ref_div = (pll >> AR934X_SRIF_DPLL1_REFDIV_SHIFT) &
270 AR934X_SRIF_DPLL1_REFDIV_MASK;
271 frac = 1 << 18;
272 } else {
273 pll = ath79_pll_rr(AR934X_PLL_CPU_CONFIG_REG);
274 out_div = (pll >> AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
275 AR934X_PLL_CPU_CONFIG_OUTDIV_MASK;
276 ref_div = (pll >> AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
277 AR934X_PLL_CPU_CONFIG_REFDIV_MASK;
278 nint = (pll >> AR934X_PLL_CPU_CONFIG_NINT_SHIFT) &
279 AR934X_PLL_CPU_CONFIG_NINT_MASK;
280 nfrac = (pll >> AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT) &
281 AR934X_PLL_CPU_CONFIG_NFRAC_MASK;
282 frac = 1 << 6;
283 }
284
285 cpu_pll = ar934x_get_pll_freq(ref_rate, ref_div, nint,
286 nfrac, frac, out_div);
287
288 pll = __raw_readl(dpll_base + AR934X_SRIF_DDR_DPLL2_REG);
289 if (pll & AR934X_SRIF_DPLL2_LOCAL_PLL) {
290 out_div = (pll >> AR934X_SRIF_DPLL2_OUTDIV_SHIFT) &
291 AR934X_SRIF_DPLL2_OUTDIV_MASK;
292 pll = __raw_readl(dpll_base + AR934X_SRIF_DDR_DPLL1_REG);
293 nint = (pll >> AR934X_SRIF_DPLL1_NINT_SHIFT) &
294 AR934X_SRIF_DPLL1_NINT_MASK;
295 nfrac = pll & AR934X_SRIF_DPLL1_NFRAC_MASK;
296 ref_div = (pll >> AR934X_SRIF_DPLL1_REFDIV_SHIFT) &
297 AR934X_SRIF_DPLL1_REFDIV_MASK;
298 frac = 1 << 18;
299 } else {
300 pll = ath79_pll_rr(AR934X_PLL_DDR_CONFIG_REG);
301 out_div = (pll >> AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
302 AR934X_PLL_DDR_CONFIG_OUTDIV_MASK;
303 ref_div = (pll >> AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
304 AR934X_PLL_DDR_CONFIG_REFDIV_MASK;
305 nint = (pll >> AR934X_PLL_DDR_CONFIG_NINT_SHIFT) &
306 AR934X_PLL_DDR_CONFIG_NINT_MASK;
307 nfrac = (pll >> AR934X_PLL_DDR_CONFIG_NFRAC_SHIFT) &
308 AR934X_PLL_DDR_CONFIG_NFRAC_MASK;
309 frac = 1 << 10;
310 }
311
312 ddr_pll = ar934x_get_pll_freq(ref_rate, ref_div, nint,
313 nfrac, frac, out_div);
314
315 clk_ctrl = ath79_pll_rr(AR934X_PLL_CPU_DDR_CLK_CTRL_REG);
316
317 postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SHIFT) &
318 AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK;
319
320 if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS)
321 cpu_rate = ref_rate;
322 else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL)
323 cpu_rate = cpu_pll / (postdiv + 1);
324 else
325 cpu_rate = ddr_pll / (postdiv + 1);
326
327 postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_SHIFT) &
328 AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK;
329
330 if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS)
331 ddr_rate = ref_rate;
332 else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL)
333 ddr_rate = ddr_pll / (postdiv + 1);
334 else
335 ddr_rate = cpu_pll / (postdiv + 1);
336
337 postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SHIFT) &
338 AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK;
339
340 if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS)
341 ahb_rate = ref_rate;
342 else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL)
343 ahb_rate = ddr_pll / (postdiv + 1);
344 else
345 ahb_rate = cpu_pll / (postdiv + 1);
346
347 ath79_add_sys_clkdev("ref", ref_rate);
348 clks[ATH79_CLK_CPU] = ath79_add_sys_clkdev("cpu", cpu_rate);
349 clks[ATH79_CLK_DDR] = ath79_add_sys_clkdev("ddr", ddr_rate);
350 clks[ATH79_CLK_AHB] = ath79_add_sys_clkdev("ahb", ahb_rate);
351
352 clk_add_alias("wdt", NULL, "ref", NULL);
353 clk_add_alias("uart", NULL, "ref", NULL);
354
355 iounmap(dpll_base);
356 }
357
qca953x_clocks_init(void)358 static void __init qca953x_clocks_init(void)
359 {
360 unsigned long ref_rate;
361 unsigned long cpu_rate;
362 unsigned long ddr_rate;
363 unsigned long ahb_rate;
364 u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv;
365 u32 cpu_pll, ddr_pll;
366 u32 bootstrap;
367
368 bootstrap = ath79_reset_rr(QCA953X_RESET_REG_BOOTSTRAP);
369 if (bootstrap & QCA953X_BOOTSTRAP_REF_CLK_40)
370 ref_rate = 40 * 1000 * 1000;
371 else
372 ref_rate = 25 * 1000 * 1000;
373
374 pll = ath79_pll_rr(QCA953X_PLL_CPU_CONFIG_REG);
375 out_div = (pll >> QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
376 QCA953X_PLL_CPU_CONFIG_OUTDIV_MASK;
377 ref_div = (pll >> QCA953X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
378 QCA953X_PLL_CPU_CONFIG_REFDIV_MASK;
379 nint = (pll >> QCA953X_PLL_CPU_CONFIG_NINT_SHIFT) &
380 QCA953X_PLL_CPU_CONFIG_NINT_MASK;
381 frac = (pll >> QCA953X_PLL_CPU_CONFIG_NFRAC_SHIFT) &
382 QCA953X_PLL_CPU_CONFIG_NFRAC_MASK;
383
384 cpu_pll = nint * ref_rate / ref_div;
385 cpu_pll += frac * (ref_rate >> 6) / ref_div;
386 cpu_pll /= (1 << out_div);
387
388 pll = ath79_pll_rr(QCA953X_PLL_DDR_CONFIG_REG);
389 out_div = (pll >> QCA953X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
390 QCA953X_PLL_DDR_CONFIG_OUTDIV_MASK;
391 ref_div = (pll >> QCA953X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
392 QCA953X_PLL_DDR_CONFIG_REFDIV_MASK;
393 nint = (pll >> QCA953X_PLL_DDR_CONFIG_NINT_SHIFT) &
394 QCA953X_PLL_DDR_CONFIG_NINT_MASK;
395 frac = (pll >> QCA953X_PLL_DDR_CONFIG_NFRAC_SHIFT) &
396 QCA953X_PLL_DDR_CONFIG_NFRAC_MASK;
397
398 ddr_pll = nint * ref_rate / ref_div;
399 ddr_pll += frac * (ref_rate >> 6) / (ref_div << 4);
400 ddr_pll /= (1 << out_div);
401
402 clk_ctrl = ath79_pll_rr(QCA953X_PLL_CLK_CTRL_REG);
403
404 postdiv = (clk_ctrl >> QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) &
405 QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_MASK;
406
407 if (clk_ctrl & QCA953X_PLL_CLK_CTRL_CPU_PLL_BYPASS)
408 cpu_rate = ref_rate;
409 else if (clk_ctrl & QCA953X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL)
410 cpu_rate = cpu_pll / (postdiv + 1);
411 else
412 cpu_rate = ddr_pll / (postdiv + 1);
413
414 postdiv = (clk_ctrl >> QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) &
415 QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_MASK;
416
417 if (clk_ctrl & QCA953X_PLL_CLK_CTRL_DDR_PLL_BYPASS)
418 ddr_rate = ref_rate;
419 else if (clk_ctrl & QCA953X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL)
420 ddr_rate = ddr_pll / (postdiv + 1);
421 else
422 ddr_rate = cpu_pll / (postdiv + 1);
423
424 postdiv = (clk_ctrl >> QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) &
425 QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_MASK;
426
427 if (clk_ctrl & QCA953X_PLL_CLK_CTRL_AHB_PLL_BYPASS)
428 ahb_rate = ref_rate;
429 else if (clk_ctrl & QCA953X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL)
430 ahb_rate = ddr_pll / (postdiv + 1);
431 else
432 ahb_rate = cpu_pll / (postdiv + 1);
433
434 ath79_add_sys_clkdev("ref", ref_rate);
435 ath79_add_sys_clkdev("cpu", cpu_rate);
436 ath79_add_sys_clkdev("ddr", ddr_rate);
437 ath79_add_sys_clkdev("ahb", ahb_rate);
438
439 clk_add_alias("wdt", NULL, "ref", NULL);
440 clk_add_alias("uart", NULL, "ref", NULL);
441 }
442
qca955x_clocks_init(void)443 static void __init qca955x_clocks_init(void)
444 {
445 unsigned long ref_rate;
446 unsigned long cpu_rate;
447 unsigned long ddr_rate;
448 unsigned long ahb_rate;
449 u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv;
450 u32 cpu_pll, ddr_pll;
451 u32 bootstrap;
452
453 bootstrap = ath79_reset_rr(QCA955X_RESET_REG_BOOTSTRAP);
454 if (bootstrap & QCA955X_BOOTSTRAP_REF_CLK_40)
455 ref_rate = 40 * 1000 * 1000;
456 else
457 ref_rate = 25 * 1000 * 1000;
458
459 pll = ath79_pll_rr(QCA955X_PLL_CPU_CONFIG_REG);
460 out_div = (pll >> QCA955X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
461 QCA955X_PLL_CPU_CONFIG_OUTDIV_MASK;
462 ref_div = (pll >> QCA955X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
463 QCA955X_PLL_CPU_CONFIG_REFDIV_MASK;
464 nint = (pll >> QCA955X_PLL_CPU_CONFIG_NINT_SHIFT) &
465 QCA955X_PLL_CPU_CONFIG_NINT_MASK;
466 frac = (pll >> QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT) &
467 QCA955X_PLL_CPU_CONFIG_NFRAC_MASK;
468
469 cpu_pll = nint * ref_rate / ref_div;
470 cpu_pll += frac * ref_rate / (ref_div * (1 << 6));
471 cpu_pll /= (1 << out_div);
472
473 pll = ath79_pll_rr(QCA955X_PLL_DDR_CONFIG_REG);
474 out_div = (pll >> QCA955X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
475 QCA955X_PLL_DDR_CONFIG_OUTDIV_MASK;
476 ref_div = (pll >> QCA955X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
477 QCA955X_PLL_DDR_CONFIG_REFDIV_MASK;
478 nint = (pll >> QCA955X_PLL_DDR_CONFIG_NINT_SHIFT) &
479 QCA955X_PLL_DDR_CONFIG_NINT_MASK;
480 frac = (pll >> QCA955X_PLL_DDR_CONFIG_NFRAC_SHIFT) &
481 QCA955X_PLL_DDR_CONFIG_NFRAC_MASK;
482
483 ddr_pll = nint * ref_rate / ref_div;
484 ddr_pll += frac * ref_rate / (ref_div * (1 << 10));
485 ddr_pll /= (1 << out_div);
486
487 clk_ctrl = ath79_pll_rr(QCA955X_PLL_CLK_CTRL_REG);
488
489 postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) &
490 QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_MASK;
491
492 if (clk_ctrl & QCA955X_PLL_CLK_CTRL_CPU_PLL_BYPASS)
493 cpu_rate = ref_rate;
494 else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL)
495 cpu_rate = ddr_pll / (postdiv + 1);
496 else
497 cpu_rate = cpu_pll / (postdiv + 1);
498
499 postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) &
500 QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_MASK;
501
502 if (clk_ctrl & QCA955X_PLL_CLK_CTRL_DDR_PLL_BYPASS)
503 ddr_rate = ref_rate;
504 else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL)
505 ddr_rate = cpu_pll / (postdiv + 1);
506 else
507 ddr_rate = ddr_pll / (postdiv + 1);
508
509 postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) &
510 QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_MASK;
511
512 if (clk_ctrl & QCA955X_PLL_CLK_CTRL_AHB_PLL_BYPASS)
513 ahb_rate = ref_rate;
514 else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL)
515 ahb_rate = ddr_pll / (postdiv + 1);
516 else
517 ahb_rate = cpu_pll / (postdiv + 1);
518
519 ath79_add_sys_clkdev("ref", ref_rate);
520 clks[ATH79_CLK_CPU] = ath79_add_sys_clkdev("cpu", cpu_rate);
521 clks[ATH79_CLK_DDR] = ath79_add_sys_clkdev("ddr", ddr_rate);
522 clks[ATH79_CLK_AHB] = ath79_add_sys_clkdev("ahb", ahb_rate);
523
524 clk_add_alias("wdt", NULL, "ref", NULL);
525 clk_add_alias("uart", NULL, "ref", NULL);
526 }
527
qca956x_clocks_init(void)528 static void __init qca956x_clocks_init(void)
529 {
530 unsigned long ref_rate;
531 unsigned long cpu_rate;
532 unsigned long ddr_rate;
533 unsigned long ahb_rate;
534 u32 pll, out_div, ref_div, nint, hfrac, lfrac, clk_ctrl, postdiv;
535 u32 cpu_pll, ddr_pll;
536 u32 bootstrap;
537
538 /*
539 * QCA956x timer init workaround has to be applied right before setting
540 * up the clock. Else, there will be no jiffies
541 */
542 u32 misc;
543
544 misc = ath79_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE);
545 misc |= MISC_INT_MIPS_SI_TIMERINT_MASK;
546 ath79_reset_wr(AR71XX_RESET_REG_MISC_INT_ENABLE, misc);
547
548 bootstrap = ath79_reset_rr(QCA956X_RESET_REG_BOOTSTRAP);
549 if (bootstrap & QCA956X_BOOTSTRAP_REF_CLK_40)
550 ref_rate = 40 * 1000 * 1000;
551 else
552 ref_rate = 25 * 1000 * 1000;
553
554 pll = ath79_pll_rr(QCA956X_PLL_CPU_CONFIG_REG);
555 out_div = (pll >> QCA956X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
556 QCA956X_PLL_CPU_CONFIG_OUTDIV_MASK;
557 ref_div = (pll >> QCA956X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
558 QCA956X_PLL_CPU_CONFIG_REFDIV_MASK;
559
560 pll = ath79_pll_rr(QCA956X_PLL_CPU_CONFIG1_REG);
561 nint = (pll >> QCA956X_PLL_CPU_CONFIG1_NINT_SHIFT) &
562 QCA956X_PLL_CPU_CONFIG1_NINT_MASK;
563 hfrac = (pll >> QCA956X_PLL_CPU_CONFIG1_NFRAC_H_SHIFT) &
564 QCA956X_PLL_CPU_CONFIG1_NFRAC_H_MASK;
565 lfrac = (pll >> QCA956X_PLL_CPU_CONFIG1_NFRAC_L_SHIFT) &
566 QCA956X_PLL_CPU_CONFIG1_NFRAC_L_MASK;
567
568 cpu_pll = nint * ref_rate / ref_div;
569 cpu_pll += (lfrac * ref_rate) / ((ref_div * 25) << 13);
570 cpu_pll += (hfrac >> 13) * ref_rate / ref_div;
571 cpu_pll /= (1 << out_div);
572
573 pll = ath79_pll_rr(QCA956X_PLL_DDR_CONFIG_REG);
574 out_div = (pll >> QCA956X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
575 QCA956X_PLL_DDR_CONFIG_OUTDIV_MASK;
576 ref_div = (pll >> QCA956X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
577 QCA956X_PLL_DDR_CONFIG_REFDIV_MASK;
578 pll = ath79_pll_rr(QCA956X_PLL_DDR_CONFIG1_REG);
579 nint = (pll >> QCA956X_PLL_DDR_CONFIG1_NINT_SHIFT) &
580 QCA956X_PLL_DDR_CONFIG1_NINT_MASK;
581 hfrac = (pll >> QCA956X_PLL_DDR_CONFIG1_NFRAC_H_SHIFT) &
582 QCA956X_PLL_DDR_CONFIG1_NFRAC_H_MASK;
583 lfrac = (pll >> QCA956X_PLL_DDR_CONFIG1_NFRAC_L_SHIFT) &
584 QCA956X_PLL_DDR_CONFIG1_NFRAC_L_MASK;
585
586 ddr_pll = nint * ref_rate / ref_div;
587 ddr_pll += (lfrac * ref_rate) / ((ref_div * 25) << 13);
588 ddr_pll += (hfrac >> 13) * ref_rate / ref_div;
589 ddr_pll /= (1 << out_div);
590
591 clk_ctrl = ath79_pll_rr(QCA956X_PLL_CLK_CTRL_REG);
592
593 postdiv = (clk_ctrl >> QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) &
594 QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_MASK;
595
596 if (clk_ctrl & QCA956X_PLL_CLK_CTRL_CPU_PLL_BYPASS)
597 cpu_rate = ref_rate;
598 else if (clk_ctrl & QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_CPUPLL)
599 cpu_rate = ddr_pll / (postdiv + 1);
600 else
601 cpu_rate = cpu_pll / (postdiv + 1);
602
603 postdiv = (clk_ctrl >> QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) &
604 QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_MASK;
605
606 if (clk_ctrl & QCA956X_PLL_CLK_CTRL_DDR_PLL_BYPASS)
607 ddr_rate = ref_rate;
608 else if (clk_ctrl & QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_DDRPLL)
609 ddr_rate = cpu_pll / (postdiv + 1);
610 else
611 ddr_rate = ddr_pll / (postdiv + 1);
612
613 postdiv = (clk_ctrl >> QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) &
614 QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_MASK;
615
616 if (clk_ctrl & QCA956X_PLL_CLK_CTRL_AHB_PLL_BYPASS)
617 ahb_rate = ref_rate;
618 else if (clk_ctrl & QCA956X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL)
619 ahb_rate = ddr_pll / (postdiv + 1);
620 else
621 ahb_rate = cpu_pll / (postdiv + 1);
622
623 ath79_add_sys_clkdev("ref", ref_rate);
624 ath79_add_sys_clkdev("cpu", cpu_rate);
625 ath79_add_sys_clkdev("ddr", ddr_rate);
626 ath79_add_sys_clkdev("ahb", ahb_rate);
627
628 clk_add_alias("wdt", NULL, "ref", NULL);
629 clk_add_alias("uart", NULL, "ref", NULL);
630 }
631
ath79_clocks_init(void)632 void __init ath79_clocks_init(void)
633 {
634 if (soc_is_ar71xx())
635 ar71xx_clocks_init();
636 else if (soc_is_ar724x() || soc_is_ar913x())
637 ar724x_clocks_init();
638 else if (soc_is_ar933x())
639 ar933x_clocks_init();
640 else if (soc_is_ar934x())
641 ar934x_clocks_init();
642 else if (soc_is_qca953x())
643 qca953x_clocks_init();
644 else if (soc_is_qca955x())
645 qca955x_clocks_init();
646 else if (soc_is_qca956x() || soc_is_tp9343())
647 qca956x_clocks_init();
648 else
649 BUG();
650 }
651
652 unsigned long __init
ath79_get_sys_clk_rate(const char * id)653 ath79_get_sys_clk_rate(const char *id)
654 {
655 struct clk *clk;
656 unsigned long rate;
657
658 clk = clk_get(NULL, id);
659 if (IS_ERR(clk))
660 panic("unable to get %s clock, err=%d", id, (int) PTR_ERR(clk));
661
662 rate = clk_get_rate(clk);
663 clk_put(clk);
664
665 return rate;
666 }
667
668 #ifdef CONFIG_OF
ath79_clocks_init_dt(struct device_node * np)669 static void __init ath79_clocks_init_dt(struct device_node *np)
670 {
671 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
672 }
673
674 CLK_OF_DECLARE(ar7100, "qca,ar7100-pll", ath79_clocks_init_dt);
675 CLK_OF_DECLARE(ar7240, "qca,ar7240-pll", ath79_clocks_init_dt);
676 CLK_OF_DECLARE(ar9340, "qca,ar9340-pll", ath79_clocks_init_dt);
677 CLK_OF_DECLARE(ar9550, "qca,qca9550-pll", ath79_clocks_init_dt);
678
ath79_clocks_init_dt_ng(struct device_node * np)679 static void __init ath79_clocks_init_dt_ng(struct device_node *np)
680 {
681 struct clk *ref_clk;
682 void __iomem *pll_base;
683
684 ref_clk = of_clk_get(np, 0);
685 if (IS_ERR(ref_clk)) {
686 pr_err("%pOF: of_clk_get failed\n", np);
687 goto err;
688 }
689
690 pll_base = of_iomap(np, 0);
691 if (!pll_base) {
692 pr_err("%pOF: can't map pll registers\n", np);
693 goto err_clk;
694 }
695
696 if (of_device_is_compatible(np, "qca,ar9130-pll"))
697 ar724x_clk_init(ref_clk, pll_base);
698 else if (of_device_is_compatible(np, "qca,ar9330-pll"))
699 ar9330_clk_init(ref_clk, pll_base);
700 else {
701 pr_err("%pOF: could not find any appropriate clk_init()\n", np);
702 goto err_iounmap;
703 }
704
705 if (of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data)) {
706 pr_err("%pOF: could not register clk provider\n", np);
707 goto err_iounmap;
708 }
709
710 return;
711
712 err_iounmap:
713 iounmap(pll_base);
714
715 err_clk:
716 clk_put(ref_clk);
717
718 err:
719 return;
720 }
721 CLK_OF_DECLARE(ar9130_clk, "qca,ar9130-pll", ath79_clocks_init_dt_ng);
722 CLK_OF_DECLARE(ar9330_clk, "qca,ar9330-pll", ath79_clocks_init_dt_ng);
723 #endif
724
