1 /*
2  * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org>
3  * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com>
4  * Copyright (c) 2007-2008 Matthew W. S. Bell  <mentor@madwifi.org>
5  * Copyright (c) 2007-2008 Luis Rodriguez <mcgrof@winlab.rutgers.edu>
6  * Copyright (c) 2007-2008 Pavel Roskin <proski@gnu.org>
7  * Copyright (c) 2007-2008 Jiri Slaby <jirislaby@gmail.com>
8  *
9  * Permission to use, copy, modify, and distribute this software for any
10  * purpose with or without fee is hereby granted, provided that the above
11  * copyright notice and this permission notice appear in all copies.
12  *
13  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
14  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
15  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
16  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
17  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
18  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
19  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20  *
21  */
22 
23 /*********************************\
24 * Protocol Control Unit Functions *
25 \*********************************/
26 
27 #include <asm/unaligned.h>
28 
29 #include "ath5k.h"
30 #include "reg.h"
31 #include "debug.h"
32 
33 /**
34  * DOC: Protocol Control Unit (PCU) functions
35  *
36  * Protocol control unit is responsible to maintain various protocol
37  * properties before a frame is send and after a frame is received to/from
38  * baseband. To be more specific, PCU handles:
39  *
40  * - Buffering of RX and TX frames (after QCU/DCUs)
41  *
42  * - Encrypting and decrypting (using the built-in engine)
43  *
44  * - Generating ACKs, RTS/CTS frames
45  *
46  * - Maintaining TSF
47  *
48  * - FCS
49  *
50  * - Updating beacon data (with TSF etc)
51  *
52  * - Generating virtual CCA
53  *
54  * - RX/Multicast filtering
55  *
56  * - BSSID filtering
57  *
58  * - Various statistics
59  *
60  * -Different operating modes: AP, STA, IBSS
61  *
62  * Note: Most of these functions can be tweaked/bypassed so you can do
63  * them on sw above for debugging or research. For more infos check out PCU
64  * registers on reg.h.
65  */
66 
67 /**
68  * DOC: ACK rates
69  *
70  * AR5212+ can use higher rates for ack transmission
71  * based on current tx rate instead of the base rate.
72  * It does this to better utilize channel usage.
73  * There is a mapping between G rates (that cover both
74  * CCK and OFDM) and ack rates that we use when setting
75  * rate -> duration table. This mapping is hw-based so
76  * don't change anything.
77  *
78  * To enable this functionality we must set
79  * ah->ah_ack_bitrate_high to true else base rate is
80  * used (1Mb for CCK, 6Mb for OFDM).
81  */
82 static const unsigned int ack_rates_high[] =
83 /* Tx	-> ACK	*/
84 /* 1Mb	-> 1Mb	*/	{ 0,
85 /* 2MB	-> 2Mb	*/	1,
86 /* 5.5Mb -> 2Mb	*/	1,
87 /* 11Mb	-> 2Mb	*/	1,
88 /* 6Mb	-> 6Mb	*/	4,
89 /* 9Mb	-> 6Mb	*/	4,
90 /* 12Mb	-> 12Mb	*/	6,
91 /* 18Mb	-> 12Mb	*/	6,
92 /* 24Mb	-> 24Mb	*/	8,
93 /* 36Mb	-> 24Mb	*/	8,
94 /* 48Mb	-> 24Mb	*/	8,
95 /* 54Mb	-> 24Mb	*/	8 };
96 
97 /*******************\
98 * Helper functions *
99 \*******************/
100 
101 /**
102  * ath5k_hw_get_frame_duration() - Get tx time of a frame
103  * @ah: The &struct ath5k_hw
104  * @len: Frame's length in bytes
105  * @rate: The @struct ieee80211_rate
106  * @shortpre: Indicate short preample
107  *
108  * Calculate tx duration of a frame given it's rate and length
109  * It extends ieee80211_generic_frame_duration for non standard
110  * bwmodes.
111  */
112 int
ath5k_hw_get_frame_duration(struct ath5k_hw * ah,enum nl80211_band band,int len,struct ieee80211_rate * rate,bool shortpre)113 ath5k_hw_get_frame_duration(struct ath5k_hw *ah, enum nl80211_band band,
114 		int len, struct ieee80211_rate *rate, bool shortpre)
115 {
116 	int sifs, preamble, plcp_bits, sym_time;
117 	int bitrate, bits, symbols, symbol_bits;
118 	int dur;
119 
120 	/* Fallback */
121 	if (!ah->ah_bwmode) {
122 		__le16 raw_dur = ieee80211_generic_frame_duration(ah->hw,
123 					NULL, band, len, rate);
124 
125 		/* subtract difference between long and short preamble */
126 		dur = le16_to_cpu(raw_dur);
127 		if (shortpre)
128 			dur -= 96;
129 
130 		return dur;
131 	}
132 
133 	bitrate = rate->bitrate;
134 	preamble = AR5K_INIT_OFDM_PREAMPLE_TIME;
135 	plcp_bits = AR5K_INIT_OFDM_PLCP_BITS;
136 	sym_time = AR5K_INIT_OFDM_SYMBOL_TIME;
137 
138 	switch (ah->ah_bwmode) {
139 	case AR5K_BWMODE_40MHZ:
140 		sifs = AR5K_INIT_SIFS_TURBO;
141 		preamble = AR5K_INIT_OFDM_PREAMBLE_TIME_MIN;
142 		break;
143 	case AR5K_BWMODE_10MHZ:
144 		sifs = AR5K_INIT_SIFS_HALF_RATE;
145 		preamble *= 2;
146 		sym_time *= 2;
147 		bitrate = DIV_ROUND_UP(bitrate, 2);
148 		break;
149 	case AR5K_BWMODE_5MHZ:
150 		sifs = AR5K_INIT_SIFS_QUARTER_RATE;
151 		preamble *= 4;
152 		sym_time *= 4;
153 		bitrate = DIV_ROUND_UP(bitrate, 4);
154 		break;
155 	default:
156 		sifs = AR5K_INIT_SIFS_DEFAULT_BG;
157 		break;
158 	}
159 
160 	bits = plcp_bits + (len << 3);
161 	/* Bit rate is in 100Kbits */
162 	symbol_bits = bitrate * sym_time;
163 	symbols = DIV_ROUND_UP(bits * 10, symbol_bits);
164 
165 	dur = sifs + preamble + (sym_time * symbols);
166 
167 	return dur;
168 }
169 
170 /**
171  * ath5k_hw_get_default_slottime() - Get the default slot time for current mode
172  * @ah: The &struct ath5k_hw
173  */
174 unsigned int
ath5k_hw_get_default_slottime(struct ath5k_hw * ah)175 ath5k_hw_get_default_slottime(struct ath5k_hw *ah)
176 {
177 	struct ieee80211_channel *channel = ah->ah_current_channel;
178 	unsigned int slot_time;
179 
180 	switch (ah->ah_bwmode) {
181 	case AR5K_BWMODE_40MHZ:
182 		slot_time = AR5K_INIT_SLOT_TIME_TURBO;
183 		break;
184 	case AR5K_BWMODE_10MHZ:
185 		slot_time = AR5K_INIT_SLOT_TIME_HALF_RATE;
186 		break;
187 	case AR5K_BWMODE_5MHZ:
188 		slot_time = AR5K_INIT_SLOT_TIME_QUARTER_RATE;
189 		break;
190 	case AR5K_BWMODE_DEFAULT:
191 	default:
192 		slot_time = AR5K_INIT_SLOT_TIME_DEFAULT;
193 		if ((channel->hw_value == AR5K_MODE_11B) && !ah->ah_short_slot)
194 			slot_time = AR5K_INIT_SLOT_TIME_B;
195 		break;
196 	}
197 
198 	return slot_time;
199 }
200 
201 /**
202  * ath5k_hw_get_default_sifs() - Get the default SIFS for current mode
203  * @ah: The &struct ath5k_hw
204  */
205 unsigned int
ath5k_hw_get_default_sifs(struct ath5k_hw * ah)206 ath5k_hw_get_default_sifs(struct ath5k_hw *ah)
207 {
208 	struct ieee80211_channel *channel = ah->ah_current_channel;
209 	unsigned int sifs;
210 
211 	switch (ah->ah_bwmode) {
212 	case AR5K_BWMODE_40MHZ:
213 		sifs = AR5K_INIT_SIFS_TURBO;
214 		break;
215 	case AR5K_BWMODE_10MHZ:
216 		sifs = AR5K_INIT_SIFS_HALF_RATE;
217 		break;
218 	case AR5K_BWMODE_5MHZ:
219 		sifs = AR5K_INIT_SIFS_QUARTER_RATE;
220 		break;
221 	case AR5K_BWMODE_DEFAULT:
222 	default:
223 		sifs = AR5K_INIT_SIFS_DEFAULT_BG;
224 		if (channel->band == NL80211_BAND_5GHZ)
225 			sifs = AR5K_INIT_SIFS_DEFAULT_A;
226 		break;
227 	}
228 
229 	return sifs;
230 }
231 
232 /**
233  * ath5k_hw_update_mib_counters() - Update MIB counters (mac layer statistics)
234  * @ah: The &struct ath5k_hw
235  *
236  * Reads MIB counters from PCU and updates sw statistics. Is called after a
237  * MIB interrupt, because one of these counters might have reached their maximum
238  * and triggered the MIB interrupt, to let us read and clear the counter.
239  *
240  * NOTE: Is called in interrupt context!
241  */
242 void
ath5k_hw_update_mib_counters(struct ath5k_hw * ah)243 ath5k_hw_update_mib_counters(struct ath5k_hw *ah)
244 {
245 	struct ath5k_statistics *stats = &ah->stats;
246 
247 	/* Read-And-Clear */
248 	stats->ack_fail += ath5k_hw_reg_read(ah, AR5K_ACK_FAIL);
249 	stats->rts_fail += ath5k_hw_reg_read(ah, AR5K_RTS_FAIL);
250 	stats->rts_ok += ath5k_hw_reg_read(ah, AR5K_RTS_OK);
251 	stats->fcs_error += ath5k_hw_reg_read(ah, AR5K_FCS_FAIL);
252 	stats->beacons += ath5k_hw_reg_read(ah, AR5K_BEACON_CNT);
253 }
254 
255 
256 /******************\
257 * ACK/CTS Timeouts *
258 \******************/
259 
260 /**
261  * ath5k_hw_write_rate_duration() - Fill rate code to duration table
262  * @ah: The &struct ath5k_hw
263  *
264  * Write the rate code to duration table upon hw reset. This is a helper for
265  * ath5k_hw_pcu_init(). It seems all this is doing is setting an ACK timeout on
266  * the hardware, based on current mode, for each rate. The rates which are
267  * capable of short preamble (802.11b rates 2Mbps, 5.5Mbps, and 11Mbps) have
268  * different rate code so we write their value twice (one for long preamble
269  * and one for short).
270  *
271  * Note: Band doesn't matter here, if we set the values for OFDM it works
272  * on both a and g modes. So all we have to do is set values for all g rates
273  * that include all OFDM and CCK rates.
274  *
275  */
276 static inline void
ath5k_hw_write_rate_duration(struct ath5k_hw * ah)277 ath5k_hw_write_rate_duration(struct ath5k_hw *ah)
278 {
279 	struct ieee80211_rate *rate;
280 	unsigned int i;
281 	/* 802.11g covers both OFDM and CCK */
282 	u8 band = NL80211_BAND_2GHZ;
283 
284 	/* Write rate duration table */
285 	for (i = 0; i < ah->sbands[band].n_bitrates; i++) {
286 		u32 reg;
287 		u16 tx_time;
288 
289 		if (ah->ah_ack_bitrate_high)
290 			rate = &ah->sbands[band].bitrates[ack_rates_high[i]];
291 		/* CCK -> 1Mb */
292 		else if (i < 4)
293 			rate = &ah->sbands[band].bitrates[0];
294 		/* OFDM -> 6Mb */
295 		else
296 			rate = &ah->sbands[band].bitrates[4];
297 
298 		/* Set ACK timeout */
299 		reg = AR5K_RATE_DUR(rate->hw_value);
300 
301 		/* An ACK frame consists of 10 bytes. If you add the FCS,
302 		 * which ieee80211_generic_frame_duration() adds,
303 		 * its 14 bytes. Note we use the control rate and not the
304 		 * actual rate for this rate. See mac80211 tx.c
305 		 * ieee80211_duration() for a brief description of
306 		 * what rate we should choose to TX ACKs. */
307 		tx_time = ath5k_hw_get_frame_duration(ah, band, 10,
308 					rate, false);
309 
310 		ath5k_hw_reg_write(ah, tx_time, reg);
311 
312 		if (!(rate->flags & IEEE80211_RATE_SHORT_PREAMBLE))
313 			continue;
314 
315 		tx_time = ath5k_hw_get_frame_duration(ah, band, 10, rate, true);
316 		ath5k_hw_reg_write(ah, tx_time,
317 			reg + (AR5K_SET_SHORT_PREAMBLE << 2));
318 	}
319 }
320 
321 /**
322  * ath5k_hw_set_ack_timeout() - Set ACK timeout on PCU
323  * @ah: The &struct ath5k_hw
324  * @timeout: Timeout in usec
325  */
326 static int
ath5k_hw_set_ack_timeout(struct ath5k_hw * ah,unsigned int timeout)327 ath5k_hw_set_ack_timeout(struct ath5k_hw *ah, unsigned int timeout)
328 {
329 	if (ath5k_hw_clocktoh(ah, AR5K_REG_MS(0xffffffff, AR5K_TIME_OUT_ACK))
330 			<= timeout)
331 		return -EINVAL;
332 
333 	AR5K_REG_WRITE_BITS(ah, AR5K_TIME_OUT, AR5K_TIME_OUT_ACK,
334 		ath5k_hw_htoclock(ah, timeout));
335 
336 	return 0;
337 }
338 
339 /**
340  * ath5k_hw_set_cts_timeout() - Set CTS timeout on PCU
341  * @ah: The &struct ath5k_hw
342  * @timeout: Timeout in usec
343  */
344 static int
ath5k_hw_set_cts_timeout(struct ath5k_hw * ah,unsigned int timeout)345 ath5k_hw_set_cts_timeout(struct ath5k_hw *ah, unsigned int timeout)
346 {
347 	if (ath5k_hw_clocktoh(ah, AR5K_REG_MS(0xffffffff, AR5K_TIME_OUT_CTS))
348 			<= timeout)
349 		return -EINVAL;
350 
351 	AR5K_REG_WRITE_BITS(ah, AR5K_TIME_OUT, AR5K_TIME_OUT_CTS,
352 			ath5k_hw_htoclock(ah, timeout));
353 
354 	return 0;
355 }
356 
357 
358 /*******************\
359 * RX filter Control *
360 \*******************/
361 
362 /**
363  * ath5k_hw_set_lladdr() - Set station id
364  * @ah: The &struct ath5k_hw
365  * @mac: The card's mac address (array of octets)
366  *
367  * Set station id on hw using the provided mac address
368  */
369 int
ath5k_hw_set_lladdr(struct ath5k_hw * ah,const u8 * mac)370 ath5k_hw_set_lladdr(struct ath5k_hw *ah, const u8 *mac)
371 {
372 	struct ath_common *common = ath5k_hw_common(ah);
373 	u32 low_id, high_id;
374 	u32 pcu_reg;
375 
376 	/* Set new station ID */
377 	memcpy(common->macaddr, mac, ETH_ALEN);
378 
379 	pcu_reg = ath5k_hw_reg_read(ah, AR5K_STA_ID1) & 0xffff0000;
380 
381 	low_id = get_unaligned_le32(mac);
382 	high_id = get_unaligned_le16(mac + 4);
383 
384 	ath5k_hw_reg_write(ah, low_id, AR5K_STA_ID0);
385 	ath5k_hw_reg_write(ah, pcu_reg | high_id, AR5K_STA_ID1);
386 
387 	return 0;
388 }
389 
390 /**
391  * ath5k_hw_set_bssid() - Set current BSSID on hw
392  * @ah: The &struct ath5k_hw
393  *
394  * Sets the current BSSID and BSSID mask we have from the
395  * common struct into the hardware
396  */
397 void
ath5k_hw_set_bssid(struct ath5k_hw * ah)398 ath5k_hw_set_bssid(struct ath5k_hw *ah)
399 {
400 	struct ath_common *common = ath5k_hw_common(ah);
401 	u16 tim_offset = 0;
402 
403 	/*
404 	 * Set BSSID mask on 5212
405 	 */
406 	if (ah->ah_version == AR5K_AR5212)
407 		ath_hw_setbssidmask(common);
408 
409 	/*
410 	 * Set BSSID
411 	 */
412 	ath5k_hw_reg_write(ah,
413 			   get_unaligned_le32(common->curbssid),
414 			   AR5K_BSS_ID0);
415 	ath5k_hw_reg_write(ah,
416 			   get_unaligned_le16(common->curbssid + 4) |
417 			   ((common->curaid & 0x3fff) << AR5K_BSS_ID1_AID_S),
418 			   AR5K_BSS_ID1);
419 
420 	if (common->curaid == 0) {
421 		ath5k_hw_disable_pspoll(ah);
422 		return;
423 	}
424 
425 	AR5K_REG_WRITE_BITS(ah, AR5K_BEACON, AR5K_BEACON_TIM,
426 			    tim_offset ? tim_offset + 4 : 0);
427 
428 	ath5k_hw_enable_pspoll(ah, NULL, 0);
429 }
430 
431 /**
432  * ath5k_hw_set_bssid_mask() - Filter out bssids we listen
433  * @ah: The &struct ath5k_hw
434  * @mask: The BSSID mask to set (array of octets)
435  *
436  * BSSID masking is a method used by AR5212 and newer hardware to inform PCU
437  * which bits of the interface's MAC address should be looked at when trying
438  * to decide which packets to ACK. In station mode and AP mode with a single
439  * BSS every bit matters since we lock to only one BSS. In AP mode with
440  * multiple BSSes (virtual interfaces) not every bit matters because hw must
441  * accept frames for all BSSes and so we tweak some bits of our mac address
442  * in order to have multiple BSSes.
443  *
444  * For more information check out ../hw.c of the common ath module.
445  */
446 void
ath5k_hw_set_bssid_mask(struct ath5k_hw * ah,const u8 * mask)447 ath5k_hw_set_bssid_mask(struct ath5k_hw *ah, const u8 *mask)
448 {
449 	struct ath_common *common = ath5k_hw_common(ah);
450 
451 	/* Cache bssid mask so that we can restore it
452 	 * on reset */
453 	memcpy(common->bssidmask, mask, ETH_ALEN);
454 	if (ah->ah_version == AR5K_AR5212)
455 		ath_hw_setbssidmask(common);
456 }
457 
458 /**
459  * ath5k_hw_set_mcast_filter() - Set multicast filter
460  * @ah: The &struct ath5k_hw
461  * @filter0: Lower 32bits of muticast filter
462  * @filter1: Higher 16bits of multicast filter
463  */
464 void
ath5k_hw_set_mcast_filter(struct ath5k_hw * ah,u32 filter0,u32 filter1)465 ath5k_hw_set_mcast_filter(struct ath5k_hw *ah, u32 filter0, u32 filter1)
466 {
467 	ath5k_hw_reg_write(ah, filter0, AR5K_MCAST_FILTER0);
468 	ath5k_hw_reg_write(ah, filter1, AR5K_MCAST_FILTER1);
469 }
470 
471 /**
472  * ath5k_hw_get_rx_filter() - Get current rx filter
473  * @ah: The &struct ath5k_hw
474  *
475  * Returns the RX filter by reading rx filter and
476  * phy error filter registers. RX filter is used
477  * to set the allowed frame types that PCU will accept
478  * and pass to the driver. For a list of frame types
479  * check out reg.h.
480  */
481 u32
ath5k_hw_get_rx_filter(struct ath5k_hw * ah)482 ath5k_hw_get_rx_filter(struct ath5k_hw *ah)
483 {
484 	u32 data, filter = 0;
485 
486 	filter = ath5k_hw_reg_read(ah, AR5K_RX_FILTER);
487 
488 	/*Radar detection for 5212*/
489 	if (ah->ah_version == AR5K_AR5212) {
490 		data = ath5k_hw_reg_read(ah, AR5K_PHY_ERR_FIL);
491 
492 		if (data & AR5K_PHY_ERR_FIL_RADAR)
493 			filter |= AR5K_RX_FILTER_RADARERR;
494 		if (data & (AR5K_PHY_ERR_FIL_OFDM | AR5K_PHY_ERR_FIL_CCK))
495 			filter |= AR5K_RX_FILTER_PHYERR;
496 	}
497 
498 	return filter;
499 }
500 
501 /**
502  * ath5k_hw_set_rx_filter() - Set rx filter
503  * @ah: The &struct ath5k_hw
504  * @filter: RX filter mask (see reg.h)
505  *
506  * Sets RX filter register and also handles PHY error filter
507  * register on 5212 and newer chips so that we have proper PHY
508  * error reporting.
509  */
510 void
ath5k_hw_set_rx_filter(struct ath5k_hw * ah,u32 filter)511 ath5k_hw_set_rx_filter(struct ath5k_hw *ah, u32 filter)
512 {
513 	u32 data = 0;
514 
515 	/* Set PHY error filter register on 5212*/
516 	if (ah->ah_version == AR5K_AR5212) {
517 		if (filter & AR5K_RX_FILTER_RADARERR)
518 			data |= AR5K_PHY_ERR_FIL_RADAR;
519 		if (filter & AR5K_RX_FILTER_PHYERR)
520 			data |= AR5K_PHY_ERR_FIL_OFDM | AR5K_PHY_ERR_FIL_CCK;
521 	}
522 
523 	/*
524 	 * The AR5210 uses promiscuous mode to detect radar activity
525 	 */
526 	if (ah->ah_version == AR5K_AR5210 &&
527 			(filter & AR5K_RX_FILTER_RADARERR)) {
528 		filter &= ~AR5K_RX_FILTER_RADARERR;
529 		filter |= AR5K_RX_FILTER_PROM;
530 	}
531 
532 	/*Zero length DMA (phy error reporting) */
533 	if (data)
534 		AR5K_REG_ENABLE_BITS(ah, AR5K_RXCFG, AR5K_RXCFG_ZLFDMA);
535 	else
536 		AR5K_REG_DISABLE_BITS(ah, AR5K_RXCFG, AR5K_RXCFG_ZLFDMA);
537 
538 	/*Write RX Filter register*/
539 	ath5k_hw_reg_write(ah, filter & 0xff, AR5K_RX_FILTER);
540 
541 	/*Write PHY error filter register on 5212*/
542 	if (ah->ah_version == AR5K_AR5212)
543 		ath5k_hw_reg_write(ah, data, AR5K_PHY_ERR_FIL);
544 
545 }
546 
547 
548 /****************\
549 * Beacon control *
550 \****************/
551 
552 #define ATH5K_MAX_TSF_READ 10
553 
554 /**
555  * ath5k_hw_get_tsf64() - Get the full 64bit TSF
556  * @ah: The &struct ath5k_hw
557  *
558  * Returns the current TSF
559  */
560 u64
ath5k_hw_get_tsf64(struct ath5k_hw * ah)561 ath5k_hw_get_tsf64(struct ath5k_hw *ah)
562 {
563 	u32 tsf_lower, tsf_upper1, tsf_upper2;
564 	int i;
565 	unsigned long flags;
566 
567 	/* This code is time critical - we don't want to be interrupted here */
568 	local_irq_save(flags);
569 
570 	/*
571 	 * While reading TSF upper and then lower part, the clock is still
572 	 * counting (or jumping in case of IBSS merge) so we might get
573 	 * inconsistent values. To avoid this, we read the upper part again
574 	 * and check it has not been changed. We make the hypothesis that a
575 	 * maximum of 3 changes can happens in a row (we use 10 as a safe
576 	 * value).
577 	 *
578 	 * Impact on performance is pretty small, since in most cases, only
579 	 * 3 register reads are needed.
580 	 */
581 
582 	tsf_upper1 = ath5k_hw_reg_read(ah, AR5K_TSF_U32);
583 	for (i = 0; i < ATH5K_MAX_TSF_READ; i++) {
584 		tsf_lower = ath5k_hw_reg_read(ah, AR5K_TSF_L32);
585 		tsf_upper2 = ath5k_hw_reg_read(ah, AR5K_TSF_U32);
586 		if (tsf_upper2 == tsf_upper1)
587 			break;
588 		tsf_upper1 = tsf_upper2;
589 	}
590 
591 	local_irq_restore(flags);
592 
593 	WARN_ON(i == ATH5K_MAX_TSF_READ);
594 
595 	return ((u64)tsf_upper1 << 32) | tsf_lower;
596 }
597 
598 #undef ATH5K_MAX_TSF_READ
599 
600 /**
601  * ath5k_hw_set_tsf64() - Set a new 64bit TSF
602  * @ah: The &struct ath5k_hw
603  * @tsf64: The new 64bit TSF
604  *
605  * Sets the new TSF
606  */
607 void
ath5k_hw_set_tsf64(struct ath5k_hw * ah,u64 tsf64)608 ath5k_hw_set_tsf64(struct ath5k_hw *ah, u64 tsf64)
609 {
610 	ath5k_hw_reg_write(ah, tsf64 & 0xffffffff, AR5K_TSF_L32);
611 	ath5k_hw_reg_write(ah, (tsf64 >> 32) & 0xffffffff, AR5K_TSF_U32);
612 }
613 
614 /**
615  * ath5k_hw_reset_tsf() - Force a TSF reset
616  * @ah: The &struct ath5k_hw
617  *
618  * Forces a TSF reset on PCU
619  */
620 void
ath5k_hw_reset_tsf(struct ath5k_hw * ah)621 ath5k_hw_reset_tsf(struct ath5k_hw *ah)
622 {
623 	u32 val;
624 
625 	val = ath5k_hw_reg_read(ah, AR5K_BEACON) | AR5K_BEACON_RESET_TSF;
626 
627 	/*
628 	 * Each write to the RESET_TSF bit toggles a hardware internal
629 	 * signal to reset TSF, but if left high it will cause a TSF reset
630 	 * on the next chip reset as well.  Thus we always write the value
631 	 * twice to clear the signal.
632 	 */
633 	ath5k_hw_reg_write(ah, val, AR5K_BEACON);
634 	ath5k_hw_reg_write(ah, val, AR5K_BEACON);
635 }
636 
637 /**
638  * ath5k_hw_init_beacon_timers() - Initialize beacon timers
639  * @ah: The &struct ath5k_hw
640  * @next_beacon: Next TBTT
641  * @interval: Current beacon interval
642  *
643  * This function is used to initialize beacon timers based on current
644  * operation mode and settings.
645  */
646 void
ath5k_hw_init_beacon_timers(struct ath5k_hw * ah,u32 next_beacon,u32 interval)647 ath5k_hw_init_beacon_timers(struct ath5k_hw *ah, u32 next_beacon, u32 interval)
648 {
649 	u32 timer1, timer2, timer3;
650 
651 	/*
652 	 * Set the additional timers by mode
653 	 */
654 	switch (ah->opmode) {
655 	case NL80211_IFTYPE_MONITOR:
656 	case NL80211_IFTYPE_STATION:
657 		/* In STA mode timer1 is used as next wakeup
658 		 * timer and timer2 as next CFP duration start
659 		 * timer. Both in 1/8TUs. */
660 		/* TODO: PCF handling */
661 		if (ah->ah_version == AR5K_AR5210) {
662 			timer1 = 0xffffffff;
663 			timer2 = 0xffffffff;
664 		} else {
665 			timer1 = 0x0000ffff;
666 			timer2 = 0x0007ffff;
667 		}
668 		/* Mark associated AP as PCF incapable for now */
669 		AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1, AR5K_STA_ID1_PCF);
670 		break;
671 	case NL80211_IFTYPE_ADHOC:
672 		AR5K_REG_ENABLE_BITS(ah, AR5K_TXCFG, AR5K_TXCFG_ADHOC_BCN_ATIM);
673 		/* fall through */
674 	default:
675 		/* On non-STA modes timer1 is used as next DMA
676 		 * beacon alert (DBA) timer and timer2 as next
677 		 * software beacon alert. Both in 1/8TUs. */
678 		timer1 = (next_beacon - AR5K_TUNE_DMA_BEACON_RESP) << 3;
679 		timer2 = (next_beacon - AR5K_TUNE_SW_BEACON_RESP) << 3;
680 		break;
681 	}
682 
683 	/* Timer3 marks the end of our ATIM window
684 	 * a zero length window is not allowed because
685 	 * we 'll get no beacons */
686 	timer3 = next_beacon + 1;
687 
688 	/*
689 	 * Set the beacon register and enable all timers.
690 	 */
691 	/* When in AP or Mesh Point mode zero timer0 to start TSF */
692 	if (ah->opmode == NL80211_IFTYPE_AP ||
693 	    ah->opmode == NL80211_IFTYPE_MESH_POINT)
694 		ath5k_hw_reg_write(ah, 0, AR5K_TIMER0);
695 
696 	ath5k_hw_reg_write(ah, next_beacon, AR5K_TIMER0);
697 	ath5k_hw_reg_write(ah, timer1, AR5K_TIMER1);
698 	ath5k_hw_reg_write(ah, timer2, AR5K_TIMER2);
699 	ath5k_hw_reg_write(ah, timer3, AR5K_TIMER3);
700 
701 	/* Force a TSF reset if requested and enable beacons */
702 	if (interval & AR5K_BEACON_RESET_TSF)
703 		ath5k_hw_reset_tsf(ah);
704 
705 	ath5k_hw_reg_write(ah, interval & (AR5K_BEACON_PERIOD |
706 					AR5K_BEACON_ENABLE),
707 						AR5K_BEACON);
708 
709 	/* Flush any pending BMISS interrupts on ISR by
710 	 * performing a clear-on-write operation on PISR
711 	 * register for the BMISS bit (writing a bit on
712 	 * ISR toggles a reset for that bit and leaves
713 	 * the remaining bits intact) */
714 	if (ah->ah_version == AR5K_AR5210)
715 		ath5k_hw_reg_write(ah, AR5K_ISR_BMISS, AR5K_ISR);
716 	else
717 		ath5k_hw_reg_write(ah, AR5K_ISR_BMISS, AR5K_PISR);
718 
719 	/* TODO: Set enhanced sleep registers on AR5212
720 	 * based on vif->bss_conf params, until then
721 	 * disable power save reporting.*/
722 	AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1, AR5K_STA_ID1_PWR_SV);
723 
724 }
725 
726 /**
727  * ath5k_check_timer_win() - Check if timer B is timer A + window
728  * @a: timer a (before b)
729  * @b: timer b (after a)
730  * @window: difference between a and b
731  * @intval: timers are increased by this interval
732  *
733  * This helper function checks if timer B is timer A + window and covers
734  * cases where timer A or B might have already been updated or wrapped
735  * around (Timers are 16 bit).
736  *
737  * Returns true if O.K.
738  */
739 static inline bool
ath5k_check_timer_win(int a,int b,int window,int intval)740 ath5k_check_timer_win(int a, int b, int window, int intval)
741 {
742 	/*
743 	 * 1.) usually B should be A + window
744 	 * 2.) A already updated, B not updated yet
745 	 * 3.) A already updated and has wrapped around
746 	 * 4.) B has wrapped around
747 	 */
748 	if ((b - a == window) ||				/* 1.) */
749 	    (a - b == intval - window) ||			/* 2.) */
750 	    ((a | 0x10000) - b == intval - window) ||		/* 3.) */
751 	    ((b | 0x10000) - a == window))			/* 4.) */
752 		return true; /* O.K. */
753 	return false;
754 }
755 
756 /**
757  * ath5k_hw_check_beacon_timers() - Check if the beacon timers are correct
758  * @ah: The &struct ath5k_hw
759  * @intval: beacon interval
760  *
761  * This is a workaround for IBSS mode
762  *
763  * The need for this function arises from the fact that we have 4 separate
764  * HW timer registers (TIMER0 - TIMER3), which are closely related to the
765  * next beacon target time (NBTT), and that the HW updates these timers
766  * separately based on the current TSF value. The hardware increments each
767  * timer by the beacon interval, when the local TSF converted to TU is equal
768  * to the value stored in the timer.
769  *
770  * The reception of a beacon with the same BSSID can update the local HW TSF
771  * at any time - this is something we can't avoid. If the TSF jumps to a
772  * time which is later than the time stored in a timer, this timer will not
773  * be updated until the TSF in TU wraps around at 16 bit (the size of the
774  * timers) and reaches the time which is stored in the timer.
775  *
776  * The problem is that these timers are closely related to TIMER0 (NBTT) and
777  * that they define a time "window". When the TSF jumps between two timers
778  * (e.g. ATIM and NBTT), the one in the past will be left behind (not
779  * updated), while the one in the future will be updated every beacon
780  * interval. This causes the window to get larger, until the TSF wraps
781  * around as described above and the timer which was left behind gets
782  * updated again. But - because the beacon interval is usually not an exact
783  * divisor of the size of the timers (16 bit), an unwanted "window" between
784  * these timers has developed!
785  *
786  * This is especially important with the ATIM window, because during
787  * the ATIM window only ATIM frames and no data frames are allowed to be
788  * sent, which creates transmission pauses after each beacon. This symptom
789  * has been described as "ramping ping" because ping times increase linearly
790  * for some time and then drop down again. A wrong window on the DMA beacon
791  * timer has the same effect, so we check for these two conditions.
792  *
793  * Returns true if O.K.
794  */
795 bool
ath5k_hw_check_beacon_timers(struct ath5k_hw * ah,int intval)796 ath5k_hw_check_beacon_timers(struct ath5k_hw *ah, int intval)
797 {
798 	unsigned int nbtt, atim, dma;
799 
800 	nbtt = ath5k_hw_reg_read(ah, AR5K_TIMER0);
801 	atim = ath5k_hw_reg_read(ah, AR5K_TIMER3);
802 	dma = ath5k_hw_reg_read(ah, AR5K_TIMER1) >> 3;
803 
804 	/* NOTE: SWBA is different. Having a wrong window there does not
805 	 * stop us from sending data and this condition is caught by
806 	 * other means (SWBA interrupt) */
807 
808 	if (ath5k_check_timer_win(nbtt, atim, 1, intval) &&
809 	    ath5k_check_timer_win(dma, nbtt, AR5K_TUNE_DMA_BEACON_RESP,
810 				  intval))
811 		return true; /* O.K. */
812 	return false;
813 }
814 
815 /**
816  * ath5k_hw_set_coverage_class() - Set IEEE 802.11 coverage class
817  * @ah: The &struct ath5k_hw
818  * @coverage_class: IEEE 802.11 coverage class number
819  *
820  * Sets IFS intervals and ACK/CTS timeouts for given coverage class.
821  */
822 void
ath5k_hw_set_coverage_class(struct ath5k_hw * ah,u8 coverage_class)823 ath5k_hw_set_coverage_class(struct ath5k_hw *ah, u8 coverage_class)
824 {
825 	/* As defined by IEEE 802.11-2007 17.3.8.6 */
826 	int slot_time = ath5k_hw_get_default_slottime(ah) + 3 * coverage_class;
827 	int ack_timeout = ath5k_hw_get_default_sifs(ah) + slot_time;
828 	int cts_timeout = ack_timeout;
829 
830 	ath5k_hw_set_ifs_intervals(ah, slot_time);
831 	ath5k_hw_set_ack_timeout(ah, ack_timeout);
832 	ath5k_hw_set_cts_timeout(ah, cts_timeout);
833 
834 	ah->ah_coverage_class = coverage_class;
835 }
836 
837 /***************************\
838 * Init/Start/Stop functions *
839 \***************************/
840 
841 /**
842  * ath5k_hw_start_rx_pcu() - Start RX engine
843  * @ah: The &struct ath5k_hw
844  *
845  * Starts RX engine on PCU so that hw can process RXed frames
846  * (ACK etc).
847  *
848  * NOTE: RX DMA should be already enabled using ath5k_hw_start_rx_dma
849  */
850 void
ath5k_hw_start_rx_pcu(struct ath5k_hw * ah)851 ath5k_hw_start_rx_pcu(struct ath5k_hw *ah)
852 {
853 	AR5K_REG_DISABLE_BITS(ah, AR5K_DIAG_SW, AR5K_DIAG_SW_DIS_RX);
854 }
855 
856 /**
857  * at5k_hw_stop_rx_pcu() - Stop RX engine
858  * @ah: The &struct ath5k_hw
859  *
860  * Stops RX engine on PCU
861  */
862 void
ath5k_hw_stop_rx_pcu(struct ath5k_hw * ah)863 ath5k_hw_stop_rx_pcu(struct ath5k_hw *ah)
864 {
865 	AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW, AR5K_DIAG_SW_DIS_RX);
866 }
867 
868 /**
869  * ath5k_hw_set_opmode() - Set PCU operating mode
870  * @ah: The &struct ath5k_hw
871  * @op_mode: One of enum nl80211_iftype
872  *
873  * Configure PCU for the various operating modes (AP/STA etc)
874  */
875 int
ath5k_hw_set_opmode(struct ath5k_hw * ah,enum nl80211_iftype op_mode)876 ath5k_hw_set_opmode(struct ath5k_hw *ah, enum nl80211_iftype op_mode)
877 {
878 	struct ath_common *common = ath5k_hw_common(ah);
879 	u32 pcu_reg, beacon_reg, low_id, high_id;
880 
881 	ATH5K_DBG(ah, ATH5K_DEBUG_MODE, "mode %d\n", op_mode);
882 
883 	/* Preserve rest settings */
884 	pcu_reg = ath5k_hw_reg_read(ah, AR5K_STA_ID1) & 0xffff0000;
885 	pcu_reg &= ~(AR5K_STA_ID1_ADHOC | AR5K_STA_ID1_AP
886 			| AR5K_STA_ID1_KEYSRCH_MODE
887 			| (ah->ah_version == AR5K_AR5210 ?
888 			(AR5K_STA_ID1_PWR_SV | AR5K_STA_ID1_NO_PSPOLL) : 0));
889 
890 	beacon_reg = 0;
891 
892 	switch (op_mode) {
893 	case NL80211_IFTYPE_ADHOC:
894 		pcu_reg |= AR5K_STA_ID1_ADHOC | AR5K_STA_ID1_KEYSRCH_MODE;
895 		beacon_reg |= AR5K_BCR_ADHOC;
896 		if (ah->ah_version == AR5K_AR5210)
897 			pcu_reg |= AR5K_STA_ID1_NO_PSPOLL;
898 		else
899 			AR5K_REG_ENABLE_BITS(ah, AR5K_CFG, AR5K_CFG_IBSS);
900 		break;
901 
902 	case NL80211_IFTYPE_AP:
903 	case NL80211_IFTYPE_MESH_POINT:
904 		pcu_reg |= AR5K_STA_ID1_AP | AR5K_STA_ID1_KEYSRCH_MODE;
905 		beacon_reg |= AR5K_BCR_AP;
906 		if (ah->ah_version == AR5K_AR5210)
907 			pcu_reg |= AR5K_STA_ID1_NO_PSPOLL;
908 		else
909 			AR5K_REG_DISABLE_BITS(ah, AR5K_CFG, AR5K_CFG_IBSS);
910 		break;
911 
912 	case NL80211_IFTYPE_STATION:
913 		pcu_reg |= AR5K_STA_ID1_KEYSRCH_MODE
914 			| (ah->ah_version == AR5K_AR5210 ?
915 				AR5K_STA_ID1_PWR_SV : 0);
916 		/* fall through */
917 	case NL80211_IFTYPE_MONITOR:
918 		pcu_reg |= AR5K_STA_ID1_KEYSRCH_MODE
919 			| (ah->ah_version == AR5K_AR5210 ?
920 				AR5K_STA_ID1_NO_PSPOLL : 0);
921 		break;
922 
923 	default:
924 		return -EINVAL;
925 	}
926 
927 	/*
928 	 * Set PCU registers
929 	 */
930 	low_id = get_unaligned_le32(common->macaddr);
931 	high_id = get_unaligned_le16(common->macaddr + 4);
932 	ath5k_hw_reg_write(ah, low_id, AR5K_STA_ID0);
933 	ath5k_hw_reg_write(ah, pcu_reg | high_id, AR5K_STA_ID1);
934 
935 	/*
936 	 * Set Beacon Control Register on 5210
937 	 */
938 	if (ah->ah_version == AR5K_AR5210)
939 		ath5k_hw_reg_write(ah, beacon_reg, AR5K_BCR);
940 
941 	return 0;
942 }
943 
944 /**
945  * ath5k_hw_pcu_init() - Initialize PCU
946  * @ah: The &struct ath5k_hw
947  * @op_mode: One of enum nl80211_iftype
948  * @mode: One of enum ath5k_driver_mode
949  *
950  * This function is used to initialize PCU by setting current
951  * operation mode and various other settings.
952  */
953 void
ath5k_hw_pcu_init(struct ath5k_hw * ah,enum nl80211_iftype op_mode)954 ath5k_hw_pcu_init(struct ath5k_hw *ah, enum nl80211_iftype op_mode)
955 {
956 	/* Set bssid and bssid mask */
957 	ath5k_hw_set_bssid(ah);
958 
959 	/* Set PCU config */
960 	ath5k_hw_set_opmode(ah, op_mode);
961 
962 	/* Write rate duration table only on AR5212 and if
963 	 * virtual interface has already been brought up
964 	 * XXX: rethink this after new mode changes to
965 	 * mac80211 are integrated */
966 	if (ah->ah_version == AR5K_AR5212 &&
967 		ah->nvifs)
968 		ath5k_hw_write_rate_duration(ah);
969 
970 	/* Set RSSI/BRSSI thresholds
971 	 *
972 	 * Note: If we decide to set this value
973 	 * dynamically, have in mind that when AR5K_RSSI_THR
974 	 * register is read it might return 0x40 if we haven't
975 	 * wrote anything to it plus BMISS RSSI threshold is zeroed.
976 	 * So doing a save/restore procedure here isn't the right
977 	 * choice. Instead store it on ath5k_hw */
978 	ath5k_hw_reg_write(ah, (AR5K_TUNE_RSSI_THRES |
979 				AR5K_TUNE_BMISS_THRES <<
980 				AR5K_RSSI_THR_BMISS_S),
981 				AR5K_RSSI_THR);
982 
983 	/* MIC QoS support */
984 	if (ah->ah_mac_srev >= AR5K_SREV_AR2413) {
985 		ath5k_hw_reg_write(ah, 0x000100aa, AR5K_MIC_QOS_CTL);
986 		ath5k_hw_reg_write(ah, 0x00003210, AR5K_MIC_QOS_SEL);
987 	}
988 
989 	/* QoS NOACK Policy */
990 	if (ah->ah_version == AR5K_AR5212) {
991 		ath5k_hw_reg_write(ah,
992 			AR5K_REG_SM(2, AR5K_QOS_NOACK_2BIT_VALUES) |
993 			AR5K_REG_SM(5, AR5K_QOS_NOACK_BIT_OFFSET)  |
994 			AR5K_REG_SM(0, AR5K_QOS_NOACK_BYTE_OFFSET),
995 			AR5K_QOS_NOACK);
996 	}
997 
998 	/* Restore slot time and ACK timeouts */
999 	if (ah->ah_coverage_class > 0)
1000 		ath5k_hw_set_coverage_class(ah, ah->ah_coverage_class);
1001 
1002 	/* Set ACK bitrate mode (see ack_rates_high) */
1003 	if (ah->ah_version == AR5K_AR5212) {
1004 		u32 val = AR5K_STA_ID1_BASE_RATE_11B | AR5K_STA_ID1_ACKCTS_6MB;
1005 		if (ah->ah_ack_bitrate_high)
1006 			AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1, val);
1007 		else
1008 			AR5K_REG_ENABLE_BITS(ah, AR5K_STA_ID1, val);
1009 	}
1010 	return;
1011 }
1012