1 // SPDX-License-Identifier: BSD-3-Clause-Clear
2 /*
3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
5 */
6
7 #include <crypto/hash.h>
8 #include "core.h"
9 #include "dp_tx.h"
10 #include "hal_tx.h"
11 #include "hif.h"
12 #include "debug.h"
13 #include "dp_rx.h"
14 #include "peer.h"
15 #include "dp_mon.h"
16
ath12k_dp_htt_htc_tx_complete(struct ath12k_base * ab,struct sk_buff * skb)17 static void ath12k_dp_htt_htc_tx_complete(struct ath12k_base *ab,
18 struct sk_buff *skb)
19 {
20 dev_kfree_skb_any(skb);
21 }
22
ath12k_dp_peer_cleanup(struct ath12k * ar,int vdev_id,const u8 * addr)23 void ath12k_dp_peer_cleanup(struct ath12k *ar, int vdev_id, const u8 *addr)
24 {
25 struct ath12k_base *ab = ar->ab;
26 struct ath12k_peer *peer;
27
28 /* TODO: Any other peer specific DP cleanup */
29
30 spin_lock_bh(&ab->base_lock);
31 peer = ath12k_peer_find(ab, vdev_id, addr);
32 if (!peer) {
33 ath12k_warn(ab, "failed to lookup peer %pM on vdev %d\n",
34 addr, vdev_id);
35 spin_unlock_bh(&ab->base_lock);
36 return;
37 }
38
39 ath12k_dp_rx_peer_tid_cleanup(ar, peer);
40 crypto_free_shash(peer->tfm_mmic);
41 spin_unlock_bh(&ab->base_lock);
42 }
43
ath12k_dp_peer_setup(struct ath12k * ar,int vdev_id,const u8 * addr)44 int ath12k_dp_peer_setup(struct ath12k *ar, int vdev_id, const u8 *addr)
45 {
46 struct ath12k_base *ab = ar->ab;
47 struct ath12k_peer *peer;
48 u32 reo_dest;
49 int ret = 0, tid;
50
51 /* NOTE: reo_dest ring id starts from 1 unlike mac_id which starts from 0 */
52 reo_dest = ar->dp.mac_id + 1;
53 ret = ath12k_wmi_set_peer_param(ar, addr, vdev_id,
54 WMI_PEER_SET_DEFAULT_ROUTING,
55 DP_RX_HASH_ENABLE | (reo_dest << 1));
56
57 if (ret) {
58 ath12k_warn(ab, "failed to set default routing %d peer :%pM vdev_id :%d\n",
59 ret, addr, vdev_id);
60 return ret;
61 }
62
63 for (tid = 0; tid <= IEEE80211_NUM_TIDS; tid++) {
64 ret = ath12k_dp_rx_peer_tid_setup(ar, addr, vdev_id, tid, 1, 0,
65 HAL_PN_TYPE_NONE);
66 if (ret) {
67 ath12k_warn(ab, "failed to setup rxd tid queue for tid %d: %d\n",
68 tid, ret);
69 goto peer_clean;
70 }
71 }
72
73 ret = ath12k_dp_rx_peer_frag_setup(ar, addr, vdev_id);
74 if (ret) {
75 ath12k_warn(ab, "failed to setup rx defrag context\n");
76 goto peer_clean;
77 }
78
79 /* TODO: Setup other peer specific resource used in data path */
80
81 return 0;
82
83 peer_clean:
84 spin_lock_bh(&ab->base_lock);
85
86 peer = ath12k_peer_find(ab, vdev_id, addr);
87 if (!peer) {
88 ath12k_warn(ab, "failed to find the peer to del rx tid\n");
89 spin_unlock_bh(&ab->base_lock);
90 return -ENOENT;
91 }
92
93 for (; tid >= 0; tid--)
94 ath12k_dp_rx_peer_tid_delete(ar, peer, tid);
95
96 spin_unlock_bh(&ab->base_lock);
97
98 return ret;
99 }
100
ath12k_dp_srng_cleanup(struct ath12k_base * ab,struct dp_srng * ring)101 void ath12k_dp_srng_cleanup(struct ath12k_base *ab, struct dp_srng *ring)
102 {
103 if (!ring->vaddr_unaligned)
104 return;
105
106 dma_free_coherent(ab->dev, ring->size, ring->vaddr_unaligned,
107 ring->paddr_unaligned);
108
109 ring->vaddr_unaligned = NULL;
110 }
111
ath12k_dp_srng_find_ring_in_mask(int ring_num,const u8 * grp_mask)112 static int ath12k_dp_srng_find_ring_in_mask(int ring_num, const u8 *grp_mask)
113 {
114 int ext_group_num;
115 u8 mask = 1 << ring_num;
116
117 for (ext_group_num = 0; ext_group_num < ATH12K_EXT_IRQ_GRP_NUM_MAX;
118 ext_group_num++) {
119 if (mask & grp_mask[ext_group_num])
120 return ext_group_num;
121 }
122
123 return -ENOENT;
124 }
125
ath12k_dp_srng_calculate_msi_group(struct ath12k_base * ab,enum hal_ring_type type,int ring_num)126 static int ath12k_dp_srng_calculate_msi_group(struct ath12k_base *ab,
127 enum hal_ring_type type, int ring_num)
128 {
129 const u8 *grp_mask;
130
131 switch (type) {
132 case HAL_WBM2SW_RELEASE:
133 if (ring_num == HAL_WBM2SW_REL_ERR_RING_NUM) {
134 grp_mask = &ab->hw_params->ring_mask->rx_wbm_rel[0];
135 ring_num = 0;
136 } else {
137 grp_mask = &ab->hw_params->ring_mask->tx[0];
138 }
139 break;
140 case HAL_REO_EXCEPTION:
141 grp_mask = &ab->hw_params->ring_mask->rx_err[0];
142 break;
143 case HAL_REO_DST:
144 grp_mask = &ab->hw_params->ring_mask->rx[0];
145 break;
146 case HAL_REO_STATUS:
147 grp_mask = &ab->hw_params->ring_mask->reo_status[0];
148 break;
149 case HAL_RXDMA_MONITOR_STATUS:
150 case HAL_RXDMA_MONITOR_DST:
151 grp_mask = &ab->hw_params->ring_mask->rx_mon_dest[0];
152 break;
153 case HAL_TX_MONITOR_DST:
154 grp_mask = &ab->hw_params->ring_mask->tx_mon_dest[0];
155 break;
156 case HAL_RXDMA_BUF:
157 grp_mask = &ab->hw_params->ring_mask->host2rxdma[0];
158 break;
159 case HAL_RXDMA_MONITOR_BUF:
160 case HAL_TCL_DATA:
161 case HAL_TCL_CMD:
162 case HAL_REO_CMD:
163 case HAL_SW2WBM_RELEASE:
164 case HAL_WBM_IDLE_LINK:
165 case HAL_TCL_STATUS:
166 case HAL_REO_REINJECT:
167 case HAL_CE_SRC:
168 case HAL_CE_DST:
169 case HAL_CE_DST_STATUS:
170 default:
171 return -ENOENT;
172 }
173
174 return ath12k_dp_srng_find_ring_in_mask(ring_num, grp_mask);
175 }
176
ath12k_dp_srng_msi_setup(struct ath12k_base * ab,struct hal_srng_params * ring_params,enum hal_ring_type type,int ring_num)177 static void ath12k_dp_srng_msi_setup(struct ath12k_base *ab,
178 struct hal_srng_params *ring_params,
179 enum hal_ring_type type, int ring_num)
180 {
181 int msi_group_number, msi_data_count;
182 u32 msi_data_start, msi_irq_start, addr_lo, addr_hi;
183 int ret;
184
185 ret = ath12k_hif_get_user_msi_vector(ab, "DP",
186 &msi_data_count, &msi_data_start,
187 &msi_irq_start);
188 if (ret)
189 return;
190
191 msi_group_number = ath12k_dp_srng_calculate_msi_group(ab, type,
192 ring_num);
193 if (msi_group_number < 0) {
194 ath12k_dbg(ab, ATH12K_DBG_PCI,
195 "ring not part of an ext_group; ring_type: %d,ring_num %d",
196 type, ring_num);
197 ring_params->msi_addr = 0;
198 ring_params->msi_data = 0;
199 return;
200 }
201
202 if (msi_group_number > msi_data_count) {
203 ath12k_dbg(ab, ATH12K_DBG_PCI,
204 "multiple msi_groups share one msi, msi_group_num %d",
205 msi_group_number);
206 }
207
208 ath12k_hif_get_msi_address(ab, &addr_lo, &addr_hi);
209
210 ring_params->msi_addr = addr_lo;
211 ring_params->msi_addr |= (dma_addr_t)(((uint64_t)addr_hi) << 32);
212 ring_params->msi_data = (msi_group_number % msi_data_count)
213 + msi_data_start;
214 ring_params->flags |= HAL_SRNG_FLAGS_MSI_INTR;
215 }
216
ath12k_dp_srng_setup(struct ath12k_base * ab,struct dp_srng * ring,enum hal_ring_type type,int ring_num,int mac_id,int num_entries)217 int ath12k_dp_srng_setup(struct ath12k_base *ab, struct dp_srng *ring,
218 enum hal_ring_type type, int ring_num,
219 int mac_id, int num_entries)
220 {
221 struct hal_srng_params params = { 0 };
222 int entry_sz = ath12k_hal_srng_get_entrysize(ab, type);
223 int max_entries = ath12k_hal_srng_get_max_entries(ab, type);
224 int ret;
225
226 if (max_entries < 0 || entry_sz < 0)
227 return -EINVAL;
228
229 if (num_entries > max_entries)
230 num_entries = max_entries;
231
232 ring->size = (num_entries * entry_sz) + HAL_RING_BASE_ALIGN - 1;
233 ring->vaddr_unaligned = dma_alloc_coherent(ab->dev, ring->size,
234 &ring->paddr_unaligned,
235 GFP_KERNEL);
236 if (!ring->vaddr_unaligned)
237 return -ENOMEM;
238
239 ring->vaddr = PTR_ALIGN(ring->vaddr_unaligned, HAL_RING_BASE_ALIGN);
240 ring->paddr = ring->paddr_unaligned + ((unsigned long)ring->vaddr -
241 (unsigned long)ring->vaddr_unaligned);
242
243 params.ring_base_vaddr = ring->vaddr;
244 params.ring_base_paddr = ring->paddr;
245 params.num_entries = num_entries;
246 ath12k_dp_srng_msi_setup(ab, ¶ms, type, ring_num + mac_id);
247
248 switch (type) {
249 case HAL_REO_DST:
250 params.intr_batch_cntr_thres_entries =
251 HAL_SRNG_INT_BATCH_THRESHOLD_RX;
252 params.intr_timer_thres_us = HAL_SRNG_INT_TIMER_THRESHOLD_RX;
253 break;
254 case HAL_RXDMA_BUF:
255 case HAL_RXDMA_MONITOR_BUF:
256 case HAL_RXDMA_MONITOR_STATUS:
257 params.low_threshold = num_entries >> 3;
258 params.flags |= HAL_SRNG_FLAGS_LOW_THRESH_INTR_EN;
259 params.intr_batch_cntr_thres_entries = 0;
260 params.intr_timer_thres_us = HAL_SRNG_INT_TIMER_THRESHOLD_RX;
261 break;
262 case HAL_TX_MONITOR_DST:
263 params.low_threshold = DP_TX_MONITOR_BUF_SIZE_MAX >> 3;
264 params.flags |= HAL_SRNG_FLAGS_LOW_THRESH_INTR_EN;
265 params.intr_batch_cntr_thres_entries = 0;
266 params.intr_timer_thres_us = HAL_SRNG_INT_TIMER_THRESHOLD_RX;
267 break;
268 case HAL_WBM2SW_RELEASE:
269 if (ab->hw_params->hw_ops->dp_srng_is_tx_comp_ring(ring_num)) {
270 params.intr_batch_cntr_thres_entries =
271 HAL_SRNG_INT_BATCH_THRESHOLD_TX;
272 params.intr_timer_thres_us =
273 HAL_SRNG_INT_TIMER_THRESHOLD_TX;
274 break;
275 }
276 /* follow through when ring_num != HAL_WBM2SW_REL_ERR_RING_NUM */
277 fallthrough;
278 case HAL_REO_EXCEPTION:
279 case HAL_REO_REINJECT:
280 case HAL_REO_CMD:
281 case HAL_REO_STATUS:
282 case HAL_TCL_DATA:
283 case HAL_TCL_CMD:
284 case HAL_TCL_STATUS:
285 case HAL_WBM_IDLE_LINK:
286 case HAL_SW2WBM_RELEASE:
287 case HAL_RXDMA_DST:
288 case HAL_RXDMA_MONITOR_DST:
289 case HAL_RXDMA_MONITOR_DESC:
290 params.intr_batch_cntr_thres_entries =
291 HAL_SRNG_INT_BATCH_THRESHOLD_OTHER;
292 params.intr_timer_thres_us = HAL_SRNG_INT_TIMER_THRESHOLD_OTHER;
293 break;
294 case HAL_RXDMA_DIR_BUF:
295 break;
296 default:
297 ath12k_warn(ab, "Not a valid ring type in dp :%d\n", type);
298 return -EINVAL;
299 }
300
301 ret = ath12k_hal_srng_setup(ab, type, ring_num, mac_id, ¶ms);
302 if (ret < 0) {
303 ath12k_warn(ab, "failed to setup srng: %d ring_id %d\n",
304 ret, ring_num);
305 return ret;
306 }
307
308 ring->ring_id = ret;
309
310 return 0;
311 }
312
313 static
ath12k_dp_tx_get_vdev_bank_config(struct ath12k_base * ab,struct ath12k_vif * arvif)314 u32 ath12k_dp_tx_get_vdev_bank_config(struct ath12k_base *ab, struct ath12k_vif *arvif)
315 {
316 u32 bank_config = 0;
317
318 /* Only valid for raw frames with HW crypto enabled.
319 * With SW crypto, mac80211 sets key per packet
320 */
321 if (arvif->tx_encap_type == HAL_TCL_ENCAP_TYPE_RAW &&
322 test_bit(ATH12K_FLAG_HW_CRYPTO_DISABLED, &ab->dev_flags))
323 bank_config |=
324 u32_encode_bits(ath12k_dp_tx_get_encrypt_type(arvif->key_cipher),
325 HAL_TX_BANK_CONFIG_ENCRYPT_TYPE);
326
327 bank_config |= u32_encode_bits(arvif->tx_encap_type,
328 HAL_TX_BANK_CONFIG_ENCAP_TYPE);
329 bank_config |= u32_encode_bits(0, HAL_TX_BANK_CONFIG_SRC_BUFFER_SWAP) |
330 u32_encode_bits(0, HAL_TX_BANK_CONFIG_LINK_META_SWAP) |
331 u32_encode_bits(0, HAL_TX_BANK_CONFIG_EPD);
332
333 /* only valid if idx_lookup_override is not set in tcl_data_cmd */
334 bank_config |= u32_encode_bits(0, HAL_TX_BANK_CONFIG_INDEX_LOOKUP_EN);
335
336 bank_config |= u32_encode_bits(arvif->hal_addr_search_flags & HAL_TX_ADDRX_EN,
337 HAL_TX_BANK_CONFIG_ADDRX_EN) |
338 u32_encode_bits(!!(arvif->hal_addr_search_flags &
339 HAL_TX_ADDRY_EN),
340 HAL_TX_BANK_CONFIG_ADDRY_EN);
341
342 bank_config |= u32_encode_bits(ieee80211_vif_is_mesh(arvif->vif) ? 3 : 0,
343 HAL_TX_BANK_CONFIG_MESH_EN) |
344 u32_encode_bits(arvif->vdev_id_check_en,
345 HAL_TX_BANK_CONFIG_VDEV_ID_CHECK_EN);
346
347 bank_config |= u32_encode_bits(0, HAL_TX_BANK_CONFIG_DSCP_TIP_MAP_ID);
348
349 return bank_config;
350 }
351
ath12k_dp_tx_get_bank_profile(struct ath12k_base * ab,struct ath12k_vif * arvif,struct ath12k_dp * dp)352 static int ath12k_dp_tx_get_bank_profile(struct ath12k_base *ab, struct ath12k_vif *arvif,
353 struct ath12k_dp *dp)
354 {
355 int bank_id = DP_INVALID_BANK_ID;
356 int i;
357 u32 bank_config;
358 bool configure_register = false;
359
360 /* convert vdev params into hal_tx_bank_config */
361 bank_config = ath12k_dp_tx_get_vdev_bank_config(ab, arvif);
362
363 spin_lock_bh(&dp->tx_bank_lock);
364 /* TODO: implement using idr kernel framework*/
365 for (i = 0; i < dp->num_bank_profiles; i++) {
366 if (dp->bank_profiles[i].is_configured &&
367 (dp->bank_profiles[i].bank_config ^ bank_config) == 0) {
368 bank_id = i;
369 goto inc_ref_and_return;
370 }
371 if (!dp->bank_profiles[i].is_configured ||
372 !dp->bank_profiles[i].num_users) {
373 bank_id = i;
374 goto configure_and_return;
375 }
376 }
377
378 if (bank_id == DP_INVALID_BANK_ID) {
379 spin_unlock_bh(&dp->tx_bank_lock);
380 ath12k_err(ab, "unable to find TX bank!");
381 return bank_id;
382 }
383
384 configure_and_return:
385 dp->bank_profiles[bank_id].is_configured = true;
386 dp->bank_profiles[bank_id].bank_config = bank_config;
387 configure_register = true;
388 inc_ref_and_return:
389 dp->bank_profiles[bank_id].num_users++;
390 spin_unlock_bh(&dp->tx_bank_lock);
391
392 if (configure_register)
393 ath12k_hal_tx_configure_bank_register(ab, bank_config, bank_id);
394
395 ath12k_dbg(ab, ATH12K_DBG_DP_HTT, "dp_htt tcl bank_id %d input 0x%x match 0x%x num_users %u",
396 bank_id, bank_config, dp->bank_profiles[bank_id].bank_config,
397 dp->bank_profiles[bank_id].num_users);
398
399 return bank_id;
400 }
401
ath12k_dp_tx_put_bank_profile(struct ath12k_dp * dp,u8 bank_id)402 void ath12k_dp_tx_put_bank_profile(struct ath12k_dp *dp, u8 bank_id)
403 {
404 spin_lock_bh(&dp->tx_bank_lock);
405 dp->bank_profiles[bank_id].num_users--;
406 spin_unlock_bh(&dp->tx_bank_lock);
407 }
408
ath12k_dp_deinit_bank_profiles(struct ath12k_base * ab)409 static void ath12k_dp_deinit_bank_profiles(struct ath12k_base *ab)
410 {
411 struct ath12k_dp *dp = &ab->dp;
412
413 kfree(dp->bank_profiles);
414 dp->bank_profiles = NULL;
415 }
416
ath12k_dp_init_bank_profiles(struct ath12k_base * ab)417 static int ath12k_dp_init_bank_profiles(struct ath12k_base *ab)
418 {
419 struct ath12k_dp *dp = &ab->dp;
420 u32 num_tcl_banks = ab->hw_params->num_tcl_banks;
421 int i;
422
423 dp->num_bank_profiles = num_tcl_banks;
424 dp->bank_profiles = kmalloc_array(num_tcl_banks,
425 sizeof(struct ath12k_dp_tx_bank_profile),
426 GFP_KERNEL);
427 if (!dp->bank_profiles)
428 return -ENOMEM;
429
430 spin_lock_init(&dp->tx_bank_lock);
431
432 for (i = 0; i < num_tcl_banks; i++) {
433 dp->bank_profiles[i].is_configured = false;
434 dp->bank_profiles[i].num_users = 0;
435 }
436
437 return 0;
438 }
439
ath12k_dp_srng_common_cleanup(struct ath12k_base * ab)440 static void ath12k_dp_srng_common_cleanup(struct ath12k_base *ab)
441 {
442 struct ath12k_dp *dp = &ab->dp;
443 int i;
444
445 ath12k_dp_srng_cleanup(ab, &dp->reo_status_ring);
446 ath12k_dp_srng_cleanup(ab, &dp->reo_cmd_ring);
447 ath12k_dp_srng_cleanup(ab, &dp->reo_except_ring);
448 ath12k_dp_srng_cleanup(ab, &dp->rx_rel_ring);
449 ath12k_dp_srng_cleanup(ab, &dp->reo_reinject_ring);
450 for (i = 0; i < ab->hw_params->max_tx_ring; i++) {
451 ath12k_dp_srng_cleanup(ab, &dp->tx_ring[i].tcl_comp_ring);
452 ath12k_dp_srng_cleanup(ab, &dp->tx_ring[i].tcl_data_ring);
453 }
454 ath12k_dp_srng_cleanup(ab, &dp->tcl_status_ring);
455 ath12k_dp_srng_cleanup(ab, &dp->tcl_cmd_ring);
456 ath12k_dp_srng_cleanup(ab, &dp->wbm_desc_rel_ring);
457 }
458
ath12k_dp_srng_common_setup(struct ath12k_base * ab)459 static int ath12k_dp_srng_common_setup(struct ath12k_base *ab)
460 {
461 struct ath12k_dp *dp = &ab->dp;
462 const struct ath12k_hal_tcl_to_wbm_rbm_map *map;
463 struct hal_srng *srng;
464 int i, ret, tx_comp_ring_num;
465 u32 ring_hash_map;
466
467 ret = ath12k_dp_srng_setup(ab, &dp->wbm_desc_rel_ring,
468 HAL_SW2WBM_RELEASE, 0, 0,
469 DP_WBM_RELEASE_RING_SIZE);
470 if (ret) {
471 ath12k_warn(ab, "failed to set up wbm2sw_release ring :%d\n",
472 ret);
473 goto err;
474 }
475
476 ret = ath12k_dp_srng_setup(ab, &dp->tcl_cmd_ring, HAL_TCL_CMD, 0, 0,
477 DP_TCL_CMD_RING_SIZE);
478 if (ret) {
479 ath12k_warn(ab, "failed to set up tcl_cmd ring :%d\n", ret);
480 goto err;
481 }
482
483 ret = ath12k_dp_srng_setup(ab, &dp->tcl_status_ring, HAL_TCL_STATUS,
484 0, 0, DP_TCL_STATUS_RING_SIZE);
485 if (ret) {
486 ath12k_warn(ab, "failed to set up tcl_status ring :%d\n", ret);
487 goto err;
488 }
489
490 for (i = 0; i < ab->hw_params->max_tx_ring; i++) {
491 map = ab->hw_params->hal_ops->tcl_to_wbm_rbm_map;
492 tx_comp_ring_num = map[i].wbm_ring_num;
493
494 ret = ath12k_dp_srng_setup(ab, &dp->tx_ring[i].tcl_data_ring,
495 HAL_TCL_DATA, i, 0,
496 DP_TCL_DATA_RING_SIZE);
497 if (ret) {
498 ath12k_warn(ab, "failed to set up tcl_data ring (%d) :%d\n",
499 i, ret);
500 goto err;
501 }
502
503 ret = ath12k_dp_srng_setup(ab, &dp->tx_ring[i].tcl_comp_ring,
504 HAL_WBM2SW_RELEASE, tx_comp_ring_num, 0,
505 DP_TX_COMP_RING_SIZE);
506 if (ret) {
507 ath12k_warn(ab, "failed to set up tcl_comp ring (%d) :%d\n",
508 tx_comp_ring_num, ret);
509 goto err;
510 }
511 }
512
513 ret = ath12k_dp_srng_setup(ab, &dp->reo_reinject_ring, HAL_REO_REINJECT,
514 0, 0, DP_REO_REINJECT_RING_SIZE);
515 if (ret) {
516 ath12k_warn(ab, "failed to set up reo_reinject ring :%d\n",
517 ret);
518 goto err;
519 }
520
521 ret = ath12k_dp_srng_setup(ab, &dp->rx_rel_ring, HAL_WBM2SW_RELEASE,
522 HAL_WBM2SW_REL_ERR_RING_NUM, 0,
523 DP_RX_RELEASE_RING_SIZE);
524 if (ret) {
525 ath12k_warn(ab, "failed to set up rx_rel ring :%d\n", ret);
526 goto err;
527 }
528
529 ret = ath12k_dp_srng_setup(ab, &dp->reo_except_ring, HAL_REO_EXCEPTION,
530 0, 0, DP_REO_EXCEPTION_RING_SIZE);
531 if (ret) {
532 ath12k_warn(ab, "failed to set up reo_exception ring :%d\n",
533 ret);
534 goto err;
535 }
536
537 ret = ath12k_dp_srng_setup(ab, &dp->reo_cmd_ring, HAL_REO_CMD,
538 0, 0, DP_REO_CMD_RING_SIZE);
539 if (ret) {
540 ath12k_warn(ab, "failed to set up reo_cmd ring :%d\n", ret);
541 goto err;
542 }
543
544 srng = &ab->hal.srng_list[dp->reo_cmd_ring.ring_id];
545 ath12k_hal_reo_init_cmd_ring(ab, srng);
546
547 ret = ath12k_dp_srng_setup(ab, &dp->reo_status_ring, HAL_REO_STATUS,
548 0, 0, DP_REO_STATUS_RING_SIZE);
549 if (ret) {
550 ath12k_warn(ab, "failed to set up reo_status ring :%d\n", ret);
551 goto err;
552 }
553
554 /* When hash based routing of rx packet is enabled, 32 entries to map
555 * the hash values to the ring will be configured. Each hash entry uses
556 * four bits to map to a particular ring. The ring mapping will be
557 * 0:TCL, 1:SW1, 2:SW2, 3:SW3, 4:SW4, 5:Release, 6:FW and 7:SW5
558 * 8:SW6, 9:SW7, 10:SW8, 11:Not used.
559 */
560 ring_hash_map = HAL_HASH_ROUTING_RING_SW1 |
561 HAL_HASH_ROUTING_RING_SW2 << 4 |
562 HAL_HASH_ROUTING_RING_SW3 << 8 |
563 HAL_HASH_ROUTING_RING_SW4 << 12 |
564 HAL_HASH_ROUTING_RING_SW1 << 16 |
565 HAL_HASH_ROUTING_RING_SW2 << 20 |
566 HAL_HASH_ROUTING_RING_SW3 << 24 |
567 HAL_HASH_ROUTING_RING_SW4 << 28;
568
569 ath12k_hal_reo_hw_setup(ab, ring_hash_map);
570
571 return 0;
572
573 err:
574 ath12k_dp_srng_common_cleanup(ab);
575
576 return ret;
577 }
578
ath12k_dp_scatter_idle_link_desc_cleanup(struct ath12k_base * ab)579 static void ath12k_dp_scatter_idle_link_desc_cleanup(struct ath12k_base *ab)
580 {
581 struct ath12k_dp *dp = &ab->dp;
582 struct hal_wbm_idle_scatter_list *slist = dp->scatter_list;
583 int i;
584
585 for (i = 0; i < DP_IDLE_SCATTER_BUFS_MAX; i++) {
586 if (!slist[i].vaddr)
587 continue;
588
589 dma_free_coherent(ab->dev, HAL_WBM_IDLE_SCATTER_BUF_SIZE_MAX,
590 slist[i].vaddr, slist[i].paddr);
591 slist[i].vaddr = NULL;
592 }
593 }
594
ath12k_dp_scatter_idle_link_desc_setup(struct ath12k_base * ab,int size,u32 n_link_desc_bank,u32 n_link_desc,u32 last_bank_sz)595 static int ath12k_dp_scatter_idle_link_desc_setup(struct ath12k_base *ab,
596 int size,
597 u32 n_link_desc_bank,
598 u32 n_link_desc,
599 u32 last_bank_sz)
600 {
601 struct ath12k_dp *dp = &ab->dp;
602 struct dp_link_desc_bank *link_desc_banks = dp->link_desc_banks;
603 struct hal_wbm_idle_scatter_list *slist = dp->scatter_list;
604 u32 n_entries_per_buf;
605 int num_scatter_buf, scatter_idx;
606 struct hal_wbm_link_desc *scatter_buf;
607 int align_bytes, n_entries;
608 dma_addr_t paddr;
609 int rem_entries;
610 int i;
611 int ret = 0;
612 u32 end_offset, cookie;
613
614 n_entries_per_buf = HAL_WBM_IDLE_SCATTER_BUF_SIZE /
615 ath12k_hal_srng_get_entrysize(ab, HAL_WBM_IDLE_LINK);
616 num_scatter_buf = DIV_ROUND_UP(size, HAL_WBM_IDLE_SCATTER_BUF_SIZE);
617
618 if (num_scatter_buf > DP_IDLE_SCATTER_BUFS_MAX)
619 return -EINVAL;
620
621 for (i = 0; i < num_scatter_buf; i++) {
622 slist[i].vaddr = dma_alloc_coherent(ab->dev,
623 HAL_WBM_IDLE_SCATTER_BUF_SIZE_MAX,
624 &slist[i].paddr, GFP_KERNEL);
625 if (!slist[i].vaddr) {
626 ret = -ENOMEM;
627 goto err;
628 }
629 }
630
631 scatter_idx = 0;
632 scatter_buf = slist[scatter_idx].vaddr;
633 rem_entries = n_entries_per_buf;
634
635 for (i = 0; i < n_link_desc_bank; i++) {
636 align_bytes = link_desc_banks[i].vaddr -
637 link_desc_banks[i].vaddr_unaligned;
638 n_entries = (DP_LINK_DESC_ALLOC_SIZE_THRESH - align_bytes) /
639 HAL_LINK_DESC_SIZE;
640 paddr = link_desc_banks[i].paddr;
641 while (n_entries) {
642 cookie = DP_LINK_DESC_COOKIE_SET(n_entries, i);
643 ath12k_hal_set_link_desc_addr(scatter_buf, cookie, paddr);
644 n_entries--;
645 paddr += HAL_LINK_DESC_SIZE;
646 if (rem_entries) {
647 rem_entries--;
648 scatter_buf++;
649 continue;
650 }
651
652 rem_entries = n_entries_per_buf;
653 scatter_idx++;
654 scatter_buf = slist[scatter_idx].vaddr;
655 }
656 }
657
658 end_offset = (scatter_buf - slist[scatter_idx].vaddr) *
659 sizeof(struct hal_wbm_link_desc);
660 ath12k_hal_setup_link_idle_list(ab, slist, num_scatter_buf,
661 n_link_desc, end_offset);
662
663 return 0;
664
665 err:
666 ath12k_dp_scatter_idle_link_desc_cleanup(ab);
667
668 return ret;
669 }
670
671 static void
ath12k_dp_link_desc_bank_free(struct ath12k_base * ab,struct dp_link_desc_bank * link_desc_banks)672 ath12k_dp_link_desc_bank_free(struct ath12k_base *ab,
673 struct dp_link_desc_bank *link_desc_banks)
674 {
675 int i;
676
677 for (i = 0; i < DP_LINK_DESC_BANKS_MAX; i++) {
678 if (link_desc_banks[i].vaddr_unaligned) {
679 dma_free_coherent(ab->dev,
680 link_desc_banks[i].size,
681 link_desc_banks[i].vaddr_unaligned,
682 link_desc_banks[i].paddr_unaligned);
683 link_desc_banks[i].vaddr_unaligned = NULL;
684 }
685 }
686 }
687
ath12k_dp_link_desc_bank_alloc(struct ath12k_base * ab,struct dp_link_desc_bank * desc_bank,int n_link_desc_bank,int last_bank_sz)688 static int ath12k_dp_link_desc_bank_alloc(struct ath12k_base *ab,
689 struct dp_link_desc_bank *desc_bank,
690 int n_link_desc_bank,
691 int last_bank_sz)
692 {
693 struct ath12k_dp *dp = &ab->dp;
694 int i;
695 int ret = 0;
696 int desc_sz = DP_LINK_DESC_ALLOC_SIZE_THRESH;
697
698 for (i = 0; i < n_link_desc_bank; i++) {
699 if (i == (n_link_desc_bank - 1) && last_bank_sz)
700 desc_sz = last_bank_sz;
701
702 desc_bank[i].vaddr_unaligned =
703 dma_alloc_coherent(ab->dev, desc_sz,
704 &desc_bank[i].paddr_unaligned,
705 GFP_KERNEL);
706 if (!desc_bank[i].vaddr_unaligned) {
707 ret = -ENOMEM;
708 goto err;
709 }
710
711 desc_bank[i].vaddr = PTR_ALIGN(desc_bank[i].vaddr_unaligned,
712 HAL_LINK_DESC_ALIGN);
713 desc_bank[i].paddr = desc_bank[i].paddr_unaligned +
714 ((unsigned long)desc_bank[i].vaddr -
715 (unsigned long)desc_bank[i].vaddr_unaligned);
716 desc_bank[i].size = desc_sz;
717 }
718
719 return 0;
720
721 err:
722 ath12k_dp_link_desc_bank_free(ab, dp->link_desc_banks);
723
724 return ret;
725 }
726
ath12k_dp_link_desc_cleanup(struct ath12k_base * ab,struct dp_link_desc_bank * desc_bank,u32 ring_type,struct dp_srng * ring)727 void ath12k_dp_link_desc_cleanup(struct ath12k_base *ab,
728 struct dp_link_desc_bank *desc_bank,
729 u32 ring_type, struct dp_srng *ring)
730 {
731 ath12k_dp_link_desc_bank_free(ab, desc_bank);
732
733 if (ring_type != HAL_RXDMA_MONITOR_DESC) {
734 ath12k_dp_srng_cleanup(ab, ring);
735 ath12k_dp_scatter_idle_link_desc_cleanup(ab);
736 }
737 }
738
ath12k_wbm_idle_ring_setup(struct ath12k_base * ab,u32 * n_link_desc)739 static int ath12k_wbm_idle_ring_setup(struct ath12k_base *ab, u32 *n_link_desc)
740 {
741 struct ath12k_dp *dp = &ab->dp;
742 u32 n_mpdu_link_desc, n_mpdu_queue_desc;
743 u32 n_tx_msdu_link_desc, n_rx_msdu_link_desc;
744 int ret = 0;
745
746 n_mpdu_link_desc = (DP_NUM_TIDS_MAX * DP_AVG_MPDUS_PER_TID_MAX) /
747 HAL_NUM_MPDUS_PER_LINK_DESC;
748
749 n_mpdu_queue_desc = n_mpdu_link_desc /
750 HAL_NUM_MPDU_LINKS_PER_QUEUE_DESC;
751
752 n_tx_msdu_link_desc = (DP_NUM_TIDS_MAX * DP_AVG_FLOWS_PER_TID *
753 DP_AVG_MSDUS_PER_FLOW) /
754 HAL_NUM_TX_MSDUS_PER_LINK_DESC;
755
756 n_rx_msdu_link_desc = (DP_NUM_TIDS_MAX * DP_AVG_MPDUS_PER_TID_MAX *
757 DP_AVG_MSDUS_PER_MPDU) /
758 HAL_NUM_RX_MSDUS_PER_LINK_DESC;
759
760 *n_link_desc = n_mpdu_link_desc + n_mpdu_queue_desc +
761 n_tx_msdu_link_desc + n_rx_msdu_link_desc;
762
763 if (*n_link_desc & (*n_link_desc - 1))
764 *n_link_desc = 1 << fls(*n_link_desc);
765
766 ret = ath12k_dp_srng_setup(ab, &dp->wbm_idle_ring,
767 HAL_WBM_IDLE_LINK, 0, 0, *n_link_desc);
768 if (ret) {
769 ath12k_warn(ab, "failed to setup wbm_idle_ring: %d\n", ret);
770 return ret;
771 }
772 return ret;
773 }
774
ath12k_dp_link_desc_setup(struct ath12k_base * ab,struct dp_link_desc_bank * link_desc_banks,u32 ring_type,struct hal_srng * srng,u32 n_link_desc)775 int ath12k_dp_link_desc_setup(struct ath12k_base *ab,
776 struct dp_link_desc_bank *link_desc_banks,
777 u32 ring_type, struct hal_srng *srng,
778 u32 n_link_desc)
779 {
780 u32 tot_mem_sz;
781 u32 n_link_desc_bank, last_bank_sz;
782 u32 entry_sz, align_bytes, n_entries;
783 struct hal_wbm_link_desc *desc;
784 u32 paddr;
785 int i, ret;
786 u32 cookie;
787
788 tot_mem_sz = n_link_desc * HAL_LINK_DESC_SIZE;
789 tot_mem_sz += HAL_LINK_DESC_ALIGN;
790
791 if (tot_mem_sz <= DP_LINK_DESC_ALLOC_SIZE_THRESH) {
792 n_link_desc_bank = 1;
793 last_bank_sz = tot_mem_sz;
794 } else {
795 n_link_desc_bank = tot_mem_sz /
796 (DP_LINK_DESC_ALLOC_SIZE_THRESH -
797 HAL_LINK_DESC_ALIGN);
798 last_bank_sz = tot_mem_sz %
799 (DP_LINK_DESC_ALLOC_SIZE_THRESH -
800 HAL_LINK_DESC_ALIGN);
801
802 if (last_bank_sz)
803 n_link_desc_bank += 1;
804 }
805
806 if (n_link_desc_bank > DP_LINK_DESC_BANKS_MAX)
807 return -EINVAL;
808
809 ret = ath12k_dp_link_desc_bank_alloc(ab, link_desc_banks,
810 n_link_desc_bank, last_bank_sz);
811 if (ret)
812 return ret;
813
814 /* Setup link desc idle list for HW internal usage */
815 entry_sz = ath12k_hal_srng_get_entrysize(ab, ring_type);
816 tot_mem_sz = entry_sz * n_link_desc;
817
818 /* Setup scatter desc list when the total memory requirement is more */
819 if (tot_mem_sz > DP_LINK_DESC_ALLOC_SIZE_THRESH &&
820 ring_type != HAL_RXDMA_MONITOR_DESC) {
821 ret = ath12k_dp_scatter_idle_link_desc_setup(ab, tot_mem_sz,
822 n_link_desc_bank,
823 n_link_desc,
824 last_bank_sz);
825 if (ret) {
826 ath12k_warn(ab, "failed to setup scatting idle list descriptor :%d\n",
827 ret);
828 goto fail_desc_bank_free;
829 }
830
831 return 0;
832 }
833
834 spin_lock_bh(&srng->lock);
835
836 ath12k_hal_srng_access_begin(ab, srng);
837
838 for (i = 0; i < n_link_desc_bank; i++) {
839 align_bytes = link_desc_banks[i].vaddr -
840 link_desc_banks[i].vaddr_unaligned;
841 n_entries = (link_desc_banks[i].size - align_bytes) /
842 HAL_LINK_DESC_SIZE;
843 paddr = link_desc_banks[i].paddr;
844 while (n_entries &&
845 (desc = ath12k_hal_srng_src_get_next_entry(ab, srng))) {
846 cookie = DP_LINK_DESC_COOKIE_SET(n_entries, i);
847 ath12k_hal_set_link_desc_addr(desc,
848 cookie, paddr);
849 n_entries--;
850 paddr += HAL_LINK_DESC_SIZE;
851 }
852 }
853
854 ath12k_hal_srng_access_end(ab, srng);
855
856 spin_unlock_bh(&srng->lock);
857
858 return 0;
859
860 fail_desc_bank_free:
861 ath12k_dp_link_desc_bank_free(ab, link_desc_banks);
862
863 return ret;
864 }
865
ath12k_dp_service_srng(struct ath12k_base * ab,struct ath12k_ext_irq_grp * irq_grp,int budget)866 int ath12k_dp_service_srng(struct ath12k_base *ab,
867 struct ath12k_ext_irq_grp *irq_grp,
868 int budget)
869 {
870 struct napi_struct *napi = &irq_grp->napi;
871 int grp_id = irq_grp->grp_id;
872 int work_done = 0;
873 int i = 0, j;
874 int tot_work_done = 0;
875 enum dp_monitor_mode monitor_mode;
876 u8 ring_mask;
877
878 while (i < ab->hw_params->max_tx_ring) {
879 if (ab->hw_params->ring_mask->tx[grp_id] &
880 BIT(ab->hw_params->hal_ops->tcl_to_wbm_rbm_map[i].wbm_ring_num))
881 ath12k_dp_tx_completion_handler(ab, i);
882 i++;
883 }
884
885 if (ab->hw_params->ring_mask->rx_err[grp_id]) {
886 work_done = ath12k_dp_rx_process_err(ab, napi, budget);
887 budget -= work_done;
888 tot_work_done += work_done;
889 if (budget <= 0)
890 goto done;
891 }
892
893 if (ab->hw_params->ring_mask->rx_wbm_rel[grp_id]) {
894 work_done = ath12k_dp_rx_process_wbm_err(ab,
895 napi,
896 budget);
897 budget -= work_done;
898 tot_work_done += work_done;
899
900 if (budget <= 0)
901 goto done;
902 }
903
904 if (ab->hw_params->ring_mask->rx[grp_id]) {
905 i = fls(ab->hw_params->ring_mask->rx[grp_id]) - 1;
906 work_done = ath12k_dp_rx_process(ab, i, napi,
907 budget);
908 budget -= work_done;
909 tot_work_done += work_done;
910 if (budget <= 0)
911 goto done;
912 }
913
914 if (ab->hw_params->ring_mask->rx_mon_dest[grp_id]) {
915 monitor_mode = ATH12K_DP_RX_MONITOR_MODE;
916 ring_mask = ab->hw_params->ring_mask->rx_mon_dest[grp_id];
917 for (i = 0; i < ab->num_radios; i++) {
918 for (j = 0; j < ab->hw_params->num_rxmda_per_pdev; j++) {
919 int id = i * ab->hw_params->num_rxmda_per_pdev + j;
920
921 if (ring_mask & BIT(id)) {
922 work_done =
923 ath12k_dp_mon_process_ring(ab, id, napi, budget,
924 monitor_mode);
925 budget -= work_done;
926 tot_work_done += work_done;
927
928 if (budget <= 0)
929 goto done;
930 }
931 }
932 }
933 }
934
935 if (ab->hw_params->ring_mask->tx_mon_dest[grp_id]) {
936 monitor_mode = ATH12K_DP_TX_MONITOR_MODE;
937 ring_mask = ab->hw_params->ring_mask->tx_mon_dest[grp_id];
938 for (i = 0; i < ab->num_radios; i++) {
939 for (j = 0; j < ab->hw_params->num_rxmda_per_pdev; j++) {
940 int id = i * ab->hw_params->num_rxmda_per_pdev + j;
941
942 if (ring_mask & BIT(id)) {
943 work_done =
944 ath12k_dp_mon_process_ring(ab, id, napi, budget,
945 monitor_mode);
946 budget -= work_done;
947 tot_work_done += work_done;
948
949 if (budget <= 0)
950 goto done;
951 }
952 }
953 }
954 }
955
956 if (ab->hw_params->ring_mask->reo_status[grp_id])
957 ath12k_dp_rx_process_reo_status(ab);
958
959 if (ab->hw_params->ring_mask->host2rxdma[grp_id]) {
960 struct ath12k_dp *dp = &ab->dp;
961 struct dp_rxdma_ring *rx_ring = &dp->rx_refill_buf_ring;
962
963 ath12k_dp_rx_bufs_replenish(ab, 0, rx_ring, 0,
964 ab->hw_params->hal_params->rx_buf_rbm,
965 true);
966 }
967
968 /* TODO: Implement handler for other interrupts */
969
970 done:
971 return tot_work_done;
972 }
973
ath12k_dp_pdev_free(struct ath12k_base * ab)974 void ath12k_dp_pdev_free(struct ath12k_base *ab)
975 {
976 int i;
977
978 del_timer_sync(&ab->mon_reap_timer);
979
980 for (i = 0; i < ab->num_radios; i++)
981 ath12k_dp_rx_pdev_free(ab, i);
982 }
983
ath12k_dp_pdev_pre_alloc(struct ath12k_base * ab)984 void ath12k_dp_pdev_pre_alloc(struct ath12k_base *ab)
985 {
986 struct ath12k *ar;
987 struct ath12k_pdev_dp *dp;
988 int i;
989
990 for (i = 0; i < ab->num_radios; i++) {
991 ar = ab->pdevs[i].ar;
992 dp = &ar->dp;
993 dp->mac_id = i;
994 atomic_set(&dp->num_tx_pending, 0);
995 init_waitqueue_head(&dp->tx_empty_waitq);
996
997 /* TODO: Add any RXDMA setup required per pdev */
998 }
999 }
1000
ath12k_dp_service_mon_ring(struct timer_list * t)1001 static void ath12k_dp_service_mon_ring(struct timer_list *t)
1002 {
1003 struct ath12k_base *ab = from_timer(ab, t, mon_reap_timer);
1004 int i;
1005
1006 for (i = 0; i < ab->hw_params->num_rxmda_per_pdev; i++)
1007 ath12k_dp_mon_process_ring(ab, i, NULL, DP_MON_SERVICE_BUDGET,
1008 ATH12K_DP_RX_MONITOR_MODE);
1009
1010 mod_timer(&ab->mon_reap_timer, jiffies +
1011 msecs_to_jiffies(ATH12K_MON_TIMER_INTERVAL));
1012 }
1013
ath12k_dp_mon_reap_timer_init(struct ath12k_base * ab)1014 static void ath12k_dp_mon_reap_timer_init(struct ath12k_base *ab)
1015 {
1016 if (ab->hw_params->rxdma1_enable)
1017 return;
1018
1019 timer_setup(&ab->mon_reap_timer, ath12k_dp_service_mon_ring, 0);
1020 }
1021
ath12k_dp_pdev_alloc(struct ath12k_base * ab)1022 int ath12k_dp_pdev_alloc(struct ath12k_base *ab)
1023 {
1024 struct ath12k *ar;
1025 int ret;
1026 int i;
1027
1028 ret = ath12k_dp_rx_htt_setup(ab);
1029 if (ret)
1030 goto out;
1031
1032 ath12k_dp_mon_reap_timer_init(ab);
1033
1034 /* TODO: Per-pdev rx ring unlike tx ring which is mapped to different AC's */
1035 for (i = 0; i < ab->num_radios; i++) {
1036 ar = ab->pdevs[i].ar;
1037 ret = ath12k_dp_rx_pdev_alloc(ab, i);
1038 if (ret) {
1039 ath12k_warn(ab, "failed to allocate pdev rx for pdev_id :%d\n",
1040 i);
1041 goto err;
1042 }
1043 ret = ath12k_dp_rx_pdev_mon_attach(ar);
1044 if (ret) {
1045 ath12k_warn(ab, "failed to initialize mon pdev %d\n", i);
1046 goto err;
1047 }
1048 }
1049
1050 return 0;
1051 err:
1052 ath12k_dp_pdev_free(ab);
1053 out:
1054 return ret;
1055 }
1056
ath12k_dp_htt_connect(struct ath12k_dp * dp)1057 int ath12k_dp_htt_connect(struct ath12k_dp *dp)
1058 {
1059 struct ath12k_htc_svc_conn_req conn_req = {0};
1060 struct ath12k_htc_svc_conn_resp conn_resp = {0};
1061 int status;
1062
1063 conn_req.ep_ops.ep_tx_complete = ath12k_dp_htt_htc_tx_complete;
1064 conn_req.ep_ops.ep_rx_complete = ath12k_dp_htt_htc_t2h_msg_handler;
1065
1066 /* connect to control service */
1067 conn_req.service_id = ATH12K_HTC_SVC_ID_HTT_DATA_MSG;
1068
1069 status = ath12k_htc_connect_service(&dp->ab->htc, &conn_req,
1070 &conn_resp);
1071
1072 if (status)
1073 return status;
1074
1075 dp->eid = conn_resp.eid;
1076
1077 return 0;
1078 }
1079
ath12k_dp_update_vdev_search(struct ath12k_vif * arvif)1080 static void ath12k_dp_update_vdev_search(struct ath12k_vif *arvif)
1081 {
1082 switch (arvif->vdev_type) {
1083 case WMI_VDEV_TYPE_STA:
1084 /* TODO: Verify the search type and flags since ast hash
1085 * is not part of peer mapv3
1086 */
1087 arvif->hal_addr_search_flags = HAL_TX_ADDRY_EN;
1088 arvif->search_type = HAL_TX_ADDR_SEARCH_DEFAULT;
1089 break;
1090 case WMI_VDEV_TYPE_AP:
1091 case WMI_VDEV_TYPE_IBSS:
1092 arvif->hal_addr_search_flags = HAL_TX_ADDRX_EN;
1093 arvif->search_type = HAL_TX_ADDR_SEARCH_DEFAULT;
1094 break;
1095 case WMI_VDEV_TYPE_MONITOR:
1096 default:
1097 return;
1098 }
1099 }
1100
ath12k_dp_vdev_tx_attach(struct ath12k * ar,struct ath12k_vif * arvif)1101 void ath12k_dp_vdev_tx_attach(struct ath12k *ar, struct ath12k_vif *arvif)
1102 {
1103 struct ath12k_base *ab = ar->ab;
1104
1105 arvif->tcl_metadata |= u32_encode_bits(1, HTT_TCL_META_DATA_TYPE) |
1106 u32_encode_bits(arvif->vdev_id,
1107 HTT_TCL_META_DATA_VDEV_ID) |
1108 u32_encode_bits(ar->pdev->pdev_id,
1109 HTT_TCL_META_DATA_PDEV_ID);
1110
1111 /* set HTT extension valid bit to 0 by default */
1112 arvif->tcl_metadata &= ~HTT_TCL_META_DATA_VALID_HTT;
1113
1114 ath12k_dp_update_vdev_search(arvif);
1115 arvif->vdev_id_check_en = true;
1116 arvif->bank_id = ath12k_dp_tx_get_bank_profile(ab, arvif, &ab->dp);
1117
1118 /* TODO: error path for bank id failure */
1119 if (arvif->bank_id == DP_INVALID_BANK_ID) {
1120 ath12k_err(ar->ab, "Failed to initialize DP TX Banks");
1121 return;
1122 }
1123 }
1124
ath12k_dp_cc_cleanup(struct ath12k_base * ab)1125 static void ath12k_dp_cc_cleanup(struct ath12k_base *ab)
1126 {
1127 struct ath12k_rx_desc_info *desc_info, *tmp;
1128 struct ath12k_tx_desc_info *tx_desc_info, *tmp1;
1129 struct ath12k_dp *dp = &ab->dp;
1130 struct sk_buff *skb;
1131 int i;
1132 u32 pool_id, tx_spt_page;
1133
1134 if (!dp->spt_info)
1135 return;
1136
1137 /* RX Descriptor cleanup */
1138 spin_lock_bh(&dp->rx_desc_lock);
1139
1140 list_for_each_entry_safe(desc_info, tmp, &dp->rx_desc_used_list, list) {
1141 list_del(&desc_info->list);
1142 skb = desc_info->skb;
1143
1144 if (!skb)
1145 continue;
1146
1147 dma_unmap_single(ab->dev, ATH12K_SKB_RXCB(skb)->paddr,
1148 skb->len + skb_tailroom(skb), DMA_FROM_DEVICE);
1149 dev_kfree_skb_any(skb);
1150 }
1151
1152 for (i = 0; i < ATH12K_NUM_RX_SPT_PAGES; i++) {
1153 if (!dp->spt_info->rxbaddr[i])
1154 continue;
1155
1156 kfree(dp->spt_info->rxbaddr[i]);
1157 dp->spt_info->rxbaddr[i] = NULL;
1158 }
1159
1160 spin_unlock_bh(&dp->rx_desc_lock);
1161
1162 /* TX Descriptor cleanup */
1163 for (i = 0; i < ATH12K_HW_MAX_QUEUES; i++) {
1164 spin_lock_bh(&dp->tx_desc_lock[i]);
1165
1166 list_for_each_entry_safe(tx_desc_info, tmp1, &dp->tx_desc_used_list[i],
1167 list) {
1168 list_del(&tx_desc_info->list);
1169 skb = tx_desc_info->skb;
1170
1171 if (!skb)
1172 continue;
1173
1174 dma_unmap_single(ab->dev, ATH12K_SKB_CB(skb)->paddr,
1175 skb->len, DMA_TO_DEVICE);
1176 dev_kfree_skb_any(skb);
1177 }
1178
1179 spin_unlock_bh(&dp->tx_desc_lock[i]);
1180 }
1181
1182 for (pool_id = 0; pool_id < ATH12K_HW_MAX_QUEUES; pool_id++) {
1183 spin_lock_bh(&dp->tx_desc_lock[pool_id]);
1184
1185 for (i = 0; i < ATH12K_TX_SPT_PAGES_PER_POOL; i++) {
1186 tx_spt_page = i + pool_id * ATH12K_TX_SPT_PAGES_PER_POOL;
1187 if (!dp->spt_info->txbaddr[tx_spt_page])
1188 continue;
1189
1190 kfree(dp->spt_info->txbaddr[tx_spt_page]);
1191 dp->spt_info->txbaddr[tx_spt_page] = NULL;
1192 }
1193
1194 spin_unlock_bh(&dp->tx_desc_lock[pool_id]);
1195 }
1196
1197 /* unmap SPT pages */
1198 for (i = 0; i < dp->num_spt_pages; i++) {
1199 if (!dp->spt_info[i].vaddr)
1200 continue;
1201
1202 dma_free_coherent(ab->dev, ATH12K_PAGE_SIZE,
1203 dp->spt_info[i].vaddr, dp->spt_info[i].paddr);
1204 dp->spt_info[i].vaddr = NULL;
1205 }
1206
1207 kfree(dp->spt_info);
1208 }
1209
ath12k_dp_reoq_lut_cleanup(struct ath12k_base * ab)1210 static void ath12k_dp_reoq_lut_cleanup(struct ath12k_base *ab)
1211 {
1212 struct ath12k_dp *dp = &ab->dp;
1213
1214 if (!ab->hw_params->reoq_lut_support)
1215 return;
1216
1217 if (!dp->reoq_lut.vaddr)
1218 return;
1219
1220 dma_free_coherent(ab->dev, DP_REOQ_LUT_SIZE,
1221 dp->reoq_lut.vaddr, dp->reoq_lut.paddr);
1222 dp->reoq_lut.vaddr = NULL;
1223
1224 ath12k_hif_write32(ab,
1225 HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO1_QDESC_LUT_BASE0(ab), 0);
1226 }
1227
ath12k_dp_free(struct ath12k_base * ab)1228 void ath12k_dp_free(struct ath12k_base *ab)
1229 {
1230 struct ath12k_dp *dp = &ab->dp;
1231 int i;
1232
1233 ath12k_dp_link_desc_cleanup(ab, dp->link_desc_banks,
1234 HAL_WBM_IDLE_LINK, &dp->wbm_idle_ring);
1235
1236 ath12k_dp_cc_cleanup(ab);
1237 ath12k_dp_reoq_lut_cleanup(ab);
1238 ath12k_dp_deinit_bank_profiles(ab);
1239 ath12k_dp_srng_common_cleanup(ab);
1240
1241 ath12k_dp_rx_reo_cmd_list_cleanup(ab);
1242
1243 for (i = 0; i < ab->hw_params->max_tx_ring; i++)
1244 kfree(dp->tx_ring[i].tx_status);
1245
1246 ath12k_dp_rx_free(ab);
1247 /* Deinit any SOC level resource */
1248 }
1249
ath12k_dp_cc_config(struct ath12k_base * ab)1250 void ath12k_dp_cc_config(struct ath12k_base *ab)
1251 {
1252 u32 cmem_base = ab->qmi.dev_mem[ATH12K_QMI_DEVMEM_CMEM_INDEX].start;
1253 u32 reo_base = HAL_SEQ_WCSS_UMAC_REO_REG;
1254 u32 wbm_base = HAL_SEQ_WCSS_UMAC_WBM_REG;
1255 u32 val = 0;
1256
1257 ath12k_hif_write32(ab, reo_base + HAL_REO1_SW_COOKIE_CFG0(ab), cmem_base);
1258
1259 val |= u32_encode_bits(ATH12K_CMEM_ADDR_MSB,
1260 HAL_REO1_SW_COOKIE_CFG_CMEM_BASE_ADDR_MSB) |
1261 u32_encode_bits(ATH12K_CC_PPT_MSB,
1262 HAL_REO1_SW_COOKIE_CFG_COOKIE_PPT_MSB) |
1263 u32_encode_bits(ATH12K_CC_SPT_MSB,
1264 HAL_REO1_SW_COOKIE_CFG_COOKIE_SPT_MSB) |
1265 u32_encode_bits(1, HAL_REO1_SW_COOKIE_CFG_ALIGN) |
1266 u32_encode_bits(1, HAL_REO1_SW_COOKIE_CFG_ENABLE) |
1267 u32_encode_bits(1, HAL_REO1_SW_COOKIE_CFG_GLOBAL_ENABLE);
1268
1269 ath12k_hif_write32(ab, reo_base + HAL_REO1_SW_COOKIE_CFG1(ab), val);
1270
1271 /* Enable HW CC for WBM */
1272 ath12k_hif_write32(ab, wbm_base + HAL_WBM_SW_COOKIE_CFG0, cmem_base);
1273
1274 val = u32_encode_bits(ATH12K_CMEM_ADDR_MSB,
1275 HAL_WBM_SW_COOKIE_CFG_CMEM_BASE_ADDR_MSB) |
1276 u32_encode_bits(ATH12K_CC_PPT_MSB,
1277 HAL_WBM_SW_COOKIE_CFG_COOKIE_PPT_MSB) |
1278 u32_encode_bits(ATH12K_CC_SPT_MSB,
1279 HAL_WBM_SW_COOKIE_CFG_COOKIE_SPT_MSB) |
1280 u32_encode_bits(1, HAL_WBM_SW_COOKIE_CFG_ALIGN);
1281
1282 ath12k_hif_write32(ab, wbm_base + HAL_WBM_SW_COOKIE_CFG1, val);
1283
1284 /* Enable conversion complete indication */
1285 val = ath12k_hif_read32(ab, wbm_base + HAL_WBM_SW_COOKIE_CFG2);
1286 val |= u32_encode_bits(1, HAL_WBM_SW_COOKIE_CFG_RELEASE_PATH_EN) |
1287 u32_encode_bits(1, HAL_WBM_SW_COOKIE_CFG_ERR_PATH_EN) |
1288 u32_encode_bits(1, HAL_WBM_SW_COOKIE_CFG_CONV_IND_EN);
1289
1290 ath12k_hif_write32(ab, wbm_base + HAL_WBM_SW_COOKIE_CFG2, val);
1291
1292 /* Enable Cookie conversion for WBM2SW Rings */
1293 val = ath12k_hif_read32(ab, wbm_base + HAL_WBM_SW_COOKIE_CONVERT_CFG);
1294 val |= u32_encode_bits(1, HAL_WBM_SW_COOKIE_CONV_CFG_GLOBAL_EN) |
1295 ab->hw_params->hal_params->wbm2sw_cc_enable;
1296
1297 ath12k_hif_write32(ab, wbm_base + HAL_WBM_SW_COOKIE_CONVERT_CFG, val);
1298 }
1299
ath12k_dp_cc_cookie_gen(u16 ppt_idx,u16 spt_idx)1300 static u32 ath12k_dp_cc_cookie_gen(u16 ppt_idx, u16 spt_idx)
1301 {
1302 return (u32)ppt_idx << ATH12K_CC_PPT_SHIFT | spt_idx;
1303 }
1304
ath12k_dp_cc_get_desc_addr_ptr(struct ath12k_base * ab,u16 ppt_idx,u16 spt_idx)1305 static inline void *ath12k_dp_cc_get_desc_addr_ptr(struct ath12k_base *ab,
1306 u16 ppt_idx, u16 spt_idx)
1307 {
1308 struct ath12k_dp *dp = &ab->dp;
1309
1310 return dp->spt_info[ppt_idx].vaddr + spt_idx;
1311 }
1312
ath12k_dp_get_rx_desc(struct ath12k_base * ab,u32 cookie)1313 struct ath12k_rx_desc_info *ath12k_dp_get_rx_desc(struct ath12k_base *ab,
1314 u32 cookie)
1315 {
1316 struct ath12k_rx_desc_info **desc_addr_ptr;
1317 u16 ppt_idx, spt_idx;
1318
1319 ppt_idx = u32_get_bits(cookie, ATH12K_DP_CC_COOKIE_PPT);
1320 spt_idx = u32_get_bits(cookie, ATH12k_DP_CC_COOKIE_SPT);
1321
1322 if (ppt_idx > ATH12K_NUM_RX_SPT_PAGES ||
1323 spt_idx > ATH12K_MAX_SPT_ENTRIES)
1324 return NULL;
1325
1326 desc_addr_ptr = ath12k_dp_cc_get_desc_addr_ptr(ab, ppt_idx, spt_idx);
1327
1328 return *desc_addr_ptr;
1329 }
1330
ath12k_dp_get_tx_desc(struct ath12k_base * ab,u32 cookie)1331 struct ath12k_tx_desc_info *ath12k_dp_get_tx_desc(struct ath12k_base *ab,
1332 u32 cookie)
1333 {
1334 struct ath12k_tx_desc_info **desc_addr_ptr;
1335 u16 ppt_idx, spt_idx;
1336
1337 ppt_idx = u32_get_bits(cookie, ATH12K_DP_CC_COOKIE_PPT);
1338 spt_idx = u32_get_bits(cookie, ATH12k_DP_CC_COOKIE_SPT);
1339
1340 if (ppt_idx < ATH12K_NUM_RX_SPT_PAGES ||
1341 ppt_idx > ab->dp.num_spt_pages ||
1342 spt_idx > ATH12K_MAX_SPT_ENTRIES)
1343 return NULL;
1344
1345 desc_addr_ptr = ath12k_dp_cc_get_desc_addr_ptr(ab, ppt_idx, spt_idx);
1346
1347 return *desc_addr_ptr;
1348 }
1349
ath12k_dp_cc_desc_init(struct ath12k_base * ab)1350 static int ath12k_dp_cc_desc_init(struct ath12k_base *ab)
1351 {
1352 struct ath12k_dp *dp = &ab->dp;
1353 struct ath12k_rx_desc_info *rx_descs, **rx_desc_addr;
1354 struct ath12k_tx_desc_info *tx_descs, **tx_desc_addr;
1355 u32 i, j, pool_id, tx_spt_page;
1356 u32 ppt_idx;
1357
1358 spin_lock_bh(&dp->rx_desc_lock);
1359
1360 /* First ATH12K_NUM_RX_SPT_PAGES of allocated SPT pages are used for RX */
1361 for (i = 0; i < ATH12K_NUM_RX_SPT_PAGES; i++) {
1362 rx_descs = kcalloc(ATH12K_MAX_SPT_ENTRIES, sizeof(*rx_descs),
1363 GFP_ATOMIC);
1364
1365 if (!rx_descs) {
1366 spin_unlock_bh(&dp->rx_desc_lock);
1367 return -ENOMEM;
1368 }
1369
1370 dp->spt_info->rxbaddr[i] = &rx_descs[0];
1371
1372 for (j = 0; j < ATH12K_MAX_SPT_ENTRIES; j++) {
1373 rx_descs[j].cookie = ath12k_dp_cc_cookie_gen(i, j);
1374 rx_descs[j].magic = ATH12K_DP_RX_DESC_MAGIC;
1375 list_add_tail(&rx_descs[j].list, &dp->rx_desc_free_list);
1376
1377 /* Update descriptor VA in SPT */
1378 rx_desc_addr = ath12k_dp_cc_get_desc_addr_ptr(ab, i, j);
1379 *rx_desc_addr = &rx_descs[j];
1380 }
1381 }
1382
1383 spin_unlock_bh(&dp->rx_desc_lock);
1384
1385 for (pool_id = 0; pool_id < ATH12K_HW_MAX_QUEUES; pool_id++) {
1386 spin_lock_bh(&dp->tx_desc_lock[pool_id]);
1387 for (i = 0; i < ATH12K_TX_SPT_PAGES_PER_POOL; i++) {
1388 tx_descs = kcalloc(ATH12K_MAX_SPT_ENTRIES, sizeof(*tx_descs),
1389 GFP_ATOMIC);
1390
1391 if (!tx_descs) {
1392 spin_unlock_bh(&dp->tx_desc_lock[pool_id]);
1393 /* Caller takes care of TX pending and RX desc cleanup */
1394 return -ENOMEM;
1395 }
1396
1397 tx_spt_page = i + pool_id * ATH12K_TX_SPT_PAGES_PER_POOL;
1398 dp->spt_info->txbaddr[tx_spt_page] = &tx_descs[0];
1399
1400 for (j = 0; j < ATH12K_MAX_SPT_ENTRIES; j++) {
1401 ppt_idx = ATH12K_NUM_RX_SPT_PAGES + tx_spt_page;
1402 tx_descs[j].desc_id = ath12k_dp_cc_cookie_gen(ppt_idx, j);
1403 tx_descs[j].pool_id = pool_id;
1404 list_add_tail(&tx_descs[j].list,
1405 &dp->tx_desc_free_list[pool_id]);
1406
1407 /* Update descriptor VA in SPT */
1408 tx_desc_addr =
1409 ath12k_dp_cc_get_desc_addr_ptr(ab, ppt_idx, j);
1410 *tx_desc_addr = &tx_descs[j];
1411 }
1412 }
1413 spin_unlock_bh(&dp->tx_desc_lock[pool_id]);
1414 }
1415 return 0;
1416 }
1417
ath12k_dp_cc_init(struct ath12k_base * ab)1418 static int ath12k_dp_cc_init(struct ath12k_base *ab)
1419 {
1420 struct ath12k_dp *dp = &ab->dp;
1421 int i, ret = 0;
1422 u32 cmem_base;
1423
1424 INIT_LIST_HEAD(&dp->rx_desc_free_list);
1425 INIT_LIST_HEAD(&dp->rx_desc_used_list);
1426 spin_lock_init(&dp->rx_desc_lock);
1427
1428 for (i = 0; i < ATH12K_HW_MAX_QUEUES; i++) {
1429 INIT_LIST_HEAD(&dp->tx_desc_free_list[i]);
1430 INIT_LIST_HEAD(&dp->tx_desc_used_list[i]);
1431 spin_lock_init(&dp->tx_desc_lock[i]);
1432 }
1433
1434 dp->num_spt_pages = ATH12K_NUM_SPT_PAGES;
1435 if (dp->num_spt_pages > ATH12K_MAX_PPT_ENTRIES)
1436 dp->num_spt_pages = ATH12K_MAX_PPT_ENTRIES;
1437
1438 dp->spt_info = kcalloc(dp->num_spt_pages, sizeof(struct ath12k_spt_info),
1439 GFP_KERNEL);
1440
1441 if (!dp->spt_info) {
1442 ath12k_warn(ab, "SPT page allocation failure");
1443 return -ENOMEM;
1444 }
1445
1446 cmem_base = ab->qmi.dev_mem[ATH12K_QMI_DEVMEM_CMEM_INDEX].start;
1447
1448 for (i = 0; i < dp->num_spt_pages; i++) {
1449 dp->spt_info[i].vaddr = dma_alloc_coherent(ab->dev,
1450 ATH12K_PAGE_SIZE,
1451 &dp->spt_info[i].paddr,
1452 GFP_KERNEL);
1453
1454 if (!dp->spt_info[i].vaddr) {
1455 ret = -ENOMEM;
1456 goto free;
1457 }
1458
1459 if (dp->spt_info[i].paddr & ATH12K_SPT_4K_ALIGN_CHECK) {
1460 ath12k_warn(ab, "SPT allocated memory is not 4K aligned");
1461 ret = -EINVAL;
1462 goto free;
1463 }
1464
1465 /* Write to PPT in CMEM */
1466 ath12k_hif_write32(ab, cmem_base + ATH12K_PPT_ADDR_OFFSET(i),
1467 dp->spt_info[i].paddr >> ATH12K_SPT_4K_ALIGN_OFFSET);
1468 }
1469
1470 ret = ath12k_dp_cc_desc_init(ab);
1471 if (ret) {
1472 ath12k_warn(ab, "HW CC desc init failed %d", ret);
1473 goto free;
1474 }
1475
1476 return 0;
1477 free:
1478 ath12k_dp_cc_cleanup(ab);
1479 return ret;
1480 }
1481
ath12k_dp_reoq_lut_setup(struct ath12k_base * ab)1482 static int ath12k_dp_reoq_lut_setup(struct ath12k_base *ab)
1483 {
1484 struct ath12k_dp *dp = &ab->dp;
1485
1486 if (!ab->hw_params->reoq_lut_support)
1487 return 0;
1488
1489 dp->reoq_lut.vaddr = dma_alloc_coherent(ab->dev,
1490 DP_REOQ_LUT_SIZE,
1491 &dp->reoq_lut.paddr,
1492 GFP_KERNEL | __GFP_ZERO);
1493 if (!dp->reoq_lut.vaddr) {
1494 ath12k_warn(ab, "failed to allocate memory for reoq table");
1495 return -ENOMEM;
1496 }
1497
1498 ath12k_hif_write32(ab, HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO1_QDESC_LUT_BASE0(ab),
1499 dp->reoq_lut.paddr);
1500 return 0;
1501 }
1502
ath12k_dp_alloc(struct ath12k_base * ab)1503 int ath12k_dp_alloc(struct ath12k_base *ab)
1504 {
1505 struct ath12k_dp *dp = &ab->dp;
1506 struct hal_srng *srng = NULL;
1507 size_t size = 0;
1508 u32 n_link_desc = 0;
1509 int ret;
1510 int i;
1511
1512 dp->ab = ab;
1513
1514 INIT_LIST_HEAD(&dp->reo_cmd_list);
1515 INIT_LIST_HEAD(&dp->reo_cmd_cache_flush_list);
1516 spin_lock_init(&dp->reo_cmd_lock);
1517
1518 dp->reo_cmd_cache_flush_count = 0;
1519
1520 ret = ath12k_wbm_idle_ring_setup(ab, &n_link_desc);
1521 if (ret) {
1522 ath12k_warn(ab, "failed to setup wbm_idle_ring: %d\n", ret);
1523 return ret;
1524 }
1525
1526 srng = &ab->hal.srng_list[dp->wbm_idle_ring.ring_id];
1527
1528 ret = ath12k_dp_link_desc_setup(ab, dp->link_desc_banks,
1529 HAL_WBM_IDLE_LINK, srng, n_link_desc);
1530 if (ret) {
1531 ath12k_warn(ab, "failed to setup link desc: %d\n", ret);
1532 return ret;
1533 }
1534
1535 ret = ath12k_dp_cc_init(ab);
1536
1537 if (ret) {
1538 ath12k_warn(ab, "failed to setup cookie converter %d\n", ret);
1539 goto fail_link_desc_cleanup;
1540 }
1541 ret = ath12k_dp_init_bank_profiles(ab);
1542 if (ret) {
1543 ath12k_warn(ab, "failed to setup bank profiles %d\n", ret);
1544 goto fail_hw_cc_cleanup;
1545 }
1546
1547 ret = ath12k_dp_srng_common_setup(ab);
1548 if (ret)
1549 goto fail_dp_bank_profiles_cleanup;
1550
1551 size = sizeof(struct hal_wbm_release_ring_tx) * DP_TX_COMP_RING_SIZE;
1552
1553 ret = ath12k_dp_reoq_lut_setup(ab);
1554 if (ret) {
1555 ath12k_warn(ab, "failed to setup reoq table %d\n", ret);
1556 goto fail_cmn_srng_cleanup;
1557 }
1558
1559 for (i = 0; i < ab->hw_params->max_tx_ring; i++) {
1560 dp->tx_ring[i].tcl_data_ring_id = i;
1561
1562 dp->tx_ring[i].tx_status_head = 0;
1563 dp->tx_ring[i].tx_status_tail = DP_TX_COMP_RING_SIZE - 1;
1564 dp->tx_ring[i].tx_status = kmalloc(size, GFP_KERNEL);
1565 if (!dp->tx_ring[i].tx_status) {
1566 ret = -ENOMEM;
1567 /* FIXME: The allocated tx status is not freed
1568 * properly here
1569 */
1570 goto fail_cmn_reoq_cleanup;
1571 }
1572 }
1573
1574 for (i = 0; i < HAL_DSCP_TID_MAP_TBL_NUM_ENTRIES_MAX; i++)
1575 ath12k_hal_tx_set_dscp_tid_map(ab, i);
1576
1577 ret = ath12k_dp_rx_alloc(ab);
1578 if (ret)
1579 goto fail_dp_rx_free;
1580
1581 /* Init any SOC level resource for DP */
1582
1583 return 0;
1584
1585 fail_dp_rx_free:
1586 ath12k_dp_rx_free(ab);
1587
1588 fail_cmn_reoq_cleanup:
1589 ath12k_dp_reoq_lut_cleanup(ab);
1590
1591 fail_cmn_srng_cleanup:
1592 ath12k_dp_srng_common_cleanup(ab);
1593
1594 fail_dp_bank_profiles_cleanup:
1595 ath12k_dp_deinit_bank_profiles(ab);
1596
1597 fail_hw_cc_cleanup:
1598 ath12k_dp_cc_cleanup(ab);
1599
1600 fail_link_desc_cleanup:
1601 ath12k_dp_link_desc_cleanup(ab, dp->link_desc_banks,
1602 HAL_WBM_IDLE_LINK, &dp->wbm_idle_ring);
1603
1604 return ret;
1605 }
1606
