1 // SPDX-License-Identifier: BSD-3-Clause-Clear
2 /*
3 * Copyright (c) 2019-2020 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021-2022, Qualcomm Innovation Center, Inc. All rights reserved.
5 */
6
7 #include <linux/module.h>
8 #include <linux/msi.h>
9 #include <linux/pci.h>
10 #include <linux/of.h>
11
12 #include "pci.h"
13 #include "core.h"
14 #include "hif.h"
15 #include "mhi.h"
16 #include "debug.h"
17 #include "pcic.h"
18
19 #define ATH11K_PCI_BAR_NUM 0
20 #define ATH11K_PCI_DMA_MASK 32
21
22 #define TCSR_SOC_HW_VERSION 0x0224
23 #define TCSR_SOC_HW_VERSION_MAJOR_MASK GENMASK(11, 8)
24 #define TCSR_SOC_HW_VERSION_MINOR_MASK GENMASK(7, 0)
25
26 #define QCA6390_DEVICE_ID 0x1101
27 #define QCN9074_DEVICE_ID 0x1104
28 #define WCN6855_DEVICE_ID 0x1103
29
30 static const struct pci_device_id ath11k_pci_id_table[] = {
31 { PCI_VDEVICE(QCOM, QCA6390_DEVICE_ID) },
32 { PCI_VDEVICE(QCOM, WCN6855_DEVICE_ID) },
33 { PCI_VDEVICE(QCOM, QCN9074_DEVICE_ID) },
34 {0}
35 };
36
37 MODULE_DEVICE_TABLE(pci, ath11k_pci_id_table);
38
ath11k_pci_bus_wake_up(struct ath11k_base * ab)39 static int ath11k_pci_bus_wake_up(struct ath11k_base *ab)
40 {
41 struct ath11k_pci *ab_pci = ath11k_pci_priv(ab);
42
43 return mhi_device_get_sync(ab_pci->mhi_ctrl->mhi_dev);
44 }
45
ath11k_pci_bus_release(struct ath11k_base * ab)46 static void ath11k_pci_bus_release(struct ath11k_base *ab)
47 {
48 struct ath11k_pci *ab_pci = ath11k_pci_priv(ab);
49
50 mhi_device_put(ab_pci->mhi_ctrl->mhi_dev);
51 }
52
ath11k_pci_get_window_start(struct ath11k_base * ab,u32 offset)53 static u32 ath11k_pci_get_window_start(struct ath11k_base *ab, u32 offset)
54 {
55 if (!ab->hw_params.static_window_map)
56 return ATH11K_PCI_WINDOW_START;
57
58 if ((offset ^ HAL_SEQ_WCSS_UMAC_OFFSET) < ATH11K_PCI_WINDOW_RANGE_MASK)
59 /* if offset lies within DP register range, use 3rd window */
60 return 3 * ATH11K_PCI_WINDOW_START;
61 else if ((offset ^ HAL_SEQ_WCSS_UMAC_CE0_SRC_REG(ab)) <
62 ATH11K_PCI_WINDOW_RANGE_MASK)
63 /* if offset lies within CE register range, use 2nd window */
64 return 2 * ATH11K_PCI_WINDOW_START;
65 else
66 return ATH11K_PCI_WINDOW_START;
67 }
68
ath11k_pci_select_window(struct ath11k_pci * ab_pci,u32 offset)69 static inline void ath11k_pci_select_window(struct ath11k_pci *ab_pci, u32 offset)
70 {
71 struct ath11k_base *ab = ab_pci->ab;
72
73 u32 window = FIELD_GET(ATH11K_PCI_WINDOW_VALUE_MASK, offset);
74
75 lockdep_assert_held(&ab_pci->window_lock);
76
77 if (window != ab_pci->register_window) {
78 iowrite32(ATH11K_PCI_WINDOW_ENABLE_BIT | window,
79 ab->mem + ATH11K_PCI_WINDOW_REG_ADDRESS);
80 ioread32(ab->mem + ATH11K_PCI_WINDOW_REG_ADDRESS);
81 ab_pci->register_window = window;
82 }
83 }
84
85 static void
ath11k_pci_window_write32(struct ath11k_base * ab,u32 offset,u32 value)86 ath11k_pci_window_write32(struct ath11k_base *ab, u32 offset, u32 value)
87 {
88 struct ath11k_pci *ab_pci = ath11k_pci_priv(ab);
89 u32 window_start;
90
91 window_start = ath11k_pci_get_window_start(ab, offset);
92
93 if (window_start == ATH11K_PCI_WINDOW_START) {
94 spin_lock_bh(&ab_pci->window_lock);
95 ath11k_pci_select_window(ab_pci, offset);
96 iowrite32(value, ab->mem + window_start +
97 (offset & ATH11K_PCI_WINDOW_RANGE_MASK));
98 spin_unlock_bh(&ab_pci->window_lock);
99 } else {
100 iowrite32(value, ab->mem + window_start +
101 (offset & ATH11K_PCI_WINDOW_RANGE_MASK));
102 }
103 }
104
ath11k_pci_window_read32(struct ath11k_base * ab,u32 offset)105 static u32 ath11k_pci_window_read32(struct ath11k_base *ab, u32 offset)
106 {
107 struct ath11k_pci *ab_pci = ath11k_pci_priv(ab);
108 u32 window_start, val;
109
110 window_start = ath11k_pci_get_window_start(ab, offset);
111
112 if (window_start == ATH11K_PCI_WINDOW_START) {
113 spin_lock_bh(&ab_pci->window_lock);
114 ath11k_pci_select_window(ab_pci, offset);
115 val = ioread32(ab->mem + window_start +
116 (offset & ATH11K_PCI_WINDOW_RANGE_MASK));
117 spin_unlock_bh(&ab_pci->window_lock);
118 } else {
119 val = ioread32(ab->mem + window_start +
120 (offset & ATH11K_PCI_WINDOW_RANGE_MASK));
121 }
122
123 return val;
124 }
125
ath11k_pci_get_msi_irq(struct ath11k_base * ab,unsigned int vector)126 int ath11k_pci_get_msi_irq(struct ath11k_base *ab, unsigned int vector)
127 {
128 struct pci_dev *pci_dev = to_pci_dev(ab->dev);
129
130 return pci_irq_vector(pci_dev, vector);
131 }
132
133 static const struct ath11k_pci_ops ath11k_pci_ops_qca6390 = {
134 .wakeup = ath11k_pci_bus_wake_up,
135 .release = ath11k_pci_bus_release,
136 .get_msi_irq = ath11k_pci_get_msi_irq,
137 .window_write32 = ath11k_pci_window_write32,
138 .window_read32 = ath11k_pci_window_read32,
139 };
140
141 static const struct ath11k_pci_ops ath11k_pci_ops_qcn9074 = {
142 .wakeup = NULL,
143 .release = NULL,
144 .get_msi_irq = ath11k_pci_get_msi_irq,
145 .window_write32 = ath11k_pci_window_write32,
146 .window_read32 = ath11k_pci_window_read32,
147 };
148
149 static const struct ath11k_msi_config msi_config_one_msi = {
150 .total_vectors = 1,
151 .total_users = 4,
152 .users = (struct ath11k_msi_user[]) {
153 { .name = "MHI", .num_vectors = 3, .base_vector = 0 },
154 { .name = "CE", .num_vectors = 1, .base_vector = 0 },
155 { .name = "WAKE", .num_vectors = 1, .base_vector = 0 },
156 { .name = "DP", .num_vectors = 1, .base_vector = 0 },
157 },
158 };
159
ath11k_pci_select_static_window(struct ath11k_pci * ab_pci)160 static inline void ath11k_pci_select_static_window(struct ath11k_pci *ab_pci)
161 {
162 u32 umac_window;
163 u32 ce_window;
164 u32 window;
165
166 umac_window = FIELD_GET(ATH11K_PCI_WINDOW_VALUE_MASK, HAL_SEQ_WCSS_UMAC_OFFSET);
167 ce_window = FIELD_GET(ATH11K_PCI_WINDOW_VALUE_MASK, HAL_CE_WFSS_CE_REG_BASE);
168 window = (umac_window << 12) | (ce_window << 6);
169
170 iowrite32(ATH11K_PCI_WINDOW_ENABLE_BIT | window,
171 ab_pci->ab->mem + ATH11K_PCI_WINDOW_REG_ADDRESS);
172 }
173
ath11k_pci_soc_global_reset(struct ath11k_base * ab)174 static void ath11k_pci_soc_global_reset(struct ath11k_base *ab)
175 {
176 u32 val, delay;
177
178 val = ath11k_pcic_read32(ab, PCIE_SOC_GLOBAL_RESET);
179
180 val |= PCIE_SOC_GLOBAL_RESET_V;
181
182 ath11k_pcic_write32(ab, PCIE_SOC_GLOBAL_RESET, val);
183
184 /* TODO: exact time to sleep is uncertain */
185 delay = 10;
186 mdelay(delay);
187
188 /* Need to toggle V bit back otherwise stuck in reset status */
189 val &= ~PCIE_SOC_GLOBAL_RESET_V;
190
191 ath11k_pcic_write32(ab, PCIE_SOC_GLOBAL_RESET, val);
192
193 mdelay(delay);
194
195 val = ath11k_pcic_read32(ab, PCIE_SOC_GLOBAL_RESET);
196 if (val == 0xffffffff)
197 ath11k_warn(ab, "link down error during global reset\n");
198 }
199
ath11k_pci_clear_dbg_registers(struct ath11k_base * ab)200 static void ath11k_pci_clear_dbg_registers(struct ath11k_base *ab)
201 {
202 u32 val;
203
204 /* read cookie */
205 val = ath11k_pcic_read32(ab, PCIE_Q6_COOKIE_ADDR);
206 ath11k_dbg(ab, ATH11K_DBG_PCI, "cookie:0x%x\n", val);
207
208 val = ath11k_pcic_read32(ab, WLAON_WARM_SW_ENTRY);
209 ath11k_dbg(ab, ATH11K_DBG_PCI, "WLAON_WARM_SW_ENTRY 0x%x\n", val);
210
211 /* TODO: exact time to sleep is uncertain */
212 mdelay(10);
213
214 /* write 0 to WLAON_WARM_SW_ENTRY to prevent Q6 from
215 * continuing warm path and entering dead loop.
216 */
217 ath11k_pcic_write32(ab, WLAON_WARM_SW_ENTRY, 0);
218 mdelay(10);
219
220 val = ath11k_pcic_read32(ab, WLAON_WARM_SW_ENTRY);
221 ath11k_dbg(ab, ATH11K_DBG_PCI, "WLAON_WARM_SW_ENTRY 0x%x\n", val);
222
223 /* A read clear register. clear the register to prevent
224 * Q6 from entering wrong code path.
225 */
226 val = ath11k_pcic_read32(ab, WLAON_SOC_RESET_CAUSE_REG);
227 ath11k_dbg(ab, ATH11K_DBG_PCI, "soc reset cause:%d\n", val);
228 }
229
ath11k_pci_set_link_reg(struct ath11k_base * ab,u32 offset,u32 value,u32 mask)230 static int ath11k_pci_set_link_reg(struct ath11k_base *ab,
231 u32 offset, u32 value, u32 mask)
232 {
233 u32 v;
234 int i;
235
236 v = ath11k_pcic_read32(ab, offset);
237 if ((v & mask) == value)
238 return 0;
239
240 for (i = 0; i < 10; i++) {
241 ath11k_pcic_write32(ab, offset, (v & ~mask) | value);
242
243 v = ath11k_pcic_read32(ab, offset);
244 if ((v & mask) == value)
245 return 0;
246
247 mdelay(2);
248 }
249
250 ath11k_warn(ab, "failed to set pcie link register 0x%08x: 0x%08x != 0x%08x\n",
251 offset, v & mask, value);
252
253 return -ETIMEDOUT;
254 }
255
ath11k_pci_fix_l1ss(struct ath11k_base * ab)256 static int ath11k_pci_fix_l1ss(struct ath11k_base *ab)
257 {
258 int ret;
259
260 ret = ath11k_pci_set_link_reg(ab,
261 PCIE_QSERDES_COM_SYSCLK_EN_SEL_REG(ab),
262 PCIE_QSERDES_COM_SYSCLK_EN_SEL_VAL,
263 PCIE_QSERDES_COM_SYSCLK_EN_SEL_MSK);
264 if (ret) {
265 ath11k_warn(ab, "failed to set sysclk: %d\n", ret);
266 return ret;
267 }
268
269 ret = ath11k_pci_set_link_reg(ab,
270 PCIE_PCS_OSC_DTCT_CONFIG1_REG(ab),
271 PCIE_PCS_OSC_DTCT_CONFIG1_VAL,
272 PCIE_PCS_OSC_DTCT_CONFIG_MSK);
273 if (ret) {
274 ath11k_warn(ab, "failed to set dtct config1 error: %d\n", ret);
275 return ret;
276 }
277
278 ret = ath11k_pci_set_link_reg(ab,
279 PCIE_PCS_OSC_DTCT_CONFIG2_REG(ab),
280 PCIE_PCS_OSC_DTCT_CONFIG2_VAL,
281 PCIE_PCS_OSC_DTCT_CONFIG_MSK);
282 if (ret) {
283 ath11k_warn(ab, "failed to set dtct config2: %d\n", ret);
284 return ret;
285 }
286
287 ret = ath11k_pci_set_link_reg(ab,
288 PCIE_PCS_OSC_DTCT_CONFIG4_REG(ab),
289 PCIE_PCS_OSC_DTCT_CONFIG4_VAL,
290 PCIE_PCS_OSC_DTCT_CONFIG_MSK);
291 if (ret) {
292 ath11k_warn(ab, "failed to set dtct config4: %d\n", ret);
293 return ret;
294 }
295
296 return 0;
297 }
298
ath11k_pci_enable_ltssm(struct ath11k_base * ab)299 static void ath11k_pci_enable_ltssm(struct ath11k_base *ab)
300 {
301 u32 val;
302 int i;
303
304 val = ath11k_pcic_read32(ab, PCIE_PCIE_PARF_LTSSM);
305
306 /* PCIE link seems very unstable after the Hot Reset*/
307 for (i = 0; val != PARM_LTSSM_VALUE && i < 5; i++) {
308 if (val == 0xffffffff)
309 mdelay(5);
310
311 ath11k_pcic_write32(ab, PCIE_PCIE_PARF_LTSSM, PARM_LTSSM_VALUE);
312 val = ath11k_pcic_read32(ab, PCIE_PCIE_PARF_LTSSM);
313 }
314
315 ath11k_dbg(ab, ATH11K_DBG_PCI, "pci ltssm 0x%x\n", val);
316
317 val = ath11k_pcic_read32(ab, GCC_GCC_PCIE_HOT_RST);
318 val |= GCC_GCC_PCIE_HOT_RST_VAL;
319 ath11k_pcic_write32(ab, GCC_GCC_PCIE_HOT_RST, val);
320 val = ath11k_pcic_read32(ab, GCC_GCC_PCIE_HOT_RST);
321
322 ath11k_dbg(ab, ATH11K_DBG_PCI, "pci pcie_hot_rst 0x%x\n", val);
323
324 mdelay(5);
325 }
326
ath11k_pci_clear_all_intrs(struct ath11k_base * ab)327 static void ath11k_pci_clear_all_intrs(struct ath11k_base *ab)
328 {
329 /* This is a WAR for PCIE Hotreset.
330 * When target receive Hotreset, but will set the interrupt.
331 * So when download SBL again, SBL will open Interrupt and
332 * receive it, and crash immediately.
333 */
334 ath11k_pcic_write32(ab, PCIE_PCIE_INT_ALL_CLEAR, PCIE_INT_CLEAR_ALL);
335 }
336
ath11k_pci_set_wlaon_pwr_ctrl(struct ath11k_base * ab)337 static void ath11k_pci_set_wlaon_pwr_ctrl(struct ath11k_base *ab)
338 {
339 u32 val;
340
341 val = ath11k_pcic_read32(ab, WLAON_QFPROM_PWR_CTRL_REG);
342 val &= ~QFPROM_PWR_CTRL_VDD4BLOW_MASK;
343 ath11k_pcic_write32(ab, WLAON_QFPROM_PWR_CTRL_REG, val);
344 }
345
ath11k_pci_force_wake(struct ath11k_base * ab)346 static void ath11k_pci_force_wake(struct ath11k_base *ab)
347 {
348 ath11k_pcic_write32(ab, PCIE_SOC_WAKE_PCIE_LOCAL_REG, 1);
349 mdelay(5);
350 }
351
ath11k_pci_sw_reset(struct ath11k_base * ab,bool power_on)352 static void ath11k_pci_sw_reset(struct ath11k_base *ab, bool power_on)
353 {
354 mdelay(100);
355
356 if (power_on) {
357 ath11k_pci_enable_ltssm(ab);
358 ath11k_pci_clear_all_intrs(ab);
359 ath11k_pci_set_wlaon_pwr_ctrl(ab);
360 if (ab->hw_params.fix_l1ss)
361 ath11k_pci_fix_l1ss(ab);
362 }
363
364 ath11k_mhi_clear_vector(ab);
365 ath11k_pci_clear_dbg_registers(ab);
366 ath11k_pci_soc_global_reset(ab);
367 ath11k_mhi_set_mhictrl_reset(ab);
368 }
369
ath11k_pci_init_qmi_ce_config(struct ath11k_base * ab)370 static void ath11k_pci_init_qmi_ce_config(struct ath11k_base *ab)
371 {
372 struct ath11k_qmi_ce_cfg *cfg = &ab->qmi.ce_cfg;
373
374 cfg->tgt_ce = ab->hw_params.target_ce_config;
375 cfg->tgt_ce_len = ab->hw_params.target_ce_count;
376
377 cfg->svc_to_ce_map = ab->hw_params.svc_to_ce_map;
378 cfg->svc_to_ce_map_len = ab->hw_params.svc_to_ce_map_len;
379 ab->qmi.service_ins_id = ab->hw_params.qmi_service_ins_id;
380
381 ath11k_ce_get_shadow_config(ab, &cfg->shadow_reg_v2,
382 &cfg->shadow_reg_v2_len);
383 }
384
ath11k_pci_msi_config(struct ath11k_pci * ab_pci,bool enable)385 static void ath11k_pci_msi_config(struct ath11k_pci *ab_pci, bool enable)
386 {
387 struct pci_dev *dev = ab_pci->pdev;
388 u16 control;
389
390 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control);
391
392 if (enable)
393 control |= PCI_MSI_FLAGS_ENABLE;
394 else
395 control &= ~PCI_MSI_FLAGS_ENABLE;
396
397 pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control);
398 }
399
ath11k_pci_msi_enable(struct ath11k_pci * ab_pci)400 static void ath11k_pci_msi_enable(struct ath11k_pci *ab_pci)
401 {
402 ath11k_pci_msi_config(ab_pci, true);
403 }
404
ath11k_pci_msi_disable(struct ath11k_pci * ab_pci)405 static void ath11k_pci_msi_disable(struct ath11k_pci *ab_pci)
406 {
407 ath11k_pci_msi_config(ab_pci, false);
408 }
409
ath11k_pci_alloc_msi(struct ath11k_pci * ab_pci)410 static int ath11k_pci_alloc_msi(struct ath11k_pci *ab_pci)
411 {
412 struct ath11k_base *ab = ab_pci->ab;
413 const struct ath11k_msi_config *msi_config = ab->pci.msi.config;
414 struct pci_dev *pci_dev = ab_pci->pdev;
415 struct msi_desc *msi_desc;
416 int num_vectors;
417 int ret;
418
419 num_vectors = pci_alloc_irq_vectors(pci_dev,
420 msi_config->total_vectors,
421 msi_config->total_vectors,
422 PCI_IRQ_MSI);
423 if (num_vectors == msi_config->total_vectors) {
424 set_bit(ATH11K_FLAG_MULTI_MSI_VECTORS, &ab->dev_flags);
425 } else {
426 num_vectors = pci_alloc_irq_vectors(ab_pci->pdev,
427 1,
428 1,
429 PCI_IRQ_MSI);
430 if (num_vectors < 0) {
431 ret = -EINVAL;
432 goto reset_msi_config;
433 }
434 clear_bit(ATH11K_FLAG_MULTI_MSI_VECTORS, &ab->dev_flags);
435 ab->pci.msi.config = &msi_config_one_msi;
436 ath11k_dbg(ab, ATH11K_DBG_PCI, "request MSI one vector\n");
437 }
438 ath11k_info(ab, "MSI vectors: %d\n", num_vectors);
439
440 ath11k_pci_msi_disable(ab_pci);
441
442 msi_desc = irq_get_msi_desc(ab_pci->pdev->irq);
443 if (!msi_desc) {
444 ath11k_err(ab, "msi_desc is NULL!\n");
445 ret = -EINVAL;
446 goto free_msi_vector;
447 }
448
449 ab->pci.msi.ep_base_data = msi_desc->msg.data;
450
451 pci_read_config_dword(pci_dev, pci_dev->msi_cap + PCI_MSI_ADDRESS_LO,
452 &ab->pci.msi.addr_lo);
453
454 if (msi_desc->pci.msi_attrib.is_64) {
455 pci_read_config_dword(pci_dev, pci_dev->msi_cap + PCI_MSI_ADDRESS_HI,
456 &ab->pci.msi.addr_hi);
457 } else {
458 ab->pci.msi.addr_hi = 0;
459 }
460
461 ath11k_dbg(ab, ATH11K_DBG_PCI, "msi base data is %d\n", ab->pci.msi.ep_base_data);
462
463 return 0;
464
465 free_msi_vector:
466 pci_free_irq_vectors(ab_pci->pdev);
467
468 reset_msi_config:
469 return ret;
470 }
471
ath11k_pci_free_msi(struct ath11k_pci * ab_pci)472 static void ath11k_pci_free_msi(struct ath11k_pci *ab_pci)
473 {
474 pci_free_irq_vectors(ab_pci->pdev);
475 }
476
ath11k_pci_config_msi_data(struct ath11k_pci * ab_pci)477 static int ath11k_pci_config_msi_data(struct ath11k_pci *ab_pci)
478 {
479 struct msi_desc *msi_desc;
480
481 msi_desc = irq_get_msi_desc(ab_pci->pdev->irq);
482 if (!msi_desc) {
483 ath11k_err(ab_pci->ab, "msi_desc is NULL!\n");
484 pci_free_irq_vectors(ab_pci->pdev);
485 return -EINVAL;
486 }
487
488 ab_pci->ab->pci.msi.ep_base_data = msi_desc->msg.data;
489
490 ath11k_dbg(ab_pci->ab, ATH11K_DBG_PCI, "pci after request_irq msi_ep_base_data %d\n",
491 ab_pci->ab->pci.msi.ep_base_data);
492
493 return 0;
494 }
495
ath11k_pci_claim(struct ath11k_pci * ab_pci,struct pci_dev * pdev)496 static int ath11k_pci_claim(struct ath11k_pci *ab_pci, struct pci_dev *pdev)
497 {
498 struct ath11k_base *ab = ab_pci->ab;
499 u16 device_id;
500 int ret = 0;
501
502 pci_read_config_word(pdev, PCI_DEVICE_ID, &device_id);
503 if (device_id != ab_pci->dev_id) {
504 ath11k_err(ab, "pci device id mismatch: 0x%x 0x%x\n",
505 device_id, ab_pci->dev_id);
506 ret = -EIO;
507 goto out;
508 }
509
510 ret = pci_assign_resource(pdev, ATH11K_PCI_BAR_NUM);
511 if (ret) {
512 ath11k_err(ab, "failed to assign pci resource: %d\n", ret);
513 goto out;
514 }
515
516 ret = pci_enable_device(pdev);
517 if (ret) {
518 ath11k_err(ab, "failed to enable pci device: %d\n", ret);
519 goto out;
520 }
521
522 ret = pci_request_region(pdev, ATH11K_PCI_BAR_NUM, "ath11k_pci");
523 if (ret) {
524 ath11k_err(ab, "failed to request pci region: %d\n", ret);
525 goto disable_device;
526 }
527
528 ret = dma_set_mask_and_coherent(&pdev->dev,
529 DMA_BIT_MASK(ATH11K_PCI_DMA_MASK));
530 if (ret) {
531 ath11k_err(ab, "failed to set pci dma mask to %d: %d\n",
532 ATH11K_PCI_DMA_MASK, ret);
533 goto release_region;
534 }
535
536 pci_set_master(pdev);
537
538 ab->mem_len = pci_resource_len(pdev, ATH11K_PCI_BAR_NUM);
539 ab->mem = pci_iomap(pdev, ATH11K_PCI_BAR_NUM, 0);
540 if (!ab->mem) {
541 ath11k_err(ab, "failed to map pci bar %d\n", ATH11K_PCI_BAR_NUM);
542 ret = -EIO;
543 goto clear_master;
544 }
545
546 ath11k_dbg(ab, ATH11K_DBG_BOOT, "boot pci_mem 0x%pK\n", ab->mem);
547 return 0;
548
549 clear_master:
550 pci_clear_master(pdev);
551 release_region:
552 pci_release_region(pdev, ATH11K_PCI_BAR_NUM);
553 disable_device:
554 pci_disable_device(pdev);
555 out:
556 return ret;
557 }
558
ath11k_pci_free_region(struct ath11k_pci * ab_pci)559 static void ath11k_pci_free_region(struct ath11k_pci *ab_pci)
560 {
561 struct ath11k_base *ab = ab_pci->ab;
562 struct pci_dev *pci_dev = ab_pci->pdev;
563
564 pci_iounmap(pci_dev, ab->mem);
565 ab->mem = NULL;
566 pci_clear_master(pci_dev);
567 pci_release_region(pci_dev, ATH11K_PCI_BAR_NUM);
568 if (pci_is_enabled(pci_dev))
569 pci_disable_device(pci_dev);
570 }
571
ath11k_pci_aspm_disable(struct ath11k_pci * ab_pci)572 static void ath11k_pci_aspm_disable(struct ath11k_pci *ab_pci)
573 {
574 struct ath11k_base *ab = ab_pci->ab;
575
576 pcie_capability_read_word(ab_pci->pdev, PCI_EXP_LNKCTL,
577 &ab_pci->link_ctl);
578
579 ath11k_dbg(ab, ATH11K_DBG_PCI, "pci link_ctl 0x%04x L0s %d L1 %d\n",
580 ab_pci->link_ctl,
581 u16_get_bits(ab_pci->link_ctl, PCI_EXP_LNKCTL_ASPM_L0S),
582 u16_get_bits(ab_pci->link_ctl, PCI_EXP_LNKCTL_ASPM_L1));
583
584 /* disable L0s and L1 */
585 pcie_capability_write_word(ab_pci->pdev, PCI_EXP_LNKCTL,
586 ab_pci->link_ctl & ~PCI_EXP_LNKCTL_ASPMC);
587
588 set_bit(ATH11K_PCI_ASPM_RESTORE, &ab_pci->flags);
589 }
590
ath11k_pci_aspm_restore(struct ath11k_pci * ab_pci)591 static void ath11k_pci_aspm_restore(struct ath11k_pci *ab_pci)
592 {
593 if (test_and_clear_bit(ATH11K_PCI_ASPM_RESTORE, &ab_pci->flags))
594 pcie_capability_write_word(ab_pci->pdev, PCI_EXP_LNKCTL,
595 ab_pci->link_ctl);
596 }
597
ath11k_pci_power_up(struct ath11k_base * ab)598 static int ath11k_pci_power_up(struct ath11k_base *ab)
599 {
600 struct ath11k_pci *ab_pci = ath11k_pci_priv(ab);
601 int ret;
602
603 ab_pci->register_window = 0;
604 clear_bit(ATH11K_FLAG_DEVICE_INIT_DONE, &ab->dev_flags);
605 ath11k_pci_sw_reset(ab_pci->ab, true);
606
607 /* Disable ASPM during firmware download due to problems switching
608 * to AMSS state.
609 */
610 ath11k_pci_aspm_disable(ab_pci);
611
612 ath11k_pci_msi_enable(ab_pci);
613
614 ret = ath11k_mhi_start(ab_pci);
615 if (ret) {
616 ath11k_err(ab, "failed to start mhi: %d\n", ret);
617 return ret;
618 }
619
620 if (ab->hw_params.static_window_map)
621 ath11k_pci_select_static_window(ab_pci);
622
623 return 0;
624 }
625
ath11k_pci_power_down(struct ath11k_base * ab)626 static void ath11k_pci_power_down(struct ath11k_base *ab)
627 {
628 struct ath11k_pci *ab_pci = ath11k_pci_priv(ab);
629
630 /* restore aspm in case firmware bootup fails */
631 ath11k_pci_aspm_restore(ab_pci);
632
633 ath11k_pci_force_wake(ab_pci->ab);
634
635 ath11k_pci_msi_disable(ab_pci);
636
637 ath11k_mhi_stop(ab_pci);
638 clear_bit(ATH11K_FLAG_DEVICE_INIT_DONE, &ab->dev_flags);
639 ath11k_pci_sw_reset(ab_pci->ab, false);
640 }
641
ath11k_pci_hif_suspend(struct ath11k_base * ab)642 static int ath11k_pci_hif_suspend(struct ath11k_base *ab)
643 {
644 struct ath11k_pci *ar_pci = ath11k_pci_priv(ab);
645
646 return ath11k_mhi_suspend(ar_pci);
647 }
648
ath11k_pci_hif_resume(struct ath11k_base * ab)649 static int ath11k_pci_hif_resume(struct ath11k_base *ab)
650 {
651 struct ath11k_pci *ar_pci = ath11k_pci_priv(ab);
652
653 return ath11k_mhi_resume(ar_pci);
654 }
655
ath11k_pci_hif_ce_irq_enable(struct ath11k_base * ab)656 static void ath11k_pci_hif_ce_irq_enable(struct ath11k_base *ab)
657 {
658 ath11k_pcic_ce_irqs_enable(ab);
659 }
660
ath11k_pci_hif_ce_irq_disable(struct ath11k_base * ab)661 static void ath11k_pci_hif_ce_irq_disable(struct ath11k_base *ab)
662 {
663 ath11k_pcic_ce_irq_disable_sync(ab);
664 }
665
ath11k_pci_start(struct ath11k_base * ab)666 static int ath11k_pci_start(struct ath11k_base *ab)
667 {
668 struct ath11k_pci *ab_pci = ath11k_pci_priv(ab);
669
670 /* TODO: for now don't restore ASPM in case of single MSI
671 * vector as MHI register reading in M2 causes system hang.
672 */
673 if (test_bit(ATH11K_FLAG_MULTI_MSI_VECTORS, &ab->dev_flags))
674 ath11k_pci_aspm_restore(ab_pci);
675 else
676 ath11k_info(ab, "leaving PCI ASPM disabled to avoid MHI M2 problems\n");
677
678 ath11k_pcic_start(ab);
679
680 return 0;
681 }
682
683 static const struct ath11k_hif_ops ath11k_pci_hif_ops = {
684 .start = ath11k_pci_start,
685 .stop = ath11k_pcic_stop,
686 .read32 = ath11k_pcic_read32,
687 .write32 = ath11k_pcic_write32,
688 .read = ath11k_pcic_read,
689 .power_down = ath11k_pci_power_down,
690 .power_up = ath11k_pci_power_up,
691 .suspend = ath11k_pci_hif_suspend,
692 .resume = ath11k_pci_hif_resume,
693 .irq_enable = ath11k_pcic_ext_irq_enable,
694 .irq_disable = ath11k_pcic_ext_irq_disable,
695 .get_msi_address = ath11k_pcic_get_msi_address,
696 .get_user_msi_vector = ath11k_pcic_get_user_msi_assignment,
697 .map_service_to_pipe = ath11k_pcic_map_service_to_pipe,
698 .ce_irq_enable = ath11k_pci_hif_ce_irq_enable,
699 .ce_irq_disable = ath11k_pci_hif_ce_irq_disable,
700 .get_ce_msi_idx = ath11k_pcic_get_ce_msi_idx,
701 };
702
ath11k_pci_read_hw_version(struct ath11k_base * ab,u32 * major,u32 * minor)703 static void ath11k_pci_read_hw_version(struct ath11k_base *ab, u32 *major, u32 *minor)
704 {
705 u32 soc_hw_version;
706
707 soc_hw_version = ath11k_pcic_read32(ab, TCSR_SOC_HW_VERSION);
708 *major = FIELD_GET(TCSR_SOC_HW_VERSION_MAJOR_MASK,
709 soc_hw_version);
710 *minor = FIELD_GET(TCSR_SOC_HW_VERSION_MINOR_MASK,
711 soc_hw_version);
712
713 ath11k_dbg(ab, ATH11K_DBG_PCI, "pci tcsr_soc_hw_version major %d minor %d\n",
714 *major, *minor);
715 }
716
ath11k_pci_set_irq_affinity_hint(struct ath11k_pci * ab_pci,const struct cpumask * m)717 static int ath11k_pci_set_irq_affinity_hint(struct ath11k_pci *ab_pci,
718 const struct cpumask *m)
719 {
720 if (test_bit(ATH11K_FLAG_MULTI_MSI_VECTORS, &ab_pci->ab->dev_flags))
721 return 0;
722
723 return irq_set_affinity_hint(ab_pci->pdev->irq, m);
724 }
725
ath11k_pci_probe(struct pci_dev * pdev,const struct pci_device_id * pci_dev)726 static int ath11k_pci_probe(struct pci_dev *pdev,
727 const struct pci_device_id *pci_dev)
728 {
729 struct ath11k_base *ab;
730 struct ath11k_pci *ab_pci;
731 u32 soc_hw_version_major, soc_hw_version_minor, addr;
732 const struct ath11k_pci_ops *pci_ops;
733 int ret;
734
735 ab = ath11k_core_alloc(&pdev->dev, sizeof(*ab_pci), ATH11K_BUS_PCI);
736
737 if (!ab) {
738 dev_err(&pdev->dev, "failed to allocate ath11k base\n");
739 return -ENOMEM;
740 }
741
742 ab->dev = &pdev->dev;
743 pci_set_drvdata(pdev, ab);
744 ab_pci = ath11k_pci_priv(ab);
745 ab_pci->dev_id = pci_dev->device;
746 ab_pci->ab = ab;
747 ab_pci->pdev = pdev;
748 ab->hif.ops = &ath11k_pci_hif_ops;
749 pci_set_drvdata(pdev, ab);
750 spin_lock_init(&ab_pci->window_lock);
751
752 /* Set fixed_mem_region to true for platforms support reserved memory
753 * from DT. If memory is reserved from DT for FW, ath11k driver need not
754 * allocate memory.
755 */
756 ret = of_property_read_u32(ab->dev->of_node, "memory-region", &addr);
757 if (!ret)
758 set_bit(ATH11K_FLAG_FIXED_MEM_RGN, &ab->dev_flags);
759
760 ret = ath11k_pci_claim(ab_pci, pdev);
761 if (ret) {
762 ath11k_err(ab, "failed to claim device: %d\n", ret);
763 goto err_free_core;
764 }
765
766 ath11k_dbg(ab, ATH11K_DBG_BOOT, "pci probe %04x:%04x %04x:%04x\n",
767 pdev->vendor, pdev->device,
768 pdev->subsystem_vendor, pdev->subsystem_device);
769
770 ab->id.vendor = pdev->vendor;
771 ab->id.device = pdev->device;
772 ab->id.subsystem_vendor = pdev->subsystem_vendor;
773 ab->id.subsystem_device = pdev->subsystem_device;
774
775 switch (pci_dev->device) {
776 case QCA6390_DEVICE_ID:
777 ath11k_pci_read_hw_version(ab, &soc_hw_version_major,
778 &soc_hw_version_minor);
779 switch (soc_hw_version_major) {
780 case 2:
781 ab->hw_rev = ATH11K_HW_QCA6390_HW20;
782 break;
783 default:
784 dev_err(&pdev->dev, "Unsupported QCA6390 SOC hardware version: %d %d\n",
785 soc_hw_version_major, soc_hw_version_minor);
786 ret = -EOPNOTSUPP;
787 goto err_pci_free_region;
788 }
789
790 pci_ops = &ath11k_pci_ops_qca6390;
791 break;
792 case QCN9074_DEVICE_ID:
793 pci_ops = &ath11k_pci_ops_qcn9074;
794 ab->hw_rev = ATH11K_HW_QCN9074_HW10;
795 break;
796 case WCN6855_DEVICE_ID:
797 ab->id.bdf_search = ATH11K_BDF_SEARCH_BUS_AND_BOARD;
798 ath11k_pci_read_hw_version(ab, &soc_hw_version_major,
799 &soc_hw_version_minor);
800 switch (soc_hw_version_major) {
801 case 2:
802 switch (soc_hw_version_minor) {
803 case 0x00:
804 case 0x01:
805 ab->hw_rev = ATH11K_HW_WCN6855_HW20;
806 break;
807 case 0x10:
808 case 0x11:
809 ab->hw_rev = ATH11K_HW_WCN6855_HW21;
810 break;
811 default:
812 goto unsupported_wcn6855_soc;
813 }
814 break;
815 default:
816 unsupported_wcn6855_soc:
817 dev_err(&pdev->dev, "Unsupported WCN6855 SOC hardware version: %d %d\n",
818 soc_hw_version_major, soc_hw_version_minor);
819 ret = -EOPNOTSUPP;
820 goto err_pci_free_region;
821 }
822
823 pci_ops = &ath11k_pci_ops_qca6390;
824 break;
825 default:
826 dev_err(&pdev->dev, "Unknown PCI device found: 0x%x\n",
827 pci_dev->device);
828 ret = -EOPNOTSUPP;
829 goto err_pci_free_region;
830 }
831
832 ret = ath11k_pcic_register_pci_ops(ab, pci_ops);
833 if (ret) {
834 ath11k_err(ab, "failed to register PCI ops: %d\n", ret);
835 goto err_pci_free_region;
836 }
837
838 ret = ath11k_pcic_init_msi_config(ab);
839 if (ret) {
840 ath11k_err(ab, "failed to init msi config: %d\n", ret);
841 goto err_pci_free_region;
842 }
843
844 ret = ath11k_pci_alloc_msi(ab_pci);
845 if (ret) {
846 ath11k_err(ab, "failed to enable msi: %d\n", ret);
847 goto err_pci_free_region;
848 }
849
850 ret = ath11k_core_pre_init(ab);
851 if (ret)
852 goto err_pci_disable_msi;
853
854 ret = ath11k_mhi_register(ab_pci);
855 if (ret) {
856 ath11k_err(ab, "failed to register mhi: %d\n", ret);
857 goto err_pci_disable_msi;
858 }
859
860 ret = ath11k_hal_srng_init(ab);
861 if (ret)
862 goto err_mhi_unregister;
863
864 ret = ath11k_ce_alloc_pipes(ab);
865 if (ret) {
866 ath11k_err(ab, "failed to allocate ce pipes: %d\n", ret);
867 goto err_hal_srng_deinit;
868 }
869
870 ath11k_pci_init_qmi_ce_config(ab);
871
872 ret = ath11k_pcic_config_irq(ab);
873 if (ret) {
874 ath11k_err(ab, "failed to config irq: %d\n", ret);
875 goto err_ce_free;
876 }
877
878 ret = ath11k_pci_set_irq_affinity_hint(ab_pci, cpumask_of(0));
879 if (ret) {
880 ath11k_err(ab, "failed to set irq affinity %d\n", ret);
881 goto err_free_irq;
882 }
883
884 /* kernel may allocate a dummy vector before request_irq and
885 * then allocate a real vector when request_irq is called.
886 * So get msi_data here again to avoid spurious interrupt
887 * as msi_data will configured to srngs.
888 */
889 ret = ath11k_pci_config_msi_data(ab_pci);
890 if (ret) {
891 ath11k_err(ab, "failed to config msi_data: %d\n", ret);
892 goto err_irq_affinity_cleanup;
893 }
894
895 ret = ath11k_core_init(ab);
896 if (ret) {
897 ath11k_err(ab, "failed to init core: %d\n", ret);
898 goto err_irq_affinity_cleanup;
899 }
900 return 0;
901
902 err_irq_affinity_cleanup:
903 ath11k_pci_set_irq_affinity_hint(ab_pci, NULL);
904
905 err_free_irq:
906 ath11k_pcic_free_irq(ab);
907
908 err_ce_free:
909 ath11k_ce_free_pipes(ab);
910
911 err_hal_srng_deinit:
912 ath11k_hal_srng_deinit(ab);
913
914 err_mhi_unregister:
915 ath11k_mhi_unregister(ab_pci);
916
917 err_pci_disable_msi:
918 ath11k_pci_free_msi(ab_pci);
919
920 err_pci_free_region:
921 ath11k_pci_free_region(ab_pci);
922
923 err_free_core:
924 ath11k_core_free(ab);
925
926 return ret;
927 }
928
ath11k_pci_remove(struct pci_dev * pdev)929 static void ath11k_pci_remove(struct pci_dev *pdev)
930 {
931 struct ath11k_base *ab = pci_get_drvdata(pdev);
932 struct ath11k_pci *ab_pci = ath11k_pci_priv(ab);
933
934 ath11k_pci_set_irq_affinity_hint(ab_pci, NULL);
935
936 if (test_bit(ATH11K_FLAG_QMI_FAIL, &ab->dev_flags)) {
937 ath11k_pci_power_down(ab);
938 ath11k_debugfs_soc_destroy(ab);
939 ath11k_qmi_deinit_service(ab);
940 goto qmi_fail;
941 }
942
943 set_bit(ATH11K_FLAG_UNREGISTERING, &ab->dev_flags);
944
945 ath11k_core_deinit(ab);
946
947 qmi_fail:
948 ath11k_mhi_unregister(ab_pci);
949
950 ath11k_pcic_free_irq(ab);
951 ath11k_pci_free_msi(ab_pci);
952 ath11k_pci_free_region(ab_pci);
953
954 ath11k_hal_srng_deinit(ab);
955 ath11k_ce_free_pipes(ab);
956 ath11k_core_free(ab);
957 }
958
ath11k_pci_shutdown(struct pci_dev * pdev)959 static void ath11k_pci_shutdown(struct pci_dev *pdev)
960 {
961 struct ath11k_base *ab = pci_get_drvdata(pdev);
962 struct ath11k_pci *ab_pci = ath11k_pci_priv(ab);
963
964 ath11k_pci_set_irq_affinity_hint(ab_pci, NULL);
965 ath11k_pci_power_down(ab);
966 }
967
ath11k_pci_pm_suspend(struct device * dev)968 static __maybe_unused int ath11k_pci_pm_suspend(struct device *dev)
969 {
970 struct ath11k_base *ab = dev_get_drvdata(dev);
971 int ret;
972
973 if (test_bit(ATH11K_FLAG_QMI_FAIL, &ab->dev_flags)) {
974 ath11k_dbg(ab, ATH11K_DBG_BOOT, "boot skipping pci suspend as qmi is not initialised\n");
975 return 0;
976 }
977
978 ret = ath11k_core_suspend(ab);
979 if (ret)
980 ath11k_warn(ab, "failed to suspend core: %d\n", ret);
981
982 return ret;
983 }
984
ath11k_pci_pm_resume(struct device * dev)985 static __maybe_unused int ath11k_pci_pm_resume(struct device *dev)
986 {
987 struct ath11k_base *ab = dev_get_drvdata(dev);
988 int ret;
989
990 if (test_bit(ATH11K_FLAG_QMI_FAIL, &ab->dev_flags)) {
991 ath11k_dbg(ab, ATH11K_DBG_BOOT, "boot skipping pci resume as qmi is not initialised\n");
992 return 0;
993 }
994
995 ret = ath11k_core_resume(ab);
996 if (ret)
997 ath11k_warn(ab, "failed to resume core: %d\n", ret);
998
999 return ret;
1000 }
1001
1002 static SIMPLE_DEV_PM_OPS(ath11k_pci_pm_ops,
1003 ath11k_pci_pm_suspend,
1004 ath11k_pci_pm_resume);
1005
1006 static struct pci_driver ath11k_pci_driver = {
1007 .name = "ath11k_pci",
1008 .id_table = ath11k_pci_id_table,
1009 .probe = ath11k_pci_probe,
1010 .remove = ath11k_pci_remove,
1011 .shutdown = ath11k_pci_shutdown,
1012 #ifdef CONFIG_PM
1013 .driver.pm = &ath11k_pci_pm_ops,
1014 #endif
1015 };
1016
ath11k_pci_init(void)1017 static int ath11k_pci_init(void)
1018 {
1019 int ret;
1020
1021 ret = pci_register_driver(&ath11k_pci_driver);
1022 if (ret)
1023 pr_err("failed to register ath11k pci driver: %d\n",
1024 ret);
1025
1026 return ret;
1027 }
1028 module_init(ath11k_pci_init);
1029
ath11k_pci_exit(void)1030 static void ath11k_pci_exit(void)
1031 {
1032 pci_unregister_driver(&ath11k_pci_driver);
1033 }
1034
1035 module_exit(ath11k_pci_exit);
1036
1037 MODULE_DESCRIPTION("Driver support for Qualcomm Technologies 802.11ax WLAN PCIe devices");
1038 MODULE_LICENSE("Dual BSD/GPL");
1039
1040 /* QCA639x 2.0 firmware files */
1041 MODULE_FIRMWARE(ATH11K_FW_DIR "/QCA6390/hw2.0/" ATH11K_BOARD_API2_FILE);
1042 MODULE_FIRMWARE(ATH11K_FW_DIR "/QCA6390/hw2.0/" ATH11K_AMSS_FILE);
1043 MODULE_FIRMWARE(ATH11K_FW_DIR "/QCA6390/hw2.0/" ATH11K_M3_FILE);
1044
