1 /*
2 * Copyright 2018 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 *
23 */
24 #include <linux/list.h>
25 #include "amdgpu.h"
26 #include "amdgpu_xgmi.h"
27 #include "amdgpu_smu.h"
28 #include "amdgpu_ras.h"
29 #include "soc15.h"
30 #include "df/df_3_6_offset.h"
31 #include "xgmi/xgmi_4_0_0_smn.h"
32 #include "xgmi/xgmi_4_0_0_sh_mask.h"
33 #include "wafl/wafl2_4_0_0_smn.h"
34 #include "wafl/wafl2_4_0_0_sh_mask.h"
35
36 static DEFINE_MUTEX(xgmi_mutex);
37
38 #define AMDGPU_MAX_XGMI_DEVICE_PER_HIVE 4
39
40 static LIST_HEAD(xgmi_hive_list);
41
42 static const int xgmi_pcs_err_status_reg_vg20[] = {
43 smnXGMI0_PCS_GOPX16_PCS_ERROR_STATUS,
44 smnXGMI0_PCS_GOPX16_PCS_ERROR_STATUS + 0x100000,
45 };
46
47 static const int wafl_pcs_err_status_reg_vg20[] = {
48 smnPCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS,
49 smnPCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS + 0x100000,
50 };
51
52 static const int xgmi_pcs_err_status_reg_arct[] = {
53 smnXGMI0_PCS_GOPX16_PCS_ERROR_STATUS,
54 smnXGMI0_PCS_GOPX16_PCS_ERROR_STATUS + 0x100000,
55 smnXGMI0_PCS_GOPX16_PCS_ERROR_STATUS + 0x500000,
56 smnXGMI0_PCS_GOPX16_PCS_ERROR_STATUS + 0x600000,
57 smnXGMI0_PCS_GOPX16_PCS_ERROR_STATUS + 0x700000,
58 smnXGMI0_PCS_GOPX16_PCS_ERROR_STATUS + 0x800000,
59 };
60
61 /* same as vg20*/
62 static const int wafl_pcs_err_status_reg_arct[] = {
63 smnPCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS,
64 smnPCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS + 0x100000,
65 };
66
67 static const struct amdgpu_pcs_ras_field xgmi_pcs_ras_fields[] = {
68 {"XGMI PCS DataLossErr",
69 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, DataLossErr)},
70 {"XGMI PCS TrainingErr",
71 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, TrainingErr)},
72 {"XGMI PCS CRCErr",
73 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, CRCErr)},
74 {"XGMI PCS BERExceededErr",
75 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, BERExceededErr)},
76 {"XGMI PCS TxMetaDataErr",
77 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, TxMetaDataErr)},
78 {"XGMI PCS ReplayBufParityErr",
79 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, ReplayBufParityErr)},
80 {"XGMI PCS DataParityErr",
81 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, DataParityErr)},
82 {"XGMI PCS ReplayFifoOverflowErr",
83 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, ReplayFifoOverflowErr)},
84 {"XGMI PCS ReplayFifoUnderflowErr",
85 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, ReplayFifoUnderflowErr)},
86 {"XGMI PCS ElasticFifoOverflowErr",
87 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, ElasticFifoOverflowErr)},
88 {"XGMI PCS DeskewErr",
89 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, DeskewErr)},
90 {"XGMI PCS DataStartupLimitErr",
91 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, DataStartupLimitErr)},
92 {"XGMI PCS FCInitTimeoutErr",
93 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, FCInitTimeoutErr)},
94 {"XGMI PCS RecoveryTimeoutErr",
95 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, RecoveryTimeoutErr)},
96 {"XGMI PCS ReadySerialTimeoutErr",
97 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, ReadySerialTimeoutErr)},
98 {"XGMI PCS ReadySerialAttemptErr",
99 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, ReadySerialAttemptErr)},
100 {"XGMI PCS RecoveryAttemptErr",
101 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, RecoveryAttemptErr)},
102 {"XGMI PCS RecoveryRelockAttemptErr",
103 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, RecoveryRelockAttemptErr)},
104 };
105
106 static const struct amdgpu_pcs_ras_field wafl_pcs_ras_fields[] = {
107 {"WAFL PCS DataLossErr",
108 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, DataLossErr)},
109 {"WAFL PCS TrainingErr",
110 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, TrainingErr)},
111 {"WAFL PCS CRCErr",
112 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, CRCErr)},
113 {"WAFL PCS BERExceededErr",
114 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, BERExceededErr)},
115 {"WAFL PCS TxMetaDataErr",
116 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, TxMetaDataErr)},
117 {"WAFL PCS ReplayBufParityErr",
118 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, ReplayBufParityErr)},
119 {"WAFL PCS DataParityErr",
120 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, DataParityErr)},
121 {"WAFL PCS ReplayFifoOverflowErr",
122 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, ReplayFifoOverflowErr)},
123 {"WAFL PCS ReplayFifoUnderflowErr",
124 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, ReplayFifoUnderflowErr)},
125 {"WAFL PCS ElasticFifoOverflowErr",
126 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, ElasticFifoOverflowErr)},
127 {"WAFL PCS DeskewErr",
128 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, DeskewErr)},
129 {"WAFL PCS DataStartupLimitErr",
130 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, DataStartupLimitErr)},
131 {"WAFL PCS FCInitTimeoutErr",
132 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, FCInitTimeoutErr)},
133 {"WAFL PCS RecoveryTimeoutErr",
134 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, RecoveryTimeoutErr)},
135 {"WAFL PCS ReadySerialTimeoutErr",
136 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, ReadySerialTimeoutErr)},
137 {"WAFL PCS ReadySerialAttemptErr",
138 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, ReadySerialAttemptErr)},
139 {"WAFL PCS RecoveryAttemptErr",
140 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, RecoveryAttemptErr)},
141 {"WAFL PCS RecoveryRelockAttemptErr",
142 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, RecoveryRelockAttemptErr)},
143 };
144
145 /**
146 * DOC: AMDGPU XGMI Support
147 *
148 * XGMI is a high speed interconnect that joins multiple GPU cards
149 * into a homogeneous memory space that is organized by a collective
150 * hive ID and individual node IDs, both of which are 64-bit numbers.
151 *
152 * The file xgmi_device_id contains the unique per GPU device ID and
153 * is stored in the /sys/class/drm/card${cardno}/device/ directory.
154 *
155 * Inside the device directory a sub-directory 'xgmi_hive_info' is
156 * created which contains the hive ID and the list of nodes.
157 *
158 * The hive ID is stored in:
159 * /sys/class/drm/card${cardno}/device/xgmi_hive_info/xgmi_hive_id
160 *
161 * The node information is stored in numbered directories:
162 * /sys/class/drm/card${cardno}/device/xgmi_hive_info/node${nodeno}/xgmi_device_id
163 *
164 * Each device has their own xgmi_hive_info direction with a mirror
165 * set of node sub-directories.
166 *
167 * The XGMI memory space is built by contiguously adding the power of
168 * two padded VRAM space from each node to each other.
169 *
170 */
171
172 static struct attribute amdgpu_xgmi_hive_id = {
173 .name = "xgmi_hive_id",
174 .mode = S_IRUGO
175 };
176
177 static struct attribute *amdgpu_xgmi_hive_attrs[] = {
178 &amdgpu_xgmi_hive_id,
179 NULL
180 };
181
amdgpu_xgmi_show_attrs(struct kobject * kobj,struct attribute * attr,char * buf)182 static ssize_t amdgpu_xgmi_show_attrs(struct kobject *kobj,
183 struct attribute *attr, char *buf)
184 {
185 struct amdgpu_hive_info *hive = container_of(
186 kobj, struct amdgpu_hive_info, kobj);
187
188 if (attr == &amdgpu_xgmi_hive_id)
189 return snprintf(buf, PAGE_SIZE, "%llu\n", hive->hive_id);
190
191 return 0;
192 }
193
amdgpu_xgmi_hive_release(struct kobject * kobj)194 static void amdgpu_xgmi_hive_release(struct kobject *kobj)
195 {
196 struct amdgpu_hive_info *hive = container_of(
197 kobj, struct amdgpu_hive_info, kobj);
198
199 mutex_destroy(&hive->hive_lock);
200 kfree(hive);
201 }
202
203 static const struct sysfs_ops amdgpu_xgmi_hive_ops = {
204 .show = amdgpu_xgmi_show_attrs,
205 };
206
207 struct kobj_type amdgpu_xgmi_hive_type = {
208 .release = amdgpu_xgmi_hive_release,
209 .sysfs_ops = &amdgpu_xgmi_hive_ops,
210 .default_attrs = amdgpu_xgmi_hive_attrs,
211 };
212
amdgpu_xgmi_show_device_id(struct device * dev,struct device_attribute * attr,char * buf)213 static ssize_t amdgpu_xgmi_show_device_id(struct device *dev,
214 struct device_attribute *attr,
215 char *buf)
216 {
217 struct drm_device *ddev = dev_get_drvdata(dev);
218 struct amdgpu_device *adev = drm_to_adev(ddev);
219
220 return snprintf(buf, PAGE_SIZE, "%llu\n", adev->gmc.xgmi.node_id);
221
222 }
223
224 #define AMDGPU_XGMI_SET_FICAA(o) ((o) | 0x456801)
amdgpu_xgmi_show_error(struct device * dev,struct device_attribute * attr,char * buf)225 static ssize_t amdgpu_xgmi_show_error(struct device *dev,
226 struct device_attribute *attr,
227 char *buf)
228 {
229 struct drm_device *ddev = dev_get_drvdata(dev);
230 struct amdgpu_device *adev = drm_to_adev(ddev);
231 uint32_t ficaa_pie_ctl_in, ficaa_pie_status_in;
232 uint64_t fica_out;
233 unsigned int error_count = 0;
234
235 ficaa_pie_ctl_in = AMDGPU_XGMI_SET_FICAA(0x200);
236 ficaa_pie_status_in = AMDGPU_XGMI_SET_FICAA(0x208);
237
238 fica_out = adev->df.funcs->get_fica(adev, ficaa_pie_ctl_in);
239 if (fica_out != 0x1f)
240 pr_err("xGMI error counters not enabled!\n");
241
242 fica_out = adev->df.funcs->get_fica(adev, ficaa_pie_status_in);
243
244 if ((fica_out & 0xffff) == 2)
245 error_count = ((fica_out >> 62) & 0x1) + (fica_out >> 63);
246
247 adev->df.funcs->set_fica(adev, ficaa_pie_status_in, 0, 0);
248
249 return snprintf(buf, PAGE_SIZE, "%d\n", error_count);
250 }
251
252
253 static DEVICE_ATTR(xgmi_device_id, S_IRUGO, amdgpu_xgmi_show_device_id, NULL);
254 static DEVICE_ATTR(xgmi_error, S_IRUGO, amdgpu_xgmi_show_error, NULL);
255
amdgpu_xgmi_sysfs_add_dev_info(struct amdgpu_device * adev,struct amdgpu_hive_info * hive)256 static int amdgpu_xgmi_sysfs_add_dev_info(struct amdgpu_device *adev,
257 struct amdgpu_hive_info *hive)
258 {
259 int ret = 0;
260 char node[10] = { 0 };
261
262 /* Create xgmi device id file */
263 ret = device_create_file(adev->dev, &dev_attr_xgmi_device_id);
264 if (ret) {
265 dev_err(adev->dev, "XGMI: Failed to create device file xgmi_device_id\n");
266 return ret;
267 }
268
269 /* Create xgmi error file */
270 ret = device_create_file(adev->dev, &dev_attr_xgmi_error);
271 if (ret)
272 pr_err("failed to create xgmi_error\n");
273
274
275 /* Create sysfs link to hive info folder on the first device */
276 if (hive->kobj.parent != (&adev->dev->kobj)) {
277 ret = sysfs_create_link(&adev->dev->kobj, &hive->kobj,
278 "xgmi_hive_info");
279 if (ret) {
280 dev_err(adev->dev, "XGMI: Failed to create link to hive info");
281 goto remove_file;
282 }
283 }
284
285 sprintf(node, "node%d", atomic_read(&hive->number_devices));
286 /* Create sysfs link form the hive folder to yourself */
287 ret = sysfs_create_link(&hive->kobj, &adev->dev->kobj, node);
288 if (ret) {
289 dev_err(adev->dev, "XGMI: Failed to create link from hive info");
290 goto remove_link;
291 }
292
293 goto success;
294
295
296 remove_link:
297 sysfs_remove_link(&adev->dev->kobj, adev_to_drm(adev)->unique);
298
299 remove_file:
300 device_remove_file(adev->dev, &dev_attr_xgmi_device_id);
301
302 success:
303 return ret;
304 }
305
amdgpu_xgmi_sysfs_rem_dev_info(struct amdgpu_device * adev,struct amdgpu_hive_info * hive)306 static void amdgpu_xgmi_sysfs_rem_dev_info(struct amdgpu_device *adev,
307 struct amdgpu_hive_info *hive)
308 {
309 char node[10];
310 memset(node, 0, sizeof(node));
311
312 device_remove_file(adev->dev, &dev_attr_xgmi_device_id);
313 device_remove_file(adev->dev, &dev_attr_xgmi_error);
314
315 if (hive->kobj.parent != (&adev->dev->kobj))
316 sysfs_remove_link(&adev->dev->kobj,"xgmi_hive_info");
317
318 sprintf(node, "node%d", atomic_read(&hive->number_devices));
319 sysfs_remove_link(&hive->kobj, node);
320
321 }
322
323
324
amdgpu_get_xgmi_hive(struct amdgpu_device * adev)325 struct amdgpu_hive_info *amdgpu_get_xgmi_hive(struct amdgpu_device *adev)
326 {
327 struct amdgpu_hive_info *hive = NULL, *tmp = NULL;
328 int ret;
329
330 if (!adev->gmc.xgmi.hive_id)
331 return NULL;
332
333 if (adev->hive) {
334 kobject_get(&adev->hive->kobj);
335 return adev->hive;
336 }
337
338 mutex_lock(&xgmi_mutex);
339
340 if (!list_empty(&xgmi_hive_list)) {
341 list_for_each_entry_safe(hive, tmp, &xgmi_hive_list, node) {
342 if (hive->hive_id == adev->gmc.xgmi.hive_id)
343 goto pro_end;
344 }
345 }
346
347 hive = kzalloc(sizeof(*hive), GFP_KERNEL);
348 if (!hive) {
349 dev_err(adev->dev, "XGMI: allocation failed\n");
350 hive = NULL;
351 goto pro_end;
352 }
353
354 /* initialize new hive if not exist */
355 ret = kobject_init_and_add(&hive->kobj,
356 &amdgpu_xgmi_hive_type,
357 &adev->dev->kobj,
358 "%s", "xgmi_hive_info");
359 if (ret) {
360 dev_err(adev->dev, "XGMI: failed initializing kobject for xgmi hive\n");
361 kfree(hive);
362 hive = NULL;
363 goto pro_end;
364 }
365
366 hive->hive_id = adev->gmc.xgmi.hive_id;
367 INIT_LIST_HEAD(&hive->device_list);
368 INIT_LIST_HEAD(&hive->node);
369 mutex_init(&hive->hive_lock);
370 atomic_set(&hive->in_reset, 0);
371 atomic_set(&hive->number_devices, 0);
372 task_barrier_init(&hive->tb);
373 hive->pstate = AMDGPU_XGMI_PSTATE_UNKNOWN;
374 hive->hi_req_gpu = NULL;
375 /*
376 * hive pstate on boot is high in vega20 so we have to go to low
377 * pstate on after boot.
378 */
379 hive->hi_req_count = AMDGPU_MAX_XGMI_DEVICE_PER_HIVE;
380 list_add_tail(&hive->node, &xgmi_hive_list);
381
382 pro_end:
383 if (hive)
384 kobject_get(&hive->kobj);
385 mutex_unlock(&xgmi_mutex);
386 return hive;
387 }
388
amdgpu_put_xgmi_hive(struct amdgpu_hive_info * hive)389 void amdgpu_put_xgmi_hive(struct amdgpu_hive_info *hive)
390 {
391 if (hive)
392 kobject_put(&hive->kobj);
393 }
394
amdgpu_xgmi_set_pstate(struct amdgpu_device * adev,int pstate)395 int amdgpu_xgmi_set_pstate(struct amdgpu_device *adev, int pstate)
396 {
397 int ret = 0;
398 struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev);
399 struct amdgpu_device *request_adev = hive->hi_req_gpu ?
400 hive->hi_req_gpu : adev;
401 bool is_hi_req = pstate == AMDGPU_XGMI_PSTATE_MAX_VEGA20;
402 bool init_low = hive->pstate == AMDGPU_XGMI_PSTATE_UNKNOWN;
403
404 amdgpu_put_xgmi_hive(hive);
405 /* fw bug so temporarily disable pstate switching */
406 return 0;
407
408 if (!hive || adev->asic_type != CHIP_VEGA20)
409 return 0;
410
411 mutex_lock(&hive->hive_lock);
412
413 if (is_hi_req)
414 hive->hi_req_count++;
415 else
416 hive->hi_req_count--;
417
418 /*
419 * Vega20 only needs single peer to request pstate high for the hive to
420 * go high but all peers must request pstate low for the hive to go low
421 */
422 if (hive->pstate == pstate ||
423 (!is_hi_req && hive->hi_req_count && !init_low))
424 goto out;
425
426 dev_dbg(request_adev->dev, "Set xgmi pstate %d.\n", pstate);
427
428 ret = amdgpu_dpm_set_xgmi_pstate(request_adev, pstate);
429 if (ret) {
430 dev_err(request_adev->dev,
431 "XGMI: Set pstate failure on device %llx, hive %llx, ret %d",
432 request_adev->gmc.xgmi.node_id,
433 request_adev->gmc.xgmi.hive_id, ret);
434 goto out;
435 }
436
437 if (init_low)
438 hive->pstate = hive->hi_req_count ?
439 hive->pstate : AMDGPU_XGMI_PSTATE_MIN;
440 else {
441 hive->pstate = pstate;
442 hive->hi_req_gpu = pstate != AMDGPU_XGMI_PSTATE_MIN ?
443 adev : NULL;
444 }
445 out:
446 mutex_unlock(&hive->hive_lock);
447 return ret;
448 }
449
amdgpu_xgmi_update_topology(struct amdgpu_hive_info * hive,struct amdgpu_device * adev)450 int amdgpu_xgmi_update_topology(struct amdgpu_hive_info *hive, struct amdgpu_device *adev)
451 {
452 int ret;
453
454 /* Each psp need to set the latest topology */
455 ret = psp_xgmi_set_topology_info(&adev->psp,
456 atomic_read(&hive->number_devices),
457 &adev->psp.xgmi_context.top_info);
458 if (ret)
459 dev_err(adev->dev,
460 "XGMI: Set topology failure on device %llx, hive %llx, ret %d",
461 adev->gmc.xgmi.node_id,
462 adev->gmc.xgmi.hive_id, ret);
463
464 return ret;
465 }
466
467
amdgpu_xgmi_get_hops_count(struct amdgpu_device * adev,struct amdgpu_device * peer_adev)468 int amdgpu_xgmi_get_hops_count(struct amdgpu_device *adev,
469 struct amdgpu_device *peer_adev)
470 {
471 struct psp_xgmi_topology_info *top = &adev->psp.xgmi_context.top_info;
472 int i;
473
474 for (i = 0 ; i < top->num_nodes; ++i)
475 if (top->nodes[i].node_id == peer_adev->gmc.xgmi.node_id)
476 return top->nodes[i].num_hops;
477 return -EINVAL;
478 }
479
amdgpu_xgmi_add_device(struct amdgpu_device * adev)480 int amdgpu_xgmi_add_device(struct amdgpu_device *adev)
481 {
482 struct psp_xgmi_topology_info *top_info;
483 struct amdgpu_hive_info *hive;
484 struct amdgpu_xgmi *entry;
485 struct amdgpu_device *tmp_adev = NULL;
486
487 int count = 0, ret = 0;
488
489 if (!adev->gmc.xgmi.supported)
490 return 0;
491
492 if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_PSP)) {
493 ret = psp_xgmi_initialize(&adev->psp);
494 if (ret) {
495 dev_err(adev->dev,
496 "XGMI: Failed to initialize xgmi session\n");
497 return ret;
498 }
499
500 ret = psp_xgmi_get_hive_id(&adev->psp, &adev->gmc.xgmi.hive_id);
501 if (ret) {
502 dev_err(adev->dev,
503 "XGMI: Failed to get hive id\n");
504 return ret;
505 }
506
507 ret = psp_xgmi_get_node_id(&adev->psp, &adev->gmc.xgmi.node_id);
508 if (ret) {
509 dev_err(adev->dev,
510 "XGMI: Failed to get node id\n");
511 return ret;
512 }
513 } else {
514 adev->gmc.xgmi.hive_id = 16;
515 adev->gmc.xgmi.node_id = adev->gmc.xgmi.physical_node_id + 16;
516 }
517
518 hive = amdgpu_get_xgmi_hive(adev);
519 if (!hive) {
520 ret = -EINVAL;
521 dev_err(adev->dev,
522 "XGMI: node 0x%llx, can not match hive 0x%llx in the hive list.\n",
523 adev->gmc.xgmi.node_id, adev->gmc.xgmi.hive_id);
524 goto exit;
525 }
526 mutex_lock(&hive->hive_lock);
527
528 top_info = &adev->psp.xgmi_context.top_info;
529
530 list_add_tail(&adev->gmc.xgmi.head, &hive->device_list);
531 list_for_each_entry(entry, &hive->device_list, head)
532 top_info->nodes[count++].node_id = entry->node_id;
533 top_info->num_nodes = count;
534 atomic_set(&hive->number_devices, count);
535
536 task_barrier_add_task(&hive->tb);
537
538 if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_PSP)) {
539 list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head) {
540 /* update node list for other device in the hive */
541 if (tmp_adev != adev) {
542 top_info = &tmp_adev->psp.xgmi_context.top_info;
543 top_info->nodes[count - 1].node_id =
544 adev->gmc.xgmi.node_id;
545 top_info->num_nodes = count;
546 }
547 ret = amdgpu_xgmi_update_topology(hive, tmp_adev);
548 if (ret)
549 goto exit_unlock;
550 }
551
552 /* get latest topology info for each device from psp */
553 list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head) {
554 ret = psp_xgmi_get_topology_info(&tmp_adev->psp, count,
555 &tmp_adev->psp.xgmi_context.top_info);
556 if (ret) {
557 dev_err(tmp_adev->dev,
558 "XGMI: Get topology failure on device %llx, hive %llx, ret %d",
559 tmp_adev->gmc.xgmi.node_id,
560 tmp_adev->gmc.xgmi.hive_id, ret);
561 /* To do : continue with some node failed or disable the whole hive */
562 goto exit_unlock;
563 }
564 }
565 }
566
567 if (!ret)
568 ret = amdgpu_xgmi_sysfs_add_dev_info(adev, hive);
569
570 exit_unlock:
571 mutex_unlock(&hive->hive_lock);
572 exit:
573 if (!ret) {
574 adev->hive = hive;
575 dev_info(adev->dev, "XGMI: Add node %d, hive 0x%llx.\n",
576 adev->gmc.xgmi.physical_node_id, adev->gmc.xgmi.hive_id);
577 } else {
578 amdgpu_put_xgmi_hive(hive);
579 dev_err(adev->dev, "XGMI: Failed to add node %d, hive 0x%llx ret: %d\n",
580 adev->gmc.xgmi.physical_node_id, adev->gmc.xgmi.hive_id,
581 ret);
582 }
583
584 return ret;
585 }
586
amdgpu_xgmi_remove_device(struct amdgpu_device * adev)587 int amdgpu_xgmi_remove_device(struct amdgpu_device *adev)
588 {
589 struct amdgpu_hive_info *hive = adev->hive;
590
591 if (!adev->gmc.xgmi.supported)
592 return -EINVAL;
593
594 if (!hive)
595 return -EINVAL;
596
597 mutex_lock(&hive->hive_lock);
598 task_barrier_rem_task(&hive->tb);
599 amdgpu_xgmi_sysfs_rem_dev_info(adev, hive);
600 if (hive->hi_req_gpu == adev)
601 hive->hi_req_gpu = NULL;
602 list_del(&adev->gmc.xgmi.head);
603 mutex_unlock(&hive->hive_lock);
604
605 amdgpu_put_xgmi_hive(hive);
606 adev->hive = NULL;
607
608 if (atomic_dec_return(&hive->number_devices) == 0) {
609 /* Remove the hive from global hive list */
610 mutex_lock(&xgmi_mutex);
611 list_del(&hive->node);
612 mutex_unlock(&xgmi_mutex);
613
614 amdgpu_put_xgmi_hive(hive);
615 }
616
617 return psp_xgmi_terminate(&adev->psp);
618 }
619
amdgpu_xgmi_ras_late_init(struct amdgpu_device * adev)620 int amdgpu_xgmi_ras_late_init(struct amdgpu_device *adev)
621 {
622 int r;
623 struct ras_ih_if ih_info = {
624 .cb = NULL,
625 };
626 struct ras_fs_if fs_info = {
627 .sysfs_name = "xgmi_wafl_err_count",
628 };
629
630 if (!adev->gmc.xgmi.supported ||
631 adev->gmc.xgmi.num_physical_nodes == 0)
632 return 0;
633
634 amdgpu_xgmi_reset_ras_error_count(adev);
635
636 if (!adev->gmc.xgmi.ras_if) {
637 adev->gmc.xgmi.ras_if = kmalloc(sizeof(struct ras_common_if), GFP_KERNEL);
638 if (!adev->gmc.xgmi.ras_if)
639 return -ENOMEM;
640 adev->gmc.xgmi.ras_if->block = AMDGPU_RAS_BLOCK__XGMI_WAFL;
641 adev->gmc.xgmi.ras_if->type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
642 adev->gmc.xgmi.ras_if->sub_block_index = 0;
643 strcpy(adev->gmc.xgmi.ras_if->name, "xgmi_wafl");
644 }
645 ih_info.head = fs_info.head = *adev->gmc.xgmi.ras_if;
646 r = amdgpu_ras_late_init(adev, adev->gmc.xgmi.ras_if,
647 &fs_info, &ih_info);
648 if (r || !amdgpu_ras_is_supported(adev, adev->gmc.xgmi.ras_if->block)) {
649 kfree(adev->gmc.xgmi.ras_if);
650 adev->gmc.xgmi.ras_if = NULL;
651 }
652
653 return r;
654 }
655
amdgpu_xgmi_ras_fini(struct amdgpu_device * adev)656 void amdgpu_xgmi_ras_fini(struct amdgpu_device *adev)
657 {
658 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__XGMI_WAFL) &&
659 adev->gmc.xgmi.ras_if) {
660 struct ras_common_if *ras_if = adev->gmc.xgmi.ras_if;
661 struct ras_ih_if ih_info = {
662 .cb = NULL,
663 };
664
665 amdgpu_ras_late_fini(adev, ras_if, &ih_info);
666 kfree(ras_if);
667 }
668 }
669
amdgpu_xgmi_get_relative_phy_addr(struct amdgpu_device * adev,uint64_t addr)670 uint64_t amdgpu_xgmi_get_relative_phy_addr(struct amdgpu_device *adev,
671 uint64_t addr)
672 {
673 struct amdgpu_xgmi *xgmi = &adev->gmc.xgmi;
674 return (addr + xgmi->physical_node_id * xgmi->node_segment_size);
675 }
676
pcs_clear_status(struct amdgpu_device * adev,uint32_t pcs_status_reg)677 static void pcs_clear_status(struct amdgpu_device *adev, uint32_t pcs_status_reg)
678 {
679 WREG32_PCIE(pcs_status_reg, 0xFFFFFFFF);
680 WREG32_PCIE(pcs_status_reg, 0);
681 }
682
amdgpu_xgmi_reset_ras_error_count(struct amdgpu_device * adev)683 void amdgpu_xgmi_reset_ras_error_count(struct amdgpu_device *adev)
684 {
685 uint32_t i;
686
687 switch (adev->asic_type) {
688 case CHIP_ARCTURUS:
689 for (i = 0; i < ARRAY_SIZE(xgmi_pcs_err_status_reg_arct); i++)
690 pcs_clear_status(adev,
691 xgmi_pcs_err_status_reg_arct[i]);
692 break;
693 case CHIP_VEGA20:
694 for (i = 0; i < ARRAY_SIZE(xgmi_pcs_err_status_reg_vg20); i++)
695 pcs_clear_status(adev,
696 xgmi_pcs_err_status_reg_vg20[i]);
697 break;
698 default:
699 break;
700 }
701 }
702
amdgpu_xgmi_query_pcs_error_status(struct amdgpu_device * adev,uint32_t value,uint32_t * ue_count,uint32_t * ce_count,bool is_xgmi_pcs)703 static int amdgpu_xgmi_query_pcs_error_status(struct amdgpu_device *adev,
704 uint32_t value,
705 uint32_t *ue_count,
706 uint32_t *ce_count,
707 bool is_xgmi_pcs)
708 {
709 int i;
710 int ue_cnt;
711
712 if (is_xgmi_pcs) {
713 /* query xgmi pcs error status,
714 * only ue is supported */
715 for (i = 0; i < ARRAY_SIZE(xgmi_pcs_ras_fields); i ++) {
716 ue_cnt = (value &
717 xgmi_pcs_ras_fields[i].pcs_err_mask) >>
718 xgmi_pcs_ras_fields[i].pcs_err_shift;
719 if (ue_cnt) {
720 dev_info(adev->dev, "%s detected\n",
721 xgmi_pcs_ras_fields[i].err_name);
722 *ue_count += ue_cnt;
723 }
724 }
725 } else {
726 /* query wafl pcs error status,
727 * only ue is supported */
728 for (i = 0; i < ARRAY_SIZE(wafl_pcs_ras_fields); i++) {
729 ue_cnt = (value &
730 wafl_pcs_ras_fields[i].pcs_err_mask) >>
731 wafl_pcs_ras_fields[i].pcs_err_shift;
732 if (ue_cnt) {
733 dev_info(adev->dev, "%s detected\n",
734 wafl_pcs_ras_fields[i].err_name);
735 *ue_count += ue_cnt;
736 }
737 }
738 }
739
740 return 0;
741 }
742
amdgpu_xgmi_query_ras_error_count(struct amdgpu_device * adev,void * ras_error_status)743 int amdgpu_xgmi_query_ras_error_count(struct amdgpu_device *adev,
744 void *ras_error_status)
745 {
746 struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
747 int i;
748 uint32_t data;
749 uint32_t ue_cnt = 0, ce_cnt = 0;
750
751 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__XGMI_WAFL))
752 return -EINVAL;
753
754 err_data->ue_count = 0;
755 err_data->ce_count = 0;
756
757 switch (adev->asic_type) {
758 case CHIP_ARCTURUS:
759 /* check xgmi pcs error */
760 for (i = 0; i < ARRAY_SIZE(xgmi_pcs_err_status_reg_arct); i++) {
761 data = RREG32_PCIE(xgmi_pcs_err_status_reg_arct[i]);
762 if (data)
763 amdgpu_xgmi_query_pcs_error_status(adev,
764 data, &ue_cnt, &ce_cnt, true);
765 }
766 /* check wafl pcs error */
767 for (i = 0; i < ARRAY_SIZE(wafl_pcs_err_status_reg_arct); i++) {
768 data = RREG32_PCIE(wafl_pcs_err_status_reg_arct[i]);
769 if (data)
770 amdgpu_xgmi_query_pcs_error_status(adev,
771 data, &ue_cnt, &ce_cnt, false);
772 }
773 break;
774 case CHIP_VEGA20:
775 default:
776 /* check xgmi pcs error */
777 for (i = 0; i < ARRAY_SIZE(xgmi_pcs_err_status_reg_vg20); i++) {
778 data = RREG32_PCIE(xgmi_pcs_err_status_reg_vg20[i]);
779 if (data)
780 amdgpu_xgmi_query_pcs_error_status(adev,
781 data, &ue_cnt, &ce_cnt, true);
782 }
783 /* check wafl pcs error */
784 for (i = 0; i < ARRAY_SIZE(wafl_pcs_err_status_reg_vg20); i++) {
785 data = RREG32_PCIE(wafl_pcs_err_status_reg_vg20[i]);
786 if (data)
787 amdgpu_xgmi_query_pcs_error_status(adev,
788 data, &ue_cnt, &ce_cnt, false);
789 }
790 break;
791 }
792
793 amdgpu_xgmi_reset_ras_error_count(adev);
794
795 err_data->ue_count += ue_cnt;
796 err_data->ce_count += ce_cnt;
797
798 return 0;
799 }
800
