1 /*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Author: Monk.liu@amd.com
23 */
24 #ifndef AMDGPU_VIRT_H
25 #define AMDGPU_VIRT_H
26
27 #include "amdgv_sriovmsg.h"
28
29 #define AMDGPU_SRIOV_CAPS_SRIOV_VBIOS (1 << 0) /* vBIOS is sr-iov ready */
30 #define AMDGPU_SRIOV_CAPS_ENABLE_IOV (1 << 1) /* sr-iov is enabled on this GPU */
31 #define AMDGPU_SRIOV_CAPS_IS_VF (1 << 2) /* this GPU is a virtual function */
32 #define AMDGPU_PASSTHROUGH_MODE (1 << 3) /* thw whole GPU is pass through for VM */
33 #define AMDGPU_SRIOV_CAPS_RUNTIME (1 << 4) /* is out of full access mode */
34 #define AMDGPU_VF_MMIO_ACCESS_PROTECT (1 << 5) /* MMIO write access is not allowed in sriov runtime */
35
36 /* flags for indirect register access path supported by rlcg for sriov */
37 #define AMDGPU_RLCG_GC_WRITE_LEGACY (0x8 << 28)
38 #define AMDGPU_RLCG_GC_WRITE (0x0 << 28)
39 #define AMDGPU_RLCG_GC_READ (0x1 << 28)
40 #define AMDGPU_RLCG_MMHUB_WRITE (0x2 << 28)
41
42 /* error code for indirect register access path supported by rlcg for sriov */
43 #define AMDGPU_RLCG_VFGATE_DISABLED 0x4000000
44 #define AMDGPU_RLCG_WRONG_OPERATION_TYPE 0x2000000
45 #define AMDGPU_RLCG_REG_NOT_IN_RANGE 0x1000000
46
47 #define AMDGPU_RLCG_SCRATCH1_ADDRESS_MASK 0xFFFFF
48
49 /* all asic after AI use this offset */
50 #define mmRCC_IOV_FUNC_IDENTIFIER 0xDE5
51 /* tonga/fiji use this offset */
52 #define mmBIF_IOV_FUNC_IDENTIFIER 0x1503
53
54 enum amdgpu_sriov_vf_mode {
55 SRIOV_VF_MODE_BARE_METAL = 0,
56 SRIOV_VF_MODE_ONE_VF,
57 SRIOV_VF_MODE_MULTI_VF,
58 };
59
60 struct amdgpu_mm_table {
61 struct amdgpu_bo *bo;
62 uint32_t *cpu_addr;
63 uint64_t gpu_addr;
64 };
65
66 #define AMDGPU_VF_ERROR_ENTRY_SIZE 16
67
68 /* struct error_entry - amdgpu VF error information. */
69 struct amdgpu_vf_error_buffer {
70 struct mutex lock;
71 int read_count;
72 int write_count;
73 uint16_t code[AMDGPU_VF_ERROR_ENTRY_SIZE];
74 uint16_t flags[AMDGPU_VF_ERROR_ENTRY_SIZE];
75 uint64_t data[AMDGPU_VF_ERROR_ENTRY_SIZE];
76 };
77
78 /**
79 * struct amdgpu_virt_ops - amdgpu device virt operations
80 */
81 struct amdgpu_virt_ops {
82 int (*req_full_gpu)(struct amdgpu_device *adev, bool init);
83 int (*rel_full_gpu)(struct amdgpu_device *adev, bool init);
84 int (*req_init_data)(struct amdgpu_device *adev);
85 int (*reset_gpu)(struct amdgpu_device *adev);
86 int (*wait_reset)(struct amdgpu_device *adev);
87 void (*trans_msg)(struct amdgpu_device *adev, u32 req, u32 data1, u32 data2, u32 data3);
88 };
89
90 /*
91 * Firmware Reserve Frame buffer
92 */
93 struct amdgpu_virt_fw_reserve {
94 struct amd_sriov_msg_pf2vf_info_header *p_pf2vf;
95 struct amd_sriov_msg_vf2pf_info_header *p_vf2pf;
96 unsigned int checksum_key;
97 };
98
99 /*
100 * Legacy GIM header
101 *
102 * Defination between PF and VF
103 * Structures forcibly aligned to 4 to keep the same style as PF.
104 */
105 #define AMDGIM_DATAEXCHANGE_OFFSET (64 * 1024)
106
107 #define AMDGIM_GET_STRUCTURE_RESERVED_SIZE(total, u8, u16, u32, u64) \
108 (total - (((u8)+3) / 4 + ((u16)+1) / 2 + (u32) + (u64)*2))
109
110 enum AMDGIM_FEATURE_FLAG {
111 /* GIM supports feature of Error log collecting */
112 AMDGIM_FEATURE_ERROR_LOG_COLLECT = 0x1,
113 /* GIM supports feature of loading uCodes */
114 AMDGIM_FEATURE_GIM_LOAD_UCODES = 0x2,
115 /* VRAM LOST by GIM */
116 AMDGIM_FEATURE_GIM_FLR_VRAMLOST = 0x4,
117 /* MM bandwidth */
118 AMDGIM_FEATURE_GIM_MM_BW_MGR = 0x8,
119 /* PP ONE VF MODE in GIM */
120 AMDGIM_FEATURE_PP_ONE_VF = (1 << 4),
121 /* Indirect Reg Access enabled */
122 AMDGIM_FEATURE_INDIRECT_REG_ACCESS = (1 << 5),
123 };
124
125 enum AMDGIM_REG_ACCESS_FLAG {
126 /* Use PSP to program IH_RB_CNTL */
127 AMDGIM_FEATURE_IH_REG_PSP_EN = (1 << 0),
128 /* Use RLC to program MMHUB regs */
129 AMDGIM_FEATURE_MMHUB_REG_RLC_EN = (1 << 1),
130 /* Use RLC to program GC regs */
131 AMDGIM_FEATURE_GC_REG_RLC_EN = (1 << 2),
132 };
133
134 struct amdgim_pf2vf_info_v1 {
135 /* header contains size and version */
136 struct amd_sriov_msg_pf2vf_info_header header;
137 /* max_width * max_height */
138 unsigned int uvd_enc_max_pixels_count;
139 /* 16x16 pixels/sec, codec independent */
140 unsigned int uvd_enc_max_bandwidth;
141 /* max_width * max_height */
142 unsigned int vce_enc_max_pixels_count;
143 /* 16x16 pixels/sec, codec independent */
144 unsigned int vce_enc_max_bandwidth;
145 /* MEC FW position in kb from the start of visible frame buffer */
146 unsigned int mecfw_kboffset;
147 /* The features flags of the GIM driver supports. */
148 unsigned int feature_flags;
149 /* use private key from mailbox 2 to create chueksum */
150 unsigned int checksum;
151 } __aligned(4);
152
153 struct amdgim_vf2pf_info_v1 {
154 /* header contains size and version */
155 struct amd_sriov_msg_vf2pf_info_header header;
156 /* driver version */
157 char driver_version[64];
158 /* driver certification, 1=WHQL, 0=None */
159 unsigned int driver_cert;
160 /* guest OS type and version: need a define */
161 unsigned int os_info;
162 /* in the unit of 1M */
163 unsigned int fb_usage;
164 /* guest gfx engine usage percentage */
165 unsigned int gfx_usage;
166 /* guest gfx engine health percentage */
167 unsigned int gfx_health;
168 /* guest compute engine usage percentage */
169 unsigned int compute_usage;
170 /* guest compute engine health percentage */
171 unsigned int compute_health;
172 /* guest vce engine usage percentage. 0xffff means N/A. */
173 unsigned int vce_enc_usage;
174 /* guest vce engine health percentage. 0xffff means N/A. */
175 unsigned int vce_enc_health;
176 /* guest uvd engine usage percentage. 0xffff means N/A. */
177 unsigned int uvd_enc_usage;
178 /* guest uvd engine usage percentage. 0xffff means N/A. */
179 unsigned int uvd_enc_health;
180 unsigned int checksum;
181 } __aligned(4);
182
183 struct amdgim_vf2pf_info_v2 {
184 /* header contains size and version */
185 struct amd_sriov_msg_vf2pf_info_header header;
186 uint32_t checksum;
187 /* driver version */
188 uint8_t driver_version[64];
189 /* driver certification, 1=WHQL, 0=None */
190 uint32_t driver_cert;
191 /* guest OS type and version: need a define */
192 uint32_t os_info;
193 /* in the unit of 1M */
194 uint32_t fb_usage;
195 /* guest gfx engine usage percentage */
196 uint32_t gfx_usage;
197 /* guest gfx engine health percentage */
198 uint32_t gfx_health;
199 /* guest compute engine usage percentage */
200 uint32_t compute_usage;
201 /* guest compute engine health percentage */
202 uint32_t compute_health;
203 /* guest vce engine usage percentage. 0xffff means N/A. */
204 uint32_t vce_enc_usage;
205 /* guest vce engine health percentage. 0xffff means N/A. */
206 uint32_t vce_enc_health;
207 /* guest uvd engine usage percentage. 0xffff means N/A. */
208 uint32_t uvd_enc_usage;
209 /* guest uvd engine usage percentage. 0xffff means N/A. */
210 uint32_t uvd_enc_health;
211 uint32_t reserved[AMDGIM_GET_STRUCTURE_RESERVED_SIZE(256, 64, 0, (12 + sizeof(struct amd_sriov_msg_vf2pf_info_header)/sizeof(uint32_t)), 0)];
212 } __aligned(4);
213
214 struct amdgpu_virt_ras_err_handler_data {
215 /* point to bad page records array */
216 struct eeprom_table_record *bps;
217 /* point to reserved bo array */
218 struct amdgpu_bo **bps_bo;
219 /* the count of entries */
220 int count;
221 /* last reserved entry's index + 1 */
222 int last_reserved;
223 };
224
225 /* GPU virtualization */
226 struct amdgpu_virt {
227 uint32_t caps;
228 struct amdgpu_bo *csa_obj;
229 void *csa_cpu_addr;
230 bool chained_ib_support;
231 uint32_t reg_val_offs;
232 struct amdgpu_irq_src ack_irq;
233 struct amdgpu_irq_src rcv_irq;
234 struct work_struct flr_work;
235 struct amdgpu_mm_table mm_table;
236 const struct amdgpu_virt_ops *ops;
237 struct amdgpu_vf_error_buffer vf_errors;
238 struct amdgpu_virt_fw_reserve fw_reserve;
239 uint32_t gim_feature;
240 uint32_t reg_access_mode;
241 int req_init_data_ver;
242 bool tdr_debug;
243 struct amdgpu_virt_ras_err_handler_data *virt_eh_data;
244 bool ras_init_done;
245 uint32_t reg_access;
246
247 /* vf2pf message */
248 struct delayed_work vf2pf_work;
249 uint32_t vf2pf_update_interval_ms;
250
251 /* multimedia bandwidth config */
252 bool is_mm_bw_enabled;
253 uint32_t decode_max_dimension_pixels;
254 uint32_t decode_max_frame_pixels;
255 uint32_t encode_max_dimension_pixels;
256 uint32_t encode_max_frame_pixels;
257
258 /* the ucode id to signal the autoload */
259 uint32_t autoload_ucode_id;
260 };
261
262 struct amdgpu_video_codec_info;
263
264 #define amdgpu_sriov_enabled(adev) \
265 ((adev)->virt.caps & AMDGPU_SRIOV_CAPS_ENABLE_IOV)
266
267 #define amdgpu_sriov_vf(adev) \
268 ((adev)->virt.caps & AMDGPU_SRIOV_CAPS_IS_VF)
269
270 #define amdgpu_sriov_bios(adev) \
271 ((adev)->virt.caps & AMDGPU_SRIOV_CAPS_SRIOV_VBIOS)
272
273 #define amdgpu_sriov_runtime(adev) \
274 ((adev)->virt.caps & AMDGPU_SRIOV_CAPS_RUNTIME)
275
276 #define amdgpu_sriov_fullaccess(adev) \
277 (amdgpu_sriov_vf((adev)) && !amdgpu_sriov_runtime((adev)))
278
279 #define amdgpu_sriov_reg_indirect_en(adev) \
280 (amdgpu_sriov_vf((adev)) && \
281 ((adev)->virt.gim_feature & (AMDGIM_FEATURE_INDIRECT_REG_ACCESS)))
282
283 #define amdgpu_sriov_reg_indirect_ih(adev) \
284 (amdgpu_sriov_vf((adev)) && \
285 ((adev)->virt.reg_access & (AMDGIM_FEATURE_IH_REG_PSP_EN)))
286
287 #define amdgpu_sriov_reg_indirect_mmhub(adev) \
288 (amdgpu_sriov_vf((adev)) && \
289 ((adev)->virt.reg_access & (AMDGIM_FEATURE_MMHUB_REG_RLC_EN)))
290
291 #define amdgpu_sriov_reg_indirect_gc(adev) \
292 (amdgpu_sriov_vf((adev)) && \
293 ((adev)->virt.reg_access & (AMDGIM_FEATURE_GC_REG_RLC_EN)))
294
295 #define amdgpu_sriov_rlcg_error_report_enabled(adev) \
296 (amdgpu_sriov_reg_indirect_mmhub(adev) || amdgpu_sriov_reg_indirect_gc(adev))
297
298 #define amdgpu_passthrough(adev) \
299 ((adev)->virt.caps & AMDGPU_PASSTHROUGH_MODE)
300
301 #define amdgpu_sriov_vf_mmio_access_protection(adev) \
302 ((adev)->virt.caps & AMDGPU_VF_MMIO_ACCESS_PROTECT)
303
is_virtual_machine(void)304 static inline bool is_virtual_machine(void)
305 {
306 #if defined(CONFIG_X86)
307 return boot_cpu_has(X86_FEATURE_HYPERVISOR);
308 #elif defined(CONFIG_ARM64)
309 return !is_kernel_in_hyp_mode();
310 #else
311 return false;
312 #endif
313 }
314
315 #define amdgpu_sriov_is_pp_one_vf(adev) \
316 ((adev)->virt.gim_feature & AMDGIM_FEATURE_PP_ONE_VF)
317 #define amdgpu_sriov_is_debug(adev) \
318 ((!amdgpu_in_reset(adev)) && adev->virt.tdr_debug)
319 #define amdgpu_sriov_is_normal(adev) \
320 ((!amdgpu_in_reset(adev)) && (!adev->virt.tdr_debug))
321 bool amdgpu_virt_mmio_blocked(struct amdgpu_device *adev);
322 void amdgpu_virt_init_setting(struct amdgpu_device *adev);
323 void amdgpu_virt_kiq_reg_write_reg_wait(struct amdgpu_device *adev,
324 uint32_t reg0, uint32_t rreg1,
325 uint32_t ref, uint32_t mask);
326 int amdgpu_virt_request_full_gpu(struct amdgpu_device *adev, bool init);
327 int amdgpu_virt_release_full_gpu(struct amdgpu_device *adev, bool init);
328 int amdgpu_virt_reset_gpu(struct amdgpu_device *adev);
329 void amdgpu_virt_request_init_data(struct amdgpu_device *adev);
330 int amdgpu_virt_wait_reset(struct amdgpu_device *adev);
331 int amdgpu_virt_alloc_mm_table(struct amdgpu_device *adev);
332 void amdgpu_virt_free_mm_table(struct amdgpu_device *adev);
333 void amdgpu_virt_release_ras_err_handler_data(struct amdgpu_device *adev);
334 void amdgpu_virt_init_data_exchange(struct amdgpu_device *adev);
335 void amdgpu_virt_exchange_data(struct amdgpu_device *adev);
336 void amdgpu_virt_fini_data_exchange(struct amdgpu_device *adev);
337 void amdgpu_detect_virtualization(struct amdgpu_device *adev);
338
339 bool amdgpu_virt_can_access_debugfs(struct amdgpu_device *adev);
340 int amdgpu_virt_enable_access_debugfs(struct amdgpu_device *adev);
341 void amdgpu_virt_disable_access_debugfs(struct amdgpu_device *adev);
342
343 enum amdgpu_sriov_vf_mode amdgpu_virt_get_sriov_vf_mode(struct amdgpu_device *adev);
344
345 void amdgpu_virt_update_sriov_video_codec(struct amdgpu_device *adev,
346 struct amdgpu_video_codec_info *encode, uint32_t encode_array_size,
347 struct amdgpu_video_codec_info *decode, uint32_t decode_array_size);
348 void amdgpu_sriov_wreg(struct amdgpu_device *adev,
349 u32 offset, u32 value,
350 u32 acc_flags, u32 hwip);
351 u32 amdgpu_sriov_rreg(struct amdgpu_device *adev,
352 u32 offset, u32 acc_flags, u32 hwip);
353 bool amdgpu_virt_fw_load_skip_check(struct amdgpu_device *adev,
354 uint32_t ucode_id);
355 #endif
356
