1 /*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
20 *
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
23 * of the Software.
24 *
25 */
26
27 #include "amdgpu.h"
28 #include "amdgpu_jpeg.h"
29 #include "amdgpu_pm.h"
30 #include "soc15d.h"
31 #include "soc15_common.h"
32
33 #define JPEG_IDLE_TIMEOUT msecs_to_jiffies(1000)
34
35 static void amdgpu_jpeg_idle_work_handler(struct work_struct *work);
36
amdgpu_jpeg_sw_init(struct amdgpu_device * adev)37 int amdgpu_jpeg_sw_init(struct amdgpu_device *adev)
38 {
39 INIT_DELAYED_WORK(&adev->jpeg.idle_work, amdgpu_jpeg_idle_work_handler);
40 mutex_init(&adev->jpeg.jpeg_pg_lock);
41 atomic_set(&adev->jpeg.total_submission_cnt, 0);
42
43 return 0;
44 }
45
amdgpu_jpeg_sw_fini(struct amdgpu_device * adev)46 int amdgpu_jpeg_sw_fini(struct amdgpu_device *adev)
47 {
48 int i, j;
49
50 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
51 if (adev->jpeg.harvest_config & (1 << i))
52 continue;
53
54 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j)
55 amdgpu_ring_fini(&adev->jpeg.inst[i].ring_dec[j]);
56 }
57
58 mutex_destroy(&adev->jpeg.jpeg_pg_lock);
59
60 return 0;
61 }
62
amdgpu_jpeg_suspend(struct amdgpu_device * adev)63 int amdgpu_jpeg_suspend(struct amdgpu_device *adev)
64 {
65 cancel_delayed_work_sync(&adev->jpeg.idle_work);
66
67 return 0;
68 }
69
amdgpu_jpeg_resume(struct amdgpu_device * adev)70 int amdgpu_jpeg_resume(struct amdgpu_device *adev)
71 {
72 return 0;
73 }
74
amdgpu_jpeg_idle_work_handler(struct work_struct * work)75 static void amdgpu_jpeg_idle_work_handler(struct work_struct *work)
76 {
77 struct amdgpu_device *adev =
78 container_of(work, struct amdgpu_device, jpeg.idle_work.work);
79 unsigned int fences = 0;
80 unsigned int i, j;
81
82 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
83 if (adev->jpeg.harvest_config & (1 << i))
84 continue;
85
86 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j)
87 fences += amdgpu_fence_count_emitted(&adev->jpeg.inst[i].ring_dec[j]);
88 }
89
90 if (!fences && !atomic_read(&adev->jpeg.total_submission_cnt))
91 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_JPEG,
92 AMD_PG_STATE_GATE);
93 else
94 schedule_delayed_work(&adev->jpeg.idle_work, JPEG_IDLE_TIMEOUT);
95 }
96
amdgpu_jpeg_ring_begin_use(struct amdgpu_ring * ring)97 void amdgpu_jpeg_ring_begin_use(struct amdgpu_ring *ring)
98 {
99 struct amdgpu_device *adev = ring->adev;
100
101 atomic_inc(&adev->jpeg.total_submission_cnt);
102 cancel_delayed_work_sync(&adev->jpeg.idle_work);
103
104 mutex_lock(&adev->jpeg.jpeg_pg_lock);
105 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_JPEG,
106 AMD_PG_STATE_UNGATE);
107 mutex_unlock(&adev->jpeg.jpeg_pg_lock);
108 }
109
amdgpu_jpeg_ring_end_use(struct amdgpu_ring * ring)110 void amdgpu_jpeg_ring_end_use(struct amdgpu_ring *ring)
111 {
112 atomic_dec(&ring->adev->jpeg.total_submission_cnt);
113 schedule_delayed_work(&ring->adev->jpeg.idle_work, JPEG_IDLE_TIMEOUT);
114 }
115
amdgpu_jpeg_dec_ring_test_ring(struct amdgpu_ring * ring)116 int amdgpu_jpeg_dec_ring_test_ring(struct amdgpu_ring *ring)
117 {
118 struct amdgpu_device *adev = ring->adev;
119 uint32_t tmp = 0;
120 unsigned i;
121 int r;
122
123 /* JPEG in SRIOV does not support direct register read/write */
124 if (amdgpu_sriov_vf(adev))
125 return 0;
126
127 r = amdgpu_ring_alloc(ring, 3);
128 if (r)
129 return r;
130
131 WREG32(adev->jpeg.inst[ring->me].external.jpeg_pitch[ring->pipe], 0xCAFEDEAD);
132 /* Add a read register to make sure the write register is executed. */
133 RREG32(adev->jpeg.inst[ring->me].external.jpeg_pitch[ring->pipe]);
134
135 amdgpu_ring_write(ring, PACKET0(adev->jpeg.internal.jpeg_pitch[ring->pipe], 0));
136 amdgpu_ring_write(ring, 0xABADCAFE);
137 amdgpu_ring_commit(ring);
138
139 for (i = 0; i < adev->usec_timeout; i++) {
140 tmp = RREG32(adev->jpeg.inst[ring->me].external.jpeg_pitch[ring->pipe]);
141 if (tmp == 0xABADCAFE)
142 break;
143 udelay(1);
144 }
145
146 if (i >= adev->usec_timeout)
147 r = -ETIMEDOUT;
148
149 return r;
150 }
151
amdgpu_jpeg_dec_set_reg(struct amdgpu_ring * ring,uint32_t handle,struct dma_fence ** fence)152 static int amdgpu_jpeg_dec_set_reg(struct amdgpu_ring *ring, uint32_t handle,
153 struct dma_fence **fence)
154 {
155 struct amdgpu_device *adev = ring->adev;
156 struct amdgpu_job *job;
157 struct amdgpu_ib *ib;
158 struct dma_fence *f = NULL;
159 const unsigned ib_size_dw = 16;
160 int i, r;
161
162 r = amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL, ib_size_dw * 4,
163 AMDGPU_IB_POOL_DIRECT, &job);
164 if (r)
165 return r;
166
167 ib = &job->ibs[0];
168
169 ib->ptr[0] = PACKETJ(adev->jpeg.internal.jpeg_pitch[ring->pipe], 0, 0, PACKETJ_TYPE0);
170 ib->ptr[1] = 0xDEADBEEF;
171 for (i = 2; i < 16; i += 2) {
172 ib->ptr[i] = PACKETJ(0, 0, 0, PACKETJ_TYPE6);
173 ib->ptr[i+1] = 0;
174 }
175 ib->length_dw = 16;
176
177 r = amdgpu_job_submit_direct(job, ring, &f);
178 if (r)
179 goto err;
180
181 if (fence)
182 *fence = dma_fence_get(f);
183 dma_fence_put(f);
184
185 return 0;
186
187 err:
188 amdgpu_job_free(job);
189 return r;
190 }
191
amdgpu_jpeg_dec_ring_test_ib(struct amdgpu_ring * ring,long timeout)192 int amdgpu_jpeg_dec_ring_test_ib(struct amdgpu_ring *ring, long timeout)
193 {
194 struct amdgpu_device *adev = ring->adev;
195 uint32_t tmp = 0;
196 unsigned i;
197 struct dma_fence *fence = NULL;
198 long r = 0;
199
200 r = amdgpu_jpeg_dec_set_reg(ring, 1, &fence);
201 if (r)
202 goto error;
203
204 r = dma_fence_wait_timeout(fence, false, timeout);
205 if (r == 0) {
206 r = -ETIMEDOUT;
207 goto error;
208 } else if (r < 0) {
209 goto error;
210 } else {
211 r = 0;
212 }
213 if (!amdgpu_sriov_vf(adev)) {
214 for (i = 0; i < adev->usec_timeout; i++) {
215 tmp = RREG32(adev->jpeg.inst[ring->me].external.jpeg_pitch[ring->pipe]);
216 if (tmp == 0xDEADBEEF)
217 break;
218 udelay(1);
219 }
220
221 if (i >= adev->usec_timeout)
222 r = -ETIMEDOUT;
223 }
224
225 dma_fence_put(fence);
226 error:
227 return r;
228 }
229
amdgpu_jpeg_process_poison_irq(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)230 int amdgpu_jpeg_process_poison_irq(struct amdgpu_device *adev,
231 struct amdgpu_irq_src *source,
232 struct amdgpu_iv_entry *entry)
233 {
234 struct ras_common_if *ras_if = adev->jpeg.ras_if;
235 struct ras_dispatch_if ih_data = {
236 .entry = entry,
237 };
238
239 if (!ras_if)
240 return 0;
241
242 ih_data.head = *ras_if;
243 amdgpu_ras_interrupt_dispatch(adev, &ih_data);
244
245 return 0;
246 }
247
amdgpu_jpeg_ras_late_init(struct amdgpu_device * adev,struct ras_common_if * ras_block)248 int amdgpu_jpeg_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block)
249 {
250 int r, i;
251
252 r = amdgpu_ras_block_late_init(adev, ras_block);
253 if (r)
254 return r;
255
256 if (amdgpu_ras_is_supported(adev, ras_block->block)) {
257 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
258 if (adev->jpeg.harvest_config & (1 << i) ||
259 !adev->jpeg.inst[i].ras_poison_irq.funcs)
260 continue;
261
262 r = amdgpu_irq_get(adev, &adev->jpeg.inst[i].ras_poison_irq, 0);
263 if (r)
264 goto late_fini;
265 }
266 }
267 return 0;
268
269 late_fini:
270 amdgpu_ras_block_late_fini(adev, ras_block);
271 return r;
272 }
273
amdgpu_jpeg_ras_sw_init(struct amdgpu_device * adev)274 int amdgpu_jpeg_ras_sw_init(struct amdgpu_device *adev)
275 {
276 int err;
277 struct amdgpu_jpeg_ras *ras;
278
279 if (!adev->jpeg.ras)
280 return 0;
281
282 ras = adev->jpeg.ras;
283 err = amdgpu_ras_register_ras_block(adev, &ras->ras_block);
284 if (err) {
285 dev_err(adev->dev, "Failed to register jpeg ras block!\n");
286 return err;
287 }
288
289 strcpy(ras->ras_block.ras_comm.name, "jpeg");
290 ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__JPEG;
291 ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__POISON;
292 adev->jpeg.ras_if = &ras->ras_block.ras_comm;
293
294 if (!ras->ras_block.ras_late_init)
295 ras->ras_block.ras_late_init = amdgpu_jpeg_ras_late_init;
296
297 return 0;
298 }
299
