1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28
29 /**
30 * DOC: Interrupt Handling
31 *
32 * Interrupts generated within GPU hardware raise interrupt requests that are
33 * passed to amdgpu IRQ handler which is responsible for detecting source and
34 * type of the interrupt and dispatching matching handlers. If handling an
35 * interrupt requires calling kernel functions that may sleep processing is
36 * dispatched to work handlers.
37 *
38 * If MSI functionality is not disabled by module parameter then MSI
39 * support will be enabled.
40 *
41 * For GPU interrupt sources that may be driven by another driver, IRQ domain
42 * support is used (with mapping between virtual and hardware IRQs).
43 */
44
45 #include <linux/irq.h>
46 #include <drm/drmP.h>
47 #include <drm/drm_crtc_helper.h>
48 #include <drm/amdgpu_drm.h>
49 #include "amdgpu.h"
50 #include "amdgpu_ih.h"
51 #include "atom.h"
52 #include "amdgpu_connectors.h"
53 #include "amdgpu_trace.h"
54
55 #include <linux/pm_runtime.h>
56
57 #ifdef CONFIG_DRM_AMD_DC
58 #include "amdgpu_dm_irq.h"
59 #endif
60
61 #define AMDGPU_WAIT_IDLE_TIMEOUT 200
62
63 /**
64 * amdgpu_hotplug_work_func - work handler for display hotplug event
65 *
66 * @work: work struct pointer
67 *
68 * This is the hotplug event work handler (all ASICs).
69 * The work gets scheduled from the IRQ handler if there
70 * was a hotplug interrupt. It walks through the connector table
71 * and calls hotplug handler for each connector. After this, it sends
72 * a DRM hotplug event to alert userspace.
73 *
74 * This design approach is required in order to defer hotplug event handling
75 * from the IRQ handler to a work handler because hotplug handler has to use
76 * mutexes which cannot be locked in an IRQ handler (since &mutex_lock may
77 * sleep).
78 */
amdgpu_hotplug_work_func(struct work_struct * work)79 static void amdgpu_hotplug_work_func(struct work_struct *work)
80 {
81 struct amdgpu_device *adev = container_of(work, struct amdgpu_device,
82 hotplug_work);
83 struct drm_device *dev = adev->ddev;
84 struct drm_mode_config *mode_config = &dev->mode_config;
85 struct drm_connector *connector;
86
87 mutex_lock(&mode_config->mutex);
88 list_for_each_entry(connector, &mode_config->connector_list, head)
89 amdgpu_connector_hotplug(connector);
90 mutex_unlock(&mode_config->mutex);
91 /* Just fire off a uevent and let userspace tell us what to do */
92 drm_helper_hpd_irq_event(dev);
93 }
94
95 /**
96 * amdgpu_irq_reset_work_func - execute GPU reset
97 *
98 * @work: work struct pointer
99 *
100 * Execute scheduled GPU reset (Cayman+).
101 * This function is called when the IRQ handler thinks we need a GPU reset.
102 */
amdgpu_irq_reset_work_func(struct work_struct * work)103 static void amdgpu_irq_reset_work_func(struct work_struct *work)
104 {
105 struct amdgpu_device *adev = container_of(work, struct amdgpu_device,
106 reset_work);
107
108 if (!amdgpu_sriov_vf(adev))
109 amdgpu_device_gpu_recover(adev, NULL, false);
110 }
111
112 /**
113 * amdgpu_irq_disable_all - disable *all* interrupts
114 *
115 * @adev: amdgpu device pointer
116 *
117 * Disable all types of interrupts from all sources.
118 */
amdgpu_irq_disable_all(struct amdgpu_device * adev)119 void amdgpu_irq_disable_all(struct amdgpu_device *adev)
120 {
121 unsigned long irqflags;
122 unsigned i, j, k;
123 int r;
124
125 spin_lock_irqsave(&adev->irq.lock, irqflags);
126 for (i = 0; i < AMDGPU_IH_CLIENTID_MAX; ++i) {
127 if (!adev->irq.client[i].sources)
128 continue;
129
130 for (j = 0; j < AMDGPU_MAX_IRQ_SRC_ID; ++j) {
131 struct amdgpu_irq_src *src = adev->irq.client[i].sources[j];
132
133 if (!src || !src->funcs->set || !src->num_types)
134 continue;
135
136 for (k = 0; k < src->num_types; ++k) {
137 atomic_set(&src->enabled_types[k], 0);
138 r = src->funcs->set(adev, src, k,
139 AMDGPU_IRQ_STATE_DISABLE);
140 if (r)
141 DRM_ERROR("error disabling interrupt (%d)\n",
142 r);
143 }
144 }
145 }
146 spin_unlock_irqrestore(&adev->irq.lock, irqflags);
147 }
148
149 /**
150 * amdgpu_irq_handler - IRQ handler
151 *
152 * @irq: IRQ number (unused)
153 * @arg: pointer to DRM device
154 *
155 * IRQ handler for amdgpu driver (all ASICs).
156 *
157 * Returns:
158 * result of handling the IRQ, as defined by &irqreturn_t
159 */
amdgpu_irq_handler(int irq,void * arg)160 irqreturn_t amdgpu_irq_handler(int irq, void *arg)
161 {
162 struct drm_device *dev = (struct drm_device *) arg;
163 struct amdgpu_device *adev = dev->dev_private;
164 irqreturn_t ret;
165
166 ret = amdgpu_ih_process(adev);
167 if (ret == IRQ_HANDLED)
168 pm_runtime_mark_last_busy(dev->dev);
169 return ret;
170 }
171
172 /**
173 * amdgpu_msi_ok - check whether MSI functionality is enabled
174 *
175 * @adev: amdgpu device pointer (unused)
176 *
177 * Checks whether MSI functionality has been disabled via module parameter
178 * (all ASICs).
179 *
180 * Returns:
181 * *true* if MSIs are allowed to be enabled or *false* otherwise
182 */
amdgpu_msi_ok(struct amdgpu_device * adev)183 static bool amdgpu_msi_ok(struct amdgpu_device *adev)
184 {
185 if (amdgpu_msi == 1)
186 return true;
187 else if (amdgpu_msi == 0)
188 return false;
189
190 return true;
191 }
192
193 /**
194 * amdgpu_irq_init - initialize interrupt handling
195 *
196 * @adev: amdgpu device pointer
197 *
198 * Sets up work functions for hotplug and reset interrupts, enables MSI
199 * functionality, initializes vblank, hotplug and reset interrupt handling.
200 *
201 * Returns:
202 * 0 on success or error code on failure
203 */
amdgpu_irq_init(struct amdgpu_device * adev)204 int amdgpu_irq_init(struct amdgpu_device *adev)
205 {
206 int r = 0;
207
208 spin_lock_init(&adev->irq.lock);
209
210 /* Enable MSI if not disabled by module parameter */
211 adev->irq.msi_enabled = false;
212
213 if (amdgpu_msi_ok(adev)) {
214 int ret = pci_enable_msi(adev->pdev);
215 if (!ret) {
216 adev->irq.msi_enabled = true;
217 dev_dbg(adev->dev, "amdgpu: using MSI.\n");
218 }
219 }
220
221 if (!amdgpu_device_has_dc_support(adev)) {
222 if (!adev->enable_virtual_display)
223 /* Disable vblank IRQs aggressively for power-saving */
224 /* XXX: can this be enabled for DC? */
225 adev->ddev->vblank_disable_immediate = true;
226
227 r = drm_vblank_init(adev->ddev, adev->mode_info.num_crtc);
228 if (r)
229 return r;
230
231 /* Pre-DCE11 */
232 INIT_WORK(&adev->hotplug_work,
233 amdgpu_hotplug_work_func);
234 }
235
236 INIT_WORK(&adev->reset_work, amdgpu_irq_reset_work_func);
237
238 adev->irq.installed = true;
239 r = drm_irq_install(adev->ddev, adev->ddev->pdev->irq);
240 if (r) {
241 adev->irq.installed = false;
242 if (!amdgpu_device_has_dc_support(adev))
243 flush_work(&adev->hotplug_work);
244 cancel_work_sync(&adev->reset_work);
245 return r;
246 }
247 adev->ddev->max_vblank_count = 0x00ffffff;
248
249 DRM_DEBUG("amdgpu: irq initialized.\n");
250 return 0;
251 }
252
253 /**
254 * amdgpu_irq_fini - shut down interrupt handling
255 *
256 * @adev: amdgpu device pointer
257 *
258 * Tears down work functions for hotplug and reset interrupts, disables MSI
259 * functionality, shuts down vblank, hotplug and reset interrupt handling,
260 * turns off interrupts from all sources (all ASICs).
261 */
amdgpu_irq_fini(struct amdgpu_device * adev)262 void amdgpu_irq_fini(struct amdgpu_device *adev)
263 {
264 unsigned i, j;
265
266 if (adev->irq.installed) {
267 drm_irq_uninstall(adev->ddev);
268 adev->irq.installed = false;
269 if (adev->irq.msi_enabled)
270 pci_disable_msi(adev->pdev);
271 if (!amdgpu_device_has_dc_support(adev))
272 flush_work(&adev->hotplug_work);
273 cancel_work_sync(&adev->reset_work);
274 }
275
276 for (i = 0; i < AMDGPU_IH_CLIENTID_MAX; ++i) {
277 if (!adev->irq.client[i].sources)
278 continue;
279
280 for (j = 0; j < AMDGPU_MAX_IRQ_SRC_ID; ++j) {
281 struct amdgpu_irq_src *src = adev->irq.client[i].sources[j];
282
283 if (!src)
284 continue;
285
286 kfree(src->enabled_types);
287 src->enabled_types = NULL;
288 if (src->data) {
289 kfree(src->data);
290 kfree(src);
291 adev->irq.client[i].sources[j] = NULL;
292 }
293 }
294 kfree(adev->irq.client[i].sources);
295 adev->irq.client[i].sources = NULL;
296 }
297 }
298
299 /**
300 * amdgpu_irq_add_id - register IRQ source
301 *
302 * @adev: amdgpu device pointer
303 * @client_id: client id
304 * @src_id: source id
305 * @source: IRQ source pointer
306 *
307 * Registers IRQ source on a client.
308 *
309 * Returns:
310 * 0 on success or error code otherwise
311 */
amdgpu_irq_add_id(struct amdgpu_device * adev,unsigned client_id,unsigned src_id,struct amdgpu_irq_src * source)312 int amdgpu_irq_add_id(struct amdgpu_device *adev,
313 unsigned client_id, unsigned src_id,
314 struct amdgpu_irq_src *source)
315 {
316 if (client_id >= AMDGPU_IH_CLIENTID_MAX)
317 return -EINVAL;
318
319 if (src_id >= AMDGPU_MAX_IRQ_SRC_ID)
320 return -EINVAL;
321
322 if (!source->funcs)
323 return -EINVAL;
324
325 if (!adev->irq.client[client_id].sources) {
326 adev->irq.client[client_id].sources =
327 kcalloc(AMDGPU_MAX_IRQ_SRC_ID,
328 sizeof(struct amdgpu_irq_src *),
329 GFP_KERNEL);
330 if (!adev->irq.client[client_id].sources)
331 return -ENOMEM;
332 }
333
334 if (adev->irq.client[client_id].sources[src_id] != NULL)
335 return -EINVAL;
336
337 if (source->num_types && !source->enabled_types) {
338 atomic_t *types;
339
340 types = kcalloc(source->num_types, sizeof(atomic_t),
341 GFP_KERNEL);
342 if (!types)
343 return -ENOMEM;
344
345 source->enabled_types = types;
346 }
347
348 adev->irq.client[client_id].sources[src_id] = source;
349 return 0;
350 }
351
352 /**
353 * amdgpu_irq_dispatch - dispatch IRQ to IP blocks
354 *
355 * @adev: amdgpu device pointer
356 * @entry: interrupt vector pointer
357 *
358 * Dispatches IRQ to IP blocks.
359 */
amdgpu_irq_dispatch(struct amdgpu_device * adev,struct amdgpu_iv_entry * entry)360 void amdgpu_irq_dispatch(struct amdgpu_device *adev,
361 struct amdgpu_iv_entry *entry)
362 {
363 unsigned client_id = entry->client_id;
364 unsigned src_id = entry->src_id;
365 struct amdgpu_irq_src *src;
366 int r;
367
368 trace_amdgpu_iv(entry);
369
370 if (client_id >= AMDGPU_IH_CLIENTID_MAX) {
371 DRM_DEBUG("Invalid client_id in IV: %d\n", client_id);
372 return;
373 }
374
375 if (src_id >= AMDGPU_MAX_IRQ_SRC_ID) {
376 DRM_DEBUG("Invalid src_id in IV: %d\n", src_id);
377 return;
378 }
379
380 if (adev->irq.virq[src_id]) {
381 generic_handle_irq(irq_find_mapping(adev->irq.domain, src_id));
382 } else {
383 if (!adev->irq.client[client_id].sources) {
384 DRM_DEBUG("Unregistered interrupt client_id: %d src_id: %d\n",
385 client_id, src_id);
386 return;
387 }
388
389 src = adev->irq.client[client_id].sources[src_id];
390 if (!src) {
391 DRM_DEBUG("Unhandled interrupt src_id: %d\n", src_id);
392 return;
393 }
394
395 r = src->funcs->process(adev, src, entry);
396 if (r)
397 DRM_ERROR("error processing interrupt (%d)\n", r);
398 }
399 }
400
401 /**
402 * amdgpu_irq_update - update hardware interrupt state
403 *
404 * @adev: amdgpu device pointer
405 * @src: interrupt source pointer
406 * @type: type of interrupt
407 *
408 * Updates interrupt state for the specific source (all ASICs).
409 */
amdgpu_irq_update(struct amdgpu_device * adev,struct amdgpu_irq_src * src,unsigned type)410 int amdgpu_irq_update(struct amdgpu_device *adev,
411 struct amdgpu_irq_src *src, unsigned type)
412 {
413 unsigned long irqflags;
414 enum amdgpu_interrupt_state state;
415 int r;
416
417 spin_lock_irqsave(&adev->irq.lock, irqflags);
418
419 /* We need to determine after taking the lock, otherwise
420 we might disable just enabled interrupts again */
421 if (amdgpu_irq_enabled(adev, src, type))
422 state = AMDGPU_IRQ_STATE_ENABLE;
423 else
424 state = AMDGPU_IRQ_STATE_DISABLE;
425
426 r = src->funcs->set(adev, src, type, state);
427 spin_unlock_irqrestore(&adev->irq.lock, irqflags);
428 return r;
429 }
430
431 /**
432 * amdgpu_irq_gpu_reset_resume_helper - update interrupt states on all sources
433 *
434 * @adev: amdgpu device pointer
435 *
436 * Updates state of all types of interrupts on all sources on resume after
437 * reset.
438 */
amdgpu_irq_gpu_reset_resume_helper(struct amdgpu_device * adev)439 void amdgpu_irq_gpu_reset_resume_helper(struct amdgpu_device *adev)
440 {
441 int i, j, k;
442
443 for (i = 0; i < AMDGPU_IH_CLIENTID_MAX; ++i) {
444 if (!adev->irq.client[i].sources)
445 continue;
446
447 for (j = 0; j < AMDGPU_MAX_IRQ_SRC_ID; ++j) {
448 struct amdgpu_irq_src *src = adev->irq.client[i].sources[j];
449
450 if (!src)
451 continue;
452 for (k = 0; k < src->num_types; k++)
453 amdgpu_irq_update(adev, src, k);
454 }
455 }
456 }
457
458 /**
459 * amdgpu_irq_get - enable interrupt
460 *
461 * @adev: amdgpu device pointer
462 * @src: interrupt source pointer
463 * @type: type of interrupt
464 *
465 * Enables specified type of interrupt on the specified source (all ASICs).
466 *
467 * Returns:
468 * 0 on success or error code otherwise
469 */
amdgpu_irq_get(struct amdgpu_device * adev,struct amdgpu_irq_src * src,unsigned type)470 int amdgpu_irq_get(struct amdgpu_device *adev, struct amdgpu_irq_src *src,
471 unsigned type)
472 {
473 if (!adev->ddev->irq_enabled)
474 return -ENOENT;
475
476 if (type >= src->num_types)
477 return -EINVAL;
478
479 if (!src->enabled_types || !src->funcs->set)
480 return -EINVAL;
481
482 if (atomic_inc_return(&src->enabled_types[type]) == 1)
483 return amdgpu_irq_update(adev, src, type);
484
485 return 0;
486 }
487
488 /**
489 * amdgpu_irq_put - disable interrupt
490 *
491 * @adev: amdgpu device pointer
492 * @src: interrupt source pointer
493 * @type: type of interrupt
494 *
495 * Enables specified type of interrupt on the specified source (all ASICs).
496 *
497 * Returns:
498 * 0 on success or error code otherwise
499 */
amdgpu_irq_put(struct amdgpu_device * adev,struct amdgpu_irq_src * src,unsigned type)500 int amdgpu_irq_put(struct amdgpu_device *adev, struct amdgpu_irq_src *src,
501 unsigned type)
502 {
503 if (!adev->ddev->irq_enabled)
504 return -ENOENT;
505
506 if (type >= src->num_types)
507 return -EINVAL;
508
509 if (!src->enabled_types || !src->funcs->set)
510 return -EINVAL;
511
512 if (atomic_dec_and_test(&src->enabled_types[type]))
513 return amdgpu_irq_update(adev, src, type);
514
515 return 0;
516 }
517
518 /**
519 * amdgpu_irq_enabled - check whether interrupt is enabled or not
520 *
521 * @adev: amdgpu device pointer
522 * @src: interrupt source pointer
523 * @type: type of interrupt
524 *
525 * Checks whether the given type of interrupt is enabled on the given source.
526 *
527 * Returns:
528 * *true* if interrupt is enabled, *false* if interrupt is disabled or on
529 * invalid parameters
530 */
amdgpu_irq_enabled(struct amdgpu_device * adev,struct amdgpu_irq_src * src,unsigned type)531 bool amdgpu_irq_enabled(struct amdgpu_device *adev, struct amdgpu_irq_src *src,
532 unsigned type)
533 {
534 if (!adev->ddev->irq_enabled)
535 return false;
536
537 if (type >= src->num_types)
538 return false;
539
540 if (!src->enabled_types || !src->funcs->set)
541 return false;
542
543 return !!atomic_read(&src->enabled_types[type]);
544 }
545
546 /* XXX: Generic IRQ handling */
amdgpu_irq_mask(struct irq_data * irqd)547 static void amdgpu_irq_mask(struct irq_data *irqd)
548 {
549 /* XXX */
550 }
551
amdgpu_irq_unmask(struct irq_data * irqd)552 static void amdgpu_irq_unmask(struct irq_data *irqd)
553 {
554 /* XXX */
555 }
556
557 /* amdgpu hardware interrupt chip descriptor */
558 static struct irq_chip amdgpu_irq_chip = {
559 .name = "amdgpu-ih",
560 .irq_mask = amdgpu_irq_mask,
561 .irq_unmask = amdgpu_irq_unmask,
562 };
563
564 /**
565 * amdgpu_irqdomain_map - create mapping between virtual and hardware IRQ numbers
566 *
567 * @d: amdgpu IRQ domain pointer (unused)
568 * @irq: virtual IRQ number
569 * @hwirq: hardware irq number
570 *
571 * Current implementation assigns simple interrupt handler to the given virtual
572 * IRQ.
573 *
574 * Returns:
575 * 0 on success or error code otherwise
576 */
amdgpu_irqdomain_map(struct irq_domain * d,unsigned int irq,irq_hw_number_t hwirq)577 static int amdgpu_irqdomain_map(struct irq_domain *d,
578 unsigned int irq, irq_hw_number_t hwirq)
579 {
580 if (hwirq >= AMDGPU_MAX_IRQ_SRC_ID)
581 return -EPERM;
582
583 irq_set_chip_and_handler(irq,
584 &amdgpu_irq_chip, handle_simple_irq);
585 return 0;
586 }
587
588 /* Implementation of methods for amdgpu IRQ domain */
589 static const struct irq_domain_ops amdgpu_hw_irqdomain_ops = {
590 .map = amdgpu_irqdomain_map,
591 };
592
593 /**
594 * amdgpu_irq_add_domain - create a linear IRQ domain
595 *
596 * @adev: amdgpu device pointer
597 *
598 * Creates an IRQ domain for GPU interrupt sources
599 * that may be driven by another driver (e.g., ACP).
600 *
601 * Returns:
602 * 0 on success or error code otherwise
603 */
amdgpu_irq_add_domain(struct amdgpu_device * adev)604 int amdgpu_irq_add_domain(struct amdgpu_device *adev)
605 {
606 adev->irq.domain = irq_domain_add_linear(NULL, AMDGPU_MAX_IRQ_SRC_ID,
607 &amdgpu_hw_irqdomain_ops, adev);
608 if (!adev->irq.domain) {
609 DRM_ERROR("GPU irq add domain failed\n");
610 return -ENODEV;
611 }
612
613 return 0;
614 }
615
616 /**
617 * amdgpu_irq_remove_domain - remove the IRQ domain
618 *
619 * @adev: amdgpu device pointer
620 *
621 * Removes the IRQ domain for GPU interrupt sources
622 * that may be driven by another driver (e.g., ACP).
623 */
amdgpu_irq_remove_domain(struct amdgpu_device * adev)624 void amdgpu_irq_remove_domain(struct amdgpu_device *adev)
625 {
626 if (adev->irq.domain) {
627 irq_domain_remove(adev->irq.domain);
628 adev->irq.domain = NULL;
629 }
630 }
631
632 /**
633 * amdgpu_irq_create_mapping - create mapping between domain Linux IRQs
634 *
635 * @adev: amdgpu device pointer
636 * @src_id: IH source id
637 *
638 * Creates mapping between a domain IRQ (GPU IH src id) and a Linux IRQ
639 * Use this for components that generate a GPU interrupt, but are driven
640 * by a different driver (e.g., ACP).
641 *
642 * Returns:
643 * Linux IRQ
644 */
amdgpu_irq_create_mapping(struct amdgpu_device * adev,unsigned src_id)645 unsigned amdgpu_irq_create_mapping(struct amdgpu_device *adev, unsigned src_id)
646 {
647 adev->irq.virq[src_id] = irq_create_mapping(adev->irq.domain, src_id);
648
649 return adev->irq.virq[src_id];
650 }
651
