1 /*
2 * Copyright 2018 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
20 *
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
23 * of the Software.
24 *
25 */
26
27 #include <linux/io-64-nonatomic-lo-hi.h>
28 #ifdef CONFIG_X86
29 #include <asm/hypervisor.h>
30 #endif
31
32 #include "amdgpu.h"
33 #include "amdgpu_gmc.h"
34 #include "amdgpu_ras.h"
35 #include "amdgpu_xgmi.h"
36
37 #include <drm/drm_drv.h>
38 #include <drm/ttm/ttm_tt.h>
39
40 /**
41 * amdgpu_gmc_pdb0_alloc - allocate vram for pdb0
42 *
43 * @adev: amdgpu_device pointer
44 *
45 * Allocate video memory for pdb0 and map it for CPU access
46 * Returns 0 for success, error for failure.
47 */
amdgpu_gmc_pdb0_alloc(struct amdgpu_device * adev)48 int amdgpu_gmc_pdb0_alloc(struct amdgpu_device *adev)
49 {
50 int r;
51 struct amdgpu_bo_param bp;
52 u64 vram_size = adev->gmc.xgmi.node_segment_size * adev->gmc.xgmi.num_physical_nodes;
53 uint32_t pde0_page_shift = adev->gmc.vmid0_page_table_block_size + 21;
54 uint32_t npdes = (vram_size + (1ULL << pde0_page_shift) -1) >> pde0_page_shift;
55
56 memset(&bp, 0, sizeof(bp));
57 bp.size = PAGE_ALIGN((npdes + 1) * 8);
58 bp.byte_align = PAGE_SIZE;
59 bp.domain = AMDGPU_GEM_DOMAIN_VRAM;
60 bp.flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
61 AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
62 bp.type = ttm_bo_type_kernel;
63 bp.resv = NULL;
64 bp.bo_ptr_size = sizeof(struct amdgpu_bo);
65
66 r = amdgpu_bo_create(adev, &bp, &adev->gmc.pdb0_bo);
67 if (r)
68 return r;
69
70 r = amdgpu_bo_reserve(adev->gmc.pdb0_bo, false);
71 if (unlikely(r != 0))
72 goto bo_reserve_failure;
73
74 r = amdgpu_bo_pin(adev->gmc.pdb0_bo, AMDGPU_GEM_DOMAIN_VRAM);
75 if (r)
76 goto bo_pin_failure;
77 r = amdgpu_bo_kmap(adev->gmc.pdb0_bo, &adev->gmc.ptr_pdb0);
78 if (r)
79 goto bo_kmap_failure;
80
81 amdgpu_bo_unreserve(adev->gmc.pdb0_bo);
82 return 0;
83
84 bo_kmap_failure:
85 amdgpu_bo_unpin(adev->gmc.pdb0_bo);
86 bo_pin_failure:
87 amdgpu_bo_unreserve(adev->gmc.pdb0_bo);
88 bo_reserve_failure:
89 amdgpu_bo_unref(&adev->gmc.pdb0_bo);
90 return r;
91 }
92
93 /**
94 * amdgpu_gmc_get_pde_for_bo - get the PDE for a BO
95 *
96 * @bo: the BO to get the PDE for
97 * @level: the level in the PD hirarchy
98 * @addr: resulting addr
99 * @flags: resulting flags
100 *
101 * Get the address and flags to be used for a PDE (Page Directory Entry).
102 */
amdgpu_gmc_get_pde_for_bo(struct amdgpu_bo * bo,int level,uint64_t * addr,uint64_t * flags)103 void amdgpu_gmc_get_pde_for_bo(struct amdgpu_bo *bo, int level,
104 uint64_t *addr, uint64_t *flags)
105 {
106 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
107
108 switch (bo->tbo.resource->mem_type) {
109 case TTM_PL_TT:
110 *addr = bo->tbo.ttm->dma_address[0];
111 break;
112 case TTM_PL_VRAM:
113 *addr = amdgpu_bo_gpu_offset(bo);
114 break;
115 default:
116 *addr = 0;
117 break;
118 }
119 *flags = amdgpu_ttm_tt_pde_flags(bo->tbo.ttm, bo->tbo.resource);
120 amdgpu_gmc_get_vm_pde(adev, level, addr, flags);
121 }
122
123 /*
124 * amdgpu_gmc_pd_addr - return the address of the root directory
125 */
amdgpu_gmc_pd_addr(struct amdgpu_bo * bo)126 uint64_t amdgpu_gmc_pd_addr(struct amdgpu_bo *bo)
127 {
128 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
129 uint64_t pd_addr;
130
131 /* TODO: move that into ASIC specific code */
132 if (adev->asic_type >= CHIP_VEGA10) {
133 uint64_t flags = AMDGPU_PTE_VALID;
134
135 amdgpu_gmc_get_pde_for_bo(bo, -1, &pd_addr, &flags);
136 pd_addr |= flags;
137 } else {
138 pd_addr = amdgpu_bo_gpu_offset(bo);
139 }
140 return pd_addr;
141 }
142
143 /**
144 * amdgpu_gmc_set_pte_pde - update the page tables using CPU
145 *
146 * @adev: amdgpu_device pointer
147 * @cpu_pt_addr: cpu address of the page table
148 * @gpu_page_idx: entry in the page table to update
149 * @addr: dst addr to write into pte/pde
150 * @flags: access flags
151 *
152 * Update the page tables using CPU.
153 */
amdgpu_gmc_set_pte_pde(struct amdgpu_device * adev,void * cpu_pt_addr,uint32_t gpu_page_idx,uint64_t addr,uint64_t flags)154 int amdgpu_gmc_set_pte_pde(struct amdgpu_device *adev, void *cpu_pt_addr,
155 uint32_t gpu_page_idx, uint64_t addr,
156 uint64_t flags)
157 {
158 void __iomem *ptr = (void *)cpu_pt_addr;
159 uint64_t value;
160
161 /*
162 * The following is for PTE only. GART does not have PDEs.
163 */
164 value = addr & 0x0000FFFFFFFFF000ULL;
165 value |= flags;
166 writeq(value, ptr + (gpu_page_idx * 8));
167
168 return 0;
169 }
170
171 /**
172 * amdgpu_gmc_agp_addr - return the address in the AGP address space
173 *
174 * @bo: TTM BO which needs the address, must be in GTT domain
175 *
176 * Tries to figure out how to access the BO through the AGP aperture. Returns
177 * AMDGPU_BO_INVALID_OFFSET if that is not possible.
178 */
amdgpu_gmc_agp_addr(struct ttm_buffer_object * bo)179 uint64_t amdgpu_gmc_agp_addr(struct ttm_buffer_object *bo)
180 {
181 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
182
183 if (bo->ttm->num_pages != 1 || bo->ttm->caching == ttm_cached)
184 return AMDGPU_BO_INVALID_OFFSET;
185
186 if (bo->ttm->dma_address[0] + PAGE_SIZE >= adev->gmc.agp_size)
187 return AMDGPU_BO_INVALID_OFFSET;
188
189 return adev->gmc.agp_start + bo->ttm->dma_address[0];
190 }
191
192 /**
193 * amdgpu_gmc_vram_location - try to find VRAM location
194 *
195 * @adev: amdgpu device structure holding all necessary information
196 * @mc: memory controller structure holding memory information
197 * @base: base address at which to put VRAM
198 *
199 * Function will try to place VRAM at base address provided
200 * as parameter.
201 */
amdgpu_gmc_vram_location(struct amdgpu_device * adev,struct amdgpu_gmc * mc,u64 base)202 void amdgpu_gmc_vram_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc,
203 u64 base)
204 {
205 uint64_t vis_limit = (uint64_t)amdgpu_vis_vram_limit << 20;
206 uint64_t limit = (uint64_t)amdgpu_vram_limit << 20;
207
208 mc->vram_start = base;
209 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
210 if (limit < mc->real_vram_size)
211 mc->real_vram_size = limit;
212
213 if (vis_limit && vis_limit < mc->visible_vram_size)
214 mc->visible_vram_size = vis_limit;
215
216 if (mc->real_vram_size < mc->visible_vram_size)
217 mc->visible_vram_size = mc->real_vram_size;
218
219 if (mc->xgmi.num_physical_nodes == 0) {
220 mc->fb_start = mc->vram_start;
221 mc->fb_end = mc->vram_end;
222 }
223 dev_info(adev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n",
224 mc->mc_vram_size >> 20, mc->vram_start,
225 mc->vram_end, mc->real_vram_size >> 20);
226 }
227
228 /** amdgpu_gmc_sysvm_location - place vram and gart in sysvm aperture
229 *
230 * @adev: amdgpu device structure holding all necessary information
231 * @mc: memory controller structure holding memory information
232 *
233 * This function is only used if use GART for FB translation. In such
234 * case, we use sysvm aperture (vmid0 page tables) for both vram
235 * and gart (aka system memory) access.
236 *
237 * GPUVM (and our organization of vmid0 page tables) require sysvm
238 * aperture to be placed at a location aligned with 8 times of native
239 * page size. For example, if vm_context0_cntl.page_table_block_size
240 * is 12, then native page size is 8G (2M*2^12), sysvm should start
241 * with a 64G aligned address. For simplicity, we just put sysvm at
242 * address 0. So vram start at address 0 and gart is right after vram.
243 */
amdgpu_gmc_sysvm_location(struct amdgpu_device * adev,struct amdgpu_gmc * mc)244 void amdgpu_gmc_sysvm_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc)
245 {
246 u64 hive_vram_start = 0;
247 u64 hive_vram_end = mc->xgmi.node_segment_size * mc->xgmi.num_physical_nodes - 1;
248 mc->vram_start = mc->xgmi.node_segment_size * mc->xgmi.physical_node_id;
249 mc->vram_end = mc->vram_start + mc->xgmi.node_segment_size - 1;
250 mc->gart_start = hive_vram_end + 1;
251 mc->gart_end = mc->gart_start + mc->gart_size - 1;
252 mc->fb_start = hive_vram_start;
253 mc->fb_end = hive_vram_end;
254 dev_info(adev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n",
255 mc->mc_vram_size >> 20, mc->vram_start,
256 mc->vram_end, mc->real_vram_size >> 20);
257 dev_info(adev->dev, "GART: %lluM 0x%016llX - 0x%016llX\n",
258 mc->gart_size >> 20, mc->gart_start, mc->gart_end);
259 }
260
261 /**
262 * amdgpu_gmc_gart_location - try to find GART location
263 *
264 * @adev: amdgpu device structure holding all necessary information
265 * @mc: memory controller structure holding memory information
266 *
267 * Function will place try to place GART before or after VRAM.
268 * If GART size is bigger than space left then we ajust GART size.
269 * Thus function will never fails.
270 */
amdgpu_gmc_gart_location(struct amdgpu_device * adev,struct amdgpu_gmc * mc)271 void amdgpu_gmc_gart_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc)
272 {
273 const uint64_t four_gb = 0x100000000ULL;
274 u64 size_af, size_bf;
275 /*To avoid the hole, limit the max mc address to AMDGPU_GMC_HOLE_START*/
276 u64 max_mc_address = min(adev->gmc.mc_mask, AMDGPU_GMC_HOLE_START - 1);
277
278 /* VCE doesn't like it when BOs cross a 4GB segment, so align
279 * the GART base on a 4GB boundary as well.
280 */
281 size_bf = mc->fb_start;
282 size_af = max_mc_address + 1 - ALIGN(mc->fb_end + 1, four_gb);
283
284 if (mc->gart_size > max(size_bf, size_af)) {
285 dev_warn(adev->dev, "limiting GART\n");
286 mc->gart_size = max(size_bf, size_af);
287 }
288
289 if ((size_bf >= mc->gart_size && size_bf < size_af) ||
290 (size_af < mc->gart_size))
291 mc->gart_start = 0;
292 else
293 mc->gart_start = max_mc_address - mc->gart_size + 1;
294
295 mc->gart_start &= ~(four_gb - 1);
296 mc->gart_end = mc->gart_start + mc->gart_size - 1;
297 dev_info(adev->dev, "GART: %lluM 0x%016llX - 0x%016llX\n",
298 mc->gart_size >> 20, mc->gart_start, mc->gart_end);
299 }
300
301 /**
302 * amdgpu_gmc_agp_location - try to find AGP location
303 * @adev: amdgpu device structure holding all necessary information
304 * @mc: memory controller structure holding memory information
305 *
306 * Function will place try to find a place for the AGP BAR in the MC address
307 * space.
308 *
309 * AGP BAR will be assigned the largest available hole in the address space.
310 * Should be called after VRAM and GART locations are setup.
311 */
amdgpu_gmc_agp_location(struct amdgpu_device * adev,struct amdgpu_gmc * mc)312 void amdgpu_gmc_agp_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc)
313 {
314 const uint64_t sixteen_gb = 1ULL << 34;
315 const uint64_t sixteen_gb_mask = ~(sixteen_gb - 1);
316 u64 size_af, size_bf;
317
318 if (amdgpu_sriov_vf(adev)) {
319 mc->agp_start = 0xffffffffffff;
320 mc->agp_end = 0x0;
321 mc->agp_size = 0;
322
323 return;
324 }
325
326 if (mc->fb_start > mc->gart_start) {
327 size_bf = (mc->fb_start & sixteen_gb_mask) -
328 ALIGN(mc->gart_end + 1, sixteen_gb);
329 size_af = mc->mc_mask + 1 - ALIGN(mc->fb_end + 1, sixteen_gb);
330 } else {
331 size_bf = mc->fb_start & sixteen_gb_mask;
332 size_af = (mc->gart_start & sixteen_gb_mask) -
333 ALIGN(mc->fb_end + 1, sixteen_gb);
334 }
335
336 if (size_bf > size_af) {
337 mc->agp_start = (mc->fb_start - size_bf) & sixteen_gb_mask;
338 mc->agp_size = size_bf;
339 } else {
340 mc->agp_start = ALIGN(mc->fb_end + 1, sixteen_gb);
341 mc->agp_size = size_af;
342 }
343
344 mc->agp_end = mc->agp_start + mc->agp_size - 1;
345 dev_info(adev->dev, "AGP: %lluM 0x%016llX - 0x%016llX\n",
346 mc->agp_size >> 20, mc->agp_start, mc->agp_end);
347 }
348
349 /**
350 * amdgpu_gmc_fault_key - get hask key from vm fault address and pasid
351 *
352 * @addr: 48 bit physical address, page aligned (36 significant bits)
353 * @pasid: 16 bit process address space identifier
354 */
amdgpu_gmc_fault_key(uint64_t addr,uint16_t pasid)355 static inline uint64_t amdgpu_gmc_fault_key(uint64_t addr, uint16_t pasid)
356 {
357 return addr << 4 | pasid;
358 }
359
360 /**
361 * amdgpu_gmc_filter_faults - filter VM faults
362 *
363 * @adev: amdgpu device structure
364 * @ih: interrupt ring that the fault received from
365 * @addr: address of the VM fault
366 * @pasid: PASID of the process causing the fault
367 * @timestamp: timestamp of the fault
368 *
369 * Returns:
370 * True if the fault was filtered and should not be processed further.
371 * False if the fault is a new one and needs to be handled.
372 */
amdgpu_gmc_filter_faults(struct amdgpu_device * adev,struct amdgpu_ih_ring * ih,uint64_t addr,uint16_t pasid,uint64_t timestamp)373 bool amdgpu_gmc_filter_faults(struct amdgpu_device *adev,
374 struct amdgpu_ih_ring *ih, uint64_t addr,
375 uint16_t pasid, uint64_t timestamp)
376 {
377 struct amdgpu_gmc *gmc = &adev->gmc;
378 uint64_t stamp, key = amdgpu_gmc_fault_key(addr, pasid);
379 struct amdgpu_gmc_fault *fault;
380 uint32_t hash;
381
382 /* Stale retry fault if timestamp goes backward */
383 if (amdgpu_ih_ts_after(timestamp, ih->processed_timestamp))
384 return true;
385
386 /* If we don't have space left in the ring buffer return immediately */
387 stamp = max(timestamp, AMDGPU_GMC_FAULT_TIMEOUT + 1) -
388 AMDGPU_GMC_FAULT_TIMEOUT;
389 if (gmc->fault_ring[gmc->last_fault].timestamp >= stamp)
390 return true;
391
392 /* Try to find the fault in the hash */
393 hash = hash_64(key, AMDGPU_GMC_FAULT_HASH_ORDER);
394 fault = &gmc->fault_ring[gmc->fault_hash[hash].idx];
395 while (fault->timestamp >= stamp) {
396 uint64_t tmp;
397
398 if (atomic64_read(&fault->key) == key) {
399 /*
400 * if we get a fault which is already present in
401 * the fault_ring and the timestamp of
402 * the fault is after the expired timestamp,
403 * then this is a new fault that needs to be added
404 * into the fault ring.
405 */
406 if (fault->timestamp_expiry != 0 &&
407 amdgpu_ih_ts_after(fault->timestamp_expiry,
408 timestamp))
409 break;
410 else
411 return true;
412 }
413
414 tmp = fault->timestamp;
415 fault = &gmc->fault_ring[fault->next];
416
417 /* Check if the entry was reused */
418 if (fault->timestamp >= tmp)
419 break;
420 }
421
422 /* Add the fault to the ring */
423 fault = &gmc->fault_ring[gmc->last_fault];
424 atomic64_set(&fault->key, key);
425 fault->timestamp = timestamp;
426
427 /* And update the hash */
428 fault->next = gmc->fault_hash[hash].idx;
429 gmc->fault_hash[hash].idx = gmc->last_fault++;
430 return false;
431 }
432
433 /**
434 * amdgpu_gmc_filter_faults_remove - remove address from VM faults filter
435 *
436 * @adev: amdgpu device structure
437 * @addr: address of the VM fault
438 * @pasid: PASID of the process causing the fault
439 *
440 * Remove the address from fault filter, then future vm fault on this address
441 * will pass to retry fault handler to recover.
442 */
amdgpu_gmc_filter_faults_remove(struct amdgpu_device * adev,uint64_t addr,uint16_t pasid)443 void amdgpu_gmc_filter_faults_remove(struct amdgpu_device *adev, uint64_t addr,
444 uint16_t pasid)
445 {
446 struct amdgpu_gmc *gmc = &adev->gmc;
447 uint64_t key = amdgpu_gmc_fault_key(addr, pasid);
448 struct amdgpu_ih_ring *ih;
449 struct amdgpu_gmc_fault *fault;
450 uint32_t last_wptr;
451 uint64_t last_ts;
452 uint32_t hash;
453 uint64_t tmp;
454
455 ih = adev->irq.retry_cam_enabled ? &adev->irq.ih_soft : &adev->irq.ih1;
456 /* Get the WPTR of the last entry in IH ring */
457 last_wptr = amdgpu_ih_get_wptr(adev, ih);
458 /* Order wptr with ring data. */
459 rmb();
460 /* Get the timetamp of the last entry in IH ring */
461 last_ts = amdgpu_ih_decode_iv_ts(adev, ih, last_wptr, -1);
462
463 hash = hash_64(key, AMDGPU_GMC_FAULT_HASH_ORDER);
464 fault = &gmc->fault_ring[gmc->fault_hash[hash].idx];
465 do {
466 if (atomic64_read(&fault->key) == key) {
467 /*
468 * Update the timestamp when this fault
469 * expired.
470 */
471 fault->timestamp_expiry = last_ts;
472 break;
473 }
474
475 tmp = fault->timestamp;
476 fault = &gmc->fault_ring[fault->next];
477 } while (fault->timestamp < tmp);
478 }
479
amdgpu_gmc_ras_sw_init(struct amdgpu_device * adev)480 int amdgpu_gmc_ras_sw_init(struct amdgpu_device *adev)
481 {
482 int r;
483
484 /* umc ras block */
485 r = amdgpu_umc_ras_sw_init(adev);
486 if (r)
487 return r;
488
489 /* mmhub ras block */
490 r = amdgpu_mmhub_ras_sw_init(adev);
491 if (r)
492 return r;
493
494 /* hdp ras block */
495 r = amdgpu_hdp_ras_sw_init(adev);
496 if (r)
497 return r;
498
499 /* mca.x ras block */
500 r = amdgpu_mca_mp0_ras_sw_init(adev);
501 if (r)
502 return r;
503
504 r = amdgpu_mca_mp1_ras_sw_init(adev);
505 if (r)
506 return r;
507
508 r = amdgpu_mca_mpio_ras_sw_init(adev);
509 if (r)
510 return r;
511
512 /* xgmi ras block */
513 r = amdgpu_xgmi_ras_sw_init(adev);
514 if (r)
515 return r;
516
517 return 0;
518 }
519
amdgpu_gmc_ras_late_init(struct amdgpu_device * adev)520 int amdgpu_gmc_ras_late_init(struct amdgpu_device *adev)
521 {
522 return 0;
523 }
524
amdgpu_gmc_ras_fini(struct amdgpu_device * adev)525 void amdgpu_gmc_ras_fini(struct amdgpu_device *adev)
526 {
527
528 }
529
530 /*
531 * The latest engine allocation on gfx9/10 is:
532 * Engine 2, 3: firmware
533 * Engine 0, 1, 4~16: amdgpu ring,
534 * subject to change when ring number changes
535 * Engine 17: Gart flushes
536 */
537 #define AMDGPU_VMHUB_INV_ENG_BITMAP 0x1FFF3
538
amdgpu_gmc_allocate_vm_inv_eng(struct amdgpu_device * adev)539 int amdgpu_gmc_allocate_vm_inv_eng(struct amdgpu_device *adev)
540 {
541 struct amdgpu_ring *ring;
542 unsigned vm_inv_engs[AMDGPU_MAX_VMHUBS] = {0};
543 unsigned i;
544 unsigned vmhub, inv_eng;
545
546 /* init the vm inv eng for all vmhubs */
547 for_each_set_bit(i, adev->vmhubs_mask, AMDGPU_MAX_VMHUBS) {
548 vm_inv_engs[i] = AMDGPU_VMHUB_INV_ENG_BITMAP;
549 /* reserve engine 5 for firmware */
550 if (adev->enable_mes)
551 vm_inv_engs[i] &= ~(1 << 5);
552 }
553
554 for (i = 0; i < adev->num_rings; ++i) {
555 ring = adev->rings[i];
556 vmhub = ring->vm_hub;
557
558 if (ring == &adev->mes.ring)
559 continue;
560
561 inv_eng = ffs(vm_inv_engs[vmhub]);
562 if (!inv_eng) {
563 dev_err(adev->dev, "no VM inv eng for ring %s\n",
564 ring->name);
565 return -EINVAL;
566 }
567
568 ring->vm_inv_eng = inv_eng - 1;
569 vm_inv_engs[vmhub] &= ~(1 << ring->vm_inv_eng);
570
571 dev_info(adev->dev, "ring %s uses VM inv eng %u on hub %u\n",
572 ring->name, ring->vm_inv_eng, ring->vm_hub);
573 }
574
575 return 0;
576 }
577
578 /**
579 * amdgpu_gmc_tmz_set -- check and set if a device supports TMZ
580 * @adev: amdgpu_device pointer
581 *
582 * Check and set if an the device @adev supports Trusted Memory
583 * Zones (TMZ).
584 */
amdgpu_gmc_tmz_set(struct amdgpu_device * adev)585 void amdgpu_gmc_tmz_set(struct amdgpu_device *adev)
586 {
587 switch (adev->ip_versions[GC_HWIP][0]) {
588 /* RAVEN */
589 case IP_VERSION(9, 2, 2):
590 case IP_VERSION(9, 1, 0):
591 /* RENOIR looks like RAVEN */
592 case IP_VERSION(9, 3, 0):
593 /* GC 10.3.7 */
594 case IP_VERSION(10, 3, 7):
595 /* GC 11.0.1 */
596 case IP_VERSION(11, 0, 1):
597 if (amdgpu_tmz == 0) {
598 adev->gmc.tmz_enabled = false;
599 dev_info(adev->dev,
600 "Trusted Memory Zone (TMZ) feature disabled (cmd line)\n");
601 } else {
602 adev->gmc.tmz_enabled = true;
603 dev_info(adev->dev,
604 "Trusted Memory Zone (TMZ) feature enabled\n");
605 }
606 break;
607 case IP_VERSION(10, 1, 10):
608 case IP_VERSION(10, 1, 1):
609 case IP_VERSION(10, 1, 2):
610 case IP_VERSION(10, 1, 3):
611 case IP_VERSION(10, 3, 0):
612 case IP_VERSION(10, 3, 2):
613 case IP_VERSION(10, 3, 4):
614 case IP_VERSION(10, 3, 5):
615 case IP_VERSION(10, 3, 6):
616 /* VANGOGH */
617 case IP_VERSION(10, 3, 1):
618 /* YELLOW_CARP*/
619 case IP_VERSION(10, 3, 3):
620 case IP_VERSION(11, 0, 4):
621 /* Don't enable it by default yet.
622 */
623 if (amdgpu_tmz < 1) {
624 adev->gmc.tmz_enabled = false;
625 dev_info(adev->dev,
626 "Trusted Memory Zone (TMZ) feature disabled as experimental (default)\n");
627 } else {
628 adev->gmc.tmz_enabled = true;
629 dev_info(adev->dev,
630 "Trusted Memory Zone (TMZ) feature enabled as experimental (cmd line)\n");
631 }
632 break;
633 default:
634 adev->gmc.tmz_enabled = false;
635 dev_info(adev->dev,
636 "Trusted Memory Zone (TMZ) feature not supported\n");
637 break;
638 }
639 }
640
641 /**
642 * amdgpu_gmc_noretry_set -- set per asic noretry defaults
643 * @adev: amdgpu_device pointer
644 *
645 * Set a per asic default for the no-retry parameter.
646 *
647 */
amdgpu_gmc_noretry_set(struct amdgpu_device * adev)648 void amdgpu_gmc_noretry_set(struct amdgpu_device *adev)
649 {
650 struct amdgpu_gmc *gmc = &adev->gmc;
651 uint32_t gc_ver = adev->ip_versions[GC_HWIP][0];
652 bool noretry_default = (gc_ver == IP_VERSION(9, 0, 1) ||
653 gc_ver == IP_VERSION(9, 3, 0) ||
654 gc_ver == IP_VERSION(9, 4, 0) ||
655 gc_ver == IP_VERSION(9, 4, 1) ||
656 gc_ver == IP_VERSION(9, 4, 2) ||
657 gc_ver == IP_VERSION(9, 4, 3) ||
658 gc_ver >= IP_VERSION(10, 3, 0));
659
660 gmc->noretry = (amdgpu_noretry == -1) ? noretry_default : amdgpu_noretry;
661 }
662
amdgpu_gmc_set_vm_fault_masks(struct amdgpu_device * adev,int hub_type,bool enable)663 void amdgpu_gmc_set_vm_fault_masks(struct amdgpu_device *adev, int hub_type,
664 bool enable)
665 {
666 struct amdgpu_vmhub *hub;
667 u32 tmp, reg, i;
668
669 hub = &adev->vmhub[hub_type];
670 for (i = 0; i < 16; i++) {
671 reg = hub->vm_context0_cntl + hub->ctx_distance * i;
672
673 tmp = (hub_type == AMDGPU_GFXHUB(0)) ?
674 RREG32_SOC15_IP(GC, reg) :
675 RREG32_SOC15_IP(MMHUB, reg);
676
677 if (enable)
678 tmp |= hub->vm_cntx_cntl_vm_fault;
679 else
680 tmp &= ~hub->vm_cntx_cntl_vm_fault;
681
682 (hub_type == AMDGPU_GFXHUB(0)) ?
683 WREG32_SOC15_IP(GC, reg, tmp) :
684 WREG32_SOC15_IP(MMHUB, reg, tmp);
685 }
686 }
687
amdgpu_gmc_get_vbios_allocations(struct amdgpu_device * adev)688 void amdgpu_gmc_get_vbios_allocations(struct amdgpu_device *adev)
689 {
690 unsigned size;
691
692 /*
693 * Some ASICs need to reserve a region of video memory to avoid access
694 * from driver
695 */
696 adev->mman.stolen_reserved_offset = 0;
697 adev->mman.stolen_reserved_size = 0;
698
699 /*
700 * TODO:
701 * Currently there is a bug where some memory client outside
702 * of the driver writes to first 8M of VRAM on S3 resume,
703 * this overrides GART which by default gets placed in first 8M and
704 * causes VM_FAULTS once GTT is accessed.
705 * Keep the stolen memory reservation until the while this is not solved.
706 */
707 switch (adev->asic_type) {
708 case CHIP_VEGA10:
709 adev->mman.keep_stolen_vga_memory = true;
710 /*
711 * VEGA10 SRIOV VF with MS_HYPERV host needs some firmware reserved area.
712 */
713 #ifdef CONFIG_X86
714 if (amdgpu_sriov_vf(adev) && hypervisor_is_type(X86_HYPER_MS_HYPERV)) {
715 adev->mman.stolen_reserved_offset = 0x500000;
716 adev->mman.stolen_reserved_size = 0x200000;
717 }
718 #endif
719 break;
720 case CHIP_RAVEN:
721 case CHIP_RENOIR:
722 adev->mman.keep_stolen_vga_memory = true;
723 break;
724 case CHIP_YELLOW_CARP:
725 if (amdgpu_discovery == 0) {
726 adev->mman.stolen_reserved_offset = 0x1ffb0000;
727 adev->mman.stolen_reserved_size = 64 * PAGE_SIZE;
728 }
729 break;
730 default:
731 adev->mman.keep_stolen_vga_memory = false;
732 break;
733 }
734
735 if (amdgpu_sriov_vf(adev) ||
736 !amdgpu_device_has_display_hardware(adev)) {
737 size = 0;
738 } else {
739 size = amdgpu_gmc_get_vbios_fb_size(adev);
740
741 if (adev->mman.keep_stolen_vga_memory)
742 size = max(size, (unsigned)AMDGPU_VBIOS_VGA_ALLOCATION);
743 }
744
745 /* set to 0 if the pre-OS buffer uses up most of vram */
746 if ((adev->gmc.real_vram_size - size) < (8 * 1024 * 1024))
747 size = 0;
748
749 if (size > AMDGPU_VBIOS_VGA_ALLOCATION) {
750 adev->mman.stolen_vga_size = AMDGPU_VBIOS_VGA_ALLOCATION;
751 adev->mman.stolen_extended_size = size - adev->mman.stolen_vga_size;
752 } else {
753 adev->mman.stolen_vga_size = size;
754 adev->mman.stolen_extended_size = 0;
755 }
756 }
757
758 /**
759 * amdgpu_gmc_init_pdb0 - initialize PDB0
760 *
761 * @adev: amdgpu_device pointer
762 *
763 * This function is only used when GART page table is used
764 * for FB address translatioin. In such a case, we construct
765 * a 2-level system VM page table: PDB0->PTB, to cover both
766 * VRAM of the hive and system memory.
767 *
768 * PDB0 is static, initialized once on driver initialization.
769 * The first n entries of PDB0 are used as PTE by setting
770 * P bit to 1, pointing to VRAM. The n+1'th entry points
771 * to a big PTB covering system memory.
772 *
773 */
amdgpu_gmc_init_pdb0(struct amdgpu_device * adev)774 void amdgpu_gmc_init_pdb0(struct amdgpu_device *adev)
775 {
776 int i;
777 uint64_t flags = adev->gart.gart_pte_flags; //TODO it is UC. explore NC/RW?
778 /* Each PDE0 (used as PTE) covers (2^vmid0_page_table_block_size)*2M
779 */
780 u64 vram_size = adev->gmc.xgmi.node_segment_size * adev->gmc.xgmi.num_physical_nodes;
781 u64 pde0_page_size = (1ULL<<adev->gmc.vmid0_page_table_block_size)<<21;
782 u64 vram_addr = adev->vm_manager.vram_base_offset -
783 adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size;
784 u64 vram_end = vram_addr + vram_size;
785 u64 gart_ptb_gpu_pa = amdgpu_gmc_vram_pa(adev, adev->gart.bo);
786 int idx;
787
788 if (!drm_dev_enter(adev_to_drm(adev), &idx))
789 return;
790
791 flags |= AMDGPU_PTE_VALID | AMDGPU_PTE_READABLE;
792 flags |= AMDGPU_PTE_WRITEABLE;
793 flags |= AMDGPU_PTE_SNOOPED;
794 flags |= AMDGPU_PTE_FRAG((adev->gmc.vmid0_page_table_block_size + 9*1));
795 flags |= AMDGPU_PDE_PTE;
796
797 /* The first n PDE0 entries are used as PTE,
798 * pointing to vram
799 */
800 for (i = 0; vram_addr < vram_end; i++, vram_addr += pde0_page_size)
801 amdgpu_gmc_set_pte_pde(adev, adev->gmc.ptr_pdb0, i, vram_addr, flags);
802
803 /* The n+1'th PDE0 entry points to a huge
804 * PTB who has more than 512 entries each
805 * pointing to a 4K system page
806 */
807 flags = AMDGPU_PTE_VALID;
808 flags |= AMDGPU_PDE_BFS(0) | AMDGPU_PTE_SNOOPED;
809 /* Requires gart_ptb_gpu_pa to be 4K aligned */
810 amdgpu_gmc_set_pte_pde(adev, adev->gmc.ptr_pdb0, i, gart_ptb_gpu_pa, flags);
811 drm_dev_exit(idx);
812 }
813
814 /**
815 * amdgpu_gmc_vram_mc2pa - calculate vram buffer's physical address from MC
816 * address
817 *
818 * @adev: amdgpu_device pointer
819 * @mc_addr: MC address of buffer
820 */
amdgpu_gmc_vram_mc2pa(struct amdgpu_device * adev,uint64_t mc_addr)821 uint64_t amdgpu_gmc_vram_mc2pa(struct amdgpu_device *adev, uint64_t mc_addr)
822 {
823 return mc_addr - adev->gmc.vram_start + adev->vm_manager.vram_base_offset;
824 }
825
826 /**
827 * amdgpu_gmc_vram_pa - calculate vram buffer object's physical address from
828 * GPU's view
829 *
830 * @adev: amdgpu_device pointer
831 * @bo: amdgpu buffer object
832 */
amdgpu_gmc_vram_pa(struct amdgpu_device * adev,struct amdgpu_bo * bo)833 uint64_t amdgpu_gmc_vram_pa(struct amdgpu_device *adev, struct amdgpu_bo *bo)
834 {
835 return amdgpu_gmc_vram_mc2pa(adev, amdgpu_bo_gpu_offset(bo));
836 }
837
838 /**
839 * amdgpu_gmc_vram_cpu_pa - calculate vram buffer object's physical address
840 * from CPU's view
841 *
842 * @adev: amdgpu_device pointer
843 * @bo: amdgpu buffer object
844 */
amdgpu_gmc_vram_cpu_pa(struct amdgpu_device * adev,struct amdgpu_bo * bo)845 uint64_t amdgpu_gmc_vram_cpu_pa(struct amdgpu_device *adev, struct amdgpu_bo *bo)
846 {
847 return amdgpu_bo_gpu_offset(bo) - adev->gmc.vram_start + adev->gmc.aper_base;
848 }
849
amdgpu_gmc_vram_checking(struct amdgpu_device * adev)850 int amdgpu_gmc_vram_checking(struct amdgpu_device *adev)
851 {
852 struct amdgpu_bo *vram_bo = NULL;
853 uint64_t vram_gpu = 0;
854 void *vram_ptr = NULL;
855
856 int ret, size = 0x100000;
857 uint8_t cptr[10];
858
859 ret = amdgpu_bo_create_kernel(adev, size, PAGE_SIZE,
860 AMDGPU_GEM_DOMAIN_VRAM,
861 &vram_bo,
862 &vram_gpu,
863 &vram_ptr);
864 if (ret)
865 return ret;
866
867 memset(vram_ptr, 0x86, size);
868 memset(cptr, 0x86, 10);
869
870 /**
871 * Check the start, the mid, and the end of the memory if the content of
872 * each byte is the pattern "0x86". If yes, we suppose the vram bo is
873 * workable.
874 *
875 * Note: If check the each byte of whole 1M bo, it will cost too many
876 * seconds, so here, we just pick up three parts for emulation.
877 */
878 ret = memcmp(vram_ptr, cptr, 10);
879 if (ret)
880 return ret;
881
882 ret = memcmp(vram_ptr + (size / 2), cptr, 10);
883 if (ret)
884 return ret;
885
886 ret = memcmp(vram_ptr + size - 10, cptr, 10);
887 if (ret)
888 return ret;
889
890 amdgpu_bo_free_kernel(&vram_bo, &vram_gpu,
891 &vram_ptr);
892
893 return 0;
894 }
895
current_memory_partition_show(struct device * dev,struct device_attribute * addr,char * buf)896 static ssize_t current_memory_partition_show(
897 struct device *dev, struct device_attribute *addr, char *buf)
898 {
899 struct drm_device *ddev = dev_get_drvdata(dev);
900 struct amdgpu_device *adev = drm_to_adev(ddev);
901 enum amdgpu_memory_partition mode;
902
903 mode = adev->gmc.gmc_funcs->query_mem_partition_mode(adev);
904 switch (mode) {
905 case AMDGPU_NPS1_PARTITION_MODE:
906 return sysfs_emit(buf, "NPS1\n");
907 case AMDGPU_NPS2_PARTITION_MODE:
908 return sysfs_emit(buf, "NPS2\n");
909 case AMDGPU_NPS3_PARTITION_MODE:
910 return sysfs_emit(buf, "NPS3\n");
911 case AMDGPU_NPS4_PARTITION_MODE:
912 return sysfs_emit(buf, "NPS4\n");
913 case AMDGPU_NPS6_PARTITION_MODE:
914 return sysfs_emit(buf, "NPS6\n");
915 case AMDGPU_NPS8_PARTITION_MODE:
916 return sysfs_emit(buf, "NPS8\n");
917 default:
918 return sysfs_emit(buf, "UNKNOWN\n");
919 }
920
921 return sysfs_emit(buf, "UNKNOWN\n");
922 }
923
924 static DEVICE_ATTR_RO(current_memory_partition);
925
amdgpu_gmc_sysfs_init(struct amdgpu_device * adev)926 int amdgpu_gmc_sysfs_init(struct amdgpu_device *adev)
927 {
928 if (!adev->gmc.gmc_funcs->query_mem_partition_mode)
929 return 0;
930
931 return device_create_file(adev->dev,
932 &dev_attr_current_memory_partition);
933 }
934
amdgpu_gmc_sysfs_fini(struct amdgpu_device * adev)935 void amdgpu_gmc_sysfs_fini(struct amdgpu_device *adev)
936 {
937 device_remove_file(adev->dev, &dev_attr_current_memory_partition);
938 }
939
